STM32_Prog_DB_0x474.xml 86 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x474</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32H50x</Name>
  9. <Series>STM32H5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- dual Bank non secure -->
  15. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  16. </Configuration>
  17. <Configuration number="0x1"> <!-- Dual Bank secure -->
  18. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  19. </Configuration>
  20. </Interface>
  21. <!-- Bootloader Interface -->
  22. <Interface name="Bootloader">
  23. <Configuration number="0x2"> <!-- Dual Bank Secure-->
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  25. </Configuration>
  26. <Configuration number="0x3"> <!-- Dual Bank non Secure-->
  27. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  28. </Configuration>
  29. </Interface>
  30. </Configurations>
  31. <!-- Peripherals -->
  32. <Peripherals>
  33. <!-- Embedded SRAM -->
  34. <Peripheral>
  35. <Name>Embedded SRAM</Name>
  36. <Type>Storage</Type>
  37. <Description/>
  38. <ErasedValue>0xFF</ErasedValue>
  39. <Access>RWE</Access>
  40. <!-- 96 KB -->
  41. <Configuration config="0,3">
  42. <Parameters address="0x20000000" name="SRAM" size="0x8000"/>
  43. <Description/>
  44. <Organization>Single</Organization>
  45. <Bank name="Bank 1">
  46. <Field>
  47. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
  48. </Field>
  49. </Bank>
  50. </Configuration>
  51. <Configuration config="1,2">
  52. <Parameters address="0x30000000" name="SRAM" size="0x8000"/>
  53. <Description/>
  54. <Organization>Single</Organization>
  55. <Bank name="Bank 1">
  56. <Field>
  57. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x8000"/>
  58. </Field>
  59. </Bank>
  60. </Configuration>
  61. </Peripheral>
  62. <!-- Embedded Flash -->
  63. <Peripheral>
  64. <Name>Embedded Flash</Name>
  65. <Type>Storage</Type>
  66. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  67. <ErasedValue>0xFF</ErasedValue>
  68. <Access>RWE</Access>
  69. <FlashSize address="0x08FFF80C" default="0x20000"/>
  70. <BootloaderVersion address="0x0BF8FFFE"/>
  71. <Configuration config="0,3"> <!-- dual Bank nn secure -->
  72. <Parameters address="0x08000000" name=" 128Kbyte Embedded Flash" size="0x20000"/>
  73. <Description/>
  74. <Organization>Dual</Organization>
  75. <Allignement>0x10</Allignement>
  76. <Bank name="Bank 1">
  77. <Field>
  78. <Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x2000"/>
  79. </Field>
  80. </Bank>
  81. <Bank name="Bank 2">
  82. <Field>
  83. <Parameters address="0x08010000" name="sector8" occurence="0x8" size="0x2000"/>
  84. </Field>
  85. </Bank>
  86. </Configuration>
  87. <Configuration config="1,2"> <!-- dual Bank secure -->
  88. <Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x20000"/>
  89. <Description/>
  90. <Organization>Dual</Organization>
  91. <Allignement>0x10</Allignement>
  92. <Bank name="Bank 1">
  93. <Field>
  94. <Parameters address="0x0c000000" name="sector0" occurence="0x10" size="0x2000"/>
  95. </Field>
  96. </Bank>
  97. <Bank name="Bank 2">
  98. <Field>
  99. <Parameters address="0x0c010000" name="sector8" occurence="0x10" size="0x2000"/>
  100. </Field>
  101. </Bank>
  102. </Configuration>
  103. </Peripheral>
  104. <!-- Data EEPROM -->
  105. <Peripheral>
  106. <Name>Data EEPROM</Name>
  107. <Type>Storage</Type>
  108. <Description>The Data EEPROM memory block. It contains user data.</Description>
  109. <ErasedValue>0xFF</ErasedValue>
  110. <Access>RWE</Access>
  111. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  112. <Configuration config="0,1,3">
  113. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  114. <Description/>
  115. <Organization>Dual</Organization>
  116. <Allignement>0x4</Allignement>
  117. <Bank name="Bank 1">
  118. <Field>
  119. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  120. </Field>
  121. </Bank>
  122. <Bank name="Bank 2">
  123. <Field>
  124. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  125. </Field>
  126. </Bank>
  127. </Configuration>
  128. </Peripheral>
  129. <!-- OTP -->
  130. <Peripheral>
  131. <Name>OTP</Name>
  132. <Type>Storage</Type>
  133. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  134. <ErasedValue>0xFF</ErasedValue>
  135. <Access>RW</Access>
  136. <!-- 2 KBytes single bank -->
  137. <Configuration>
  138. <Parameters address="0x08FFF000" name=" 2 KBytes Data OTP" size="0x800"/>
  139. <Description/>
  140. <Organization>Single</Organization>
  141. <Allignement>0x2</Allignement>
  142. <Bank name="OTP">
  143. <Field>
  144. <Parameters address="0x08FFF000" name="OTP" occurence="0x1" size="0x800"/>
  145. </Field>
  146. </Bank>
  147. </Configuration>
  148. </Peripheral>
  149. <!-- Option Bytes -->
  150. <Peripheral>
  151. <Name>Option Bytes</Name>
  152. <Type>Configuration</Type>
  153. <Description/>
  154. <Access>RW</Access>
  155. <Configuration config="0">
  156. <Bank interface="JTAG_SWD">
  157. <Parameters address="0x40022050" name="Bank 1" size="0x70"/>
  158. <Category>
  159. <Name>Product state</Name>
  160. <Field>
  161. <Parameters address="0x40022050" name="CUR" size="0x4"/>
  162. <AssignedBits>
  163. <Bit>
  164. <Name>PRODUCT_STATE</Name>
  165. <Description>Life state code.</Description>
  166. <BitOffset>0x8</BitOffset>
  167. <BitWidth>0x8</BitWidth>
  168. <Access>R</Access>
  169. <Values>
  170. <Val value="0xED">Open</Val>
  171. <Val value="0x17">Provisioning</Val>
  172. <Val value="0x2E">Provisioned</Val>
  173. <Val value="0x72">Closed</Val>
  174. <Val value="0x5C">Locked</Val>
  175. <Val value="0x9A">Regression</Val>
  176. </Values>
  177. </Bit>
  178. </AssignedBits>
  179. </Field>
  180. <Field>
  181. <Parameters address="0x40022054" name="PRG" size="0x4"/>
  182. <AssignedBits>
  183. <Bit>
  184. <Name>PRODUCT_STATE</Name>
  185. <Description>Life state code.</Description>
  186. <BitOffset>0x8</BitOffset>
  187. <BitWidth>0x8</BitWidth>
  188. <Access>W</Access>
  189. <Values>
  190. <Val value="0xED">Open</Val>
  191. <Val value="0x17">Provisioning</Val>
  192. <Val value="0x2E">Provisioned</Val>
  193. <Val value="0x72">Closed</Val>
  194. <Val value="0x5C">Locked</Val>
  195. <Val value="0x9A">Regression</Val>
  196. </Values>
  197. </Bit>
  198. </AssignedBits>
  199. </Field>
  200. </Category>
  201. <Category>
  202. <Name>BOR Level</Name>
  203. <Field>
  204. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  205. <AssignedBits>
  206. <Bit>
  207. <Name>BORH_EN</Name>
  208. <Description>Brownout high enable configuration bit</Description>
  209. <BitOffset>0x2</BitOffset>
  210. <BitWidth>0x1</BitWidth>
  211. <Access>R</Access>
  212. <Val value="0x0">disabled</Val>
  213. <Val value="0x1">enabled</Val>
  214. </Bit>
  215. </AssignedBits>
  216. </Field>
  217. <Field>
  218. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  219. <AssignedBits>
  220. <Bit>
  221. <Name>BORH_EN</Name>
  222. <Description>Brownout high enable configuration bit</Description>
  223. <BitOffset>0x2</BitOffset>
  224. <BitWidth>0x1</BitWidth>
  225. <Access>W</Access>
  226. <Val value="0x0">disabled</Val>
  227. <Val value="0x1">enabled</Val>
  228. </Bit>
  229. </AssignedBits>
  230. </Field>
  231. <Field>
  232. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  233. <AssignedBits>
  234. <Bit>
  235. <Name>BOR_LEV</Name>
  236. <Description>Brownout level option status bit.</Description>
  237. <BitOffset>0x0</BitOffset>
  238. <BitWidth>0x2</BitWidth>
  239. <Access>R</Access>
  240. <Values>
  241. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  242. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  243. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  244. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  245. </Values>
  246. </Bit>
  247. </AssignedBits>
  248. </Field>
  249. <Field>
  250. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  251. <AssignedBits>
  252. <Bit>
  253. <Name>BOR_LEV</Name>
  254. <Description>Brownout level option status bit.</Description>
  255. <BitOffset>0x0</BitOffset>
  256. <BitWidth>0x2</BitWidth>
  257. <Access>W</Access>
  258. <Values>
  259. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  260. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  261. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  262. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  263. </Values>
  264. </Bit>
  265. </AssignedBits>
  266. </Field>
  267. </Category>
  268. <Category>
  269. <Name>User Configuration</Name>
  270. <Field>
  271. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  272. <AssignedBits>
  273. <Bit>
  274. <Name>IO_VDDIO2_HSLV</Name>
  275. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  276. <BitOffset>0x11</BitOffset>
  277. <BitWidth>0x1</BitWidth>
  278. <Access>R</Access>
  279. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  280. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  281. </Bit>
  282. </AssignedBits>
  283. </Field>
  284. <Field>
  285. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  286. <AssignedBits>
  287. <Bit>
  288. <Name>IO_VDDIO2_HSLV</Name>
  289. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  290. <BitOffset>0x11</BitOffset>
  291. <BitWidth>0x1</BitWidth>
  292. <Access>W</Access>
  293. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  294. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  295. </Bit>
  296. </AssignedBits>
  297. </Field>
  298. <Field>
  299. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  300. <AssignedBits>
  301. <Bit>
  302. <Name>IO_VDD_HSLV</Name>
  303. <Description>High-speed IO at low VDD voltage status bit.</Description>
  304. <BitOffset>0x10</BitOffset>
  305. <BitWidth>0x1</BitWidth>
  306. <Access>R</Access>
  307. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  308. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  309. </Bit>
  310. </AssignedBits>
  311. </Field>
  312. <Field>
  313. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  314. <AssignedBits>
  315. <Bit>
  316. <Name>IO_VDD_HSLV</Name>
  317. <Description>High-speed IO at low VDD voltage status bit.</Description>
  318. <BitOffset>0x10</BitOffset>
  319. <BitWidth>0x1</BitWidth>
  320. <Access>W</Access>
  321. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  322. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  323. </Bit>
  324. </AssignedBits>
  325. </Field>
  326. <Field>
  327. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  328. <AssignedBits>
  329. <Bit>
  330. <Name>IWDG_STDBY</Name>
  331. <Description>Standby mode freeze option status bit.</Description>
  332. <BitOffset>0x15</BitOffset>
  333. <BitWidth>0x1</BitWidth>
  334. <Access>R</Access>
  335. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  336. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  337. </Bit>
  338. </AssignedBits>
  339. </Field>
  340. <Field>
  341. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  342. <AssignedBits>
  343. <Bit>
  344. <Name>IWDG_STDBY</Name>
  345. <Description>Standby mode freeze option status bit.</Description>
  346. <BitOffset>0x15</BitOffset>
  347. <BitWidth>0x1</BitWidth>
  348. <Access>W</Access>
  349. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  350. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  351. </Bit>
  352. </AssignedBits>
  353. </Field>
  354. <Field>
  355. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  356. <AssignedBits>
  357. <Bit>
  358. <Name>IWDG_STOP</Name>
  359. <Description>Stop mode freeze option status bit.</Description>
  360. <BitOffset>0x14</BitOffset>
  361. <BitWidth>0x1</BitWidth>
  362. <Access>R</Access>
  363. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  364. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  365. </Bit>
  366. </AssignedBits>
  367. </Field>
  368. <Field>
  369. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  370. <AssignedBits>
  371. <Bit>
  372. <Name>IWDG_STOP</Name>
  373. <Description>Stop mode freeze option status bit.</Description>
  374. <BitOffset>0x14</BitOffset>
  375. <BitWidth>0x1</BitWidth>
  376. <Access>W</Access>
  377. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  378. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  379. </Bit>
  380. </AssignedBits>
  381. </Field>
  382. <Field>
  383. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  384. <AssignedBits>
  385. <Bit>
  386. <Name>SWAP_BANK</Name>
  387. <Description>Bank swapping option status bit.</Description>
  388. <BitOffset>0x1F</BitOffset>
  389. <BitWidth>0x1</BitWidth>
  390. <Access>R</Access>
  391. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  392. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  393. </Bit>
  394. </AssignedBits>
  395. </Field>
  396. <Field>
  397. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  398. <AssignedBits>
  399. <Bit>
  400. <Name>SWAP_BANK</Name>
  401. <Description>Bank swapping option status bit.</Description>
  402. <BitOffset>0x1F</BitOffset>
  403. <BitWidth>0x1</BitWidth>
  404. <Access>W</Access>
  405. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  406. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  407. </Bit>
  408. </AssignedBits>
  409. </Field>
  410. <Field>
  411. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  412. <AssignedBits>
  413. <Bit>
  414. <Name>IWDG_SW</Name>
  415. <Description>IWDG control mode option status bit.</Description>
  416. <BitOffset>0x3</BitOffset>
  417. <BitWidth>0x1</BitWidth>
  418. <Access>R</Access>
  419. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  420. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  421. </Bit>
  422. </AssignedBits>
  423. </Field>
  424. <Field>
  425. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  426. <AssignedBits>
  427. <Bit>
  428. <Name>IWDG_SW</Name>
  429. <Description>IWDG control mode option status bit.</Description>
  430. <BitOffset>0x3</BitOffset>
  431. <BitWidth>0x1</BitWidth>
  432. <Access>W</Access>
  433. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  434. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  435. </Bit>
  436. </AssignedBits>
  437. </Field>
  438. <Field>
  439. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  440. <AssignedBits>
  441. <Bit>
  442. <Name>WWDG_SW</Name>
  443. <Description>WWDG control mode option status bit.</Description>
  444. <BitOffset>0x4</BitOffset>
  445. <BitWidth>0x1</BitWidth>
  446. <Access>R</Access>
  447. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  448. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  449. </Bit>
  450. </AssignedBits>
  451. </Field>
  452. <Field>
  453. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  454. <AssignedBits>
  455. <Bit>
  456. <Name>WWDG_SW</Name>
  457. <Description>WWDG control mode option status bit.</Description>
  458. <BitOffset>0x4</BitOffset>
  459. <BitWidth>0x1</BitWidth>
  460. <Access>W</Access>
  461. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  462. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  463. </Bit>
  464. </AssignedBits>
  465. </Field>
  466. <Field>
  467. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  468. <AssignedBits>
  469. <Bit>
  470. <Name>NRST_STOP</Name>
  471. <Description>Core domain Stop entry reset option status bit.</Description>
  472. <BitOffset>0x6</BitOffset>
  473. <BitWidth>0x1</BitWidth>
  474. <Access>R</Access>
  475. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  476. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  477. </Bit>
  478. </AssignedBits>
  479. </Field>
  480. <Field>
  481. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  482. <AssignedBits>
  483. <Bit>
  484. <Name>NRST_STOP</Name>
  485. <Description>Core domain Stop entry reset option status bit.</Description>
  486. <BitOffset>0x6</BitOffset>
  487. <BitWidth>0x1</BitWidth>
  488. <Access>W</Access>
  489. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  490. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  491. </Bit>
  492. </AssignedBits>
  493. </Field>
  494. <Field>
  495. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  496. <AssignedBits>
  497. <Bit>
  498. <Name>NRST_STDBY</Name>
  499. <Description>Core domain Standby entry reset option status bit.</Description>
  500. <BitOffset>0x7</BitOffset>
  501. <BitWidth>0x1</BitWidth>
  502. <Access>R</Access>
  503. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  504. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  505. </Bit>
  506. </AssignedBits>
  507. </Field>
  508. <Field>
  509. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  510. <AssignedBits>
  511. <Bit>
  512. <Name>NRST_STDBY</Name>
  513. <Description>Core domain Standby entry reset option status bit.</Description>
  514. <BitOffset>0x7</BitOffset>
  515. <BitWidth>0x1</BitWidth>
  516. <Access>W</Access>
  517. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  518. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  519. </Bit>
  520. </AssignedBits>
  521. </Field>
  522. </Category>
  523. </Bank>
  524. <Bank interface="JTAG_SWD">
  525. <Parameters address="0x40022070" name="Bank 2" size="0x8"/>
  526. <Category>
  527. <Name>User Configuration 2</Name>
  528. <Field>
  529. <Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
  530. <AssignedBits>
  531. <Bit>
  532. <Name>SRAM1_ECC</Name>
  533. <Description>ECC in SRAM1 region configuration bit</Description>
  534. <BitOffset>0xA</BitOffset>
  535. <BitWidth>0x1</BitWidth>
  536. <Access>R</Access>
  537. <Values>
  538. <Val value="0x0">SRAM1 ECC check enabled </Val>
  539. <Val value="0x1">SRAM1 ECC check disabled</Val>
  540. </Values>
  541. </Bit>
  542. <Bit>
  543. <Name>SRAM1_RST</Name>
  544. <Description>SRAM1 erase upon system reset</Description>
  545. <BitOffset>0x9</BitOffset>
  546. <BitWidth>0x1</BitWidth>
  547. <Access>R</Access>
  548. <Values>
  549. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  550. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  551. </Values>
  552. </Bit>
  553. <Bit>
  554. <Name>SRAM2_ECC</Name>
  555. <Description>ECC in SRAM2 region configuration bit</Description>
  556. <BitOffset>0x6</BitOffset>
  557. <BitWidth>0x1</BitWidth>
  558. <Access>R</Access>
  559. <Values>
  560. <Val value="0x0">SRAM2 ECC check enabled </Val>
  561. <Val value="0x1">SRAM2 ECC check disabled</Val>
  562. </Values>
  563. </Bit>
  564. <Bit>
  565. <Name>BKPRAM_ECC</Name>
  566. <Description>ECC in BKPRAM region configuration bit</Description>
  567. <BitOffset>0x4</BitOffset>
  568. <BitWidth>0x1</BitWidth>
  569. <Access>R</Access>
  570. <Values>
  571. <Val value="0x0">BKPRAM ECC check enabled </Val>
  572. <Val value="0x1">BKPRAM ECC check disabled</Val>
  573. </Values>
  574. </Bit>
  575. <Bit>
  576. <Name>SRAM2_RST</Name>
  577. <Description>SRAM2 erase when system reset</Description>
  578. <BitOffset>0x3</BitOffset>
  579. <BitWidth>0x1</BitWidth>
  580. <Access>R</Access>
  581. <Values>
  582. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  583. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  584. </Values>
  585. </Bit>
  586. </AssignedBits>
  587. </Field>
  588. <Field>
  589. <Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
  590. <AssignedBits>
  591. <Bit>
  592. <Name>SRAM1_ECC</Name>
  593. <Description>ECC in SRAM1 region configuration bit</Description>
  594. <BitOffset>0xA</BitOffset>
  595. <BitWidth>0x1</BitWidth>
  596. <Access>W</Access>
  597. <Values>
  598. <Val value="0x0">SRAM1 ECC check enabled </Val>
  599. <Val value="0x1">SRAM1 ECC check disabled</Val>
  600. </Values>
  601. </Bit>
  602. <Bit>
  603. <Name>SRAM1_RST</Name>
  604. <Description>SRAM1 erase upon system reset</Description>
  605. <BitOffset>0x9</BitOffset>
  606. <BitWidth>0x1</BitWidth>
  607. <Access>W</Access>
  608. <Values>
  609. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  610. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  611. </Values>
  612. </Bit>
  613. <Bit>
  614. <Name>SRAM2_ECC</Name>
  615. <Description>ECC in SRAM2 region configuration bit</Description>
  616. <BitOffset>0x6</BitOffset>
  617. <BitWidth>0x1</BitWidth>
  618. <Access>W</Access>
  619. <Values>
  620. <Val value="0x0">SRAM2 ECC check enabled </Val>
  621. <Val value="0x1">SRAM2 ECC check disabled</Val>
  622. </Values>
  623. </Bit>
  624. <Bit>
  625. <Name>BKPRAM_ECC</Name>
  626. <Description>ECC in BKPRAM region configuration bit</Description>
  627. <BitOffset>0x4</BitOffset>
  628. <BitWidth>0x1</BitWidth>
  629. <Access>W</Access>
  630. <Values>
  631. <Val value="0x0">BKPRAM ECC check enabled </Val>
  632. <Val value="0x1">BKPRAM ECC check disabled</Val>
  633. </Values>
  634. </Bit>
  635. <Bit>
  636. <Name>SRAM2_RST</Name>
  637. <Description>SRAM2 erase when system reset</Description>
  638. <BitOffset>0x3</BitOffset>
  639. <BitWidth>0x1</BitWidth>
  640. <Access>W</Access>
  641. <Values>
  642. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  643. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  644. </Values>
  645. </Bit>
  646. </AssignedBits>
  647. </Field>
  648. </Category>
  649. </Bank>
  650. <Bank interface="JTAG_SWD">
  651. <Parameters address="0x40022080" name="Bank 3" size="0x8"/>
  652. <Category>
  653. <Name>Boot Configuration</Name>
  654. <Field>
  655. <Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
  656. <AssignedBits>
  657. <Bit>
  658. <Name>NSBOOTADD</Name>
  659. <Description>Unique Boot Entry Address</Description>
  660. <BitOffset>0x8</BitOffset>
  661. <BitWidth>0x18</BitWidth>
  662. <Access>R</Access>
  663. <Equation multiplier="0x100" offset="0x00000000"/>
  664. </Bit>
  665. <Bit>
  666. <Name>NSBOOT_LOCK</Name>
  667. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  668. <BitOffset>0x0</BitOffset>
  669. <BitWidth>0x8</BitWidth>
  670. <Access>R</Access>
  671. <Values>
  672. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  673. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  674. </Values>
  675. </Bit>
  676. </AssignedBits>
  677. </Field>
  678. <Field>
  679. <Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
  680. <AssignedBits>
  681. <Bit>
  682. <Name>NSBOOTADD</Name>
  683. <Description>Unique Boot Entry Address</Description>
  684. <BitOffset>0x8</BitOffset>
  685. <BitWidth>0x18</BitWidth>
  686. <Access>W</Access>
  687. <Equation multiplier="0x100" offset="0x00000000"/>
  688. </Bit>
  689. <Bit>
  690. <Name>NSBOOT_LOCK</Name>
  691. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  692. <BitOffset>0x0</BitOffset>
  693. <BitWidth>0x8</BitWidth>
  694. <Access>W</Access>
  695. <Values>
  696. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  697. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  698. </Values>
  699. </Bit>
  700. </AssignedBits>
  701. </Field>
  702. </Category>
  703. </Bank>
  704. <Bank interface="JTAG_SWD">
  705. <Parameters address="0x400220E8" name="Bank 4" size="0x8"/>
  706. <Category>
  707. <Name>Write sector group protection 1</Name>
  708. <Field>
  709. <Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
  710. <AssignedBits>
  711. <Bit>
  712. <Name>WRPSGn1</Name>
  713. <Description>Bank 1 sector group protection option status byte</Description>
  714. <BitOffset>0x0</BitOffset>
  715. <BitWidth>0x8</BitWidth>
  716. <Access>R</Access>
  717. <Equation multiplier="0x2000" offset="0x08000000"/>
  718. </Bit>
  719. </AssignedBits>
  720. </Field>
  721. <Field>
  722. <Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
  723. <AssignedBits>
  724. <Bit>
  725. <Name>WRPSGn1</Name>
  726. <Description>Bank 1 sector group protection option status byte</Description>
  727. <BitOffset>0x0</BitOffset>
  728. <BitWidth>0x8</BitWidth>
  729. <Access>W</Access>
  730. <Equation multiplier="0x2000" offset="0x08000000"/>
  731. </Bit>
  732. </AssignedBits>
  733. </Field>
  734. </Category>
  735. </Bank>
  736. <Bank interface="JTAG_SWD">
  737. <Parameters address="0x400221E8" name="Bank 5" size="0x8"/>
  738. <Category>
  739. <Name>Write sector group protection 2</Name>
  740. <Field>
  741. <Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
  742. <AssignedBits>
  743. <Bit>
  744. <Name>WRPSGn2</Name>
  745. <Description>Bank 2 sector group protection option status byte</Description>
  746. <BitOffset>0x0</BitOffset>
  747. <BitWidth>0x8</BitWidth>
  748. <Access>R</Access>
  749. <Equation multiplier="0x2000" offset="0x08010000"/>
  750. </Bit>
  751. </AssignedBits>
  752. </Field>
  753. <Field>
  754. <Parameters address="0x400221EC" name="FLASH_WRP2BR" size="0x4"/>
  755. <AssignedBits>
  756. <Bit>
  757. <Name>WRPSGn2</Name>
  758. <Description>Bank 2 sector group protection option status byte</Description>
  759. <BitOffset>0x0</BitOffset>
  760. <BitWidth>0x8</BitWidth>
  761. <Access>W</Access>
  762. <Equation multiplier="0x2000" offset="0x08010000"/>
  763. </Bit>
  764. </AssignedBits>
  765. </Field>
  766. </Category>
  767. </Bank>
  768. <Bank interface="JTAG_SWD">
  769. <Parameters address="0x40022090" name="Bank 6" size="0x8"/>
  770. <Category>
  771. <Name>OTP write protection</Name>
  772. <Field>
  773. <Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
  774. <AssignedBits>
  775. <Bit>
  776. <Name>LOCKBL</Name>
  777. <Description>OTP Block Lock</Description>
  778. <BitOffset>0x0</BitOffset>
  779. <BitWidth>0x20</BitWidth>
  780. <Access>R</Access>
  781. <Equation multiplier="0x2000" offset="0x00000000"/>
  782. </Bit>
  783. </AssignedBits>
  784. </Field>
  785. <Field>
  786. <Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
  787. <AssignedBits>
  788. <Bit>
  789. <Name>LOCKBL</Name>
  790. <Description>OTP Block Lock</Description>
  791. <BitOffset>0x0</BitOffset>
  792. <BitWidth>0x20</BitWidth>
  793. <Access>W</Access>
  794. <Equation multiplier="0x2000" offset="0x00000000"/>
  795. </Bit>
  796. </AssignedBits>
  797. </Field>
  798. </Category>
  799. </Bank>
  800. <Bank interface="JTAG_SWD">
  801. <Parameters address="0x400220F8" name="Bank 10" size="0x8"/>
  802. <Category>
  803. <Name>Flash HDP bank 1</Name>
  804. <Field>
  805. <Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
  806. <AssignedBits>
  807. <Bit>
  808. <Name>HDP1_STRT</Name>
  809. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  810. <BitOffset>0x0</BitOffset>
  811. <BitWidth>0x3</BitWidth>
  812. <Access>R</Access>
  813. <Equation multiplier="0x2000" offset="0x00000000"/>
  814. </Bit>
  815. <Bit>
  816. <Name>HDP1_END</Name>
  817. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  818. <BitOffset>0x10</BitOffset>
  819. <BitWidth>0x3</BitWidth>
  820. <Access>R</Access>
  821. <Equation multiplier="0x2000" offset="0x00000000"/>
  822. </Bit>
  823. </AssignedBits>
  824. </Field>
  825. <Field>
  826. <Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
  827. <AssignedBits>
  828. <Bit>
  829. <Name>HDP1_STRT</Name>
  830. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  831. <BitOffset>0x0</BitOffset>
  832. <BitWidth>0x3</BitWidth>
  833. <Access>W</Access>
  834. <Equation multiplier="0x2000" offset="0x00000000"/>
  835. </Bit>
  836. <Bit>
  837. <Name>HDP1_END</Name>
  838. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  839. <BitOffset>0x10</BitOffset>
  840. <BitWidth>0x3</BitWidth>
  841. <Access>W</Access>
  842. <Equation multiplier="0x2000" offset="0x00000000"/>
  843. </Bit>
  844. </AssignedBits>
  845. </Field>
  846. </Category>
  847. </Bank>
  848. <Bank interface="JTAG_SWD">
  849. <Parameters address="0x400221F8" name="Bank 11" size="0x8"/>
  850. <Category>
  851. <Name>Flash HDP bank 2</Name>
  852. <Field>
  853. <Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
  854. <AssignedBits>
  855. <Bit>
  856. <Name>HDP2_STRT</Name>
  857. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  858. <BitOffset>0x0</BitOffset>
  859. <BitWidth>0x3</BitWidth>
  860. <Access>R</Access>
  861. <Equation multiplier="0x2000" offset="0x00000000"/>
  862. </Bit>
  863. <Bit>
  864. <Name>HDP2_END</Name>
  865. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  866. <BitOffset>0x10</BitOffset>
  867. <BitWidth>0x3</BitWidth>
  868. <Access>R</Access>
  869. <Equation multiplier="0x2000" offset="0x00000000"/>
  870. </Bit>
  871. </AssignedBits>
  872. </Field>
  873. <Field>
  874. <Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
  875. <AssignedBits>
  876. <Bit>
  877. <Name>HDP2_STRT</Name>
  878. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  879. <BitOffset>0x0</BitOffset>
  880. <BitWidth>0x3</BitWidth>
  881. <Access>W</Access>
  882. <Equation multiplier="0x2000" offset="0x00000000"/>
  883. </Bit>
  884. <Bit>
  885. <Name>HDP2_END</Name>
  886. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  887. <BitOffset>0x10</BitOffset>
  888. <BitWidth>0x3</BitWidth>
  889. <Access>W</Access>
  890. <Equation multiplier="0x2000" offset="0x00000000"/>
  891. </Bit>
  892. </AssignedBits>
  893. </Field>
  894. </Category>
  895. </Bank>
  896. </Configuration>
  897. <Configuration config="1">
  898. <Bank interface="JTAG_SWD">
  899. <Parameters address="0x50022050" name="Bank 1" size="0x70"/>
  900. <Category>
  901. <Name>Product state</Name>
  902. <Field>
  903. <Parameters address="0x50022050" name="CUR" size="0x4"/>
  904. <AssignedBits>
  905. <Bit>
  906. <Name>PRODUCT_STATE</Name>
  907. <Description>Life state code.</Description>
  908. <BitOffset>0x8</BitOffset>
  909. <BitWidth>0x8</BitWidth>
  910. <Access>R</Access>
  911. <Values>
  912. <Val value="0xED">Open</Val>
  913. <Val value="0x17">Provisioning</Val>
  914. <Val value="0x2E">Provisioned</Val>
  915. <Val value="0x72">Closed</Val>
  916. <Val value="0x5C">Locked</Val>
  917. <Val value="0x9A">Regression</Val>
  918. </Values>
  919. </Bit>
  920. </AssignedBits>
  921. </Field>
  922. <Field>
  923. <Parameters address="0x50022054" name="PRG" size="0x4"/>
  924. <AssignedBits>
  925. <Bit>
  926. <Name>PRODUCT_STATE</Name>
  927. <Description>Life state code.</Description>
  928. <BitOffset>0x8</BitOffset>
  929. <BitWidth>0x8</BitWidth>
  930. <Access>W</Access>
  931. <Values>
  932. <Val value="0xED">Open</Val>
  933. <Val value="0x17">Provisioning</Val>
  934. <Val value="0x2E">Provisioned</Val>
  935. <Val value="0x72">Closed</Val>
  936. <Val value="0x5C">Locked</Val>
  937. <Val value="0x9A">Regression</Val>
  938. </Values>
  939. </Bit>
  940. </AssignedBits>
  941. </Field>
  942. </Category>
  943. <Category>
  944. <Name>BOR Level</Name>
  945. <Field>
  946. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  947. <AssignedBits>
  948. <Bit>
  949. <Name>BORH_EN</Name>
  950. <Description>Brownout high enable configuration bit</Description>
  951. <BitOffset>0x2</BitOffset>
  952. <BitWidth>0x1</BitWidth>
  953. <Access>R</Access>
  954. <Val value="0x0">disabled</Val>
  955. <Val value="0x1">enabled</Val>
  956. </Bit>
  957. </AssignedBits>
  958. </Field>
  959. <Field>
  960. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  961. <AssignedBits>
  962. <Bit>
  963. <Name>BORH_EN</Name>
  964. <Description>Brownout high enable configuration bit</Description>
  965. <BitOffset>0x2</BitOffset>
  966. <BitWidth>0x1</BitWidth>
  967. <Access>W</Access>
  968. <Val value="0x0">disabled</Val>
  969. <Val value="0x1">enabled</Val>
  970. </Bit>
  971. </AssignedBits>
  972. </Field>
  973. <Field>
  974. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  975. <AssignedBits>
  976. <Bit>
  977. <Name>BOR_LEV</Name>
  978. <Description>Brownout level option status bit.</Description>
  979. <BitOffset>0x0</BitOffset>
  980. <BitWidth>0x2</BitWidth>
  981. <Access>R</Access>
  982. <Values>
  983. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  984. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  985. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  986. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  987. </Values>
  988. </Bit>
  989. </AssignedBits>
  990. </Field>
  991. <Field>
  992. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  993. <AssignedBits>
  994. <Bit>
  995. <Name>BOR_LEV</Name>
  996. <Description>Brownout level option status bit.</Description>
  997. <BitOffset>0x0</BitOffset>
  998. <BitWidth>0x2</BitWidth>
  999. <Access>W</Access>
  1000. <Values>
  1001. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1002. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1003. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1004. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1005. </Values>
  1006. </Bit>
  1007. </AssignedBits>
  1008. </Field>
  1009. </Category>
  1010. <Category>
  1011. <Name>User Configuration</Name>
  1012. <Field>
  1013. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1014. <AssignedBits>
  1015. <Bit>
  1016. <Name>IO_VDDIO2_HSLV</Name>
  1017. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  1018. <BitOffset>0x11</BitOffset>
  1019. <BitWidth>0x1</BitWidth>
  1020. <Access>R</Access>
  1021. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  1022. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  1023. </Bit>
  1024. </AssignedBits>
  1025. </Field>
  1026. <Field>
  1027. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1028. <AssignedBits>
  1029. <Bit>
  1030. <Name>IO_VDDIO2_HSLV</Name>
  1031. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  1032. <BitOffset>0x11</BitOffset>
  1033. <BitWidth>0x1</BitWidth>
  1034. <Access>W</Access>
  1035. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  1036. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  1037. </Bit>
  1038. </AssignedBits>
  1039. </Field>
  1040. <Field>
  1041. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1042. <AssignedBits>
  1043. <Bit>
  1044. <Name>IO_VDD_HSLV</Name>
  1045. <Description>High-speed IO at low VDD voltage status bit.</Description>
  1046. <BitOffset>0x10</BitOffset>
  1047. <BitWidth>0x1</BitWidth>
  1048. <Access>R</Access>
  1049. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  1050. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  1051. </Bit>
  1052. </AssignedBits>
  1053. </Field>
  1054. <Field>
  1055. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1056. <AssignedBits>
  1057. <Bit>
  1058. <Name>IO_VDD_HSLV</Name>
  1059. <Description>High-speed IO at low VDD voltage status bit.</Description>
  1060. <BitOffset>0x10</BitOffset>
  1061. <BitWidth>0x1</BitWidth>
  1062. <Access>W</Access>
  1063. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  1064. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  1065. </Bit>
  1066. </AssignedBits>
  1067. </Field>
  1068. <Field>
  1069. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1070. <AssignedBits>
  1071. <Bit>
  1072. <Name>IWDG_STOP</Name>
  1073. <Description>Stop mode freeze option status bit.</Description>
  1074. <BitOffset>0x14</BitOffset>
  1075. <BitWidth>0x1</BitWidth>
  1076. <Access>R</Access>
  1077. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1078. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1079. </Bit>
  1080. </AssignedBits>
  1081. </Field>
  1082. <Field>
  1083. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1084. <AssignedBits>
  1085. <Bit>
  1086. <Name>IWDG_STOP</Name>
  1087. <Description>Stop mode freeze option status bit.</Description>
  1088. <BitOffset>0x14</BitOffset>
  1089. <BitWidth>0x1</BitWidth>
  1090. <Access>W</Access>
  1091. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1092. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1093. </Bit>
  1094. </AssignedBits>
  1095. </Field>
  1096. <Field>
  1097. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1098. <AssignedBits>
  1099. <Bit>
  1100. <Name>IWDG_STDBY</Name>
  1101. <Description>Standby mode freeze option status bit.</Description>
  1102. <BitOffset>0x15</BitOffset>
  1103. <BitWidth>0x1</BitWidth>
  1104. <Access>R</Access>
  1105. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1106. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  1107. </Bit>
  1108. </AssignedBits>
  1109. </Field>
  1110. <Field>
  1111. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1112. <AssignedBits>
  1113. <Bit>
  1114. <Name>IWDG_STDBY</Name>
  1115. <Description>Standby mode freeze option status bit.</Description>
  1116. <BitOffset>0x15</BitOffset>
  1117. <BitWidth>0x1</BitWidth>
  1118. <Access>W</Access>
  1119. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1120. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  1121. </Bit>
  1122. </AssignedBits>
  1123. </Field>
  1124. <Field>
  1125. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1126. <AssignedBits>
  1127. <Bit>
  1128. <Name>SWAP_BANK</Name>
  1129. <Description>Bank swapping option status bit.</Description>
  1130. <BitOffset>0x1F</BitOffset>
  1131. <BitWidth>0x1</BitWidth>
  1132. <Access>R</Access>
  1133. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1134. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1135. </Bit>
  1136. </AssignedBits>
  1137. </Field>
  1138. <Field>
  1139. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1140. <AssignedBits>
  1141. <Bit>
  1142. <Name>SWAP_BANK</Name>
  1143. <Description>Bank swapping option status bit.</Description>
  1144. <BitOffset>0x1F</BitOffset>
  1145. <BitWidth>0x1</BitWidth>
  1146. <Access>W</Access>
  1147. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1148. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1149. </Bit>
  1150. </AssignedBits>
  1151. </Field>
  1152. <Field>
  1153. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1154. <AssignedBits>
  1155. <Bit>
  1156. <Name>IWDG_SW</Name>
  1157. <Description>IWDG control mode option status bit.</Description>
  1158. <BitOffset>0x3</BitOffset>
  1159. <BitWidth>0x1</BitWidth>
  1160. <Access>R</Access>
  1161. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1162. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1163. </Bit>
  1164. </AssignedBits>
  1165. </Field>
  1166. <Field>
  1167. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1168. <AssignedBits>
  1169. <Bit>
  1170. <Name>IWDG_SW</Name>
  1171. <Description>IWDG control mode option status bit.</Description>
  1172. <BitOffset>0x3</BitOffset>
  1173. <BitWidth>0x1</BitWidth>
  1174. <Access>W</Access>
  1175. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1176. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1177. </Bit>
  1178. </AssignedBits>
  1179. </Field>
  1180. <Field>
  1181. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1182. <AssignedBits>
  1183. <Bit>
  1184. <Name>WWDG_SW</Name>
  1185. <Description>WWDG control mode option status bit.</Description>
  1186. <BitOffset>0x4</BitOffset>
  1187. <BitWidth>0x1</BitWidth>
  1188. <Access>R</Access>
  1189. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1190. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1191. </Bit>
  1192. </AssignedBits>
  1193. </Field>
  1194. <Field>
  1195. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1196. <AssignedBits>
  1197. <Bit>
  1198. <Name>WWDG_SW</Name>
  1199. <Description>WWDG control mode option status bit.</Description>
  1200. <BitOffset>0x4</BitOffset>
  1201. <BitWidth>0x1</BitWidth>
  1202. <Access>W</Access>
  1203. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1204. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1205. </Bit>
  1206. </AssignedBits>
  1207. </Field>
  1208. <Field>
  1209. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1210. <AssignedBits>
  1211. <Bit>
  1212. <Name>NRST_STOP</Name>
  1213. <Description>Core domain Stop entry reset option status bit.</Description>
  1214. <BitOffset>0x6</BitOffset>
  1215. <BitWidth>0x1</BitWidth>
  1216. <Access>R</Access>
  1217. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  1218. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  1219. </Bit>
  1220. </AssignedBits>
  1221. </Field>
  1222. <Field>
  1223. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1224. <AssignedBits>
  1225. <Bit>
  1226. <Name>NRST_STOP</Name>
  1227. <Description>Core domain Stop entry reset option status bit.</Description>
  1228. <BitOffset>0x6</BitOffset>
  1229. <BitWidth>0x1</BitWidth>
  1230. <Access>W</Access>
  1231. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  1232. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  1233. </Bit>
  1234. </AssignedBits>
  1235. </Field>
  1236. <Field>
  1237. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1238. <AssignedBits>
  1239. <Bit>
  1240. <Name>NRST_STDBY</Name>
  1241. <Description>Core domain Standby entry reset option status bit.</Description>
  1242. <BitOffset>0x7</BitOffset>
  1243. <BitWidth>0x1</BitWidth>
  1244. <Access>R</Access>
  1245. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1246. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1247. </Bit>
  1248. </AssignedBits>
  1249. </Field>
  1250. <Field>
  1251. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1252. <AssignedBits>
  1253. <Bit>
  1254. <Name>NRST_STDBY</Name>
  1255. <Description>Core domain Standby entry reset option status bit.</Description>
  1256. <BitOffset>0x7</BitOffset>
  1257. <BitWidth>0x1</BitWidth>
  1258. <Access>W</Access>
  1259. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1260. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1261. </Bit>
  1262. </AssignedBits>
  1263. </Field>
  1264. </Category>
  1265. </Bank>
  1266. <Bank interface="JTAG_SWD">
  1267. <Parameters address="0x50022070" name="Bank 2" size="0x10"/>
  1268. <Category>
  1269. <Name>User Configuration 2</Name>
  1270. <Field>
  1271. <Parameters address="0x50022070" name="FLASH_WRP1AR" size="0x4"/>
  1272. <AssignedBits>
  1273. <Bit>
  1274. <Name>SRAM1_ECC</Name>
  1275. <Description>ECC in SRAM1 region configuration bit</Description>
  1276. <BitOffset>0xA</BitOffset>
  1277. <BitWidth>0x1</BitWidth>
  1278. <Access>R</Access>
  1279. <Values>
  1280. <Val value="0x0">SRAM1 ECC check enabled </Val>
  1281. <Val value="0x1">SRAM1 ECC check disabled</Val>
  1282. </Values>
  1283. </Bit>
  1284. <Bit>
  1285. <Name>SRAM1_RST</Name>
  1286. <Description>SRAM1 erase upon system reset</Description>
  1287. <BitOffset>0x9</BitOffset>
  1288. <BitWidth>0x1</BitWidth>
  1289. <Access>R</Access>
  1290. <Values>
  1291. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  1292. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  1293. </Values>
  1294. </Bit>
  1295. <Bit>
  1296. <Name>SRAM2_ECC</Name>
  1297. <Description>ECC in SRAM2 region configuration bit</Description>
  1298. <BitOffset>0x6</BitOffset>
  1299. <BitWidth>0x1</BitWidth>
  1300. <Access>R</Access>
  1301. <Values>
  1302. <Val value="0x0">SRAM2 ECC check enabled </Val>
  1303. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1304. </Values>
  1305. </Bit>
  1306. <Bit>
  1307. <Name>BKPRAM_ECC</Name>
  1308. <Description>ECC in BKPRAM region configuration bit</Description>
  1309. <BitOffset>0x4</BitOffset>
  1310. <BitWidth>0x1</BitWidth>
  1311. <Access>R</Access>
  1312. <Values>
  1313. <Val value="0x0">BKPRAM ECC check enabled </Val>
  1314. <Val value="0x1">BKPRAM ECC check disabled</Val>
  1315. </Values>
  1316. </Bit>
  1317. <Bit>
  1318. <Name>SRAM2_RST</Name>
  1319. <Description>SRAM2 erase when system reset</Description>
  1320. <BitOffset>0x3</BitOffset>
  1321. <BitWidth>0x1</BitWidth>
  1322. <Access>R</Access>
  1323. <Values>
  1324. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  1325. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  1326. </Values>
  1327. </Bit>
  1328. </AssignedBits>
  1329. </Field>
  1330. <Field>
  1331. <Parameters address="0x50022074" name="FLASH_WRP1AR" size="0x4"/>
  1332. <AssignedBits>
  1333. <Bit>
  1334. <Name>SRAM1_ECC</Name>
  1335. <Description>ECC in SRAM1 region configuration bit</Description>
  1336. <BitOffset>0xA</BitOffset>
  1337. <BitWidth>0x1</BitWidth>
  1338. <Access>W</Access>
  1339. <Values>
  1340. <Val value="0x0">SRAM1 ECC check enabled </Val>
  1341. <Val value="0x1">SRAM1 ECC check disabled</Val>
  1342. </Values>
  1343. </Bit>
  1344. <Bit>
  1345. <Name>SRAM1_RST</Name>
  1346. <Description>SRAM1 erase upon system reset</Description>
  1347. <BitOffset>0x9</BitOffset>
  1348. <BitWidth>0x1</BitWidth>
  1349. <Access>W</Access>
  1350. <Values>
  1351. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  1352. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  1353. </Values>
  1354. </Bit>
  1355. <Bit>
  1356. <Name>SRAM2_ECC</Name>
  1357. <Description>ECC in SRAM2 region configuration bit</Description>
  1358. <BitOffset>0x6</BitOffset>
  1359. <BitWidth>0x1</BitWidth>
  1360. <Access>W</Access>
  1361. <Values>
  1362. <Val value="0x0">SRAM2 ECC check enabled </Val>
  1363. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1364. </Values>
  1365. </Bit>
  1366. <Bit>
  1367. <Name>BKPRAM_ECC</Name>
  1368. <Description>ECC in BKPRAM region configuration bit</Description>
  1369. <BitOffset>0x4</BitOffset>
  1370. <BitWidth>0x1</BitWidth>
  1371. <Access>W</Access>
  1372. <Values>
  1373. <Val value="0x0">BKPRAM ECC check enabled </Val>
  1374. <Val value="0x1">BKPRAM ECC check disabled</Val>
  1375. </Values>
  1376. </Bit>
  1377. <Bit>
  1378. <Name>SRAM2_RST</Name>
  1379. <Description>SRAM2 erase when system reset</Description>
  1380. <BitOffset>0x3</BitOffset>
  1381. <BitWidth>0x1</BitWidth>
  1382. <Access>W</Access>
  1383. <Values>
  1384. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  1385. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  1386. </Values>
  1387. </Bit>
  1388. </AssignedBits>
  1389. </Field>
  1390. </Category>
  1391. </Bank>
  1392. <Bank interface="JTAG_SWD">
  1393. <Parameters address="0x50022080" name="Bank 3" size="0x8"/>
  1394. <Category>
  1395. <Name>Boot Configuration</Name>
  1396. <Field>
  1397. <Parameters address="0x50022080" name="FLASH_WRP2AR" size="0x4"/>
  1398. <AssignedBits>
  1399. <Bit>
  1400. <Name>NSBOOTADD</Name>
  1401. <Description>Unique Boot Entry Address</Description>
  1402. <BitOffset>0x8</BitOffset>
  1403. <BitWidth>0x18</BitWidth>
  1404. <Access>R</Access>
  1405. <Equation multiplier="0x100" offset="0x0"/>
  1406. </Bit>
  1407. <Bit>
  1408. <Name>NSBOOT_LOCK</Name>
  1409. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  1410. <BitOffset>0x0</BitOffset>
  1411. <BitWidth>0x8</BitWidth>
  1412. <Access>R</Access>
  1413. <Values>
  1414. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  1415. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  1416. </Values>
  1417. </Bit>
  1418. </AssignedBits>
  1419. </Field>
  1420. <Field>
  1421. <Parameters address="0x50022084" name="FLASH_WRP2AR" size="0x4"/>
  1422. <AssignedBits>
  1423. <Bit>
  1424. <Name>NSBOOTADD</Name>
  1425. <Description>Unique Boot Entry Address</Description>
  1426. <BitOffset>0x8</BitOffset>
  1427. <BitWidth>0x18</BitWidth>
  1428. <Access>W</Access>
  1429. <Equation multiplier="0x100" offset="0x00000000"/>
  1430. </Bit>
  1431. <Bit>
  1432. <Name>NSBOOT_LOCK</Name>
  1433. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  1434. <BitOffset>0x0</BitOffset>
  1435. <BitWidth>0x8</BitWidth>
  1436. <Access>W</Access>
  1437. <Values>
  1438. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  1439. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  1440. </Values>
  1441. </Bit>
  1442. </AssignedBits>
  1443. </Field>
  1444. </Category>
  1445. </Bank>
  1446. <Bank interface="JTAG_SWD">
  1447. <Parameters address="0x500220E8" name="Bank 4" size="0x8"/>
  1448. <Category>
  1449. <Name>Write sector group protection 1</Name>
  1450. <Field>
  1451. <Parameters address="0x500220E8" name="FLASH_WRP2BR" size="0x4"/>
  1452. <AssignedBits>
  1453. <Bit>
  1454. <Name>WRPSGn1</Name>
  1455. <Description>Bank 1 sector group protection option status byte</Description>
  1456. <BitOffset>0x0</BitOffset>
  1457. <BitWidth>0x8</BitWidth>
  1458. <Access>R</Access>
  1459. <Equation multiplier="0x2000" offset="0x08000000"/>
  1460. </Bit>
  1461. </AssignedBits>
  1462. </Field>
  1463. <Field>
  1464. <Parameters address="0x500220EC" name="FLASH_WRP2BR" size="0x4"/>
  1465. <AssignedBits>
  1466. <Bit>
  1467. <Name>WRPSGn1</Name>
  1468. <Description>Bank 1 sector group protection option status byte</Description>
  1469. <BitOffset>0x0</BitOffset>
  1470. <BitWidth>0x8</BitWidth>
  1471. <Access>W</Access>
  1472. <Equation multiplier="0x2000" offset="0x08000000"/>
  1473. </Bit>
  1474. </AssignedBits>
  1475. </Field>
  1476. </Category>
  1477. </Bank>
  1478. <Bank interface="JTAG_SWD">
  1479. <Parameters address="0x500221E8" name="Bank 5" size="0x8"/>
  1480. <Category>
  1481. <Name>Write sector group protection 2</Name>
  1482. <Field>
  1483. <Parameters address="0x500221E8" name="FLASH_WRP2BR" size="0x4"/>
  1484. <AssignedBits>
  1485. <Bit>
  1486. <Name>WRPSGn2</Name>
  1487. <Description>Bank 2 sector group protection option status byte</Description>
  1488. <BitOffset>0x0</BitOffset>
  1489. <BitWidth>0x8</BitWidth>
  1490. <Access>R</Access>
  1491. <Equation multiplier="0x2000" offset="0x08000000"/>
  1492. </Bit>
  1493. </AssignedBits>
  1494. </Field>
  1495. <Field>
  1496. <Parameters address="0x500221EC" name="FLASH_WRP2BR" size="0x4"/>
  1497. <AssignedBits>
  1498. <Bit>
  1499. <Name>WRPSGn2</Name>
  1500. <Description>Bank 2 sector group protection option status byte</Description>
  1501. <BitOffset>0x0</BitOffset>
  1502. <BitWidth>0x8</BitWidth>
  1503. <Access>W</Access>
  1504. <Equation multiplier="0x2000" offset="0x08000000"/>
  1505. </Bit>
  1506. </AssignedBits>
  1507. </Field>
  1508. </Category>
  1509. </Bank>
  1510. <Bank interface="JTAG_SWD">
  1511. <Parameters address="0x50022090" name="Bank 6" size="0x8"/>
  1512. <Category>
  1513. <Name>OTP write protection</Name>
  1514. <Field>
  1515. <Parameters address="0x50022090" name="FLASH_WRP2BR" size="0x4"/>
  1516. <AssignedBits>
  1517. <Bit>
  1518. <Name>LOCKBL</Name>
  1519. <Description>OTP Block Lock</Description>
  1520. <BitOffset>0x0</BitOffset>
  1521. <BitWidth>0x20</BitWidth>
  1522. <Access>R</Access>
  1523. <Equation multiplier="0x2000" offset="0x00000000"/>
  1524. </Bit>
  1525. </AssignedBits>
  1526. </Field>
  1527. <Field>
  1528. <Parameters address="0x50022094" name="FLASH_WRP2BR" size="0x4"/>
  1529. <AssignedBits>
  1530. <Bit>
  1531. <Name>LOCKBL</Name>
  1532. <Description>OTP Block Lock</Description>
  1533. <BitOffset>0x0</BitOffset>
  1534. <BitWidth>0x20</BitWidth>
  1535. <Access>W</Access>
  1536. <Equation multiplier="0x2000" offset="0x00000000"/>
  1537. </Bit>
  1538. </AssignedBits>
  1539. </Field>
  1540. </Category>
  1541. </Bank>
  1542. <Bank interface="JTAG_SWD">
  1543. <Parameters address="0x500220F8" name="Bank 10" size="0x8"/>
  1544. <Category>
  1545. <Name>Flash HDP bank 1</Name>
  1546. <Field>
  1547. <Parameters address="0x500220F8" name="FLASH_WRP2BR" size="0x4"/>
  1548. <AssignedBits>
  1549. <Bit>
  1550. <Name>HDP1_STRT</Name>
  1551. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  1552. <BitOffset>0x0</BitOffset>
  1553. <BitWidth>0x3</BitWidth>
  1554. <Access>R</Access>
  1555. <Equation multiplier="0x2000" offset="0x00000000"/>
  1556. </Bit>
  1557. <Bit>
  1558. <Name>HDP1_END</Name>
  1559. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  1560. <BitOffset>0x10</BitOffset>
  1561. <BitWidth>0x3</BitWidth>
  1562. <Access>R</Access>
  1563. <Equation multiplier="0x2000" offset="0x00000000"/>
  1564. </Bit>
  1565. </AssignedBits>
  1566. </Field>
  1567. <Field>
  1568. <Parameters address="0x500220FC" name="FLASH_WRP2BR" size="0x4"/>
  1569. <AssignedBits>
  1570. <Bit>
  1571. <Name>HDP1_STRT</Name>
  1572. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  1573. <BitOffset>0x0</BitOffset>
  1574. <BitWidth>0x3</BitWidth>
  1575. <Access>W</Access>
  1576. <Equation multiplier="0x2000" offset="0x00000000"/>
  1577. </Bit>
  1578. <Bit>
  1579. <Name>HDP1_END</Name>
  1580. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  1581. <BitOffset>0x10</BitOffset>
  1582. <BitWidth>0x3</BitWidth>
  1583. <Access>W</Access>
  1584. <Equation multiplier="0x2000" offset="0x00000000"/>
  1585. </Bit>
  1586. </AssignedBits>
  1587. </Field>
  1588. </Category>
  1589. </Bank>
  1590. <Bank interface="JTAG_SWD">
  1591. <Parameters address="0x500221F8" name="Bank 11" size="0x8"/>
  1592. <Category>
  1593. <Name>Flash HDP bank 2</Name>
  1594. <Field>
  1595. <Parameters address="0x500221F8" name="FLASH_WRP2BR" size="0x4"/>
  1596. <AssignedBits>
  1597. <Bit>
  1598. <Name>HDP2_STRT</Name>
  1599. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  1600. <BitOffset>0x0</BitOffset>
  1601. <BitWidth>0x3</BitWidth>
  1602. <Access>R</Access>
  1603. <Equation multiplier="0x2000" offset="0x00000000"/>
  1604. </Bit>
  1605. <Bit>
  1606. <Name>HDP2_END</Name>
  1607. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  1608. <BitOffset>0x10</BitOffset>
  1609. <BitWidth>0x3</BitWidth>
  1610. <Access>R</Access>
  1611. <Equation multiplier="0x2000" offset="0x00000000"/>
  1612. </Bit>
  1613. </AssignedBits>
  1614. </Field>
  1615. <Field>
  1616. <Parameters address="0x500221FC" name="FLASH_WRP2BR" size="0x4"/>
  1617. <AssignedBits>
  1618. <Bit>
  1619. <Name>HDP2_STRT</Name>
  1620. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  1621. <BitOffset>0x0</BitOffset>
  1622. <BitWidth>0x3</BitWidth>
  1623. <Access>W</Access>
  1624. <Equation multiplier="0x2000" offset="0x00000000"/>
  1625. </Bit>
  1626. <Bit>
  1627. <Name>HDP2_END</Name>
  1628. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  1629. <BitOffset>0x10</BitOffset>
  1630. <BitWidth>0x3</BitWidth>
  1631. <Access>W</Access>
  1632. <Equation multiplier="0x2000" offset="0x00000000"/>
  1633. </Bit>
  1634. </AssignedBits>
  1635. </Field>
  1636. </Category>
  1637. </Bank>
  1638. </Configuration>
  1639. <Bank interface="Bootloader">
  1640. <Parameters address="0x40022050" name="Bank 1" size="0xB0"/>
  1641. <Category>
  1642. <Name>Product state</Name>
  1643. <Field>
  1644. <Parameters address="0x40022050" name="CUR" size="0x4"/>
  1645. <AssignedBits>
  1646. <Bit>
  1647. <Name>PRODUCT_STATE</Name>
  1648. <Description>Life state code.</Description>
  1649. <BitOffset>0x8</BitOffset>
  1650. <BitWidth>0x8</BitWidth>
  1651. <Access>R</Access>
  1652. <Values>
  1653. <Val value="0xED">Open</Val>
  1654. <Val value="0x17">Provisioning</Val>
  1655. <Val value="0x2E">Provisioned</Val>
  1656. <Val value="0x72">Closed</Val>
  1657. <Val value="0x5C">Locked</Val>
  1658. <Val value="0x9A">Regression</Val>
  1659. </Values>
  1660. </Bit>
  1661. </AssignedBits>
  1662. </Field>
  1663. <Field>
  1664. <Parameters address="0x40022054" name="PRG" size="0x4"/>
  1665. <AssignedBits>
  1666. <Bit>
  1667. <Name>PRODUCT_STATE</Name>
  1668. <Description>Life state code.</Description>
  1669. <BitOffset>0x8</BitOffset>
  1670. <BitWidth>0x8</BitWidth>
  1671. <Access>W</Access>
  1672. <Values>
  1673. <Val value="0xED">Open</Val>
  1674. <Val value="0x17">Provisioning</Val>
  1675. <Val value="0x2E">Provisioned</Val>
  1676. <Val value="0x72">Closed</Val>
  1677. <Val value="0x5C">Locked</Val>
  1678. <Val value="0x9A">Regression</Val>
  1679. </Values>
  1680. </Bit>
  1681. </AssignedBits>
  1682. </Field>
  1683. </Category>
  1684. <Category>
  1685. <Name>BOR Level</Name>
  1686. <Field>
  1687. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1688. <AssignedBits>
  1689. <Bit>
  1690. <Name>BORH_EN</Name>
  1691. <Description>Brownout high enable configuration bit</Description>
  1692. <BitOffset>0x2</BitOffset>
  1693. <BitWidth>0x1</BitWidth>
  1694. <Access>R</Access>
  1695. <Val value="0x0">disabled</Val>
  1696. <Val value="0x1">enabled</Val>
  1697. </Bit>
  1698. </AssignedBits>
  1699. </Field>
  1700. <Field>
  1701. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1702. <AssignedBits>
  1703. <Bit>
  1704. <Name>BORH_EN</Name>
  1705. <Description>Brownout high enable configuration bit</Description>
  1706. <BitOffset>0x2</BitOffset>
  1707. <BitWidth>0x1</BitWidth>
  1708. <Access>W</Access>
  1709. <Val value="0x0">disabled</Val>
  1710. <Val value="0x1">enabled</Val>
  1711. </Bit>
  1712. </AssignedBits>
  1713. </Field>
  1714. <Field>
  1715. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1716. <AssignedBits>
  1717. <Bit>
  1718. <Name>BOR_LEV</Name>
  1719. <Description>Brownout level option status bit.</Description>
  1720. <BitOffset>0x0</BitOffset>
  1721. <BitWidth>0x2</BitWidth>
  1722. <Access>R</Access>
  1723. <Values>
  1724. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1725. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1726. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1727. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1728. </Values>
  1729. </Bit>
  1730. </AssignedBits>
  1731. </Field>
  1732. <Field>
  1733. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1734. <AssignedBits>
  1735. <Bit>
  1736. <Name>BOR_LEV</Name>
  1737. <Description>Brownout level option status bit.</Description>
  1738. <BitOffset>0x0</BitOffset>
  1739. <BitWidth>0x2</BitWidth>
  1740. <Access>W</Access>
  1741. <Values>
  1742. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1743. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1744. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1745. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1746. </Values>
  1747. </Bit>
  1748. </AssignedBits>
  1749. </Field>
  1750. </Category>
  1751. <Category>
  1752. <Name>User Configuration</Name>
  1753. <Field>
  1754. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1755. <AssignedBits>
  1756. <Bit>
  1757. <Name>IO_VDDIO2_HSLV</Name>
  1758. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  1759. <BitOffset>0x11</BitOffset>
  1760. <BitWidth>0x1</BitWidth>
  1761. <Access>R</Access>
  1762. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  1763. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  1764. </Bit>
  1765. </AssignedBits>
  1766. </Field>
  1767. <Field>
  1768. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1769. <AssignedBits>
  1770. <Bit>
  1771. <Name>IO_VDDIO2_HSLV</Name>
  1772. <Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
  1773. <BitOffset>0x11</BitOffset>
  1774. <BitWidth>0x1</BitWidth>
  1775. <Access>W</Access>
  1776. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
  1777. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
  1778. </Bit>
  1779. </AssignedBits>
  1780. </Field>
  1781. <Field>
  1782. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1783. <AssignedBits>
  1784. <Bit>
  1785. <Name>IO_VDD_HSLV</Name>
  1786. <Description>High-speed IO at low VDD voltage status bit.</Description>
  1787. <BitOffset>0x10</BitOffset>
  1788. <BitWidth>0x1</BitWidth>
  1789. <Access>R</Access>
  1790. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  1791. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  1792. </Bit>
  1793. </AssignedBits>
  1794. </Field>
  1795. <Field>
  1796. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1797. <AssignedBits>
  1798. <Bit>
  1799. <Name>IO_VDD_HSLV</Name>
  1800. <Description>High-speed IO at low VDD voltage status bit.</Description>
  1801. <BitOffset>0x10</BitOffset>
  1802. <BitWidth>0x1</BitWidth>
  1803. <Access>W</Access>
  1804. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
  1805. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
  1806. </Bit>
  1807. </AssignedBits>
  1808. </Field>
  1809. <Field>
  1810. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1811. <AssignedBits>
  1812. <Bit>
  1813. <Name>IWDG_STDBY</Name>
  1814. <Description>Standby mode freeze option status bit.</Description>
  1815. <BitOffset>0x15</BitOffset>
  1816. <BitWidth>0x1</BitWidth>
  1817. <Access>R</Access>
  1818. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1819. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  1820. </Bit>
  1821. </AssignedBits>
  1822. </Field>
  1823. <Field>
  1824. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1825. <AssignedBits>
  1826. <Bit>
  1827. <Name>IWDG_STDBY</Name>
  1828. <Description>Standby mode freeze option status bit.</Description>
  1829. <BitOffset>0x15</BitOffset>
  1830. <BitWidth>0x1</BitWidth>
  1831. <Access>W</Access>
  1832. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1833. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  1834. </Bit>
  1835. </AssignedBits>
  1836. </Field>
  1837. <Field>
  1838. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1839. <AssignedBits>
  1840. <Bit>
  1841. <Name>IWDG_STOP</Name>
  1842. <Description>Stop mode freeze option status bit.</Description>
  1843. <BitOffset>0x14</BitOffset>
  1844. <BitWidth>0x1</BitWidth>
  1845. <Access>R</Access>
  1846. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1847. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1848. </Bit>
  1849. </AssignedBits>
  1850. </Field>
  1851. <Field>
  1852. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1853. <AssignedBits>
  1854. <Bit>
  1855. <Name>IWDG_STOP</Name>
  1856. <Description>Stop mode freeze option status bit.</Description>
  1857. <BitOffset>0x14</BitOffset>
  1858. <BitWidth>0x1</BitWidth>
  1859. <Access>W</Access>
  1860. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1861. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1862. </Bit>
  1863. </AssignedBits>
  1864. </Field>
  1865. <Field>
  1866. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1867. <AssignedBits>
  1868. <Bit>
  1869. <Name>SWAP_BANK</Name>
  1870. <Description>Bank swapping option status bit.</Description>
  1871. <BitOffset>0x1F</BitOffset>
  1872. <BitWidth>0x1</BitWidth>
  1873. <Access>R</Access>
  1874. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1875. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1876. </Bit>
  1877. </AssignedBits>
  1878. </Field>
  1879. <Field>
  1880. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1881. <AssignedBits>
  1882. <Bit>
  1883. <Name>SWAP_BANK</Name>
  1884. <Description>Bank swapping option status bit.</Description>
  1885. <BitOffset>0x1F</BitOffset>
  1886. <BitWidth>0x1</BitWidth>
  1887. <Access>W</Access>
  1888. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1889. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1890. </Bit>
  1891. </AssignedBits>
  1892. </Field>
  1893. <Field>
  1894. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1895. <AssignedBits>
  1896. <Bit>
  1897. <Name>IWDG_SW</Name>
  1898. <Description>IWDG control mode option status bit.</Description>
  1899. <BitOffset>0x3</BitOffset>
  1900. <BitWidth>0x1</BitWidth>
  1901. <Access>R</Access>
  1902. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1903. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1904. </Bit>
  1905. </AssignedBits>
  1906. </Field>
  1907. <Field>
  1908. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1909. <AssignedBits>
  1910. <Bit>
  1911. <Name>IWDG_SW</Name>
  1912. <Description>IWDG control mode option status bit.</Description>
  1913. <BitOffset>0x3</BitOffset>
  1914. <BitWidth>0x1</BitWidth>
  1915. <Access>W</Access>
  1916. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1917. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1918. </Bit>
  1919. </AssignedBits>
  1920. </Field>
  1921. <Field>
  1922. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1923. <AssignedBits>
  1924. <Bit>
  1925. <Name>WWDG_SW</Name>
  1926. <Description>WWDG control mode option status bit.</Description>
  1927. <BitOffset>0x4</BitOffset>
  1928. <BitWidth>0x1</BitWidth>
  1929. <Access>R</Access>
  1930. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1931. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1932. </Bit>
  1933. </AssignedBits>
  1934. </Field>
  1935. <Field>
  1936. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1937. <AssignedBits>
  1938. <Bit>
  1939. <Name>WWDG_SW</Name>
  1940. <Description>WWDG control mode option status bit.</Description>
  1941. <BitOffset>0x4</BitOffset>
  1942. <BitWidth>0x1</BitWidth>
  1943. <Access>W</Access>
  1944. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1945. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1946. </Bit>
  1947. </AssignedBits>
  1948. </Field>
  1949. <Field>
  1950. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1951. <AssignedBits>
  1952. <Bit>
  1953. <Name>NRST_STOP</Name>
  1954. <Description>Core domain Stop entry reset option status bit.</Description>
  1955. <BitOffset>0x6</BitOffset>
  1956. <BitWidth>0x1</BitWidth>
  1957. <Access>R</Access>
  1958. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  1959. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  1960. </Bit>
  1961. </AssignedBits>
  1962. </Field>
  1963. <Field>
  1964. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1965. <AssignedBits>
  1966. <Bit>
  1967. <Name>NRST_STOP</Name>
  1968. <Description>Core domain Stop entry reset option status bit.</Description>
  1969. <BitOffset>0x6</BitOffset>
  1970. <BitWidth>0x1</BitWidth>
  1971. <Access>W</Access>
  1972. <Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
  1973. <Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
  1974. </Bit>
  1975. </AssignedBits>
  1976. </Field>
  1977. <Field>
  1978. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  1979. <AssignedBits>
  1980. <Bit>
  1981. <Name>NRST_STDBY</Name>
  1982. <Description>Core domain Standby entry reset option status bit.</Description>
  1983. <BitOffset>0x7</BitOffset>
  1984. <BitWidth>0x1</BitWidth>
  1985. <Access>R</Access>
  1986. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1987. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1988. </Bit>
  1989. </AssignedBits>
  1990. </Field>
  1991. <Field>
  1992. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  1993. <AssignedBits>
  1994. <Bit>
  1995. <Name>NRST_STDBY</Name>
  1996. <Description>Core domain Standby entry reset option status bit.</Description>
  1997. <BitOffset>0x7</BitOffset>
  1998. <BitWidth>0x1</BitWidth>
  1999. <Access>W</Access>
  2000. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  2001. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  2002. </Bit>
  2003. </AssignedBits>
  2004. </Field>
  2005. </Category>
  2006. <Category>
  2007. <Name>User Configuration 2</Name>
  2008. <Field>
  2009. <Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
  2010. <AssignedBits>
  2011. <Bit>
  2012. <Name>SRAM1_ECC</Name>
  2013. <Description>ECC in SRAM1 region configuration bit</Description>
  2014. <BitOffset>0xA</BitOffset>
  2015. <BitWidth>0x1</BitWidth>
  2016. <Access>R</Access>
  2017. <Values>
  2018. <Val value="0x0">SRAM1 ECC check enabled </Val>
  2019. <Val value="0x1">SRAM1 ECC check disabled</Val>
  2020. </Values>
  2021. </Bit>
  2022. <Bit>
  2023. <Name>SRAM1_RST</Name>
  2024. <Description>SRAM1 erase upon system reset</Description>
  2025. <BitOffset>0x9</BitOffset>
  2026. <BitWidth>0x1</BitWidth>
  2027. <Access>R</Access>
  2028. <Values>
  2029. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  2030. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  2031. </Values>
  2032. </Bit>
  2033. <Bit>
  2034. <Name>SRAM2_ECC</Name>
  2035. <Description>ECC in SRAM2 region configuration bit</Description>
  2036. <BitOffset>0x6</BitOffset>
  2037. <BitWidth>0x1</BitWidth>
  2038. <Access>R</Access>
  2039. <Values>
  2040. <Val value="0x0">SRAM2 ECC check enabled </Val>
  2041. <Val value="0x1">SRAM2 ECC check disabled</Val>
  2042. </Values>
  2043. </Bit>
  2044. <Bit>
  2045. <Name>BKPRAM_ECC</Name>
  2046. <Description>ECC in BKPRAM region configuration bit</Description>
  2047. <BitOffset>0x4</BitOffset>
  2048. <BitWidth>0x1</BitWidth>
  2049. <Access>R</Access>
  2050. <Values>
  2051. <Val value="0x0">BKPRAM ECC check enabled </Val>
  2052. <Val value="0x1">BKPRAM ECC check disabled</Val>
  2053. </Values>
  2054. </Bit>
  2055. <Bit>
  2056. <Name>SRAM2_RST</Name>
  2057. <Description>SRAM2 erase when system reset</Description>
  2058. <BitOffset>0x3</BitOffset>
  2059. <BitWidth>0x1</BitWidth>
  2060. <Access>R</Access>
  2061. <Values>
  2062. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  2063. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  2064. </Values>
  2065. </Bit>
  2066. </AssignedBits>
  2067. </Field>
  2068. <Field>
  2069. <Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
  2070. <AssignedBits>
  2071. <Bit>
  2072. <Name>SRAM1_ECC</Name>
  2073. <Description>ECC in SRAM1 region configuration bit</Description>
  2074. <BitOffset>0xA</BitOffset>
  2075. <BitWidth>0x1</BitWidth>
  2076. <Access>W</Access>
  2077. <Values>
  2078. <Val value="0x0">SRAM1 ECC check enabled </Val>
  2079. <Val value="0x1">SRAM1 ECC check disabled</Val>
  2080. </Values>
  2081. </Bit>
  2082. <Bit>
  2083. <Name>SRAM1_RST</Name>
  2084. <Description>SRAM1 erase upon system reset</Description>
  2085. <BitOffset>0x9</BitOffset>
  2086. <BitWidth>0x1</BitWidth>
  2087. <Access>W</Access>
  2088. <Values>
  2089. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  2090. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  2091. </Values>
  2092. </Bit>
  2093. <Bit>
  2094. <Name>SRAM2_ECC</Name>
  2095. <Description>ECC in SRAM2 region configuration bit</Description>
  2096. <BitOffset>0x6</BitOffset>
  2097. <BitWidth>0x1</BitWidth>
  2098. <Access>W</Access>
  2099. <Values>
  2100. <Val value="0x0">SRAM2 ECC check enabled </Val>
  2101. <Val value="0x1">SRAM2 ECC check disabled</Val>
  2102. </Values>
  2103. </Bit>
  2104. <Bit>
  2105. <Name>BKPRAM_ECC</Name>
  2106. <Description>ECC in BKPRAM region configuration bit</Description>
  2107. <BitOffset>0x4</BitOffset>
  2108. <BitWidth>0x1</BitWidth>
  2109. <Access>W</Access>
  2110. <Values>
  2111. <Val value="0x0">BKPRAM ECC check enabled </Val>
  2112. <Val value="0x1">BKPRAM ECC check disabled</Val>
  2113. </Values>
  2114. </Bit>
  2115. <Bit>
  2116. <Name>SRAM2_RST</Name>
  2117. <Description>SRAM2 erase when system reset</Description>
  2118. <BitOffset>0x3</BitOffset>
  2119. <BitWidth>0x1</BitWidth>
  2120. <Access>W</Access>
  2121. <Values>
  2122. <Val value="0x0">SRAM2 erase when system reset occurs</Val>
  2123. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  2124. </Values>
  2125. </Bit>
  2126. </AssignedBits>
  2127. </Field>
  2128. </Category>
  2129. <Category>
  2130. <Name>Boot Configuration</Name>
  2131. <Field>
  2132. <Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
  2133. <AssignedBits>
  2134. <Bit>
  2135. <Name>NSBOOTADD</Name>
  2136. <Description>Unique Boot Entry Address</Description>
  2137. <BitOffset>0x8</BitOffset>
  2138. <BitWidth>0x18</BitWidth>
  2139. <Access>R</Access>
  2140. <Equation multiplier="0x100" offset="0x00000000"/>
  2141. </Bit>
  2142. <Bit>
  2143. <Name>NSBOOT_LOCK</Name>
  2144. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  2145. <BitOffset>0x0</BitOffset>
  2146. <BitWidth>0x8</BitWidth>
  2147. <Access>R</Access>
  2148. <Values>
  2149. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  2150. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  2151. </Values>
  2152. </Bit>
  2153. </AssignedBits>
  2154. </Field>
  2155. <Field>
  2156. <Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
  2157. <AssignedBits>
  2158. <Bit>
  2159. <Name>NSBOOTADD</Name>
  2160. <Description>Unique Boot Entry Address</Description>
  2161. <BitOffset>0x8</BitOffset>
  2162. <BitWidth>0x18</BitWidth>
  2163. <Access>W</Access>
  2164. <Equation multiplier="0x100" offset="0x00000000"/>
  2165. </Bit>
  2166. <Bit>
  2167. <Name>NSBOOT_LOCK</Name>
  2168. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
  2169. <BitOffset>0x0</BitOffset>
  2170. <BitWidth>0x8</BitWidth>
  2171. <Access>W</Access>
  2172. <Values>
  2173. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  2174. <Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
  2175. </Values>
  2176. </Bit>
  2177. </AssignedBits>
  2178. </Field>
  2179. </Category>
  2180. <Category>
  2181. <Name>OTP write protection</Name>
  2182. <Field>
  2183. <Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
  2184. <AssignedBits>
  2185. <Bit>
  2186. <Name>LOCKBL</Name>
  2187. <Description>OTP Block Lock</Description>
  2188. <BitOffset>0x0</BitOffset>
  2189. <BitWidth>0x20</BitWidth>
  2190. <Access>R</Access>
  2191. <Equation multiplier="0x2000" offset="0x00000000"/>
  2192. </Bit>
  2193. </AssignedBits>
  2194. </Field>
  2195. <Field>
  2196. <Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
  2197. <AssignedBits>
  2198. <Bit>
  2199. <Name>LOCKBL</Name>
  2200. <Description>OTP Block Lock</Description>
  2201. <BitOffset>0x0</BitOffset>
  2202. <BitWidth>0x20</BitWidth>
  2203. <Access>W</Access>
  2204. <Equation multiplier="0x2000" offset="0x00000000"/>
  2205. </Bit>
  2206. </AssignedBits>
  2207. </Field>
  2208. </Category>
  2209. <Category>
  2210. <Name>Write sector group protection 1</Name>
  2211. <Field>
  2212. <Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
  2213. <AssignedBits>
  2214. <Bit>
  2215. <Name>WRPSGn1</Name>
  2216. <Description>Bank 1 sector group protection option status byte</Description>
  2217. <BitOffset>0x0</BitOffset>
  2218. <BitWidth>0x8</BitWidth>
  2219. <Access>R</Access>
  2220. <Equation multiplier="0x2000" offset="0x08000000"/>
  2221. </Bit>
  2222. </AssignedBits>
  2223. </Field>
  2224. <Field>
  2225. <Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
  2226. <AssignedBits>
  2227. <Bit>
  2228. <Name>WRPSGn1</Name>
  2229. <Description>Bank 1 sector group protection option status byte</Description>
  2230. <BitOffset>0x0</BitOffset>
  2231. <BitWidth>0x8</BitWidth>
  2232. <Access>W</Access>
  2233. <Equation multiplier="0x2000" offset="0x08000000"/>
  2234. </Bit>
  2235. </AssignedBits>
  2236. </Field>
  2237. </Category>
  2238. <Category>
  2239. <Name>Flash HDP bank 1</Name>
  2240. <Field>
  2241. <Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
  2242. <AssignedBits>
  2243. <Bit>
  2244. <Name>HDP1_STRT</Name>
  2245. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  2246. <BitOffset>0x0</BitOffset>
  2247. <BitWidth>0x3</BitWidth>
  2248. <Access>R</Access>
  2249. <Equation multiplier="0x2000" offset="0x00000000"/>
  2250. </Bit>
  2251. <Bit>
  2252. <Name>HDP1_END</Name>
  2253. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  2254. <BitOffset>0x10</BitOffset>
  2255. <BitWidth>0x3</BitWidth>
  2256. <Access>R</Access>
  2257. <Equation multiplier="0x2000" offset="0x00000000"/>
  2258. </Bit>
  2259. </AssignedBits>
  2260. </Field>
  2261. <Field>
  2262. <Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
  2263. <AssignedBits>
  2264. <Bit>
  2265. <Name>HDP1_STRT</Name>
  2266. <Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
  2267. <BitOffset>0x0</BitOffset>
  2268. <BitWidth>0x3</BitWidth>
  2269. <Access>W</Access>
  2270. <Equation multiplier="0x2000" offset="0x00000000"/>
  2271. </Bit>
  2272. <Bit>
  2273. <Name>HDP1_END</Name>
  2274. <Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
  2275. <BitOffset>0x10</BitOffset>
  2276. <BitWidth>0x3</BitWidth>
  2277. <Access>W</Access>
  2278. <Equation multiplier="0x2000" offset="0x00000000"/>
  2279. </Bit>
  2280. </AssignedBits>
  2281. </Field>
  2282. </Category>
  2283. </Bank>
  2284. <Bank interface="Bootloader">
  2285. <Parameters address="0x400221E8" name="Bank 2" size="0x18"/>
  2286. <Category>
  2287. <Name>Write sector group protection 2</Name>
  2288. <Field>
  2289. <Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
  2290. <AssignedBits>
  2291. <Bit>
  2292. <Name>WRPSGn2</Name>
  2293. <Description>Bank 2 sector group protection option status byte</Description>
  2294. <BitOffset>0x0</BitOffset>
  2295. <BitWidth>0x8</BitWidth>
  2296. <Access>R</Access>
  2297. <Equation multiplier="0x2000" offset="0x08010000"/>
  2298. </Bit>
  2299. </AssignedBits>
  2300. </Field>
  2301. <Field>
  2302. <Parameters address="0x400221EC" name="FLASH_WRP2BR" size="0x4"/>
  2303. <AssignedBits>
  2304. <Bit>
  2305. <Name>WRPSGn2</Name>
  2306. <Description>Bank 2 sector group protection option status byte</Description>
  2307. <BitOffset>0x0</BitOffset>
  2308. <BitWidth>0x8</BitWidth>
  2309. <Access>W</Access>
  2310. <Equation multiplier="0x2000" offset="0x08010000"/>
  2311. </Bit>
  2312. </AssignedBits>
  2313. </Field>
  2314. </Category>
  2315. <Category>
  2316. <Name>Flash HDP bank 2</Name>
  2317. <Field>
  2318. <Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
  2319. <AssignedBits>
  2320. <Bit>
  2321. <Name>HDP2_STRT</Name>
  2322. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  2323. <BitOffset>0x0</BitOffset>
  2324. <BitWidth>0x3</BitWidth>
  2325. <Access>R</Access>
  2326. <Equation multiplier="0x2000" offset="0x00000000"/>
  2327. </Bit>
  2328. <Bit>
  2329. <Name>HDP2_END</Name>
  2330. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  2331. <BitOffset>0x10</BitOffset>
  2332. <BitWidth>0x3</BitWidth>
  2333. <Access>R</Access>
  2334. <Equation multiplier="0x2000" offset="0x00000000"/>
  2335. </Bit>
  2336. </AssignedBits>
  2337. </Field>
  2338. <Field>
  2339. <Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
  2340. <AssignedBits>
  2341. <Bit>
  2342. <Name>HDP2_STRT</Name>
  2343. <Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
  2344. <BitOffset>0x0</BitOffset>
  2345. <BitWidth>0x3</BitWidth>
  2346. <Access>W</Access>
  2347. <Equation multiplier="0x2000" offset="0x00000000"/>
  2348. </Bit>
  2349. <Bit>
  2350. <Name>HDP2_END</Name>
  2351. <Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
  2352. <BitOffset>0x10</BitOffset>
  2353. <BitWidth>0x3</BitWidth>
  2354. <Access>W</Access>
  2355. <Equation multiplier="0x2000" offset="0x00000000"/>
  2356. </Bit>
  2357. </AssignedBits>
  2358. </Field>
  2359. </Category>
  2360. </Bank>
  2361. </Peripheral>
  2362. </Peripherals>
  2363. </Device>
  2364. </Root>