STM32_Prog_DB_0x476.xml 103 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x476</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32U5Fx</Name>
  9. <Series>STM32U5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Single Bank non secure -->
  15. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  16. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  17. </Configuration>
  18. <Configuration number="0x1"> <!-- Dual Bank non secure -->
  19. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  20. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  21. </Configuration>
  22. <Configuration number="0x2"> <!-- Single Bank secure + RDP=0xAA -->
  23. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  25. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  26. </Configuration>
  27. <Configuration number="0x3"> <!-- Dual Bank secure + RDP=0xAA -->
  28. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  29. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  30. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  31. </Configuration>
  32. <Configuration number="0xA"> <!-- Single Bank + RDP=0x55 -->
  33. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  34. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x00000055"/> </RDP>
  35. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  36. </Configuration>
  37. <Configuration number="0xB"> <!-- Dual Bank + RDP=0x55 -->
  38. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  39. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x00000055"/> </RDP>
  40. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  41. </Configuration>
  42. <Configuration number="0x4"> <!-- Single Bank secure -->
  43. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  44. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  45. </Configuration>
  46. <Configuration number="0x5"> <!-- Dual Bank secure -->
  47. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  48. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  49. </Configuration>
  50. </Interface>
  51. <!-- Bootloader Interface -->
  52. <Interface name="Bootloader">
  53. <Configuration number="0x6"> <!-- Single Bank-->
  54. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  55. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  56. </Configuration>
  57. <Configuration number="0x7"> <!-- Dual Bank-->
  58. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  59. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  60. </Configuration>
  61. <Configuration number="0x8"> <!-- Single Bank secure-->
  62. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  63. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  64. <!--<RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>-->
  65. </Configuration>
  66. <Configuration number="0x9"> <!-- Dual Bank seure-->
  67. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  68. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  69. <!--<RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>-->
  70. </Configuration>
  71. </Interface>
  72. </Configurations>
  73. <!-- Peripherals -->
  74. <Peripherals>
  75. <!-- Embedded SRAM -->
  76. <Peripheral>
  77. <Name>Embedded SRAM</Name>
  78. <Type>Storage</Type>
  79. <Description/>
  80. <ErasedValue>0xFF</ErasedValue>
  81. <Access>RWE</Access>
  82. <!-- 96 KB -->
  83. <Configuration config="0,1,6,7,8,9,10,11">
  84. <Parameters address="0x20000000" name="SRAM" size="0x8000"/>
  85. <Description/>
  86. <Organization>Single</Organization>
  87. <Bank name="Bank 1">
  88. <Field>
  89. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
  90. </Field>
  91. </Bank>
  92. </Configuration>
  93. <Configuration config="2,3,4,5">
  94. <Parameters address="0x30000000" name="SRAM" size="0x8000"/>
  95. <Description/>
  96. <Organization>Single</Organization>
  97. <Bank name="Bank 1">
  98. <Field>
  99. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x8000"/>
  100. </Field>
  101. </Bank>
  102. </Configuration>
  103. </Peripheral>
  104. <!-- Embedded Flash -->
  105. <Peripheral>
  106. <Name>Embedded Flash</Name>
  107. <Type>Storage</Type>
  108. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  109. <ErasedValue>0xFF</ErasedValue>
  110. <Access>RWE</Access>
  111. <FlashSize address="0x0BFA0764" default="0x400000"/>
  112. <BootloaderVersion address="0x0BF99EFE"/>
  113. <DBGMCU_CR address="0xE0044004" mask="0x06"/>
  114. <DBGMCU_APB1_FZ address="0xE0044008" mask="0x1800"/>
  115. <Configuration config="0,6,10"> <!-- Single Bank -->
  116. <Parameters address="0x08000000" name=" 4096 Kbyte Embedded Flash" size="0x400000"/>
  117. <Description/>
  118. <Organization>Single</Organization>
  119. <Allignement>0x10</Allignement>
  120. <Bank name="Bank 1">
  121. <Field>
  122. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x4000"/>
  123. </Field>
  124. </Bank>
  125. </Configuration>
  126. <Configuration config="1,7,11"> <!-- dual Bank -->
  127. <Parameters address="0x08000000" name=" 4 Mbyte Embedded Flash" size="0x400000"/>
  128. <Description/>
  129. <Organization>Dual</Organization>
  130. <Allignement>0x10</Allignement>
  131. <Bank name="Bank 1">
  132. <Field>
  133. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x2000"/>
  134. </Field>
  135. </Bank>
  136. <Bank name="Bank 2">
  137. <Field>
  138. <Parameters address="0x08200000" name="sector256" occurence="0x100" size="0x2000"/>
  139. </Field>
  140. </Bank>
  141. </Configuration>
  142. <Configuration config="2,4,8"> <!-- Single Bank secure -->
  143. <Parameters address="0x0C000000" name=" 4 Mbyte Embedded Flash" size="0x400000"/>
  144. <Description/>
  145. <Organization>Single</Organization>
  146. <Allignement>0x10</Allignement>
  147. <Bank name="Bank 1">
  148. <Field>
  149. <Parameters address="0x0c000000" name="sector0" occurence="0x100" size="0x4000"/>
  150. </Field>
  151. </Bank>
  152. </Configuration>
  153. <Configuration config="3,5,9"> <!-- dual Bank secure -->
  154. <Parameters address="0x0c000000" name=" 4 Mbyte Embedded Flash" size="0x400000"/>
  155. <Description/>
  156. <Organization>Dual</Organization>
  157. <Allignement>0x10</Allignement>
  158. <Bank name="Bank 1">
  159. <Field>
  160. <Parameters address="0x0c000000" name="sector0" occurence="0x100" size="0x2000"/>
  161. </Field>
  162. </Bank>
  163. <Bank name="Bank 2">
  164. <Field>
  165. <Parameters address="0x0c200000" name="sector256" occurence="0x100" size="0x2000"/>
  166. </Field>
  167. </Bank>
  168. </Configuration>
  169. </Peripheral>
  170. <!-- Data EEPROM -->
  171. <Peripheral>
  172. <Name>Data EEPROM</Name>
  173. <Type>Storage</Type>
  174. <Description>The Data EEPROM memory block. It contains user data.</Description>
  175. <ErasedValue>0xFF</ErasedValue>
  176. <Access>RWE</Access>
  177. <Configuration config="2,4,7,9,10">
  178. <Parameters address="0x08000000" name=" 4 Mbyte Data EEPROM" size="0x400000"/>
  179. <Description/>
  180. <Organization>Single</Organization>
  181. <Allignement>0x4</Allignement>
  182. <Bank name="Bank 1">
  183. <Field>
  184. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x4000"/>
  185. </Field>
  186. </Bank>
  187. </Configuration>
  188. <Configuration config="3,5,6,8,11">
  189. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x400000"/>
  190. <Description/>
  191. <Organization>Single</Organization>
  192. <Allignement>0x4</Allignement>
  193. <Bank name="Bank 1">
  194. <Field>
  195. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x2000"/>
  196. </Field>
  197. </Bank>
  198. <Bank name="Bank 2">
  199. <Field>
  200. <Parameters address="0x08200000" name="sector256" occurence="0x100" size="0x2000"/>
  201. </Field>
  202. </Bank>
  203. </Configuration>
  204. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  205. <Configuration config="1">
  206. <Parameters address="0x0C000000" name=" 4 Mbyte Data EEPROM" size="0x400000"/>
  207. <Description/>
  208. <Organization>Single</Organization>
  209. <Allignement>0x4</Allignement>
  210. <Bank name="Bank 1">
  211. <Field>
  212. <Parameters address="0x0C000000" name="sector0" occurence="0x100" size="0x2000"/>
  213. </Field>
  214. </Bank>
  215. <Bank name="Bank 2">
  216. <Field>
  217. <Parameters address="0x0C200000" name="sector256" occurence="0x100" size="0x2000"/>
  218. </Field>
  219. </Bank>
  220. </Configuration>
  221. </Peripheral>
  222. <!-- OTP -->
  223. <Peripheral>
  224. <Name>OTP</Name>
  225. <Type>Storage</Type>
  226. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  227. <ErasedValue>0xFF</ErasedValue>
  228. <Access>RW</Access>
  229. <!-- 512 Bytes single bank -->
  230. <Configuration>
  231. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  232. <Description/>
  233. <Organization>Single</Organization>
  234. <Allignement>0x4</Allignement>
  235. <Bank name="OTP">
  236. <Field>
  237. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  238. </Field>
  239. </Bank>
  240. </Configuration>
  241. </Peripheral>
  242. <!-- Option Bytes -->
  243. <Peripheral>
  244. <Name>Option Bytes</Name>
  245. <Type>Configuration</Type>
  246. <Description/>
  247. <Access>RW</Access>
  248. <Configuration config="0,1,10,11">
  249. <Bank interface="JTAG_SWD"> <!-- Bank 1: address="0x40022040" name="Bank 1" size="0x20" -->
  250. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  251. <Category>
  252. <Name>Read Out Protection</Name>
  253. <Field>
  254. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  255. <AssignedBits>
  256. <Bit>
  257. <Name>RDP</Name>
  258. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  259. <BitOffset>0x0</BitOffset>
  260. <BitWidth>0x8</BitWidth>
  261. <Access>RW</Access>
  262. <Values>
  263. <Val value="0xAA">Level 0, no protection</Val>
  264. <Val value="0xDC">Level 1, read protection of memories</Val>
  265. <Val value="0xCC">Level 2, chip protection</Val>
  266. </Values>
  267. </Bit>
  268. </AssignedBits>
  269. </Field>
  270. </Category>
  271. <Category>
  272. <Name>BOR Level</Name>
  273. <Field>
  274. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  275. <AssignedBits>
  276. <Bit>
  277. <Name>BOR_LEV</Name>
  278. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  279. <BitOffset>0x8</BitOffset>
  280. <BitWidth>0x3</BitWidth>
  281. <Access>RW</Access>
  282. <Values>
  283. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  284. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  285. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  286. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  287. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  288. </Values>
  289. </Bit>
  290. </AssignedBits>
  291. </Field>
  292. </Category>
  293. <Category>
  294. <Name>User Configuration</Name>
  295. <Field>
  296. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  297. <AssignedBits>
  298. <Bit>
  299. <Name>TZEN</Name>
  300. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  301. <BitOffset>0x1F</BitOffset>
  302. <BitWidth>0x1</BitWidth>
  303. <Access>RW</Access>
  304. <Values>
  305. <Val value="0x0">Global TrustZone security disabled</Val>
  306. <Val value="0x1">Global TrustZone security enabled</Val>
  307. </Values>
  308. </Bit>
  309. <Bit>
  310. <Name>nRST_STOP</Name>
  311. <Description/>
  312. <BitOffset>0xC</BitOffset>
  313. <BitWidth>0x1</BitWidth>
  314. <Access>RW</Access>
  315. <Values>
  316. <Val value="0x0">Reset generated when entering Stop mode</Val>
  317. <Val value="0x1">No reset generated when entering Stop mode</Val>
  318. </Values>
  319. </Bit>
  320. <Bit>
  321. <Name>nRST_STDBY</Name>
  322. <Description/>
  323. <BitOffset>0xD</BitOffset>
  324. <BitWidth>0x1</BitWidth>
  325. <Access>RW</Access>
  326. <Values>
  327. <Val value="0x0">Reset generated when entering Standby mode</Val>
  328. <Val value="0x1">No reset generated when entering Standby mode</Val>
  329. </Values>
  330. </Bit>
  331. <Bit>
  332. <Name>nRST_SHDW</Name>
  333. <Description/>
  334. <BitOffset>0xE</BitOffset>
  335. <BitWidth>0x1</BitWidth>
  336. <Access>RW</Access>
  337. <Values>
  338. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  339. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  340. </Values>
  341. </Bit>
  342. <Bit>
  343. <Name>SRAM1345_RST</Name>
  344. <Description>SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset</Description>
  345. <BitOffset>0xF</BitOffset>
  346. <BitWidth>0x1</BitWidth>
  347. <Access>RW</Access>
  348. <Values>
  349. <Val value="0x0">SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs</Val>
  350. <Val value="0x1">SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs</Val>
  351. </Values>
  352. </Bit>
  353. <Bit>
  354. <Name>IWDG_SW</Name>
  355. <Description/>
  356. <BitOffset>0x10</BitOffset>
  357. <BitWidth>0x1</BitWidth>
  358. <Access>RW</Access>
  359. <Values>
  360. <Val value="0x0">Hardware independant watchdog</Val>
  361. <Val value="0x1">Software independant watchdog</Val>
  362. </Values>
  363. </Bit>
  364. <Bit>
  365. <Name>IWDG_STOP</Name>
  366. <Description/>
  367. <BitOffset>0x11</BitOffset>
  368. <BitWidth>0x1</BitWidth>
  369. <Access>RW</Access>
  370. <Values>
  371. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  372. <Val value="0x1">IWDG counter active in stop mode</Val>
  373. </Values>
  374. </Bit>
  375. <Bit>
  376. <Name>IWDG_STDBY</Name>
  377. <Description/>
  378. <BitOffset>0x12</BitOffset>
  379. <BitWidth>0x1</BitWidth>
  380. <Access>RW</Access>
  381. <Values>
  382. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  383. <Val value="0x1">IWDG counter active in standby mode</Val>
  384. </Values>
  385. </Bit>
  386. <Bit>
  387. <Name>WWDG_SW</Name>
  388. <Description/>
  389. <BitOffset>0x13</BitOffset>
  390. <BitWidth>0x1</BitWidth>
  391. <Access>RW</Access>
  392. <Values>
  393. <Val value="0x0">Hardware window watchdog</Val>
  394. <Val value="0x1">Software window watchdog</Val>
  395. </Values>
  396. </Bit>
  397. <Bit>
  398. <Name>SWAP_BANK</Name>
  399. <Description/>
  400. <BitOffset>0x14</BitOffset>
  401. <BitWidth>0x1</BitWidth>
  402. <Access>RW</Access>
  403. <Values>
  404. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  405. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  406. </Values>
  407. </Bit>
  408. <Bit>
  409. <Name>DBANK</Name>
  410. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  411. <BitOffset>0x15</BitOffset>
  412. <BitWidth>0x1</BitWidth>
  413. <Access>RW</Access>
  414. <Values>
  415. <Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
  416. <Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
  417. </Values>
  418. </Bit>
  419. <Bit>
  420. <Name>BKPRAM_ECC</Name>
  421. <Description>SRAM2 parity check enable</Description>
  422. <BitOffset>0x16</BitOffset>
  423. <BitWidth>0x1</BitWidth>
  424. <Access>RW</Access>
  425. <Values>
  426. <Val value="0x0">Backup RAM ECC check enabled</Val>
  427. <Val value="0x1">Backup RAM ECC check disabled</Val>
  428. </Values>
  429. </Bit>
  430. <Bit>
  431. <Name>SRAM3_ECC</Name>
  432. <Description>SRAM3 ECC detection and correction enable</Description>
  433. <BitOffset>0x17</BitOffset>
  434. <BitWidth>0x1</BitWidth>
  435. <Access>RW</Access>
  436. <Values>
  437. <Val value="0x0">SRAM3 ECC check enabled</Val>
  438. <Val value="0x1">SRAM3 ECC check disabled</Val>
  439. </Values>
  440. </Bit>
  441. <Bit>
  442. <Name>SRAM2_ECC</Name>
  443. <Description>SRAM2 ECC detection and correction enable</Description>
  444. <BitOffset>0x18</BitOffset>
  445. <BitWidth>0x1</BitWidth>
  446. <Access>RW</Access>
  447. <Values>
  448. <Val value="0x0">SRAM2 ECC check enabled</Val>
  449. <Val value="0x1">SRAM2 ECC check disabled</Val>
  450. </Values>
  451. </Bit>
  452. <Bit>
  453. <Name>SRAM2_RST</Name>
  454. <Description>SRAM2 Erase when system reset</Description>
  455. <BitOffset>0x19</BitOffset>
  456. <BitWidth>0x1</BitWidth>
  457. <Access>RW</Access>
  458. <Values>
  459. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  460. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  461. </Values>
  462. </Bit>
  463. <Bit>
  464. <Name>nSWBOOT0</Name>
  465. <Description>Software BOOT0</Description>
  466. <BitOffset>0x1A</BitOffset>
  467. <BitWidth>0x1</BitWidth>
  468. <Access>RW</Access>
  469. <Values>
  470. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  471. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  472. </Values>
  473. </Bit>
  474. <Bit>
  475. <Name>nBOOT0</Name>
  476. <Description>nBOOT0 option bit</Description>
  477. <BitOffset>0x1B</BitOffset>
  478. <BitWidth>0x1</BitWidth>
  479. <Access>RW</Access>
  480. <Values>
  481. <Val value="0x0">nBOOT0 = 0</Val>
  482. <Val value="0x1">nBOOT0 = 1</Val>
  483. </Values>
  484. </Bit>
  485. <Bit>
  486. <Name>PA15_PUPEN</Name>
  487. <Description>PA15 pull-up enable</Description>
  488. <BitOffset>0x1C</BitOffset>
  489. <BitWidth>0x1</BitWidth>
  490. <Access>RW</Access>
  491. <Values>
  492. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  493. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  494. </Values>
  495. </Bit>
  496. <Bit>
  497. <Name>IO_VDD_HSLV</Name>
  498. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  499. <BitOffset>0x1D</BitOffset>
  500. <BitWidth>0x1</BitWidth>
  501. <Access>RW</Access>
  502. <Values>
  503. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  504. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  505. </Values>
  506. </Bit>
  507. <Bit>
  508. <Name>IO_VDDIO2_HSLV</Name>
  509. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  510. <BitOffset>0x1E</BitOffset>
  511. <BitWidth>0x1</BitWidth>
  512. <Access>RW</Access>
  513. <Values>
  514. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  515. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  516. </Values>
  517. </Bit>
  518. </AssignedBits>
  519. </Field>
  520. </Category>
  521. <Category>
  522. <Name>Boot Configuration</Name>
  523. <Field>
  524. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  525. <AssignedBits>
  526. <Bit>
  527. <Name>NSBOOTADD0</Name>
  528. <Description>Non-secure Boot base address 0</Description>
  529. <BitOffset>0x7</BitOffset>
  530. <BitWidth>0x19</BitWidth>
  531. <Access>RW</Access>
  532. <Equation multiplier="0x80" offset="0x0000000"/>
  533. </Bit>
  534. </AssignedBits>
  535. </Field>
  536. <Field>
  537. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  538. <AssignedBits>
  539. <Bit>
  540. <Name>NSBOOTADD1</Name>
  541. <Description>Non-secure Boot base address 1</Description>
  542. <BitOffset>0x7</BitOffset>
  543. <BitWidth>0x19</BitWidth>
  544. <Access>RW</Access>
  545. <Equation multiplier="0x80" offset="0x0000000"/>
  546. </Bit>
  547. </AssignedBits>
  548. </Field>
  549. </Category>
  550. <Category>
  551. <Name>Write Protection 1</Name>
  552. <Field>
  553. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  554. <AssignedBits>
  555. <Bit config="0,10">
  556. <Name>WRP1A_PSTRT</Name>
  557. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  558. <BitOffset>0x0</BitOffset>
  559. <BitWidth>0x8</BitWidth>
  560. <Access>RW</Access>
  561. <Equation multiplier="0x4000" offset="0x08000000"/>
  562. </Bit>
  563. <Bit config="1,11">
  564. <Name>WRP1A_PSTRT</Name>
  565. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  566. <BitOffset>0x0</BitOffset>
  567. <BitWidth>0x8</BitWidth>
  568. <Access>RW</Access>
  569. <Equation multiplier="0x2000" offset="0x08000000"/>
  570. </Bit>
  571. <Bit config="0,10">
  572. <Name>WRP1A_PEND</Name>
  573. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  574. <BitOffset>0x10</BitOffset>
  575. <BitWidth>0x8</BitWidth>
  576. <Access>RW</Access>
  577. <Equation multiplier="0x4000" offset="0x08000000"/>
  578. </Bit>
  579. <Bit config="1,11">
  580. <Name>WRP1A_PEND</Name>
  581. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  582. <BitOffset>0x10</BitOffset>
  583. <BitWidth>0x8</BitWidth>
  584. <Access>RW</Access>
  585. <Equation multiplier="0x2000" offset="0x08000000"/>
  586. </Bit>
  587. <Bit>
  588. <Name>UNLOCK_1A</Name>
  589. <Description>Bank 1 WPR first area A unlock</Description>
  590. <BitOffset>0x1F</BitOffset>
  591. <BitWidth>0x1</BitWidth>
  592. <Access>RW</Access>
  593. <Values>
  594. <Val value="0x0">WRP1A start and end pages locked</Val>
  595. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  596. </Values>
  597. </Bit>
  598. </AssignedBits>
  599. </Field>
  600. <Field>
  601. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  602. <AssignedBits>
  603. <Bit config="0,10">
  604. <Name>WRP1B_PSTRT</Name>
  605. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  606. <BitOffset>0x0</BitOffset>
  607. <BitWidth>0x8</BitWidth>
  608. <Access>RW</Access>
  609. <Equation multiplier="0x4000" offset="0x08000000"/>
  610. </Bit>
  611. <Bit config="1,11">
  612. <Name>WRP1B_PSTRT</Name>
  613. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  614. <BitOffset>0x0</BitOffset>
  615. <BitWidth>0x8</BitWidth>
  616. <Access>RW</Access>
  617. <Equation multiplier="0x2000" offset="0x08000000"/>
  618. </Bit>
  619. <Bit config="0,10">
  620. <Name>WRP1B_PEND</Name>
  621. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  622. <BitOffset>0x10</BitOffset>
  623. <BitWidth>0x8</BitWidth>
  624. <Access>RW</Access>
  625. <Equation multiplier="0x4000" offset="0x08000000"/>
  626. </Bit>
  627. <Bit config="1,11">
  628. <Name>WRP1B_PEND</Name>
  629. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  630. <BitOffset>0x10</BitOffset>
  631. <BitWidth>0x8</BitWidth>
  632. <Access>RW</Access>
  633. <Equation multiplier="0x2000" offset="0x08000000"/>
  634. </Bit>
  635. <Bit>
  636. <Name>UNLOCK_1B</Name>
  637. <Description>Bank 1 WPR first area B unlock</Description>
  638. <BitOffset>0x1F</BitOffset>
  639. <BitWidth>0x1</BitWidth>
  640. <Access>RW</Access>
  641. <Values>
  642. <Val value="0x0">WRP1B start and end pages locked</Val>
  643. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  644. </Values>
  645. </Bit>
  646. </AssignedBits>
  647. </Field>
  648. </Category>
  649. </Bank>
  650. <Bank interface="JTAG_SWD"> <!-- Bank 2: address="0x40022068" name="Bank 2" size="0x8" -->
  651. <Parameters address="0x40022068" name="Bank 2" size="0x8"/>
  652. <Category>
  653. <Name>Write Protection 2</Name>
  654. <Field>
  655. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  656. <AssignedBits>
  657. <Bit config="0,10">
  658. <Name>WRP2A_PSTRT</Name>
  659. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  660. <BitOffset>0x0</BitOffset>
  661. <BitWidth>0x8</BitWidth>
  662. <Access>RW</Access>
  663. <Equation multiplier="0x4000" offset="0x08000000"/>
  664. </Bit>
  665. <Bit config="1,11">
  666. <Name>WRP2A_PSTRT</Name>
  667. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  668. <BitOffset>0x0</BitOffset>
  669. <BitWidth>0x8</BitWidth>
  670. <Access>RW</Access>
  671. <Equation multiplier="0x2000" offset="0x08200000"/>
  672. </Bit>
  673. <Bit config="0,10">
  674. <Name>WRP2A_PEND</Name>
  675. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  676. <BitOffset>0x10</BitOffset>
  677. <BitWidth>0x8</BitWidth>
  678. <Access>RW</Access>
  679. <Equation multiplier="0x4000" offset="0x08000000"/>
  680. </Bit>
  681. <Bit config="1,11">
  682. <Name>WRP2A_PEND</Name>
  683. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  684. <BitOffset>0x10</BitOffset>
  685. <BitWidth>0x8</BitWidth>
  686. <Access>RW</Access>
  687. <Equation multiplier="0x2000" offset="0x08200000"/>
  688. </Bit>
  689. <Bit>
  690. <Name>UNLOCK_2A</Name>
  691. <Description>Bank 2 WPR first area A unlock</Description>
  692. <BitOffset>0x1F</BitOffset>
  693. <BitWidth>0x1</BitWidth>
  694. <Access>RW</Access>
  695. <Values>
  696. <Val value="0x0">WRP2A start and end pages locked</Val>
  697. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  698. </Values>
  699. </Bit>
  700. </AssignedBits>
  701. </Field>
  702. <Field>
  703. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  704. <AssignedBits>
  705. <Bit config="0,10">
  706. <Name>WRP2B_PSTRT</Name>
  707. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  708. <BitOffset>0x0</BitOffset>
  709. <BitWidth>0x8</BitWidth>
  710. <Access>RW</Access>
  711. <Equation multiplier="0x4000" offset="0x08000000"/>
  712. </Bit>
  713. <Bit config="1,11">
  714. <Name>WRP2B_PSTRT</Name>
  715. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  716. <BitOffset>0x0</BitOffset>
  717. <BitWidth>0x8</BitWidth>
  718. <Access>RW</Access>
  719. <Equation multiplier="0x2000" offset="0x08200000"/>
  720. </Bit>
  721. <Bit config="0,10">
  722. <Name>WRP2B_PEND</Name>
  723. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  724. <BitOffset>0x10</BitOffset>
  725. <BitWidth>0x8</BitWidth>
  726. <Access>RW</Access>
  727. <Equation multiplier="0x4000" offset="0x08000000"/>
  728. </Bit>
  729. <Bit config="1,11">
  730. <Name>WRP2B_PEND</Name>
  731. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  732. <BitOffset>0x10</BitOffset>
  733. <BitWidth>0x8</BitWidth>
  734. <Access>RW</Access>
  735. <Equation multiplier="0x2000" offset="0x08200000"/>
  736. </Bit>
  737. <Bit>
  738. <Name>UNLOCK_2B</Name>
  739. <Description>Bank 2 WPR first area B unlock</Description>
  740. <BitOffset>0x1F</BitOffset>
  741. <BitWidth>0x1</BitWidth>
  742. <Access>RW</Access>
  743. <Values>
  744. <Val value="0x0">WRP2B start and end pages locked</Val>
  745. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  746. </Values>
  747. </Bit>
  748. </AssignedBits>
  749. </Field>
  750. </Category>
  751. </Bank>
  752. </Configuration>
  753. <Configuration config="2,3">
  754. <Bank interface="JTAG_SWD"> <!-- Bank 1: address="0x50022040" name="Bank 1" size="0x28" -->
  755. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  756. <Category>
  757. <Name>Read Out Protection</Name>
  758. <Field>
  759. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  760. <AssignedBits>
  761. <Bit>
  762. <Name>RDP</Name>
  763. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  764. <BitOffset>0x0</BitOffset>
  765. <BitWidth>0x8</BitWidth>
  766. <Access>RW</Access>
  767. <Values>
  768. <Val value="0xAA">Level 0, no protection</Val>
  769. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  770. <Val value="0xDC">Level 1, read protection of memories</Val>
  771. <Val value="0xCC">Level 2, chip protection</Val>
  772. </Values>
  773. </Bit>
  774. </AssignedBits>
  775. </Field>
  776. </Category>
  777. <Category>
  778. <Name>BOR Level</Name>
  779. <Field>
  780. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  781. <AssignedBits>
  782. <Bit>
  783. <Name>BOR_LEV</Name>
  784. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  785. <BitOffset>0x8</BitOffset>
  786. <BitWidth>0x3</BitWidth>
  787. <Access>RW</Access>
  788. <Values>
  789. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  790. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  791. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  792. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  793. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  794. </Values>
  795. </Bit>
  796. </AssignedBits>
  797. </Field>
  798. </Category>
  799. <Category>
  800. <Name>User Configuration</Name>
  801. <Field>
  802. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  803. <AssignedBits>
  804. <Bit>
  805. <Name>TZEN</Name>
  806. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  807. <BitOffset>0x1F</BitOffset>
  808. <BitWidth>0x1</BitWidth>
  809. <Access>RW</Access>
  810. <Values>
  811. <Val value="0x0">Global TrustZone security disabled</Val>
  812. <Val value="0x1">Global TrustZone security enabled</Val>
  813. </Values>
  814. </Bit>
  815. <Bit>
  816. <Name>nRST_STOP</Name>
  817. <Description/>
  818. <BitOffset>0xC</BitOffset>
  819. <BitWidth>0x1</BitWidth>
  820. <Access>RW</Access>
  821. <Values>
  822. <Val value="0x0">Reset generated when entering Stop mode</Val>
  823. <Val value="0x1">No reset generated when entering Stop mode</Val>
  824. </Values>
  825. </Bit>
  826. <Bit>
  827. <Name>nRST_STDBY</Name>
  828. <Description/>
  829. <BitOffset>0xD</BitOffset>
  830. <BitWidth>0x1</BitWidth>
  831. <Access>RW</Access>
  832. <Values>
  833. <Val value="0x0">Reset generated when entering Standby mode</Val>
  834. <Val value="0x1">No reset generated when entering Standby mode</Val>
  835. </Values>
  836. </Bit>
  837. <Bit>
  838. <Name>nRST_SHDW</Name>
  839. <Description/>
  840. <BitOffset>0xE</BitOffset>
  841. <BitWidth>0x1</BitWidth>
  842. <Access>RW</Access>
  843. <Values>
  844. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  845. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  846. </Values>
  847. </Bit>
  848. <Bit>
  849. <Name>SRAM1345_RST</Name>
  850. <Description>SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset</Description>
  851. <BitOffset>0xF</BitOffset>
  852. <BitWidth>0x1</BitWidth>
  853. <Access>RW</Access>
  854. <Values>
  855. <Val value="0x0">SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs</Val>
  856. <Val value="0x1">SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs</Val>
  857. </Values>
  858. </Bit>
  859. <Bit>
  860. <Name>IWDG_SW</Name>
  861. <Description/>
  862. <BitOffset>0x10</BitOffset>
  863. <BitWidth>0x1</BitWidth>
  864. <Access>RW</Access>
  865. <Values>
  866. <Val value="0x0">Hardware independant watchdog</Val>
  867. <Val value="0x1">Software independant watchdog</Val>
  868. </Values>
  869. </Bit>
  870. <Bit>
  871. <Name>IWDG_STOP</Name>
  872. <Description/>
  873. <BitOffset>0x11</BitOffset>
  874. <BitWidth>0x1</BitWidth>
  875. <Access>RW</Access>
  876. <Values>
  877. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  878. <Val value="0x1">IWDG counter active in stop mode</Val>
  879. </Values>
  880. </Bit>
  881. <Bit>
  882. <Name>IWDG_STDBY</Name>
  883. <Description/>
  884. <BitOffset>0x12</BitOffset>
  885. <BitWidth>0x1</BitWidth>
  886. <Access>RW</Access>
  887. <Values>
  888. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  889. <Val value="0x1">IWDG counter active in standby mode</Val>
  890. </Values>
  891. </Bit>
  892. <Bit>
  893. <Name>WWDG_SW</Name>
  894. <Description/>
  895. <BitOffset>0x13</BitOffset>
  896. <BitWidth>0x1</BitWidth>
  897. <Access>RW</Access>
  898. <Values>
  899. <Val value="0x0">Hardware window watchdog</Val>
  900. <Val value="0x1">Software window watchdog</Val>
  901. </Values>
  902. </Bit>
  903. <Bit>
  904. <Name>SWAP_BANK</Name>
  905. <Description/>
  906. <BitOffset>0x14</BitOffset>
  907. <BitWidth>0x1</BitWidth>
  908. <Access>RW</Access>
  909. <Values>
  910. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  911. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  912. </Values>
  913. </Bit>
  914. <Bit>
  915. <Name>DBANK</Name>
  916. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  917. <BitOffset>0x15</BitOffset>
  918. <BitWidth>0x1</BitWidth>
  919. <Access>RW</Access>
  920. <Values>
  921. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  922. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  923. </Values>
  924. </Bit>
  925. <Bit>
  926. <Name>SRAM2_PE</Name>
  927. <Description>SRAM2 parity check enable</Description>
  928. <BitOffset>0x18</BitOffset>
  929. <BitWidth>0x1</BitWidth>
  930. <Access>RW</Access>
  931. <Values>
  932. <Val value="0x0">SRAM2 parity check enable</Val>
  933. <Val value="0x1">SRAM2 parity check disable</Val>
  934. </Values>
  935. </Bit>
  936. <Bit>
  937. <Name>SRAM2_RST</Name>
  938. <Description>SRAM2 Erase when system reset</Description>
  939. <BitOffset>0x19</BitOffset>
  940. <BitWidth>0x1</BitWidth>
  941. <Access>RW</Access>
  942. <Values>
  943. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  944. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  945. </Values>
  946. </Bit>
  947. <Bit>
  948. <Name>nSWBOOT0</Name>
  949. <Description>Software BOOT0</Description>
  950. <BitOffset>0x1A</BitOffset>
  951. <BitWidth>0x1</BitWidth>
  952. <Access>RW</Access>
  953. <Values>
  954. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  955. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  956. </Values>
  957. </Bit>
  958. <Bit>
  959. <Name>nBOOT0</Name>
  960. <Description>nBOOT0 option bit</Description>
  961. <BitOffset>0x1B</BitOffset>
  962. <BitWidth>0x1</BitWidth>
  963. <Access>RW</Access>
  964. <Values>
  965. <Val value="0x0">nBOOT0 = 0</Val>
  966. <Val value="0x1">nBOOT0 = 1</Val>
  967. </Values>
  968. </Bit>
  969. <Bit>
  970. <Name>PA15_PUPEN</Name>
  971. <Description>PA15 pull-up enable</Description>
  972. <BitOffset>0x1C</BitOffset>
  973. <BitWidth>0x1</BitWidth>
  974. <Access>RW</Access>
  975. <Values>
  976. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  977. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  978. </Values>
  979. </Bit>
  980. <Bit>
  981. <Name>BKPRAM_ECC</Name>
  982. <Description>SRAM2 parity check enable</Description>
  983. <BitOffset>0x16</BitOffset>
  984. <BitWidth>0x1</BitWidth>
  985. <Access>RW</Access>
  986. <Values>
  987. <Val value="0x0">Backup RAM ECC check enabled</Val>
  988. <Val value="0x1">Backup RAM ECC check disabled</Val>
  989. </Values>
  990. </Bit>
  991. <Bit>
  992. <Name>SRAM3_ECC</Name>
  993. <Description>SRAM3 ECC detection and correction enable</Description>
  994. <BitOffset>0x17</BitOffset>
  995. <BitWidth>0x1</BitWidth>
  996. <Access>RW</Access>
  997. <Values>
  998. <Val value="0x0">SRAM3 ECC check enabled</Val>
  999. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1000. </Values>
  1001. </Bit>
  1002. <Bit>
  1003. <Name>SRAM2_ECC</Name>
  1004. <Description>SRAM2 ECC detection and correction enable</Description>
  1005. <BitOffset>0x18</BitOffset>
  1006. <BitWidth>0x1</BitWidth>
  1007. <Access>RW</Access>
  1008. <Values>
  1009. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1010. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1011. </Values>
  1012. </Bit>
  1013. <Bit>
  1014. <Name>IO_VDD_HSLV</Name>
  1015. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1016. <BitOffset>0x1D</BitOffset>
  1017. <BitWidth>0x1</BitWidth>
  1018. <Access>RW</Access>
  1019. <Values>
  1020. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1021. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1022. </Values>
  1023. </Bit>
  1024. <Bit>
  1025. <Name>IO_VDDIO2_HSLV</Name>
  1026. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1027. <BitOffset>0x1E</BitOffset>
  1028. <BitWidth>0x1</BitWidth>
  1029. <Access>RW</Access>
  1030. <Values>
  1031. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1032. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1033. </Values>
  1034. </Bit>
  1035. </AssignedBits>
  1036. </Field>
  1037. </Category>
  1038. <Category>
  1039. <Name>Boot Configuration</Name>
  1040. <Field>
  1041. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1042. <AssignedBits>
  1043. <Bit>
  1044. <Name>NSBOOTADD0</Name>
  1045. <Description>Non-secure Boot base address 0</Description>
  1046. <BitOffset>0x7</BitOffset>
  1047. <BitWidth>0x19</BitWidth>
  1048. <Access>RW</Access>
  1049. <Equation multiplier="0x80" offset="0x0000000"/>
  1050. </Bit>
  1051. </AssignedBits>
  1052. </Field>
  1053. <Field>
  1054. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1055. <AssignedBits>
  1056. <Bit>
  1057. <Name>NSBOOTADD1</Name>
  1058. <Description>Non-secure Boot base address 1</Description>
  1059. <BitOffset>0x7</BitOffset>
  1060. <BitWidth>0x19</BitWidth>
  1061. <Access>RW</Access>
  1062. <Equation multiplier="0x80" offset="0x0000000"/>
  1063. </Bit>
  1064. </AssignedBits>
  1065. </Field>
  1066. <Field>
  1067. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1068. <AssignedBits>
  1069. <Bit>
  1070. <Name>SECBOOTADD0</Name>
  1071. <Description>Secure boot base address 0</Description>
  1072. <BitOffset>0x7</BitOffset>
  1073. <BitWidth>0x19</BitWidth>
  1074. <Access>RW</Access>
  1075. <Equation multiplier="0x80" offset="0x0000000"/>
  1076. </Bit>
  1077. </AssignedBits>
  1078. </Field>
  1079. <Field>
  1080. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  1081. <AssignedBits>
  1082. <Bit>
  1083. <Name>BOOT_LOCK</Name>
  1084. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1085. <BitOffset>0x0</BitOffset>
  1086. <BitWidth>0x1</BitWidth>
  1087. <Access>RW</Access>
  1088. <Values>
  1089. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1090. <Val value="0x1">Boot forced from base address memory</Val>
  1091. </Values>
  1092. </Bit>
  1093. </AssignedBits>
  1094. </Field>
  1095. </Category>
  1096. <Category>
  1097. <Name>Secure Area 1</Name>
  1098. <Field>
  1099. <Parameters address="0x50022050" name="FLASH_SECWM1R1" size="0x4"/>
  1100. <AssignedBits>
  1101. <Bit config="2">
  1102. <Name>SECWM1_PSTRT</Name>
  1103. <Description>Start page of first secure area</Description>
  1104. <BitOffset>0x0</BitOffset>
  1105. <BitWidth>0x8</BitWidth>
  1106. <Access>RW</Access>
  1107. <Equation multiplier="0x4000" offset="0x08000000"/>
  1108. </Bit>
  1109. <Bit config="3">
  1110. <Name>SECWM1_PSTRT</Name>
  1111. <Description>Start page of first secure area</Description>
  1112. <BitOffset>0x0</BitOffset>
  1113. <BitWidth>0x8</BitWidth>
  1114. <Access>RW</Access>
  1115. <Equation multiplier="0x2000" offset="0x08000000"/>
  1116. </Bit>
  1117. <Bit config="2">
  1118. <Name>SECWM1_PEND</Name>
  1119. <Description>End page of first secure area</Description>
  1120. <BitOffset>0x10</BitOffset>
  1121. <BitWidth>0x8</BitWidth>
  1122. <Access>RW</Access>
  1123. <Equation multiplier="0x4000" offset="0x08000000"/>
  1124. </Bit>
  1125. <Bit config="3">
  1126. <Name>SECWM1_PEND</Name>
  1127. <Description>End page of first secure area</Description>
  1128. <BitOffset>0x10</BitOffset>
  1129. <BitWidth>0x8</BitWidth>
  1130. <Access>RW</Access>
  1131. <Equation multiplier="0x2000" offset="0x08000000"/>
  1132. </Bit>
  1133. </AssignedBits>
  1134. </Field>
  1135. <Field>
  1136. <Parameters address="0x50022054" name="FLASH_SECWM1R2" size="0x4"/>
  1137. <AssignedBits>
  1138. <Bit>
  1139. <Name>HDP1_PEND</Name>
  1140. <Description>End page of first hide protection area</Description>
  1141. <BitOffset>0x10</BitOffset>
  1142. <BitWidth>0x8</BitWidth>
  1143. <Access>RW</Access>
  1144. <Equation multiplier="0x2000" offset="0xC000000"/>
  1145. </Bit>
  1146. <Bit>
  1147. <Name>HDP1EN</Name>
  1148. <Description>Hide protection first area enable</Description>
  1149. <BitOffset>0x1F</BitOffset>
  1150. <BitWidth>0x1</BitWidth>
  1151. <Access>RW</Access>
  1152. <Values>
  1153. <Val value="0x0">No HDP area 1</Val>
  1154. <Val value="0x1">HDP first area is enabled</Val>
  1155. </Values>
  1156. </Bit>
  1157. </AssignedBits>
  1158. </Field>
  1159. </Category>
  1160. <Category>
  1161. <Name>Write Protection 1</Name>
  1162. <Field>
  1163. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  1164. <AssignedBits>
  1165. <Bit config="2">
  1166. <Name>WRP1A_PSTRT</Name>
  1167. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1168. <BitOffset>0x0</BitOffset>
  1169. <BitWidth>0x8</BitWidth>
  1170. <Access>RW</Access>
  1171. <Equation multiplier="0x4000" offset="0x08000000"/>
  1172. </Bit>
  1173. <Bit config="3">
  1174. <Name>WRP1A_PSTRT</Name>
  1175. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1176. <BitOffset>0x0</BitOffset>
  1177. <BitWidth>0x8</BitWidth>
  1178. <Access>RW</Access>
  1179. <Equation multiplier="0x2000" offset="0x08000000"/>
  1180. </Bit>
  1181. <Bit config="2">
  1182. <Name>WRP1A_PEND</Name>
  1183. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1184. <BitOffset>0x10</BitOffset>
  1185. <BitWidth>0x8</BitWidth>
  1186. <Access>RW</Access>
  1187. <Equation multiplier="0x4000" offset="0x08000000"/>
  1188. </Bit>
  1189. <Bit config="3">
  1190. <Name>WRP1A_PEND</Name>
  1191. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1192. <BitOffset>0x10</BitOffset>
  1193. <BitWidth>0x8</BitWidth>
  1194. <Access>RW</Access>
  1195. <Equation multiplier="0x2000" offset="0x08000000"/>
  1196. </Bit>
  1197. <Bit>
  1198. <Name>UNLOCK_1A</Name>
  1199. <Description>Bank 1 WPR first area A unlock</Description>
  1200. <BitOffset>0x1F</BitOffset>
  1201. <BitWidth>0x1</BitWidth>
  1202. <Access>RW</Access>
  1203. <Values>
  1204. <Val value="0x0">WRP1A start and end pages locked</Val>
  1205. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1206. </Values>
  1207. </Bit>
  1208. </AssignedBits>
  1209. </Field>
  1210. <Field>
  1211. <Parameters address="0x5002205C" name="FLASH_WRP1BR" size="0x4"/>
  1212. <AssignedBits>
  1213. <Bit config="2">
  1214. <Name>WRP1B_PSTRT</Name>
  1215. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1216. <BitOffset>0x0</BitOffset>
  1217. <BitWidth>0x8</BitWidth>
  1218. <Access>RW</Access>
  1219. <Equation multiplier="0x4000" offset="0x08000000"/>
  1220. </Bit>
  1221. <Bit config="3">
  1222. <Name>WRP1B_PSTRT</Name>
  1223. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1224. <BitOffset>0x0</BitOffset>
  1225. <BitWidth>0x8</BitWidth>
  1226. <Access>RW</Access>
  1227. <Equation multiplier="0x2000" offset="0x08000000"/>
  1228. </Bit>
  1229. <Bit config="2">
  1230. <Name>WRP1B_PEND</Name>
  1231. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1232. <BitOffset>0x10</BitOffset>
  1233. <BitWidth>0x8</BitWidth>
  1234. <Access>RW</Access>
  1235. <Equation multiplier="0x4000" offset="0x08000000"/>
  1236. </Bit>
  1237. <Bit config="3">
  1238. <Name>WRP1B_PEND</Name>
  1239. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1240. <BitOffset>0x10</BitOffset>
  1241. <BitWidth>0x8</BitWidth>
  1242. <Access>RW</Access>
  1243. <Equation multiplier="0x2000" offset="0x08000000"/>
  1244. </Bit>
  1245. <Bit>
  1246. <Name>UNLOCK_1B</Name>
  1247. <Description>Bank 1 WPR first area B unlock</Description>
  1248. <BitOffset>0x1F</BitOffset>
  1249. <BitWidth>0x1</BitWidth>
  1250. <Access>RW</Access>
  1251. <Values>
  1252. <Val value="0x0">WRP1B start and end pages locked</Val>
  1253. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1254. </Values>
  1255. </Bit>
  1256. </AssignedBits>
  1257. </Field>
  1258. </Category>
  1259. </Bank>
  1260. <Bank interface="JTAG_SWD"> <!-- Bank 2: address="0x50022060" name="Bank 2" size="0x10"-->
  1261. <Parameters address="0x50022060" name="Bank 2" size="0x10"/>
  1262. <Category>
  1263. <Name>Secure Area 2</Name>
  1264. <Field>
  1265. <Parameters address="0x50022060" name="FLASH_SECWM2R1" size="0x4"/>
  1266. <AssignedBits>
  1267. <Bit config="2">
  1268. <Name>SECWM2_PSTRT</Name>
  1269. <Description>Start page of second secure area</Description>
  1270. <BitOffset>0x0</BitOffset>
  1271. <BitWidth>0x8</BitWidth>
  1272. <Access>RW</Access>
  1273. <Equation multiplier="0x4000" offset="0x08000000"/>
  1274. </Bit>
  1275. <Bit config="3">
  1276. <Name>SECWM2_PSTRT</Name>
  1277. <Description>Start page of second secure area</Description>
  1278. <BitOffset>0x0</BitOffset>
  1279. <BitWidth>0x8</BitWidth>
  1280. <Access>RW</Access>
  1281. <Equation multiplier="0x2000" offset="0x08200000"/>
  1282. </Bit>
  1283. <Bit config="2">
  1284. <Name>SECWM2_PEND</Name>
  1285. <Description>End page of second secure area</Description>
  1286. <BitOffset>0x10</BitOffset>
  1287. <BitWidth>0x8</BitWidth>
  1288. <Access>RW</Access>
  1289. <Equation multiplier="0x4000" offset="0x08000000"/>
  1290. </Bit>
  1291. <Bit config="3">
  1292. <Name>SECWM2_PEND</Name>
  1293. <Description>End page of second secure area</Description>
  1294. <BitOffset>0x10</BitOffset>
  1295. <BitWidth>0x8</BitWidth>
  1296. <Access>RW</Access>
  1297. <Equation multiplier="0x2000" offset="0x08200000"/>
  1298. </Bit>
  1299. </AssignedBits>
  1300. </Field>
  1301. <Field>
  1302. <Parameters address="0x50022064" name="FLASH_SECWM2R2" size="0x4"/>
  1303. <AssignedBits>
  1304. <Bit>
  1305. <Name>HDP2_PEND</Name>
  1306. <Description>End page of second hide protection area</Description>
  1307. <BitOffset>0x10</BitOffset>
  1308. <BitWidth>0x8</BitWidth>
  1309. <Access>RW</Access>
  1310. <Equation multiplier="0x2000" offset="0xC200000"/>
  1311. </Bit>
  1312. <Bit>
  1313. <Name>HDP2EN</Name>
  1314. <Description>Hide protection second area enable</Description>
  1315. <BitOffset>0x1F</BitOffset>
  1316. <BitWidth>0x1</BitWidth>
  1317. <Access>RW</Access>
  1318. <Values>
  1319. <Val value="0x0">No HDP area 2</Val>
  1320. <Val value="0x1">HDP second area is enabled</Val>
  1321. </Values>
  1322. </Bit>
  1323. </AssignedBits>
  1324. </Field>
  1325. </Category>
  1326. <Category>
  1327. <Name>Write Protection 2</Name>
  1328. <Field>
  1329. <Parameters address="0x50022068" name="FLASH_WRP2AR" size="0x4"/>
  1330. <AssignedBits>
  1331. <Bit config="2">
  1332. <Name>WRP2A_PSTRT</Name>
  1333. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1334. <BitOffset>0x0</BitOffset>
  1335. <BitWidth>0x8</BitWidth>
  1336. <Access>RW</Access>
  1337. <Equation multiplier="0x4000" offset="0x08200000"/>
  1338. </Bit>
  1339. <Bit config="3">
  1340. <Name>WRP2A_PSTRT</Name>
  1341. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1342. <BitOffset>0x0</BitOffset>
  1343. <BitWidth>0x8</BitWidth>
  1344. <Access>RW</Access>
  1345. <Equation multiplier="0x2000" offset="0x08200000"/>
  1346. </Bit>
  1347. <Bit config="2">
  1348. <Name>WRP2A_PEND</Name>
  1349. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1350. <BitOffset>0x10</BitOffset>
  1351. <BitWidth>0x8</BitWidth>
  1352. <Access>RW</Access>
  1353. <Equation multiplier="0x4000" offset="0x08200000"/>
  1354. </Bit>
  1355. <Bit config="3">
  1356. <Name>WRP2A_PEND</Name>
  1357. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1358. <BitOffset>0x10</BitOffset>
  1359. <BitWidth>0x8</BitWidth>
  1360. <Access>RW</Access>
  1361. <Equation multiplier="0x2000" offset="0x08200000"/>
  1362. </Bit>
  1363. <Bit>
  1364. <Name>UNLOCK_2A</Name>
  1365. <Description>Bank 2 WPR first area A unlock</Description>
  1366. <BitOffset>0x1F</BitOffset>
  1367. <BitWidth>0x1</BitWidth>
  1368. <Access>RW</Access>
  1369. <Values>
  1370. <Val value="0x0">WRP2A start and end pages locked</Val>
  1371. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1372. </Values>
  1373. </Bit>
  1374. </AssignedBits>
  1375. </Field>
  1376. <Field>
  1377. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  1378. <AssignedBits>
  1379. <Bit config="2">
  1380. <Name>WRP2B_PSTRT</Name>
  1381. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1382. <BitOffset>0x0</BitOffset>
  1383. <BitWidth>0x8</BitWidth>
  1384. <Access>RW</Access>
  1385. <Equation multiplier="0x4000" offset="0x08200000"/>
  1386. </Bit>
  1387. <Bit config="3">
  1388. <Name>WRP2B_PSTRT</Name>
  1389. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1390. <BitOffset>0x0</BitOffset>
  1391. <BitWidth>0x8</BitWidth>
  1392. <Access>RW</Access>
  1393. <Equation multiplier="0x2000" offset="0x08200000"/>
  1394. </Bit>
  1395. <Bit config="2">
  1396. <Name>WRP2B_PEND</Name>
  1397. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1398. <BitOffset>0x10</BitOffset>
  1399. <BitWidth>0x8</BitWidth>
  1400. <Access>RW</Access>
  1401. <Equation multiplier="0x4000" offset="0x08200000"/>
  1402. </Bit>
  1403. <Bit config="3">
  1404. <Name>WRP2B_PEND</Name>
  1405. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1406. <BitOffset>0x10</BitOffset>
  1407. <BitWidth>0x8</BitWidth>
  1408. <Access>RW</Access>
  1409. <Equation multiplier="0x2000" offset="0x08200000"/>
  1410. </Bit>
  1411. <Bit>
  1412. <Name>UNLOCK_2B</Name>
  1413. <Description>Bank 2 WPR first area B unlock</Description>
  1414. <BitOffset>0x1F</BitOffset>
  1415. <BitWidth>0x1</BitWidth>
  1416. <Access>RW</Access>
  1417. <Values>
  1418. <Val value="0x0">WRP2B start and end pages locked</Val>
  1419. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1420. </Values>
  1421. </Bit>
  1422. </AssignedBits>
  1423. </Field>
  1424. </Category>
  1425. </Bank>
  1426. </Configuration>
  1427. <Configuration config="4,5">
  1428. <Bank interface="JTAG_SWD"> <!-- Bank 1: address="0x40022040" name="Bank 1" size="0x28"-->
  1429. <Parameters address="0x40022040" name="Bank 1" size="0x28"/>
  1430. <Category>
  1431. <Name>Read Out Protection</Name>
  1432. <Field>
  1433. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1434. <AssignedBits>
  1435. <Bit>
  1436. <Name>RDP</Name>
  1437. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1438. <BitOffset>0x0</BitOffset>
  1439. <BitWidth>0x8</BitWidth>
  1440. <Access>RW</Access>
  1441. <Values>
  1442. <Val value="0xAA">Level 0, no protection</Val>
  1443. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1444. <Val value="0xDC">Level 1, read protection of memories</Val>
  1445. <Val value="0xCC">Level 2, chip protection</Val>
  1446. </Values>
  1447. </Bit>
  1448. </AssignedBits>
  1449. </Field>
  1450. </Category>
  1451. <Category>
  1452. <Name>BOR Level</Name>
  1453. <Field>
  1454. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1455. <AssignedBits>
  1456. <Bit>
  1457. <Name>BOR_LEV</Name>
  1458. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  1459. <BitOffset>0x8</BitOffset>
  1460. <BitWidth>0x3</BitWidth>
  1461. <Access>RW</Access>
  1462. <Values>
  1463. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1464. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1465. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1466. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1467. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1468. </Values>
  1469. </Bit>
  1470. </AssignedBits>
  1471. </Field>
  1472. </Category>
  1473. <Category>
  1474. <Name>User Configuration</Name>
  1475. <Field>
  1476. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1477. <AssignedBits>
  1478. <Bit>
  1479. <Name>TZEN</Name>
  1480. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneouslyDescription</Description>
  1481. <BitOffset>0x1F</BitOffset>
  1482. <BitWidth>0x1</BitWidth>
  1483. <Access>RW</Access>
  1484. <Values>
  1485. <Val value="0x0">Global TrustZone security disabled</Val>
  1486. <Val value="0x1">Global TrustZone security enabled</Val>
  1487. </Values>
  1488. </Bit>
  1489. <Bit>
  1490. <Name>nRST_STOP</Name>
  1491. <Description/>
  1492. <BitOffset>0xC</BitOffset>
  1493. <BitWidth>0x1</BitWidth>
  1494. <Access>RW</Access>
  1495. <Values>
  1496. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1497. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1498. </Values>
  1499. </Bit>
  1500. <Bit>
  1501. <Name>nRST_STDBY</Name>
  1502. <Description/>
  1503. <BitOffset>0xD</BitOffset>
  1504. <BitWidth>0x1</BitWidth>
  1505. <Access>RW</Access>
  1506. <Values>
  1507. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1508. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1509. </Values>
  1510. </Bit>
  1511. <Bit>
  1512. <Name>nRST_SHDW</Name>
  1513. <Description/>
  1514. <BitOffset>0xE</BitOffset>
  1515. <BitWidth>0x1</BitWidth>
  1516. <Access>RW</Access>
  1517. <Values>
  1518. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1519. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1520. </Values>
  1521. </Bit>
  1522. <Bit>
  1523. <Name>SRAM1345_RST</Name>
  1524. <Description>SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset</Description>
  1525. <BitOffset>0xF</BitOffset>
  1526. <BitWidth>0x1</BitWidth>
  1527. <Access>RW</Access>
  1528. <Values>
  1529. <Val value="0x0">SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs</Val>
  1530. <Val value="0x1">SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs</Val>
  1531. </Values>
  1532. </Bit>
  1533. <Bit>
  1534. <Name>IWDG_SW</Name>
  1535. <Description/>
  1536. <BitOffset>0x10</BitOffset>
  1537. <BitWidth>0x1</BitWidth>
  1538. <Access>RW</Access>
  1539. <Values>
  1540. <Val value="0x0">Hardware independant watchdog</Val>
  1541. <Val value="0x1">Software independant watchdog</Val>
  1542. </Values>
  1543. </Bit>
  1544. <Bit>
  1545. <Name>IWDG_STOP</Name>
  1546. <Description/>
  1547. <BitOffset>0x11</BitOffset>
  1548. <BitWidth>0x1</BitWidth>
  1549. <Access>RW</Access>
  1550. <Values>
  1551. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1552. <Val value="0x1">IWDG counter active in stop mode</Val>
  1553. </Values>
  1554. </Bit>
  1555. <Bit>
  1556. <Name>IWDG_STDBY</Name>
  1557. <Description/>
  1558. <BitOffset>0x12</BitOffset>
  1559. <BitWidth>0x1</BitWidth>
  1560. <Access>RW</Access>
  1561. <Values>
  1562. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1563. <Val value="0x1">IWDG counter active in standby mode</Val>
  1564. </Values>
  1565. </Bit>
  1566. <Bit>
  1567. <Name>WWDG_SW</Name>
  1568. <Description/>
  1569. <BitOffset>0x13</BitOffset>
  1570. <BitWidth>0x1</BitWidth>
  1571. <Access>RW</Access>
  1572. <Values>
  1573. <Val value="0x0">Hardware window watchdog</Val>
  1574. <Val value="0x1">Software window watchdog</Val>
  1575. </Values>
  1576. </Bit>
  1577. <Bit>
  1578. <Name>SWAP_BANK</Name>
  1579. <Description/>
  1580. <BitOffset>0x14</BitOffset>
  1581. <BitWidth>0x1</BitWidth>
  1582. <Access>RW</Access>
  1583. <Values>
  1584. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1585. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1586. </Values>
  1587. </Bit>
  1588. <Bit>
  1589. <Name>DBANK</Name>
  1590. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  1591. <BitOffset>0x15</BitOffset>
  1592. <BitWidth>0x1</BitWidth>
  1593. <Access>RW</Access>
  1594. <Values>
  1595. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1596. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1597. </Values>
  1598. </Bit>
  1599. <Bit>
  1600. <Name>SRAM2_PE</Name>
  1601. <Description>SRAM2 parity check enable</Description>
  1602. <BitOffset>0x18</BitOffset>
  1603. <BitWidth>0x1</BitWidth>
  1604. <Access>RW</Access>
  1605. <Values>
  1606. <Val value="0x0">SRAM2 parity check enable</Val>
  1607. <Val value="0x1">SRAM2 parity check disable</Val>
  1608. </Values>
  1609. </Bit>
  1610. <Bit>
  1611. <Name>SRAM2_RST</Name>
  1612. <Description>SRAM2 Erase when system reset</Description>
  1613. <BitOffset>0x19</BitOffset>
  1614. <BitWidth>0x1</BitWidth>
  1615. <Access>RW</Access>
  1616. <Values>
  1617. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1618. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1619. </Values>
  1620. </Bit>
  1621. <Bit>
  1622. <Name>nSWBOOT0</Name>
  1623. <Description>Software BOOT0</Description>
  1624. <BitOffset>0x1A</BitOffset>
  1625. <BitWidth>0x1</BitWidth>
  1626. <Access>RW</Access>
  1627. <Values>
  1628. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1629. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1630. </Values>
  1631. </Bit>
  1632. <Bit>
  1633. <Name>nBOOT0</Name>
  1634. <Description>nBOOT0 option bit</Description>
  1635. <BitOffset>0x1B</BitOffset>
  1636. <BitWidth>0x1</BitWidth>
  1637. <Access>RW</Access>
  1638. <Values>
  1639. <Val value="0x0">nBOOT0 = 0</Val>
  1640. <Val value="0x1">nBOOT0 = 1</Val>
  1641. </Values>
  1642. </Bit>
  1643. <Bit>
  1644. <Name>PA15_PUPEN</Name>
  1645. <Description>PA15 pull-up enable</Description>
  1646. <BitOffset>0x1C</BitOffset>
  1647. <BitWidth>0x1</BitWidth>
  1648. <Access>RW</Access>
  1649. <Values>
  1650. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1651. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1652. </Values>
  1653. </Bit>
  1654. <Bit>
  1655. <Name>BKPRAM_ECC</Name>
  1656. <Description>SRAM2 parity check enable</Description>
  1657. <BitOffset>0x16</BitOffset>
  1658. <BitWidth>0x1</BitWidth>
  1659. <Access>RW</Access>
  1660. <Values>
  1661. <Val value="0x0">Backup RAM ECC check enabled</Val>
  1662. <Val value="0x1">Backup RAM ECC check disabled</Val>
  1663. </Values>
  1664. </Bit>
  1665. <Bit>
  1666. <Name>SRAM3_ECC</Name>
  1667. <Description>SRAM3 ECC detection and correction enable</Description>
  1668. <BitOffset>0x17</BitOffset>
  1669. <BitWidth>0x1</BitWidth>
  1670. <Access>RW</Access>
  1671. <Values>
  1672. <Val value="0x0">SRAM3 ECC check enabled</Val>
  1673. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1674. </Values>
  1675. </Bit>
  1676. <Bit>
  1677. <Name>SRAM2_ECC</Name>
  1678. <Description>SRAM2 ECC detection and correction enable</Description>
  1679. <BitOffset>0x18</BitOffset>
  1680. <BitWidth>0x1</BitWidth>
  1681. <Access>RW</Access>
  1682. <Values>
  1683. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1684. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1685. </Values>
  1686. </Bit>
  1687. <Bit>
  1688. <Name>IO_VDD_HSLV</Name>
  1689. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1690. <BitOffset>0x1D</BitOffset>
  1691. <BitWidth>0x1</BitWidth>
  1692. <Access>RW</Access>
  1693. <Values>
  1694. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1695. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1696. </Values>
  1697. </Bit>
  1698. <Bit>
  1699. <Name>IO_VDDIO2_HSLV</Name>
  1700. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1701. <BitOffset>0x1E</BitOffset>
  1702. <BitWidth>0x1</BitWidth>
  1703. <Access>RW</Access>
  1704. <Values>
  1705. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1706. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1707. </Values>
  1708. </Bit>
  1709. </AssignedBits>
  1710. </Field>
  1711. </Category>
  1712. <Category>
  1713. <Name>Boot Configuration</Name>
  1714. <Field>
  1715. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1716. <AssignedBits>
  1717. <Bit>
  1718. <Name>NSBOOTADD0</Name>
  1719. <Description>Non-secure Boot base address 0</Description>
  1720. <BitOffset>0x7</BitOffset>
  1721. <BitWidth>0x19</BitWidth>
  1722. <Access>RW</Access>
  1723. <Equation multiplier="0x80" offset="0x0000000"/>
  1724. </Bit>
  1725. </AssignedBits>
  1726. </Field>
  1727. <Field>
  1728. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1729. <AssignedBits>
  1730. <Bit>
  1731. <Name>NSBOOTADD1</Name>
  1732. <Description>Non-secure Boot base address 1</Description>
  1733. <BitOffset>0x7</BitOffset>
  1734. <BitWidth>0x19</BitWidth>
  1735. <Access>RW</Access>
  1736. <Equation multiplier="0x80" offset="0x0000000"/>
  1737. </Bit>
  1738. </AssignedBits>
  1739. </Field>
  1740. <Field>
  1741. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1742. <AssignedBits>
  1743. <Bit>
  1744. <Name>SECBOOTADD0</Name>
  1745. <Description>Secure boot base address 0</Description>
  1746. <BitOffset>0x7</BitOffset>
  1747. <BitWidth>0x19</BitWidth>
  1748. <Access>RW</Access>
  1749. <Equation multiplier="0x80" offset="0x0000000"/>
  1750. </Bit>
  1751. </AssignedBits>
  1752. </Field>
  1753. <Field>
  1754. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1755. <AssignedBits>
  1756. <Bit>
  1757. <Name>BOOT_LOCK</Name>
  1758. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1759. <BitOffset>0x0</BitOffset>
  1760. <BitWidth>0x1</BitWidth>
  1761. <Access>RW</Access>
  1762. <Values>
  1763. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1764. <Val value="0x1">Boot forced from base address memory</Val>
  1765. </Values>
  1766. </Bit>
  1767. </AssignedBits>
  1768. </Field>
  1769. </Category>
  1770. <Category>
  1771. <Name>Secure Area 1</Name>
  1772. <Field>
  1773. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  1774. <AssignedBits>
  1775. <Bit config="4">
  1776. <Name>SECWM1_PSTRT</Name>
  1777. <Description>Start page of first secure area</Description>
  1778. <BitOffset>0x0</BitOffset>
  1779. <BitWidth>0x8</BitWidth>
  1780. <Access>RW</Access>
  1781. <Equation multiplier="0x4000" offset="0x08000000"/>
  1782. </Bit>
  1783. <Bit config="5">
  1784. <Name>SECWM1_PSTRT</Name>
  1785. <Description>Start page of first secure area</Description>
  1786. <BitOffset>0x0</BitOffset>
  1787. <BitWidth>0x8</BitWidth>
  1788. <Access>RW</Access>
  1789. <Equation multiplier="0x2000" offset="0x08000000"/>
  1790. </Bit>
  1791. <Bit config="4">
  1792. <Name>SECWM1_PEND</Name>
  1793. <Description>End page of first secure area</Description>
  1794. <BitOffset>0x10</BitOffset>
  1795. <BitWidth>0x8</BitWidth>
  1796. <Access>RW</Access>
  1797. <Equation multiplier="0x4000" offset="0x08000000"/>
  1798. </Bit>
  1799. <Bit config="5">
  1800. <Name>SECWM1_PEND</Name>
  1801. <Description>End page of first secure area</Description>
  1802. <BitOffset>0x10</BitOffset>
  1803. <BitWidth>0x8</BitWidth>
  1804. <Access>RW</Access>
  1805. <Equation multiplier="0x2000" offset="0x08000000"/>
  1806. </Bit>
  1807. </AssignedBits>
  1808. </Field>
  1809. <Field>
  1810. <Parameters address="0x40022054" name="FLASH_SECWM1R2" size="0x4"/>
  1811. <AssignedBits>
  1812. <Bit>
  1813. <Name>HDP1_PEND</Name>
  1814. <Description>End page of first hide protection area</Description>
  1815. <BitOffset>0x10</BitOffset>
  1816. <BitWidth>0x8</BitWidth>
  1817. <Access>RW</Access>
  1818. <Equation multiplier="0x2000" offset="0xC000000"/>
  1819. </Bit>
  1820. <Bit>
  1821. <Name>HDP1EN</Name>
  1822. <Description>Hide protection first area enable</Description>
  1823. <BitOffset>0x1F</BitOffset>
  1824. <BitWidth>0x1</BitWidth>
  1825. <Access>RW</Access>
  1826. <Values>
  1827. <Val value="0x0">No HDP area 1</Val>
  1828. <Val value="0x1">HDP first area is enabled</Val>
  1829. </Values>
  1830. </Bit>
  1831. </AssignedBits>
  1832. </Field>
  1833. </Category>
  1834. <Category>
  1835. <Name>Write Protection 1</Name>
  1836. <Field>
  1837. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  1838. <AssignedBits>
  1839. <Bit config="4">
  1840. <Name>WRP1A_PSTRT</Name>
  1841. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1842. <BitOffset>0x0</BitOffset>
  1843. <BitWidth>0x8</BitWidth>
  1844. <Access>RW</Access>
  1845. <Equation multiplier="0x4000" offset="0x08000000"/>
  1846. </Bit>
  1847. <Bit config="5">
  1848. <Name>WRP1A_PSTRT</Name>
  1849. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1850. <BitOffset>0x0</BitOffset>
  1851. <BitWidth>0x8</BitWidth>
  1852. <Access>RW</Access>
  1853. <Equation multiplier="0x2000" offset="0x08000000"/>
  1854. </Bit>
  1855. <Bit config="4">
  1856. <Name>WRP1A_PEND</Name>
  1857. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1858. <BitOffset>0x10</BitOffset>
  1859. <BitWidth>0x8</BitWidth>
  1860. <Access>RW</Access>
  1861. <Equation multiplier="0x4000" offset="0x08000000"/>
  1862. </Bit>
  1863. <Bit config="5">
  1864. <Name>WRP1A_PEND</Name>
  1865. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1866. <BitOffset>0x10</BitOffset>
  1867. <BitWidth>0x8</BitWidth>
  1868. <Access>RW</Access>
  1869. <Equation multiplier="0x2000" offset="0x08000000"/>
  1870. </Bit>
  1871. <Bit>
  1872. <Name>UNLOCK_1A</Name>
  1873. <Description>Bank 1 WPR first area A unlock</Description>
  1874. <BitOffset>0x1F</BitOffset>
  1875. <BitWidth>0x1</BitWidth>
  1876. <Access>RW</Access>
  1877. <Values>
  1878. <Val value="0x0">WRP1A start and end pages locked</Val>
  1879. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1880. </Values>
  1881. </Bit>
  1882. </AssignedBits>
  1883. </Field>
  1884. <Field>
  1885. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  1886. <AssignedBits>
  1887. <Bit config="4">
  1888. <Name>WRP1B_PSTRT</Name>
  1889. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1890. <BitOffset>0x0</BitOffset>
  1891. <BitWidth>0x8</BitWidth>
  1892. <Access>RW</Access>
  1893. <Equation multiplier="0x4000" offset="0x08000000"/>
  1894. </Bit>
  1895. <Bit config="5">
  1896. <Name>WRP1B_PSTRT</Name>
  1897. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1898. <BitOffset>0x0</BitOffset>
  1899. <BitWidth>0x8</BitWidth>
  1900. <Access>RW</Access>
  1901. <Equation multiplier="0x2000" offset="0x08000000"/>
  1902. </Bit>
  1903. <Bit config="4">
  1904. <Name>WRP1B_PEND</Name>
  1905. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1906. <BitOffset>0x10</BitOffset>
  1907. <BitWidth>0x8</BitWidth>
  1908. <Access>RW</Access>
  1909. <Equation multiplier="0x4000" offset="0x08000000"/>
  1910. </Bit>
  1911. <Bit config="5">
  1912. <Name>WRP1B_PEND</Name>
  1913. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1914. <BitOffset>0x10</BitOffset>
  1915. <BitWidth>0x8</BitWidth>
  1916. <Access>RW</Access>
  1917. <Equation multiplier="0x2000" offset="0x08000000"/>
  1918. </Bit>
  1919. <Bit>
  1920. <Name>UNLOCK_1B</Name>
  1921. <Description>Bank 1 WPR first area B unlock</Description>
  1922. <BitOffset>0x1F</BitOffset>
  1923. <BitWidth>0x1</BitWidth>
  1924. <Access>RW</Access>
  1925. <Values>
  1926. <Val value="0x0">WRP1B start and end pages locked</Val>
  1927. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1928. </Values>
  1929. </Bit>
  1930. </AssignedBits>
  1931. </Field>
  1932. </Category>
  1933. </Bank>
  1934. <Bank interface="JTAG_SWD"> <!-- Bank 2: address="0x40022060" name="Bank 2" size="0x10"-->
  1935. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  1936. <Category>
  1937. <Name>Secure Area 2</Name>
  1938. <Field>
  1939. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  1940. <AssignedBits>
  1941. <Bit config="4">
  1942. <Name>SECWM2_PSTRT</Name>
  1943. <Description>Start page of second secure area</Description>
  1944. <BitOffset>0x0</BitOffset>
  1945. <BitWidth>0x8</BitWidth>
  1946. <Access>RW</Access>
  1947. <Equation multiplier="0x4000" offset="0x08000000"/>
  1948. </Bit>
  1949. <Bit config="5">
  1950. <Name>SECWM2_PSTRT</Name>
  1951. <Description>Start page of second secure area</Description>
  1952. <BitOffset>0x0</BitOffset>
  1953. <BitWidth>0x8</BitWidth>
  1954. <Access>RW</Access>
  1955. <Equation multiplier="0x2000" offset="0x08200000"/>
  1956. </Bit>
  1957. <Bit config="4">
  1958. <Name>SECWM2_PEND</Name>
  1959. <Description>End page of second secure area</Description>
  1960. <BitOffset>0x10</BitOffset>
  1961. <BitWidth>0x8</BitWidth>
  1962. <Access>RW</Access>
  1963. <Equation multiplier="0x4000" offset="0x08000000"/>
  1964. </Bit>
  1965. <Bit config="5">
  1966. <Name>SECWM2_PEND</Name>
  1967. <Description>End page of second secure area</Description>
  1968. <BitOffset>0x10</BitOffset>
  1969. <BitWidth>0x8</BitWidth>
  1970. <Access>RW</Access>
  1971. <Equation multiplier="0x2000" offset="0x08200000"/>
  1972. </Bit>
  1973. </AssignedBits>
  1974. </Field>
  1975. <Field>
  1976. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  1977. <AssignedBits>
  1978. <Bit config="4">
  1979. <Name>HDP2_PEND</Name>
  1980. <Description>End page of second hide protection area</Description>
  1981. <BitOffset>0x10</BitOffset>
  1982. <BitWidth>0x8</BitWidth>
  1983. <Access>RW</Access>
  1984. <Equation multiplier="0x2000" offset="0xC200000"/>
  1985. </Bit>
  1986. <Bit config="4">
  1987. <Name>HDP2EN</Name>
  1988. <Description>Hide protection second area enable</Description>
  1989. <BitOffset>0x1F</BitOffset>
  1990. <BitWidth>0x1</BitWidth>
  1991. <Access>RW</Access>
  1992. <Values>
  1993. <Val value="0x0">No HDP area 2</Val>
  1994. <Val value="0x1">HDP second area is enabled</Val>
  1995. </Values>
  1996. </Bit>
  1997. <Bit config="5">
  1998. <Name>HDP2_PEND</Name>
  1999. <Description>End page of second hide protection area</Description>
  2000. <BitOffset>0x10</BitOffset>
  2001. <BitWidth>0x8</BitWidth>
  2002. <Access>RW</Access>
  2003. <Equation multiplier="0x2000" offset="0xC200000"/>
  2004. </Bit>
  2005. <Bit config="5">
  2006. <Name>HDP2EN</Name>
  2007. <Description>Hide protection second area enable</Description>
  2008. <BitOffset>0x1F</BitOffset>
  2009. <BitWidth>0x1</BitWidth>
  2010. <Access>RW</Access>
  2011. <Values>
  2012. <Val value="0x0">No HDP area 2</Val>
  2013. <Val value="0x1">HDP second area is enabled</Val>
  2014. </Values>
  2015. </Bit>
  2016. </AssignedBits>
  2017. </Field>
  2018. </Category>
  2019. <Category>
  2020. <Name>Write Protection 2</Name>
  2021. <Field>
  2022. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2023. <AssignedBits>
  2024. <Bit config="4">
  2025. <Name>WRP2A_PSTRT</Name>
  2026. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2027. <BitOffset>0x0</BitOffset>
  2028. <BitWidth>0x8</BitWidth>
  2029. <Access>RW</Access>
  2030. <Equation multiplier="0x4000" offset="0x08200000"/>
  2031. </Bit>
  2032. <Bit config="5">
  2033. <Name>WRP2A_PSTRT</Name>
  2034. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2035. <BitOffset>0x0</BitOffset>
  2036. <BitWidth>0x8</BitWidth>
  2037. <Access>RW</Access>
  2038. <Equation multiplier="0x2000" offset="0x08200000"/>
  2039. </Bit>
  2040. <Bit config="4">
  2041. <Name>WRP2A_PEND</Name>
  2042. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2043. <BitOffset>0x10</BitOffset>
  2044. <BitWidth>0x8</BitWidth>
  2045. <Access>RW</Access>
  2046. <Equation multiplier="0x4000" offset="0x08200000"/>
  2047. </Bit>
  2048. <Bit config="5">
  2049. <Name>WRP2A_PEND</Name>
  2050. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2051. <BitOffset>0x10</BitOffset>
  2052. <BitWidth>0x8</BitWidth>
  2053. <Access>RW</Access>
  2054. <Equation multiplier="0x2000" offset="0x08200000"/>
  2055. </Bit>
  2056. <Bit>
  2057. <Name>UNLOCK_2A</Name>
  2058. <Description>Bank 2 WPR first area A unlock</Description>
  2059. <BitOffset>0x1F</BitOffset>
  2060. <BitWidth>0x1</BitWidth>
  2061. <Access>RW</Access>
  2062. <Values>
  2063. <Val value="0x0">WRP2A start and end pages locked</Val>
  2064. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2065. </Values>
  2066. </Bit>
  2067. </AssignedBits>
  2068. </Field>
  2069. <Field>
  2070. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2071. <AssignedBits>
  2072. <Bit config="4">
  2073. <Name>WRP2B_PSTRT</Name>
  2074. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2075. <BitOffset>0x0</BitOffset>
  2076. <BitWidth>0x8</BitWidth>
  2077. <Access>RW</Access>
  2078. <Equation multiplier="0x4000" offset="0x08200000"/>
  2079. </Bit>
  2080. <Bit config="5">
  2081. <Name>WRP2B_PSTRT</Name>
  2082. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2083. <BitOffset>0x0</BitOffset>
  2084. <BitWidth>0x8</BitWidth>
  2085. <Access>RW</Access>
  2086. <Equation multiplier="0x2000" offset="0x08200000"/>
  2087. </Bit>
  2088. <Bit config="4">
  2089. <Name>WRP2B_PEND</Name>
  2090. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2091. <BitOffset>0x10</BitOffset>
  2092. <BitWidth>0x8</BitWidth>
  2093. <Access>RW</Access>
  2094. <Equation multiplier="0x4000" offset="0x08200000"/>
  2095. </Bit>
  2096. <Bit config="5">
  2097. <Name>WRP2B_PEND</Name>
  2098. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2099. <BitOffset>0x10</BitOffset>
  2100. <BitWidth>0x8</BitWidth>
  2101. <Access>RW</Access>
  2102. <Equation multiplier="0x2000" offset="0x08200000"/>
  2103. </Bit>
  2104. <Bit>
  2105. <Name>UNLOCK_2B</Name>
  2106. <Description>Bank 2 WPR first area B unlock</Description>
  2107. <BitOffset>0x1F</BitOffset>
  2108. <BitWidth>0x1</BitWidth>
  2109. <Access>RW</Access>
  2110. <Values>
  2111. <Val value="0x0">WRP2B start and end pages locked</Val>
  2112. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2113. </Values>
  2114. </Bit>
  2115. </AssignedBits>
  2116. </Field>
  2117. </Category>
  2118. </Bank>
  2119. </Configuration>
  2120. <Bank interface="Bootloader">
  2121. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  2122. <Category>
  2123. <Name>Read Out Protection</Name>
  2124. <Field>
  2125. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2126. <AssignedBits>
  2127. <Bit>
  2128. <Name>RDP</Name>
  2129. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  2130. <BitOffset>0x0</BitOffset>
  2131. <BitWidth>0x8</BitWidth>
  2132. <Access>RW</Access>
  2133. <Values>
  2134. <Val value="0xAA">Level 0, no protection</Val>
  2135. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  2136. <Val value="0xDC">Level 1, read protection of memories</Val>
  2137. <Val value="0xCC">Level 2, chip protection</Val>
  2138. </Values>
  2139. </Bit>
  2140. </AssignedBits>
  2141. </Field>
  2142. </Category>
  2143. <Category>
  2144. <Name>BOR Level</Name>
  2145. <Field>
  2146. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2147. <AssignedBits>
  2148. <Bit>
  2149. <Name>BOR_LEV</Name>
  2150. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  2151. <BitOffset>0x8</BitOffset>
  2152. <BitWidth>0x3</BitWidth>
  2153. <Access>RW</Access>
  2154. <Values>
  2155. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  2156. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  2157. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  2158. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  2159. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  2160. </Values>
  2161. </Bit>
  2162. </AssignedBits>
  2163. </Field>
  2164. </Category>
  2165. <Category>
  2166. <Name>User Configuration</Name>
  2167. <Field>
  2168. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2169. <AssignedBits>
  2170. <Bit>
  2171. <Name>TZEN</Name>
  2172. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  2173. <BitOffset>0x1F</BitOffset>
  2174. <BitWidth>0x1</BitWidth>
  2175. <Access>RW</Access>
  2176. <Values>
  2177. <Val value="0x0">Global TrustZone security disabled</Val>
  2178. <Val value="0x1">Global TrustZone security enabled</Val>
  2179. </Values>
  2180. </Bit>
  2181. <Bit>
  2182. <Name>nRST_STOP</Name>
  2183. <Description/>
  2184. <BitOffset>0xC</BitOffset>
  2185. <BitWidth>0x1</BitWidth>
  2186. <Access>RW</Access>
  2187. <Values>
  2188. <Val value="0x0">Reset generated when entering Stop mode</Val>
  2189. <Val value="0x1">No reset generated when entering Stop mode</Val>
  2190. </Values>
  2191. </Bit>
  2192. <Bit>
  2193. <Name>nRST_STDBY</Name>
  2194. <Description/>
  2195. <BitOffset>0xD</BitOffset>
  2196. <BitWidth>0x1</BitWidth>
  2197. <Access>RW</Access>
  2198. <Values>
  2199. <Val value="0x0">Reset generated when entering Standby mode</Val>
  2200. <Val value="0x1">No reset generated when entering Standby mode</Val>
  2201. </Values>
  2202. </Bit>
  2203. <Bit>
  2204. <Name>nRST_SHDW</Name>
  2205. <Description/>
  2206. <BitOffset>0xE</BitOffset>
  2207. <BitWidth>0x1</BitWidth>
  2208. <Access>RW</Access>
  2209. <Values>
  2210. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  2211. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  2212. </Values>
  2213. </Bit>
  2214. <Bit>
  2215. <Name>SRAM1345_RST</Name>
  2216. <Description>SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset</Description>
  2217. <BitOffset>0xF</BitOffset>
  2218. <BitWidth>0x1</BitWidth>
  2219. <Access>RW</Access>
  2220. <Values>
  2221. <Val value="0x0">SRAM1, SRAM3,SRAM4 and SRAM5 erased when a system reset occurs</Val>
  2222. <Val value="0x1">SRAM1, SRAM3,SRAM4 and SRAM5 not erased when a system reset occurs</Val>
  2223. </Values>
  2224. </Bit>
  2225. <Bit>
  2226. <Name>IWDG_SW</Name>
  2227. <Description/>
  2228. <BitOffset>0x10</BitOffset>
  2229. <BitWidth>0x1</BitWidth>
  2230. <Access>RW</Access>
  2231. <Values>
  2232. <Val value="0x0">Hardware independant watchdog</Val>
  2233. <Val value="0x1">Software independant watchdog</Val>
  2234. </Values>
  2235. </Bit>
  2236. <Bit>
  2237. <Name>IWDG_STOP</Name>
  2238. <Description/>
  2239. <BitOffset>0x11</BitOffset>
  2240. <BitWidth>0x1</BitWidth>
  2241. <Access>RW</Access>
  2242. <Values>
  2243. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  2244. <Val value="0x1">IWDG counter active in stop mode</Val>
  2245. </Values>
  2246. </Bit>
  2247. <Bit>
  2248. <Name>IWDG_STDBY</Name>
  2249. <Description/>
  2250. <BitOffset>0x12</BitOffset>
  2251. <BitWidth>0x1</BitWidth>
  2252. <Access>RW</Access>
  2253. <Values>
  2254. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  2255. <Val value="0x1">IWDG counter active in standby mode</Val>
  2256. </Values>
  2257. </Bit>
  2258. <Bit>
  2259. <Name>WWDG_SW</Name>
  2260. <Description/>
  2261. <BitOffset>0x13</BitOffset>
  2262. <BitWidth>0x1</BitWidth>
  2263. <Access>RW</Access>
  2264. <Values>
  2265. <Val value="0x0">Hardware window watchdog</Val>
  2266. <Val value="0x1">Software window watchdog</Val>
  2267. </Values>
  2268. </Bit>
  2269. <Bit>
  2270. <Name>SWAP_BANK</Name>
  2271. <Description/>
  2272. <BitOffset>0x14</BitOffset>
  2273. <BitWidth>0x1</BitWidth>
  2274. <Access>RW</Access>
  2275. <Values>
  2276. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  2277. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  2278. </Values>
  2279. </Bit>
  2280. <Bit>
  2281. <Name>DBANK</Name>
  2282. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  2283. <BitOffset>0x15</BitOffset>
  2284. <BitWidth>0x1</BitWidth>
  2285. <Access>RW</Access>
  2286. <Values>
  2287. <Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
  2288. <Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
  2289. </Values>
  2290. </Bit>
  2291. <Bit>
  2292. <Name>BKPRAM_ECC</Name>
  2293. <Description>SRAM2 parity check enable</Description>
  2294. <BitOffset>0x16</BitOffset>
  2295. <BitWidth>0x1</BitWidth>
  2296. <Access>RW</Access>
  2297. <Values>
  2298. <Val value="0x0">Backup RAM ECC check enabled</Val>
  2299. <Val value="0x1">Backup RAM ECC check disabled</Val>
  2300. </Values>
  2301. </Bit>
  2302. <Bit>
  2303. <Name>SRAM3_ECC</Name>
  2304. <Description>SRAM3 ECC detection and correction enable</Description>
  2305. <BitOffset>0x17</BitOffset>
  2306. <BitWidth>0x1</BitWidth>
  2307. <Access>RW</Access>
  2308. <Values>
  2309. <Val value="0x0">SRAM3 ECC check enabled</Val>
  2310. <Val value="0x1">SRAM3 ECC check disabled</Val>
  2311. </Values>
  2312. </Bit>
  2313. <Bit>
  2314. <Name>SRAM2_ECC</Name>
  2315. <Description>SRAM2 ECC detection and correction enable</Description>
  2316. <BitOffset>0x18</BitOffset>
  2317. <BitWidth>0x1</BitWidth>
  2318. <Access>RW</Access>
  2319. <Values>
  2320. <Val value="0x0">SRAM2 ECC check enabled</Val>
  2321. <Val value="0x1">SRAM2 ECC check disabled</Val>
  2322. </Values>
  2323. </Bit>
  2324. <Bit>
  2325. <Name>SRAM2_RST</Name>
  2326. <Description>SRAM2 Erase when system reset</Description>
  2327. <BitOffset>0x19</BitOffset>
  2328. <BitWidth>0x1</BitWidth>
  2329. <Access>RW</Access>
  2330. <Values>
  2331. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  2332. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  2333. </Values>
  2334. </Bit>
  2335. <Bit>
  2336. <Name>nSWBOOT0</Name>
  2337. <Description>Software BOOT0</Description>
  2338. <BitOffset>0x1A</BitOffset>
  2339. <BitWidth>0x1</BitWidth>
  2340. <Access>RW</Access>
  2341. <Values>
  2342. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  2343. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  2344. </Values>
  2345. </Bit>
  2346. <Bit>
  2347. <Name>nBOOT0</Name>
  2348. <Description>nBOOT0 option bit</Description>
  2349. <BitOffset>0x1B</BitOffset>
  2350. <BitWidth>0x1</BitWidth>
  2351. <Access>RW</Access>
  2352. <Values>
  2353. <Val value="0x0">nBOOT0 = 0</Val>
  2354. <Val value="0x1">nBOOT0 = 1</Val>
  2355. </Values>
  2356. </Bit>
  2357. <Bit>
  2358. <Name>PA15_PUPEN</Name>
  2359. <Description>PA15 pull-up enable</Description>
  2360. <BitOffset>0x1C</BitOffset>
  2361. <BitWidth>0x1</BitWidth>
  2362. <Access>RW</Access>
  2363. <Values>
  2364. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  2365. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  2366. </Values>
  2367. </Bit>
  2368. <Bit>
  2369. <Name>IO_VDD_HSLV</Name>
  2370. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  2371. <BitOffset>0x1D</BitOffset>
  2372. <BitWidth>0x1</BitWidth>
  2373. <Access>RW</Access>
  2374. <Values>
  2375. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  2376. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  2377. </Values>
  2378. </Bit>
  2379. <Bit>
  2380. <Name>IO_VDDIO2_HSLV</Name>
  2381. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  2382. <BitOffset>0x1E</BitOffset>
  2383. <BitWidth>0x1</BitWidth>
  2384. <Access>RW</Access>
  2385. <Values>
  2386. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  2387. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  2388. </Values>
  2389. </Bit>
  2390. </AssignedBits>
  2391. </Field>
  2392. </Category>
  2393. <Category>
  2394. <Name>Boot Configuration</Name>
  2395. <Field>
  2396. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2397. <AssignedBits>
  2398. <Bit config="6,7,8,9">
  2399. <Name>NSBOOTADD0</Name>
  2400. <Description>Non-secure Boot base address 0</Description>
  2401. <BitOffset>0x7</BitOffset>
  2402. <BitWidth>0x19</BitWidth>
  2403. <Access>RW</Access>
  2404. <Equation multiplier="0x80" offset="0x0000000"/>
  2405. </Bit>
  2406. </AssignedBits>
  2407. </Field>
  2408. <Field>
  2409. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2410. <AssignedBits>
  2411. <Bit config="6,7,8,9">
  2412. <Name>NSBOOTADD1</Name>
  2413. <Description>Non-secure Boot base address 1</Description>
  2414. <BitOffset>0x7</BitOffset>
  2415. <BitWidth>0x19</BitWidth>
  2416. <Access>RW</Access>
  2417. <Equation multiplier="0x80" offset="0x0000000"/>
  2418. </Bit>
  2419. </AssignedBits>
  2420. </Field>
  2421. <Field>
  2422. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  2423. <AssignedBits>
  2424. <Bit config="8,9">
  2425. <Name>SECBOOTADD0</Name>
  2426. <Description>Secure boot base address 0</Description>
  2427. <BitOffset>0x7</BitOffset>
  2428. <BitWidth>0x19</BitWidth>
  2429. <Access>RW</Access>
  2430. <Equation multiplier="0x80" offset="0x0000000"/>
  2431. </Bit>
  2432. </AssignedBits>
  2433. </Field>
  2434. <Field>
  2435. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  2436. <AssignedBits>
  2437. <Bit config="8,9">
  2438. <Name>BOOT_LOCK</Name>
  2439. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  2440. <BitOffset>0x0</BitOffset>
  2441. <BitWidth>0x1</BitWidth>
  2442. <Access>RW</Access>
  2443. <Values>
  2444. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  2445. <Val value="0x1">Boot forced from base address memory</Val>
  2446. </Values>
  2447. </Bit>
  2448. </AssignedBits>
  2449. </Field>
  2450. </Category>
  2451. <Category>
  2452. <Name>Secure Area 1</Name>
  2453. <Field>
  2454. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  2455. <AssignedBits>
  2456. <Bit config="8">
  2457. <Name>SECWM1_PSTRT</Name>
  2458. <Description>Start page of first secure area</Description>
  2459. <BitOffset>0x0</BitOffset>
  2460. <BitWidth>0x8</BitWidth>
  2461. <Access>RW</Access>
  2462. <Equation multiplier="0x4000" offset="0x08000000"/>
  2463. </Bit>
  2464. <Bit config="9">
  2465. <Name>SECWM1_PSTRT</Name>
  2466. <Description>Start page of first secure area</Description>
  2467. <BitOffset>0x0</BitOffset>
  2468. <BitWidth>0x8</BitWidth>
  2469. <Access>RW</Access>
  2470. <Equation multiplier="0x2000" offset="0x08000000"/>
  2471. </Bit>
  2472. <Bit config="8">
  2473. <Name>SECWM1_PEND</Name>
  2474. <Description>End page of first secure area</Description>
  2475. <BitOffset>0x10</BitOffset>
  2476. <BitWidth>0x8</BitWidth>
  2477. <Access>RW</Access>
  2478. <Equation multiplier="0x4000" offset="0x08000000"/>
  2479. </Bit>
  2480. <Bit config="9">
  2481. <Name>SECWM1_PEND</Name>
  2482. <Description>End page of first secure area</Description>
  2483. <BitOffset>0x10</BitOffset>
  2484. <BitWidth>0x8</BitWidth>
  2485. <Access>RW</Access>
  2486. <Equation multiplier="0x2000" offset="0x08000000"/>
  2487. </Bit>
  2488. </AssignedBits>
  2489. </Field>
  2490. <Field>
  2491. <Parameters address="0x40022054" name="FLASH_SECWM1R2" size="0x4"/>
  2492. <AssignedBits>
  2493. <Bit config="8,9">
  2494. <Name>HDP1_PEND</Name>
  2495. <Description>End page of first hide protection area</Description>
  2496. <BitOffset>0x10</BitOffset>
  2497. <BitWidth>0x8</BitWidth>
  2498. <Access>RW</Access>
  2499. <Equation multiplier="0x2000" offset="0xC000000"/>
  2500. </Bit>
  2501. <Bit config="8,9">
  2502. <Name>HDP1EN</Name>
  2503. <Description>Hide protection first area enable</Description>
  2504. <BitOffset>0x1F</BitOffset>
  2505. <BitWidth>0x1</BitWidth>
  2506. <Access>RW</Access>
  2507. <Values>
  2508. <Val value="0x0">No HDP area 1</Val>
  2509. <Val value="0x1">HDP first area is enabled</Val>
  2510. </Values>
  2511. </Bit>
  2512. </AssignedBits>
  2513. </Field>
  2514. </Category>
  2515. <Category>
  2516. <Name>Write Protection 1</Name>
  2517. <Field>
  2518. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2519. <AssignedBits>
  2520. <Bit config="6,8">
  2521. <Name>WRP1A_PSTRT</Name>
  2522. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2523. <BitOffset>0x0</BitOffset>
  2524. <BitWidth>0x8</BitWidth>
  2525. <Access>RW</Access>
  2526. <Equation multiplier="0x4000" offset="0x08000000"/>
  2527. </Bit>
  2528. <Bit config="7,9">
  2529. <Name>WRP1A_PSTRT</Name>
  2530. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2531. <BitOffset>0x0</BitOffset>
  2532. <BitWidth>0x8</BitWidth>
  2533. <Access>RW</Access>
  2534. <Equation multiplier="0x2000" offset="0x08000000"/>
  2535. </Bit>
  2536. <Bit config="6,8">
  2537. <Name>WRP1A_PEND</Name>
  2538. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2539. <BitOffset>0x10</BitOffset>
  2540. <BitWidth>0x8</BitWidth>
  2541. <Access>RW</Access>
  2542. <Equation multiplier="0x4000" offset="0x08000000"/>
  2543. </Bit>
  2544. <Bit config="7,9">
  2545. <Name>WRP1A_PEND</Name>
  2546. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2547. <BitOffset>0x10</BitOffset>
  2548. <BitWidth>0x8</BitWidth>
  2549. <Access>RW</Access>
  2550. <Equation multiplier="0x2000" offset="0x08000000"/>
  2551. </Bit>
  2552. <Bit>
  2553. <Name>UNLOCK1A</Name>
  2554. <Description>Bank 1 WPR first area A unlock</Description>
  2555. <BitOffset>0x1F</BitOffset>
  2556. <BitWidth>0x1</BitWidth>
  2557. <Access>RW</Access>
  2558. <Values>
  2559. <Val value="0x0">WRP1A start and end pages locked</Val>
  2560. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  2561. </Values>
  2562. </Bit>
  2563. </AssignedBits>
  2564. </Field>
  2565. <Field>
  2566. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  2567. <AssignedBits>
  2568. <Bit config="6,8">
  2569. <Name>WRP1B_PSTRT</Name>
  2570. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2571. <BitOffset>0x0</BitOffset>
  2572. <BitWidth>0x8</BitWidth>
  2573. <Access>RW</Access>
  2574. <Equation multiplier="0x4000" offset="0x08000000"/>
  2575. </Bit>
  2576. <Bit config="7,9">
  2577. <Name>WRP1B_PSTRT</Name>
  2578. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2579. <BitOffset>0x0</BitOffset>
  2580. <BitWidth>0x8</BitWidth>
  2581. <Access>RW</Access>
  2582. <Equation multiplier="0x2000" offset="0x08000000"/>
  2583. </Bit>
  2584. <Bit config="6,8">
  2585. <Name>WRP1B_PEND</Name>
  2586. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2587. <BitOffset>0x10</BitOffset>
  2588. <BitWidth>0x8</BitWidth>
  2589. <Access>RW</Access>
  2590. <Equation multiplier="0x4000" offset="0x08000000"/>
  2591. </Bit>
  2592. <Bit config="7,9">
  2593. <Name>WRP1B_PEND</Name>
  2594. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2595. <BitOffset>0x10</BitOffset>
  2596. <BitWidth>0x8</BitWidth>
  2597. <Access>RW</Access>
  2598. <Equation multiplier="0x2000" offset="0x08000000"/>
  2599. </Bit>
  2600. <Bit>
  2601. <Name>UNLOCK_1B</Name>
  2602. <Description>Bank 1 WPR first area B unlock</Description>
  2603. <BitOffset>0x1F</BitOffset>
  2604. <BitWidth>0x1</BitWidth>
  2605. <Access>RW</Access>
  2606. <Values>
  2607. <Val value="0x0">WRP1B start and end pages locked</Val>
  2608. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  2609. </Values>
  2610. </Bit>
  2611. </AssignedBits>
  2612. </Field>
  2613. </Category>
  2614. <Category>
  2615. <Name>Secure Area 2</Name>
  2616. <Field>
  2617. <Parameters address="0x4002205C" name="FLASH_SECWM2R1" size="0x4"/>
  2618. <AssignedBits>
  2619. <Bit config="8">
  2620. <Name>SECWM2_PSTRT</Name>
  2621. <Description>Start page of second secure area</Description>
  2622. <BitOffset>0x0</BitOffset>
  2623. <BitWidth>0x8</BitWidth>
  2624. <Access>RW</Access>
  2625. <Equation multiplier="0x4000" offset="0x08000000"/>
  2626. </Bit>
  2627. <Bit config="9">
  2628. <Name>SECWM2_PSTRT</Name>
  2629. <Description>Start page of second secure area</Description>
  2630. <BitOffset>0x0</BitOffset>
  2631. <BitWidth>0x8</BitWidth>
  2632. <Access>RW</Access>
  2633. <Equation multiplier="0x2000" offset="0x08200000"/>
  2634. </Bit>
  2635. <Bit config="8">
  2636. <Name>SECWM2_PEND</Name>
  2637. <Description>End page of second secure area</Description>
  2638. <BitOffset>0x10</BitOffset>
  2639. <BitWidth>0x8</BitWidth>
  2640. <Access>RW</Access>
  2641. <Equation multiplier="0x4000" offset="0x08000000"/>
  2642. </Bit>
  2643. <Bit config="9">
  2644. <Name>SECWM2_PEND</Name>
  2645. <Description>End page of second secure area</Description>
  2646. <BitOffset>0x10</BitOffset>
  2647. <BitWidth>0x8</BitWidth>
  2648. <Access>RW</Access>
  2649. <Equation multiplier="0x2000" offset="0x08200000"/>
  2650. </Bit>
  2651. </AssignedBits>
  2652. </Field>
  2653. <Field>
  2654. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2655. <AssignedBits>
  2656. <Bit config="8,9">
  2657. <Name>HDP2_PEND</Name>
  2658. <Description>End page of second hide protection area</Description>
  2659. <BitOffset>0x10</BitOffset>
  2660. <BitWidth>0x8</BitWidth>
  2661. <Access>RW</Access>
  2662. <Equation multiplier="0x2000" offset="0xC200000"/>
  2663. </Bit>
  2664. <Bit config="8,9">
  2665. <Name>HDP2EN</Name>
  2666. <Description>Hide protection second area enable</Description>
  2667. <BitOffset>0x1F</BitOffset>
  2668. <BitWidth>0x1</BitWidth>
  2669. <Access>RW</Access>
  2670. <Values>
  2671. <Val value="0x0">No HDP area 2</Val>
  2672. <Val value="0x1">HDP second area is enabled</Val>
  2673. </Values>
  2674. </Bit>
  2675. </AssignedBits>
  2676. </Field>
  2677. </Category>
  2678. <Category>
  2679. <Name>Write Protection 2</Name>
  2680. <Field>
  2681. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2682. <AssignedBits>
  2683. <Bit config="6,8">
  2684. <Name>WRP2A_PSTRT</Name>
  2685. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2686. <BitOffset>0x0</BitOffset>
  2687. <BitWidth>0x8</BitWidth>
  2688. <Access>RW</Access>
  2689. <Equation multiplier="0x4000" offset="0x08000000"/>
  2690. </Bit>
  2691. <Bit config="7,9">
  2692. <Name>WRP2A_PSTRT</Name>
  2693. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2694. <BitOffset>0x0</BitOffset>
  2695. <BitWidth>0x8</BitWidth>
  2696. <Access>RW</Access>
  2697. <Equation multiplier="0x2000" offset="0x08200000"/>
  2698. </Bit>
  2699. <Bit config="6,8">
  2700. <Name>WRP2A_PEND</Name>
  2701. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2702. <BitOffset>0x10</BitOffset>
  2703. <BitWidth>0x8</BitWidth>
  2704. <Access>RW</Access>
  2705. <Equation multiplier="0x4000" offset="0x08000000"/>
  2706. </Bit>
  2707. <Bit config="7,9">
  2708. <Name>WRP2A_PEND</Name>
  2709. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2710. <BitOffset>0x10</BitOffset>
  2711. <BitWidth>0x8</BitWidth>
  2712. <Access>RW</Access>
  2713. <Equation multiplier="0x2000" offset="0x08200000"/>
  2714. </Bit>
  2715. <Bit>
  2716. <Name>UNLOCK_2A</Name>
  2717. <Description>Bank 2 WPR first area A unlock</Description>
  2718. <BitOffset>0x1F</BitOffset>
  2719. <BitWidth>0x1</BitWidth>
  2720. <Access>RW</Access>
  2721. <Values>
  2722. <Val value="0x0">WRP2A start and end pages locked</Val>
  2723. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2724. </Values>
  2725. </Bit>
  2726. </AssignedBits>
  2727. </Field>
  2728. <Field>
  2729. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2730. <AssignedBits>
  2731. <Bit config="6,8">
  2732. <Name>WRP2B_PSTRT</Name>
  2733. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2734. <BitOffset>0x0</BitOffset>
  2735. <BitWidth>0x8</BitWidth>
  2736. <Access>RW</Access>
  2737. <Equation multiplier="0x4000" offset="0x08000000"/>
  2738. </Bit>
  2739. <Bit config="7,9">
  2740. <Name>WRP2B_PSTRT</Name>
  2741. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2742. <BitOffset>0x0</BitOffset>
  2743. <BitWidth>0x8</BitWidth>
  2744. <Access>RW</Access>
  2745. <Equation multiplier="0x2000" offset="0x08200000"/>
  2746. </Bit>
  2747. <Bit config="6,8">
  2748. <Name>WRP2B_PEND</Name>
  2749. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2750. <BitOffset>0x10</BitOffset>
  2751. <BitWidth>0x8</BitWidth>
  2752. <Access>RW</Access>
  2753. <Equation multiplier="0x4000" offset="0x08000000"/>
  2754. </Bit>
  2755. <Bit config="7,9">
  2756. <Name>WRP2B_PEND</Name>
  2757. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2758. <BitOffset>0x10</BitOffset>
  2759. <BitWidth>0x8</BitWidth>
  2760. <Access>RW</Access>
  2761. <Equation multiplier="0x2000" offset="0x08200000"/>
  2762. </Bit>
  2763. <Bit>
  2764. <Name>UNLOCK_2B</Name>
  2765. <Description>Bank 2 WPR first area B unlock</Description>
  2766. <BitOffset>0x1F</BitOffset>
  2767. <BitWidth>0x1</BitWidth>
  2768. <Access>RW</Access>
  2769. <Values>
  2770. <Val value="0x0">WRP2B start and end pages locked</Val>
  2771. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2772. </Values>
  2773. </Bit>
  2774. </AssignedBits>
  2775. </Field>
  2776. </Category>
  2777. </Bank>
  2778. </Peripheral>
  2779. </Peripherals>
  2780. </Device>
  2781. </Root>