STM32_Prog_DB_0x480.xml 31 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x480</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32H7A/B</Name>
  9. <Series>STM32H7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0xA">
  15. <SecurityEx>
  16. <WriteRegister address="0x580244F4" value="0x2"/>
  17. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  18. <ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
  19. </SecurityEx>
  20. </Configuration>
  21. <Configuration number="0xB">
  22. <SecurityEx>
  23. <WriteRegister address="0x580244F4" value="0x2"/>
  24. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  25. <ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
  26. </SecurityEx>
  27. </Configuration>
  28. <Configuration number="0x0"> <!-- Security extension available -->
  29. <SecurityEx>
  30. <WriteRegister address="0x580244F4" value="0x2"/>
  31. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  32. </SecurityEx>
  33. </Configuration>
  34. <Configuration number="0x1"> <!-- Security extension not available -->
  35. <SecurityEx>
  36. <WriteRegister address="0x580244F4" value="0x2"/>
  37. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  38. </SecurityEx>
  39. </Configuration>
  40. </Interface>
  41. <!-- Bootloader Interface -->
  42. <Interface name="Bootloader">
  43. <Configuration number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
  44. <Dummy>
  45. <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
  46. </Dummy>
  47. </Configuration>
  48. </Interface>
  49. </Configurations>
  50. <!-- Peripherals -->
  51. <Peripherals>
  52. <!-- Embedded SRAM -->
  53. <Peripheral>
  54. <Name>Embedded SRAM</Name>
  55. <Type>Storage</Type>
  56. <Description/>
  57. <ErasedValue>0x00</ErasedValue>
  58. <Access>RWE</Access>
  59. <!-- 1024 KB -->
  60. <Configuration>
  61. <Parameters address="0x24000000" name="SRAM" size="0x100000"/>
  62. <Description/>
  63. <Organization>Single</Organization>
  64. <Bank name="Bank 1">
  65. <Field>
  66. <Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x100000"/>
  67. </Field>
  68. </Bank>
  69. </Configuration>
  70. </Peripheral>
  71. <!-- Embedded Flash -->
  72. <Peripheral>
  73. <Name>Embedded Flash</Name>
  74. <Type>Storage</Type>
  75. <Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  76. <ErasedValue>0xFF</ErasedValue>
  77. <Access>RWE</Access>
  78. <FlashSize address="0x08fff80c" default="0x200000"/>
  79. <BootloaderVersion address="0x1FF13FFE"/>
  80. <!-- 2MB Dual Bank -->
  81. <Configuration config="0,1">
  82. <Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  83. <Description/>
  84. <Organization>Dual</Organization>
  85. <Allignement>0x20</Allignement>
  86. <Bank name="Bank 1">
  87. <Field>
  88. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  89. </Field>
  90. </Bank>
  91. <Bank name="Bank 2">
  92. <Field>
  93. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  94. </Field>
  95. </Bank>
  96. </Configuration>
  97. <!-- 1MB Dual Bank -->
  98. <Configuration config="10,11">
  99. <Parameters address="0x08000000" name="1 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  100. <Description/>
  101. <Organization>Dual</Organization>
  102. <Allignement>0x20</Allignement>
  103. <Bank name="Bank 1">
  104. <Field>
  105. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  106. </Field>
  107. </Bank>
  108. <Bank name="Bank 2">
  109. <Field>
  110. <Parameters address="0x08080000" name="sector64" occurence="0x80" size="0x2000"/>
  111. </Field>
  112. </Bank>
  113. </Configuration>
  114. </Peripheral>
  115. <!-- OTP -->
  116. <Peripheral>
  117. <Name>OTP</Name>
  118. <Type>Storage</Type>
  119. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  120. <ErasedValue>0xFF</ErasedValue>
  121. <Access>RW</Access>
  122. <!-- 1 KBytes single bank -->
  123. <Configuration>
  124. <Parameters address="0x08FFF000" name=" 1 KBytes Data OTP" size="0x400"/>
  125. <Description/>
  126. <Organization>Single</Organization>
  127. <Allignement>0x20</Allignement>
  128. <Bank name="OTP">
  129. <Field>
  130. <Parameters address="0x08FFF000" name="OTP" occurence="0x1" size="0x400"/>
  131. </Field>
  132. </Bank>
  133. </Configuration>
  134. </Peripheral>
  135. <!-- Option Bytes -->
  136. <Peripheral>
  137. <Name>Option Bytes</Name>
  138. <Type>Configuration</Type>
  139. <Description/>
  140. <Access>RW</Access>
  141. <Bank>
  142. <Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
  143. <Category>
  144. <Name>Read Out Protection</Name>
  145. <Field>
  146. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  147. <AssignedBits>
  148. <Bit>
  149. <Name>RDP</Name>
  150. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  151. <BitOffset>0x8</BitOffset>
  152. <BitWidth>0x8</BitWidth>
  153. <Access>R</Access>
  154. <Values>
  155. <Val value="0xAA">Level 0, no protection</Val>
  156. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  157. <Val value="0xCC">Level 2, chip protection</Val>
  158. </Values>
  159. </Bit>
  160. </AssignedBits>
  161. </Field>
  162. <Field>
  163. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  164. <AssignedBits>
  165. <Bit>
  166. <Name>RDP</Name>
  167. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  168. <BitOffset>0x8</BitOffset>
  169. <BitWidth>0x8</BitWidth>
  170. <Access>W</Access>
  171. <Values>
  172. <Val value="0xAA">Level 0, no protection</Val>
  173. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  174. <Val value="0xCC">Level 2, chip protection</Val>
  175. </Values>
  176. </Bit>
  177. </AssignedBits>
  178. </Field>
  179. </Category>
  180. <Category>
  181. <Name>BOR Level</Name>
  182. <Field>
  183. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  184. <AssignedBits>
  185. <Bit>
  186. <Name>BOR_LEV</Name>
  187. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  188. <BitOffset>0x2</BitOffset>
  189. <BitWidth>0x2</BitWidth>
  190. <Access>R</Access>
  191. <Values>
  192. <Val value="0x0">reset level OFF</Val>
  193. <Val value="0x1">reset level is set to 2.1 V</Val>
  194. <Val value="0x2">reset level is set to 2.4 V</Val>
  195. <Val value="0x3">reset level is set to 2.7 V</Val>
  196. </Values>
  197. </Bit>
  198. </AssignedBits>
  199. </Field>
  200. <Field>
  201. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  202. <AssignedBits>
  203. <Bit>
  204. <Name>BOR_LEV</Name>
  205. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  206. <BitOffset>0x2</BitOffset>
  207. <BitWidth>0x2</BitWidth>
  208. <Access>W</Access>
  209. <Values>
  210. <Val value="0x0">reset level OFF</Val>
  211. <Val value="0x1">reset level is set to 2.1 V</Val>
  212. <Val value="0x2">reset level is set to 2.4 V</Val>
  213. <Val value="0x3">reset level is set to 2.7 V</Val>
  214. </Values>
  215. </Bit>
  216. </AssignedBits>
  217. </Field>
  218. </Category>
  219. <Category>
  220. <Name>User Configuration</Name>
  221. <Field>
  222. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  223. <AssignedBits>
  224. <Bit>
  225. <Name>IWDG1_SW</Name>
  226. <Description/>
  227. <BitOffset>0x4</BitOffset>
  228. <BitWidth>0x1</BitWidth>
  229. <Access>R</Access>
  230. <Values>
  231. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  232. <Val value="0x1">Independent watchdog is controlled by software</Val>
  233. </Values>
  234. </Bit>
  235. <Bit>
  236. <Name>NRST_STOP</Name>
  237. <Description/>
  238. <BitOffset>0x6</BitOffset>
  239. <BitWidth>0x1</BitWidth>
  240. <Access>R</Access>
  241. <Values>
  242. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  243. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  244. </Values>
  245. </Bit>
  246. <Bit>
  247. <Name>NRST_STBY</Name>
  248. <Description/>
  249. <BitOffset>0x7</BitOffset>
  250. <BitWidth>0x1</BitWidth>
  251. <Access>R</Access>
  252. <Values>
  253. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  254. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  255. </Values>
  256. </Bit>
  257. <Bit>
  258. <Name>VDDMMC_HSLV</Name>
  259. <Description/>
  260. <BitOffset>0x10</BitOffset>
  261. <BitWidth>0x1</BitWidth>
  262. <Access>R</Access>
  263. <Values>
  264. <Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
  265. <Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  266. </Values>
  267. </Bit>
  268. <Bit>
  269. <Name>IWDG_FZ_STOP</Name>
  270. <Description/>
  271. <BitOffset>0x11</BitOffset>
  272. <BitWidth>0x1</BitWidth>
  273. <Access>R</Access>
  274. <Values>
  275. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  276. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  277. </Values>
  278. </Bit>
  279. <Bit>
  280. <Name>IWDG_FZ_SDBY</Name>
  281. <Description/>
  282. <BitOffset>0x12</BitOffset>
  283. <BitWidth>0x1</BitWidth>
  284. <Access>R</Access>
  285. <Values>
  286. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  287. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  288. </Values>
  289. </Bit>
  290. <Bit config="0,10">
  291. <Name>SECURITY</Name>
  292. <Description/>
  293. <BitOffset>0x15</BitOffset>
  294. <BitWidth>0x1</BitWidth>
  295. <Access>R</Access>
  296. <Values>
  297. <Val value="0x0">Security feature disabled</Val>
  298. <Val value="0x1">Security feature enabled</Val>
  299. </Values>
  300. </Bit>
  301. <Bit>
  302. <Name>VDDIO_HSLV</Name>
  303. <Description/>
  304. <BitOffset>0x1D</BitOffset>
  305. <BitWidth>0x1</BitWidth>
  306. <Access>R</Access>
  307. <Values>
  308. <Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
  309. <Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
  310. </Values>
  311. </Bit>
  312. <Bit>
  313. <Name>SWAP_BANK_OPT</Name>
  314. <Description/>
  315. <BitOffset>0x1F</BitOffset>
  316. <BitWidth>0x1</BitWidth>
  317. <Access>R</Access>
  318. <Values>
  319. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  320. <Val value="0x1">after boot loading, user sectors swapped</Val>
  321. </Values>
  322. </Bit>
  323. </AssignedBits>
  324. </Field>
  325. <Field>
  326. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  327. <AssignedBits>
  328. <Bit>
  329. <Name>IWDG1_SW</Name>
  330. <Description/>
  331. <BitOffset>0x4</BitOffset>
  332. <BitWidth>0x1</BitWidth>
  333. <Access>W</Access>
  334. <Values>
  335. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  336. <Val value="0x1">Independent watchdog is controlled by software</Val>
  337. </Values>
  338. </Bit>
  339. <Bit>
  340. <Name>NRST_STOP</Name>
  341. <Description/>
  342. <BitOffset>0x6</BitOffset>
  343. <BitWidth>0x1</BitWidth>
  344. <Access>W</Access>
  345. <Values>
  346. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  347. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  348. </Values>
  349. </Bit>
  350. <Bit>
  351. <Name>NRST_STBY</Name>
  352. <Description/>
  353. <BitOffset>0x7</BitOffset>
  354. <BitWidth>0x1</BitWidth>
  355. <Access>W</Access>
  356. <Values>
  357. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  358. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  359. </Values>
  360. </Bit>
  361. <Bit>
  362. <Name>VDDMMC_HSLV</Name>
  363. <Description/>
  364. <BitOffset>0x10</BitOffset>
  365. <BitWidth>0x1</BitWidth>
  366. <Access>W</Access>
  367. <Values>
  368. <Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
  369. <Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  370. </Values>
  371. </Bit>
  372. <Bit>
  373. <Name>IWDG_FZ_STOP</Name>
  374. <Description/>
  375. <BitOffset>0x11</BitOffset>
  376. <BitWidth>0x1</BitWidth>
  377. <Access>W</Access>
  378. <Values>
  379. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  380. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  381. </Values>
  382. </Bit>
  383. <Bit>
  384. <Name>IWDG_FZ_SDBY</Name>
  385. <Description/>
  386. <BitOffset>0x12</BitOffset>
  387. <BitWidth>0x1</BitWidth>
  388. <Access>W</Access>
  389. <Values>
  390. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  391. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  392. </Values>
  393. </Bit>
  394. <Bit config="0,10">
  395. <Name>SECURITY</Name>
  396. <Description/>
  397. <BitOffset>0x15</BitOffset>
  398. <BitWidth>0x1</BitWidth>
  399. <Access>W</Access>
  400. <Values>
  401. <Val value="0x0">Security feature disabled</Val>
  402. <Val value="0x1">Security feature enabled</Val>
  403. </Values>
  404. </Bit>
  405. <Bit>
  406. <Name>VDDIO_HSLV</Name>
  407. <Description/>
  408. <BitOffset>0x1D</BitOffset>
  409. <BitWidth>0x1</BitWidth>
  410. <Access>W</Access>
  411. <Values>
  412. <Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
  413. <Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
  414. </Values>
  415. </Bit>
  416. <Bit>
  417. <Name>SWAP_BANK_OPT</Name>
  418. <Description/>
  419. <BitOffset>0x1F</BitOffset>
  420. <BitWidth>0x1</BitWidth>
  421. <Access>W</Access>
  422. <Values>
  423. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  424. <Val value="0x1">after boot loading, user sectors swapped</Val>
  425. </Values>
  426. </Bit>
  427. </AssignedBits>
  428. </Field>
  429. </Category>
  430. <Category>
  431. <Name>Boot address Option Bytes</Name>
  432. <Field>
  433. <Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
  434. <AssignedBits>
  435. <Bit>
  436. <Name>BOOT_CM7_ADD0</Name>
  437. <Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
  438. <BitOffset>0x0</BitOffset>
  439. <BitWidth>0x10</BitWidth>
  440. <Access>R</Access>
  441. <Equation multiplier="0x10000" offset="0x0"/>
  442. </Bit>
  443. <Bit>
  444. <Name>BOOT_CM7_ADD1</Name>
  445. <Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
  446. <BitOffset>0x10</BitOffset>
  447. <BitWidth>0x10</BitWidth>
  448. <Access>R</Access>
  449. <Equation multiplier="0x10000" offset="0x0"/>
  450. </Bit>
  451. </AssignedBits>
  452. </Field>
  453. <Field>
  454. <Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
  455. <AssignedBits>
  456. <Bit>
  457. <Name>BOOT_CM7_ADD0</Name>
  458. <Description/>
  459. <BitOffset>0x0</BitOffset>
  460. <BitWidth>0x10</BitWidth>
  461. <Access>W</Access>
  462. <Equation multiplier="0x10000" offset="0x0"/>
  463. </Bit>
  464. <Bit>
  465. <Name>BOOT_CM7_ADD1</Name>
  466. <Description/>
  467. <BitOffset>0x10</BitOffset>
  468. <BitWidth>0x10</BitWidth>
  469. <Access>W</Access>
  470. <Equation multiplier="0x10000" offset="0x0"/>
  471. </Bit>
  472. </AssignedBits>
  473. </Field>
  474. </Category>
  475. <Category>
  476. <Name>PCROP Protection</Name>
  477. <Field>
  478. <Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
  479. <AssignedBits>
  480. <Bit>
  481. <Name>PROT_AREA_START1</Name>
  482. <Description>Flash Bank 1 PCROP start address</Description>
  483. <BitOffset>0x0</BitOffset>
  484. <BitWidth>0xC</BitWidth>
  485. <Access>R</Access>
  486. <Equation multiplier="0x100" offset="0x08000000"/>
  487. </Bit>
  488. <Bit>
  489. <Name>PROT_AREA_END1</Name>
  490. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
  491. <BitOffset>0x10</BitOffset>
  492. <BitWidth>0xC</BitWidth>
  493. <Access>R</Access>
  494. <Equation multiplier="0x100" offset="0x080000FF"/>
  495. </Bit>
  496. <Bit>
  497. <Name>DMEP1</Name>
  498. <Description/>
  499. <BitOffset>0x1F</BitOffset>
  500. <BitWidth>0x1</BitWidth>
  501. <Access>R</Access>
  502. <Values>
  503. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  504. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  505. </Values>
  506. </Bit>
  507. </AssignedBits>
  508. </Field>
  509. <Field>
  510. <Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
  511. <AssignedBits>
  512. <Bit>
  513. <Name>PROT_AREA_START1</Name>
  514. <Description>Flash Bank 1 PCROP start address</Description>
  515. <BitOffset>0x0</BitOffset>
  516. <BitWidth>0xC</BitWidth>
  517. <Access>W</Access>
  518. <Equation multiplier="0x100" offset="0x08000000"/>
  519. </Bit>
  520. <Bit>
  521. <Name>PROT_AREA_END1</Name>
  522. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  523. <BitOffset>0x10</BitOffset>
  524. <BitWidth>0xC</BitWidth>
  525. <Access>W</Access>
  526. <Equation multiplier="0x100" offset="0x080000FF"/>
  527. </Bit>
  528. <Bit>
  529. <Name>DMEP1</Name>
  530. <Description/>
  531. <BitOffset>0x1F</BitOffset>
  532. <BitWidth>0x1</BitWidth>
  533. <Access>W</Access>
  534. <Values>
  535. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  536. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  537. </Values>
  538. </Bit>
  539. </AssignedBits>
  540. </Field>
  541. <Field>
  542. <Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
  543. <AssignedBits>
  544. <Bit>
  545. <Name>PROT_AREA_START2</Name>
  546. <Description>Flash Bank 2 PCROP start address</Description>
  547. <BitOffset>0x0</BitOffset>
  548. <BitWidth>0xC</BitWidth>
  549. <Access>R</Access>
  550. <Equation multiplier="0x100" offset="0x08100000"/>
  551. </Bit>
  552. <Bit>
  553. <Name>PROT_AREA_END2</Name>
  554. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  555. <BitOffset>0x10</BitOffset>
  556. <BitWidth>0xC</BitWidth>
  557. <Access>R</Access>
  558. <Equation multiplier="0x100" offset="0x081000FF"/>
  559. </Bit>
  560. <Bit>
  561. <Name>DMEP2</Name>
  562. <Description/>
  563. <BitOffset>0x1F</BitOffset>
  564. <BitWidth>0x1</BitWidth>
  565. <Access>R</Access>
  566. <Values>
  567. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  568. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  569. </Values>
  570. </Bit>
  571. </AssignedBits>
  572. </Field>
  573. <Field>
  574. <Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
  575. <AssignedBits>
  576. <Bit>
  577. <Name>PROT_AREA_START2</Name>
  578. <Description>Flash Bank 2 PCROP start address</Description>
  579. <BitOffset>0x0</BitOffset>
  580. <BitWidth>0xC</BitWidth>
  581. <Access>W</Access>
  582. <Equation multiplier="0x100" offset="0x08100000"/>
  583. </Bit>
  584. <Bit>
  585. <Name>PROT_AREA_END2</Name>
  586. <Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  587. <BitOffset>0x10</BitOffset>
  588. <BitWidth>0xC</BitWidth>
  589. <Access>W</Access>
  590. <Equation multiplier="0x100" offset="0x081000FF"/>
  591. </Bit>
  592. <Bit>
  593. <Name>DMEP2</Name>
  594. <Description/>
  595. <BitOffset>0x1F</BitOffset>
  596. <BitWidth>0x1</BitWidth>
  597. <Access>W</Access>
  598. <Values>
  599. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  600. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  601. </Values>
  602. </Bit>
  603. </AssignedBits>
  604. </Field>
  605. </Category>
  606. <Category>
  607. <Name>Secure Protection</Name>
  608. <Field>
  609. <Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
  610. <AssignedBits>
  611. <Bit config="0,10">
  612. <Name>SEC_AREA_START1</Name>
  613. <Description>Flash Bank 1 secure area start address</Description>
  614. <BitOffset>0x0</BitOffset>
  615. <BitWidth>0xC</BitWidth>
  616. <Access>R</Access>
  617. <Equation multiplier="0x100" offset="0x08000000"/>
  618. </Bit>
  619. <Bit config="0,10">
  620. <Name>SEC_AREA_END1</Name>
  621. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  622. <BitOffset>0x10</BitOffset>
  623. <BitWidth>0xC</BitWidth>
  624. <Access>R</Access>
  625. <Equation multiplier="0x100" offset="0x080000FF"/>
  626. </Bit>
  627. <Bit config="0,10">
  628. <Name>DMES1</Name>
  629. <Description/>
  630. <BitOffset>0x1F</BitOffset>
  631. <BitWidth>0x1</BitWidth>
  632. <Access>R</Access>
  633. <Values>
  634. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  635. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  636. </Values>
  637. </Bit>
  638. </AssignedBits>
  639. </Field>
  640. <Field>
  641. <Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
  642. <AssignedBits>
  643. <Bit config="0,10">
  644. <Name>SEC_AREA_START1</Name>
  645. <Description>Flash Bank 1 secure area start address</Description>
  646. <BitOffset>0x0</BitOffset>
  647. <BitWidth>0xC</BitWidth>
  648. <Access>W</Access>
  649. <Equation multiplier="0x100" offset="0x08000000"/>
  650. </Bit>
  651. <Bit config="0,10">
  652. <Name>SEC_AREA_END1</Name>
  653. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  654. <BitOffset>0x10</BitOffset>
  655. <BitWidth>0xC</BitWidth>
  656. <Access>W</Access>
  657. <Equation multiplier="0x100" offset="0x080000FF"/>
  658. </Bit>
  659. <Bit config="0,10">
  660. <Name>DMES1</Name>
  661. <Description/>
  662. <BitOffset>0x1F</BitOffset>
  663. <BitWidth>0x1</BitWidth>
  664. <Access>W</Access>
  665. <Values>
  666. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  667. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  668. </Values>
  669. </Bit>
  670. </AssignedBits>
  671. </Field>
  672. <Field>
  673. <Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
  674. <AssignedBits>
  675. <Bit config="0,10">
  676. <Name>SEC_AREA_START2</Name>
  677. <Description>Flash Bank 2 secure area start address</Description>
  678. <BitOffset>0x0</BitOffset>
  679. <BitWidth>0xC</BitWidth>
  680. <Access>R</Access>
  681. <Equation multiplier="0x100" offset="0x08100000"/>
  682. </Bit>
  683. <Bit config="0,10">
  684. <Name>SEC_AREA_END2</Name>
  685. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  686. <BitOffset>0x10</BitOffset>
  687. <BitWidth>0xC</BitWidth>
  688. <Access>R</Access>
  689. <Equation multiplier="0x100" offset="0x081000FF"/>
  690. </Bit>
  691. <Bit config="0,10">
  692. <Name>DMES2</Name>
  693. <Description/>
  694. <BitOffset>0x1F</BitOffset>
  695. <BitWidth>0x1</BitWidth>
  696. <Access>R</Access>
  697. <Values>
  698. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  699. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  700. </Values>
  701. </Bit>
  702. </AssignedBits>
  703. </Field>
  704. <Field>
  705. <Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
  706. <AssignedBits>
  707. <Bit config="0,10">
  708. <Name>SEC_AREA_START2</Name>
  709. <Description>Flash Bank 2 secure area start address</Description>
  710. <BitOffset>0x0</BitOffset>
  711. <BitWidth>0xC</BitWidth>
  712. <Access>W</Access>
  713. <Equation multiplier="0x100" offset="0x08100000"/>
  714. </Bit>
  715. <Bit config="0,10">
  716. <Name>SEC_AREA_END2</Name>
  717. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  718. <BitOffset>0x10</BitOffset>
  719. <BitWidth>0xC</BitWidth>
  720. <Access>W</Access>
  721. <Equation multiplier="0x100" offset="0x081000FF"/>
  722. </Bit>
  723. <Bit config="0,10">
  724. <Name>DMES2</Name>
  725. <Description/>
  726. <BitOffset>0x1F</BitOffset>
  727. <BitWidth>0x1</BitWidth>
  728. <Access>W</Access>
  729. <Values>
  730. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  731. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  732. </Values>
  733. </Bit>
  734. </AssignedBits>
  735. </Field>
  736. </Category>
  737. <Category>
  738. <Name>DTCM RAM Protection</Name>
  739. <Field>
  740. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  741. <AssignedBits>
  742. <Bit>
  743. <Name>ST_RAM_SIZE</Name>
  744. <Description/>
  745. <BitOffset>0x13</BitOffset>
  746. <BitWidth>0x2</BitWidth>
  747. <Access>R</Access>
  748. <Values>
  749. <Val value="0x0">2 KB</Val>
  750. <Val value="0x1">4 KB</Val>
  751. <Val value="0x2">8 KB</Val>
  752. <Val value="0x3">16 KB</Val>
  753. </Values>
  754. </Bit>
  755. </AssignedBits>
  756. </Field>
  757. <Field>
  758. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  759. <AssignedBits>
  760. <Bit>
  761. <Name>ST_RAM_SIZE</Name>
  762. <Description/>
  763. <BitOffset>0x13</BitOffset>
  764. <BitWidth>0x2</BitWidth>
  765. <Access>W</Access>
  766. <Values>
  767. <Val value="0x0">2 KB</Val>
  768. <Val value="0x1">4 KB</Val>
  769. <Val value="0x2">8 KB</Val>
  770. <Val value="0x3">16 KB</Val>
  771. </Values>
  772. </Bit>
  773. </AssignedBits>
  774. </Field>
  775. </Category>
  776. <Category>
  777. <Name>Write Protection</Name>
  778. <Field>
  779. <Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
  780. <AssignedBits>
  781. <Bit>
  782. <Name>nWRP0</Name>
  783. <Description/>
  784. <BitOffset>0x0</BitOffset>
  785. <BitWidth>0x20</BitWidth>
  786. <Access>R</Access>
  787. <Values ByBit="true">
  788. <Val value="0x0">Write protection active</Val>
  789. <Val value="0x1">Write protection not active</Val>
  790. </Values>
  791. </Bit>
  792. </AssignedBits>
  793. </Field>
  794. <Field>
  795. <Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
  796. <AssignedBits>
  797. <Bit>
  798. <Name>nWRP0</Name>
  799. <Description/>
  800. <BitOffset>0x0</BitOffset>
  801. <BitWidth>0x20</BitWidth>
  802. <Access>W</Access>
  803. <Values ByBit="true">
  804. <Val value="0x0">Write protection active</Val>
  805. <Val value="0x1">Write protection not active</Val>
  806. </Values>
  807. </Bit>
  808. </AssignedBits>
  809. </Field>
  810. <Field>
  811. <Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
  812. <AssignedBits>
  813. <Bit>
  814. <Name>nWRP32</Name>
  815. <Description/>
  816. <BitOffset>0x0</BitOffset>
  817. <BitWidth>0x20</BitWidth>
  818. <Access>R</Access>
  819. <Values ByBit="true">
  820. <Val value="0x0">Write protection active</Val>
  821. <Val value="0x1">Write protection not active</Val>
  822. </Values>
  823. </Bit>
  824. </AssignedBits>
  825. </Field>
  826. <Field>
  827. <Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
  828. <AssignedBits>
  829. <Bit>
  830. <Name>nWRP32</Name>
  831. <Description/>
  832. <BitOffset>0x0</BitOffset>
  833. <BitWidth>0x20</BitWidth>
  834. <Access>W</Access>
  835. <Values ByBit="true">
  836. <Val value="0x0">Write protection active</Val>
  837. <Val value="0x1">Write protection not active</Val>
  838. </Values>
  839. </Bit>
  840. </AssignedBits>
  841. </Field>
  842. </Category>
  843. </Bank>
  844. </Peripheral>
  845. </Peripherals>
  846. </Device>
  847. </Root>