STM32_Prog_DB_0x484.xml 106 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x484</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32H5xx</Name>
  9. <Series>STM32H5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- dual Bank non secure -->
  15. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  16. </Configuration>
  17. <Configuration number="0x4"> <!-- Dual Bank secure+PROVISIONED STATE -->
  18. <RDP reference="0x1"> <ReadRegister address="0x40022050" mask="0x0000FF00" value="0x00002E00"/> </RDP>
  19. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  20. </Configuration>
  21. <Configuration number="0x5"> <!-- Dual Bank secure provisioning -->
  22. <RDP reference="0x1"> <ReadRegister address="0x50022050" mask="0x0000FF00" value="0x00000000"/> </RDP>
  23. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  24. </Configuration>
  25. <Configuration number="0x1"> <!-- Dual Bank secure -->
  26. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  27. </Configuration>
  28. </Interface>
  29. <!-- Bootloader Interface -->
  30. <Interface name="Bootloader">
  31. <Configuration number="0x2"> <!-- Dual Bank Secure-->
  32. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  33. </Configuration>
  34. <Configuration number="0x3"> <!-- Dual Bank non Secure-->
  35. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  36. </Configuration>
  37. </Interface>
  38. </Configurations>
  39. <!-- Peripherals -->
  40. <Peripherals>
  41. <!-- Embedded SRAM -->
  42. <Peripheral>
  43. <Name>Embedded SRAM</Name>
  44. <Type>Storage</Type>
  45. <Description/>
  46. <ErasedValue>0xFF</ErasedValue>
  47. <Access>RWE</Access>
  48. <!-- 96 KB -->
  49. <Configuration config="0,3">
  50. <Parameters address="0x20003000" name="SRAM" size="0x40000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Bank name="Bank 1">
  54. <Field>
  55. <Parameters address="0x20003000" name="SRAM" occurence="0x1" size="0x40000"/>
  56. </Field>
  57. </Bank>
  58. </Configuration>
  59. <Configuration config="1,2,4,5">
  60. <Parameters address="0x20003000" name="SRAM" size="0x10000"/>
  61. <Description/>
  62. <Organization>Single</Organization>
  63. <Bank name="Bank 1">
  64. <Field>
  65. <Parameters address="0x20003000" name="SRAM" occurence="0x1" size="0x10000"/>
  66. </Field>
  67. </Bank>
  68. </Configuration>
  69. </Peripheral>
  70. <!-- Embedded Flash -->
  71. <Peripheral>
  72. <Name>Embedded Flash</Name>
  73. <Type>Storage</Type>
  74. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  75. <ErasedValue>0xFF</ErasedValue>
  76. <Access>RWE</Access>
  77. <FlashSize address="0x08FFF80C" default="0x200000"/>
  78. <BootloaderVersion address="0x0BF9FCFE"/>
  79. <Configuration config="0,2,3"> <!-- dual Bank nn secure -->
  80. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  81. <Description/>
  82. <Organization>Dual</Organization>
  83. <Allignement>0x10</Allignement>
  84. <Bank name="Bank 1">
  85. <Field>
  86. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  87. </Field>
  88. </Bank>
  89. <Bank name="Bank 2">
  90. <Field>
  91. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  92. </Field>
  93. </Bank>
  94. </Configuration>
  95. <Configuration config="1,4,5"> <!-- dual Bank secure -->
  96. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  97. <Description/>
  98. <Organization>Dual</Organization>
  99. <Allignement>0x10</Allignement>
  100. <Bank name="Bank 1">
  101. <Field>
  102. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  103. </Field>
  104. </Bank>
  105. <Bank name="Bank 2">
  106. <Field>
  107. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  108. </Field>
  109. </Bank>
  110. </Configuration>
  111. </Peripheral>
  112. <!-- Data EEPROM -->
  113. <Peripheral>
  114. <Name>Data EEPROM</Name>
  115. <Type>Storage</Type>
  116. <Description>The Data EEPROM memory block. It contains user data.</Description>
  117. <ErasedValue>0xFF</ErasedValue>
  118. <Access>RWE</Access>
  119. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  120. <Configuration config="0,1,3,5">
  121. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  122. <Description/>
  123. <Organization>Dual</Organization>
  124. <Allignement>0x4</Allignement>
  125. <Bank name="Bank 1">
  126. <Field>
  127. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  128. </Field>
  129. </Bank>
  130. <Bank name="Bank 2">
  131. <Field>
  132. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  133. </Field>
  134. </Bank>
  135. </Configuration>
  136. </Peripheral>
  137. <!-- OTP -->
  138. <Peripheral>
  139. <Name>OTP</Name>
  140. <Type>Storage</Type>
  141. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  142. <ErasedValue>0xFF</ErasedValue>
  143. <Access>RW</Access>
  144. <!-- 2 kBytes single bank -->
  145. <Configuration>
  146. <Parameters address="0x08FFF000" name=" 2 kBytes Data OTP" size="0x800"/>
  147. <Description/>
  148. <Organization>Single</Organization>
  149. <Allignement>0x4</Allignement>
  150. <Bank name="OTP">
  151. <Field>
  152. <Parameters address="0x08FFF000" name="OTP" occurence="0x1" size="0x800"/>
  153. </Field>
  154. </Bank>
  155. </Configuration>
  156. </Peripheral>
  157. <!-- Option Bytes -->
  158. <Peripheral>
  159. <Name>Option Bytes</Name>
  160. <Type>Configuration</Type>
  161. <Description/>
  162. <Access>RW</Access>
  163. <Configuration config="0,4,5">
  164. <Bank interface="JTAG_SWD">
  165. <Parameters address="0x40022050" name="Bank 1" size="0x70"/>
  166. <Category>
  167. <Name>Product state</Name>
  168. <Field>
  169. <Parameters address="0x40022050" name="CUR" size="0x4"/>
  170. <AssignedBits>
  171. <Bit>
  172. <Name>PRODUCT_STATE</Name>
  173. <Description>Life state code.</Description>
  174. <BitOffset>0x8</BitOffset>
  175. <BitWidth>0x8</BitWidth>
  176. <Access>R</Access>
  177. <Values>
  178. <Val value="0xED">Open</Val>
  179. <Val value="0x17">Provisioning</Val>
  180. <Val value="0x2E">iRoT-provisioned</Val>
  181. <Val value="0xC6">TZ-Closed</Val>
  182. <Val value="0x72">Closed</Val>
  183. <Val value="0x5C">Locked</Val>
  184. <Val value="0x9A">Regression</Val>
  185. <Val value="0xA3">NS-Regression</Val>
  186. </Values>
  187. </Bit>
  188. </AssignedBits>
  189. </Field>
  190. <Field>
  191. <Parameters address="0x40022054" name="PRG" size="0x4"/>
  192. <AssignedBits>
  193. <Bit>
  194. <Name>PRODUCT_STATE</Name>
  195. <Description>Life state code.</Description>
  196. <BitOffset>0x8</BitOffset>
  197. <BitWidth>0x8</BitWidth>
  198. <Access>W</Access>
  199. <Values>
  200. <Val value="0xED">Open</Val>
  201. <Val value="0x17">Provisioning</Val>
  202. <Val value="0x2E">iRoT-provisioned</Val>
  203. <Val value="0xC6">TZ-Closed</Val>
  204. <Val value="0x72">Closed</Val>
  205. <Val value="0x5C">Locked</Val>
  206. <Val value="0x9A">Regression</Val>
  207. <Val value="0xA3">NS-Regression</Val>
  208. </Values>
  209. </Bit>
  210. </AssignedBits>
  211. </Field>
  212. </Category>
  213. <Category>
  214. <Name>BOR Level</Name>
  215. <Field>
  216. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  217. <AssignedBits>
  218. <Bit>
  219. <Name>BOR_LEV</Name>
  220. <Description>Brownout level option status bit.</Description>
  221. <BitOffset>0x0</BitOffset>
  222. <BitWidth>0x2</BitWidth>
  223. <Access>R</Access>
  224. <Values>
  225. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  226. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  227. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  228. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  229. </Values>
  230. </Bit>
  231. </AssignedBits>
  232. </Field>
  233. <Field>
  234. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  235. <AssignedBits>
  236. <Bit>
  237. <Name>BOR_LEV</Name>
  238. <Description>Brownout level option status bit.</Description>
  239. <BitOffset>0x0</BitOffset>
  240. <BitWidth>0x2</BitWidth>
  241. <Access>W</Access>
  242. <Values>
  243. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  244. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  245. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  246. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  247. </Values>
  248. </Bit>
  249. </AssignedBits>
  250. </Field>
  251. <Field>
  252. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  253. <AssignedBits>
  254. <Bit>
  255. <Name>BORH_EN</Name>
  256. <Description>Brownout high enable configuration bit</Description>
  257. <BitOffset>0x2</BitOffset>
  258. <BitWidth>0x1</BitWidth>
  259. <Access>R</Access>
  260. <Val value="0x0">disabled</Val>
  261. <Val value="0x1">enabled</Val>
  262. </Bit>
  263. </AssignedBits>
  264. </Field>
  265. <Field>
  266. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  267. <AssignedBits>
  268. <Bit>
  269. <Name>BORH_EN</Name>
  270. <Description>Brownout high enable configuration bit</Description>
  271. <BitOffset>0x2</BitOffset>
  272. <BitWidth>0x1</BitWidth>
  273. <Access>W</Access>
  274. <Val value="0x0">disabled</Val>
  275. <Val value="0x1">enabled</Val>
  276. </Bit>
  277. </AssignedBits>
  278. </Field>
  279. </Category>
  280. <Category>
  281. <Name>User Configuration</Name>
  282. <Field>
  283. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  284. <AssignedBits>
  285. <Bit>
  286. <Name>IO_VDD_HSLV</Name>
  287. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  288. <BitOffset>0x10</BitOffset>
  289. <BitWidth>0x1</BitWidth>
  290. <Access>R</Access>
  291. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  292. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  293. </Bit>
  294. </AssignedBits>
  295. </Field>
  296. <Field>
  297. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  298. <AssignedBits>
  299. <Bit>
  300. <Name>IO_VDD_HSLV</Name>
  301. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  302. <BitOffset>0x10</BitOffset>
  303. <BitWidth>0x1</BitWidth>
  304. <Access>W</Access>
  305. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  306. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  307. </Bit>
  308. </AssignedBits>
  309. </Field>
  310. <Field>
  311. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  312. <AssignedBits>
  313. <Bit>
  314. <Name>IO_VDDIO2_HSLV</Name>
  315. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  316. <BitOffset>0x11</BitOffset>
  317. <BitWidth>0x1</BitWidth>
  318. <Access>R</Access>
  319. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  320. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  321. </Bit>
  322. </AssignedBits>
  323. </Field>
  324. <Field>
  325. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  326. <AssignedBits>
  327. <Bit>
  328. <Name>IO_VDDIO2_HSLV</Name>
  329. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  330. <BitOffset>0x11</BitOffset>
  331. <BitWidth>0x1</BitWidth>
  332. <Access>W</Access>
  333. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  334. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  335. </Bit>
  336. </AssignedBits>
  337. </Field>
  338. <Field>
  339. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  340. <AssignedBits>
  341. <Bit>
  342. <Name>IWDG_STOP</Name>
  343. <Description>Stop mode freeze option status bit.</Description>
  344. <BitOffset>0x14</BitOffset>
  345. <BitWidth>0x1</BitWidth>
  346. <Access>R</Access>
  347. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  348. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  349. </Bit>
  350. </AssignedBits>
  351. </Field>
  352. <Field>
  353. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  354. <AssignedBits>
  355. <Bit>
  356. <Name>IWDG_STOP</Name>
  357. <Description>Stop mode freeze option status bit.</Description>
  358. <BitOffset>0x14</BitOffset>
  359. <BitWidth>0x1</BitWidth>
  360. <Access>W</Access>
  361. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  362. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  363. </Bit>
  364. </AssignedBits>
  365. </Field>
  366. <Field>
  367. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  368. <AssignedBits>
  369. <Bit>
  370. <Name>IWDG_STDBY</Name>
  371. <Description>Standby mode freeze option status bit.</Description>
  372. <BitOffset>0x15</BitOffset>
  373. <BitWidth>0x1</BitWidth>
  374. <Access>R</Access>
  375. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  376. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  377. </Bit>
  378. </AssignedBits>
  379. </Field>
  380. <Field>
  381. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  382. <AssignedBits>
  383. <Bit>
  384. <Name>IWDG_STDBY</Name>
  385. <Description>Standby mode freeze option status bit.</Description>
  386. <BitOffset>0x15</BitOffset>
  387. <BitWidth>0x1</BitWidth>
  388. <Access>W</Access>
  389. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  390. <Val value="0x1">Independent watchdog keep running in standby Stop mode.</Val>
  391. </Bit>
  392. </AssignedBits>
  393. </Field>
  394. <Field>
  395. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  396. <AssignedBits>
  397. <Bit>
  398. <Name>BOOT_UBE</Name>
  399. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  400. <BitOffset>0x16</BitOffset>
  401. <BitWidth>0x8</BitWidth>
  402. <Access>R</Access>
  403. <Values>
  404. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  405. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  406. </Values>
  407. </Bit>
  408. </AssignedBits>
  409. </Field>
  410. <Field>
  411. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  412. <AssignedBits>
  413. <Bit>
  414. <Name>BOOT_UBE</Name>
  415. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  416. <BitOffset>0x16</BitOffset>
  417. <BitWidth>0x8</BitWidth>
  418. <Access>W</Access>
  419. <Values>
  420. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  421. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  422. </Values>
  423. </Bit>
  424. </AssignedBits>
  425. </Field>
  426. <Field>
  427. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  428. <AssignedBits>
  429. <Bit>
  430. <Name>SWAP_BANK</Name>
  431. <Description>Bank swapping option status bit.</Description>
  432. <BitOffset>0x1F</BitOffset>
  433. <BitWidth>0x1</BitWidth>
  434. <Access>R</Access>
  435. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  436. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  437. </Bit>
  438. </AssignedBits>
  439. </Field>
  440. <Field>
  441. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  442. <AssignedBits>
  443. <Bit>
  444. <Name>SWAP_BANK</Name>
  445. <Description>Bank swapping option status bit.</Description>
  446. <BitOffset>0x1F</BitOffset>
  447. <BitWidth>0x1</BitWidth>
  448. <Access>W</Access>
  449. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  450. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  451. </Bit>
  452. </AssignedBits>
  453. </Field>
  454. <Field>
  455. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  456. <AssignedBits>
  457. <Bit>
  458. <Name>IWDG_SW</Name>
  459. <Description>IWDG control mode option status bit.</Description>
  460. <BitOffset>0x3</BitOffset>
  461. <BitWidth>0x1</BitWidth>
  462. <Access>R</Access>
  463. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  464. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  465. </Bit>
  466. </AssignedBits>
  467. </Field>
  468. <Field>
  469. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  470. <AssignedBits>
  471. <Bit>
  472. <Name>IWDG_SW</Name>
  473. <Description>IWDG control mode option status bit.</Description>
  474. <BitOffset>0x3</BitOffset>
  475. <BitWidth>0x1</BitWidth>
  476. <Access>W</Access>
  477. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  478. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  479. </Bit>
  480. </AssignedBits>
  481. </Field>
  482. <Field>
  483. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  484. <AssignedBits>
  485. <Bit>
  486. <Name>WWDG_SW</Name>
  487. <Description>WWDG control mode option status bit.</Description>
  488. <BitOffset>0x4</BitOffset>
  489. <BitWidth>0x1</BitWidth>
  490. <Access>R</Access>
  491. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  492. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  493. </Bit>
  494. </AssignedBits>
  495. </Field>
  496. <Field>
  497. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  498. <AssignedBits>
  499. <Bit>
  500. <Name>WWDG_SW</Name>
  501. <Description>WWDG control mode option status bit.</Description>
  502. <BitOffset>0x4</BitOffset>
  503. <BitWidth>0x1</BitWidth>
  504. <Access>W</Access>
  505. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  506. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  507. </Bit>
  508. </AssignedBits>
  509. </Field>
  510. <Field>
  511. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  512. <AssignedBits>
  513. <Bit>
  514. <Name>NRST_STOP</Name>
  515. <Description>Core domain Stop entry reset option status bit.</Description>
  516. <BitOffset>0x6</BitOffset>
  517. <BitWidth>0x1</BitWidth>
  518. <Access>R</Access>
  519. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  520. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  521. </Bit>
  522. </AssignedBits>
  523. </Field>
  524. <Field>
  525. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  526. <AssignedBits>
  527. <Bit>
  528. <Name>NRST_STOP</Name>
  529. <Description>Core domain Stop entry reset option status bit.</Description>
  530. <BitOffset>0x6</BitOffset>
  531. <BitWidth>0x1</BitWidth>
  532. <Access>W</Access>
  533. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  534. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  535. </Bit>
  536. </AssignedBits>
  537. </Field>
  538. <Field>
  539. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  540. <AssignedBits>
  541. <Bit>
  542. <Name>NRST_STDBY</Name>
  543. <Description>Core domain Standby entry reset option status bit.</Description>
  544. <BitOffset>0x7</BitOffset>
  545. <BitWidth>0x1</BitWidth>
  546. <Access>R</Access>
  547. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  548. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  549. </Bit>
  550. </AssignedBits>
  551. </Field>
  552. <Field>
  553. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  554. <AssignedBits>
  555. <Bit>
  556. <Name>NRST_STDBY</Name>
  557. <Description>Core domain Standby entry reset option status bit.</Description>
  558. <BitOffset>0x7</BitOffset>
  559. <BitWidth>0x1</BitWidth>
  560. <Access>W</Access>
  561. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  562. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  563. </Bit>
  564. </AssignedBits>
  565. </Field>
  566. </Category>
  567. </Bank>
  568. <Bank interface="JTAG_SWD">
  569. <Parameters address="0x40022070" name="Bank 2" size="0x10"/>
  570. <Category>
  571. <Name>User Configuration 2</Name>
  572. <Field>
  573. <Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
  574. <AssignedBits>
  575. <Bit>
  576. <Name>TZEN</Name>
  577. <Description>Trust Zone Enable configuration bits</Description>
  578. <BitOffset>0x18</BitOffset>
  579. <BitWidth>0x8</BitWidth>
  580. <Access>R</Access>
  581. <Values>
  582. <Val value="0xC3">Trust zone disabled</Val>
  583. <Val value="0xB4">Trust zone enabled</Val>
  584. </Values>
  585. </Bit>
  586. <Bit>
  587. <Name>HUK_PUF</Name>
  588. <Description>This bit configures the source and use of the unique key</Description>
  589. <BitOffset>0xF</BitOffset>
  590. <BitWidth>0x1</BitWidth>
  591. <Access>R</Access>
  592. <Values>
  593. <Val value="0x0">The key is treated as HUK</Val>
  594. <Val value="0x1">The key is treated as PUF</Val>
  595. </Values>
  596. </Bit>
  597. <Bit>
  598. <Name>USBPD_DIS</Name>
  599. <Description>USB power delivery configuration option bit</Description>
  600. <BitOffset>0x8</BitOffset>
  601. <BitWidth>0x1</BitWidth>
  602. <Access>R</Access>
  603. <Values>
  604. <Val value="0x0">Enabled</Val>
  605. <Val value="0x1">Disabled</Val>
  606. </Values>
  607. </Bit>
  608. <Bit>
  609. <Name>SRAM2_ECC</Name>
  610. <Description>ECC in SRAM2 region configuration bit</Description>
  611. <BitOffset>0x6</BitOffset>
  612. <BitWidth>0x1</BitWidth>
  613. <Access>R</Access>
  614. <Values>
  615. <Val value="0x0">SRAM2 ECC check enabled </Val>
  616. <Val value="0x1">SRAM2 ECC check disabled</Val>
  617. </Values>
  618. </Bit>
  619. <Bit>
  620. <Name>SRAM3_ECC</Name>
  621. <Description>ECC in SRAM3 region configuration bit</Description>
  622. <BitOffset>0x5</BitOffset>
  623. <BitWidth>0x1</BitWidth>
  624. <Access>R</Access>
  625. <Values>
  626. <Val value="0x0">SRAM3 ECC check enabled </Val>
  627. <Val value="0x1">SRAM3 ECC check disabled</Val>
  628. </Values>
  629. </Bit>
  630. <Bit>
  631. <Name>BKPRAM_ECC</Name>
  632. <Description>ECC in BKPRAM region configuration bit</Description>
  633. <BitOffset>0x4</BitOffset>
  634. <BitWidth>0x1</BitWidth>
  635. <Access>R</Access>
  636. <Values>
  637. <Val value="0x0">BKPRAM ECC check enabled </Val>
  638. <Val value="0x1">BKPRAM ECC check disabled</Val>
  639. </Values>
  640. </Bit>
  641. <Bit>
  642. <Name>SRAM2_RST</Name>
  643. <Description>SRAM2 Erase when system reset</Description>
  644. <BitOffset>0x3</BitOffset>
  645. <BitWidth>0x1</BitWidth>
  646. <Access>R</Access>
  647. <Values>
  648. <Val value="0x0">SRAM2 erase when system reset</Val>
  649. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  650. </Values>
  651. </Bit>
  652. <Bit>
  653. <Name>SRAM1_3_RST</Name>
  654. <Description>SRAM1 and SRAM3 erase upon system reset</Description>
  655. <BitOffset>0x2</BitOffset>
  656. <BitWidth>0x1</BitWidth>
  657. <Access>R</Access>
  658. <Values>
  659. <Val value="0x0">SRAM1 and SRAM3 erased when a system reset occurs</Val>
  660. <Val value="0x1">SRAM1 and SRAM3 not erased when a system reset occurs</Val>
  661. </Values>
  662. </Bit>
  663. </AssignedBits>
  664. </Field>
  665. <Field>
  666. <Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
  667. <AssignedBits>
  668. <Bit>
  669. <Name>TZEN</Name>
  670. <Description>Trust Zone Enable configuration bits</Description>
  671. <BitOffset>0x18</BitOffset>
  672. <BitWidth>0x8</BitWidth>
  673. <Access>W</Access>
  674. <Values>
  675. <Val value="0xC3">Trust zone disabled</Val>
  676. <Val value="0xB4">Trust zone enabled</Val>
  677. </Values>
  678. </Bit>
  679. <Bit>
  680. <Name>HUK_PUF</Name>
  681. <Description>This bit configures the source and use of the unique key</Description>
  682. <BitOffset>0xF</BitOffset>
  683. <BitWidth>0x1</BitWidth>
  684. <Access>W</Access>
  685. <Values>
  686. <Val value="0x0">The key is treated as HUK</Val>
  687. <Val value="0x1">The key is treated as PUF</Val>
  688. </Values>
  689. </Bit>
  690. <Bit>
  691. <Name>USBPD_DIS</Name>
  692. <Description>USB power delivery configuration option bit</Description>
  693. <BitOffset>0x8</BitOffset>
  694. <BitWidth>0x1</BitWidth>
  695. <Access>W</Access>
  696. <Values>
  697. <Val value="0x0">Enabled</Val>
  698. <Val value="0x1">Disabled</Val>
  699. </Values>
  700. </Bit>
  701. <Bit>
  702. <Name>SRAM2_ECC</Name>
  703. <Description>ECC in SRAM2 region configuration bit</Description>
  704. <BitOffset>0x6</BitOffset>
  705. <BitWidth>0x1</BitWidth>
  706. <Access>W</Access>
  707. <Values>
  708. <Val value="0x0">SRAM2 ECC check enabled </Val>
  709. <Val value="0x1">SRAM2 ECC check disabled</Val>
  710. </Values>
  711. </Bit>
  712. <Bit>
  713. <Name>SRAM3_ECC</Name>
  714. <Description>ECC in SRAM3 region configuration bit</Description>
  715. <BitOffset>0x5</BitOffset>
  716. <BitWidth>0x1</BitWidth>
  717. <Access>W</Access>
  718. <Values>
  719. <Val value="0x0">SRAM3 ECC check enabled </Val>
  720. <Val value="0x1">SRAM3 ECC check disabled</Val>
  721. </Values>
  722. </Bit>
  723. <Bit>
  724. <Name>BKPRAM_ECC</Name>
  725. <Description>ECC in BKPRAM region configuration bit</Description>
  726. <BitOffset>0x4</BitOffset>
  727. <BitWidth>0x1</BitWidth>
  728. <Access>W</Access>
  729. <Values>
  730. <Val value="0x0">BKPRAM ECC check enabled </Val>
  731. <Val value="0x1">BKPRAM ECC check disabled</Val>
  732. </Values>
  733. </Bit>
  734. <Bit>
  735. <Name>SRAM2_RST</Name>
  736. <Description>SRAM2 Erase when system reset</Description>
  737. <BitOffset>0x3</BitOffset>
  738. <BitWidth>0x1</BitWidth>
  739. <Access>W</Access>
  740. <Values>
  741. <Val value="0x0">SRAM2 erase when system reset</Val>
  742. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  743. </Values>
  744. </Bit>
  745. <Bit>
  746. <Name>SRAM1_3_RST</Name>
  747. <Description>SRAM1 and SRAM3 erase upon system reset</Description>
  748. <BitOffset>0x2</BitOffset>
  749. <BitWidth>0x1</BitWidth>
  750. <Access>W</Access>
  751. <Values>
  752. <Val value="0x0">SRAM1 and SRAM3 erased when a system reset occurs</Val>
  753. <Val value="0x1">SRAM1 and SRAM3 not erased when a system reset occurs</Val>
  754. </Values>
  755. </Bit>
  756. </AssignedBits>
  757. </Field>
  758. </Category>
  759. </Bank>
  760. <Bank interface="JTAG_SWD">
  761. <Parameters address="0x40022080" name="Bank 3" size="0x10"/>
  762. <Category>
  763. <Name>Boot Configuration</Name>
  764. <Field>
  765. <Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
  766. <AssignedBits>
  767. <Bit>
  768. <Name>NSBOOTADD</Name>
  769. <Description>Non secure unique boot entry address</Description>
  770. <BitOffset>0x8</BitOffset>
  771. <BitWidth>0x18</BitWidth>
  772. <Access>R</Access>
  773. <Equation multiplier="0x100" offset="0x00000000"/>
  774. </Bit>
  775. <Bit>
  776. <Name>NSBOOT_LOCK</Name>
  777. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings</Description>
  778. <BitOffset>0x0</BitOffset>
  779. <BitWidth>0x8</BitWidth>
  780. <Access>R</Access>
  781. <Values>
  782. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  783. <Val value="0xB4">The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  784. </Values>
  785. </Bit>
  786. </AssignedBits>
  787. </Field>
  788. <Field>
  789. <Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
  790. <AssignedBits>
  791. <Bit>
  792. <Name>NSBOOTADD</Name>
  793. <Description>Non secure unique boot entry address</Description>
  794. <BitOffset>0x8</BitOffset>
  795. <BitWidth>0x18</BitWidth>
  796. <Access>W</Access>
  797. <Equation multiplier="0x100" offset="0x00000000"/>
  798. </Bit>
  799. <Bit>
  800. <Name>NSBOOT_LOCK</Name>
  801. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings</Description>
  802. <BitOffset>0x0</BitOffset>
  803. <BitWidth>0x8</BitWidth>
  804. <Access>W</Access>
  805. <Values>
  806. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  807. <Val value="0xB4">The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  808. </Values>
  809. </Bit>
  810. </AssignedBits>
  811. </Field>
  812. <Field>
  813. <Parameters address="0x40022088" name="FLASH_OPTR" size="0x4"/>
  814. <AssignedBits>
  815. <Bit>
  816. <Name>SECBOOT_LOCK</Name>
  817. <Description>A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.</Description>
  818. <BitOffset>0x0</BitOffset>
  819. <BitWidth>0x8</BitWidth>
  820. <Access>R</Access>
  821. <Values>
  822. <Val value="0xC3">The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.</Val>
  823. <Val value="0xB4">The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  824. </Values>
  825. </Bit>
  826. <Bit>
  827. <Name>SECBOOTADD</Name>
  828. <Description>Unique Boot Entry Secure Adress</Description>
  829. <BitOffset>0x8</BitOffset>
  830. <BitWidth>0x18</BitWidth>
  831. <Access>R</Access>
  832. <!--<Equation multiplier="0x2000" offset="0x08000000"/> -->
  833. </Bit>
  834. </AssignedBits>
  835. </Field>
  836. <Field>
  837. <Parameters address="0x4002208C" name="FLASH_OPTR" size="0x4"/>
  838. <AssignedBits>
  839. <Bit>
  840. <Name>SECBOOT_LOCK</Name>
  841. <Description>A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.</Description>
  842. <BitOffset>0x0</BitOffset>
  843. <BitWidth>0x8</BitWidth>
  844. <Access>W</Access>
  845. <Values>
  846. <Val value="0xC3">The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.</Val>
  847. <Val value="0xB4">The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  848. </Values>
  849. </Bit>
  850. <Bit>
  851. <Name>SECBOOTADD</Name>
  852. <Description>Unique Boot Entry Secure Adress.</Description>
  853. <BitOffset>0x8</BitOffset>
  854. <BitWidth>0x18</BitWidth>
  855. <Access>W</Access>
  856. <!--<Equation multiplier="0x2000" offset="0x08000000"/> -->
  857. </Bit>
  858. </AssignedBits>
  859. </Field>
  860. </Category>
  861. </Bank>
  862. <Bank interface="JTAG_SWD">
  863. <Parameters address="0x400220E0" name="Bank 4" size="0x10"/>
  864. <Category>
  865. <Name>Bank1 - Flash watermark area definition</Name>
  866. <Field>
  867. <Parameters address="0x400220E0" name="FLASH_SECWM_CUR1R" size="0x4"/>
  868. <AssignedBits>
  869. <Bit>
  870. <Name>SECWM1_STRT</Name>
  871. <Description>Bank 1 security WM area 1 start sector</Description>
  872. <BitOffset>0x0</BitOffset>
  873. <BitWidth>0x7</BitWidth>
  874. <Access>R</Access>
  875. <Equation multiplier="0x2000" offset="0x08000000"/>
  876. </Bit>
  877. <Bit>
  878. <Name>SECWM1_END</Name>
  879. <Description>Bank 1 security WM area 1 end sector</Description>
  880. <BitOffset>0x10</BitOffset>
  881. <BitWidth>0x7</BitWidth>
  882. <Access>R</Access>
  883. <Equation multiplier="0x2000" offset="0x08000000"/>
  884. </Bit>
  885. </AssignedBits>
  886. </Field>
  887. <Field>
  888. <Parameters address="0x400220E4" name="FLASH_SECWM_PRG1R" size="0x4"/>
  889. <AssignedBits>
  890. <Bit>
  891. <Name>SECWM1_STRT</Name>
  892. <Description>Bank 1 security WM area 1 start sector</Description>
  893. <BitOffset>0x0</BitOffset>
  894. <BitWidth>0x7</BitWidth>
  895. <Access>W</Access>
  896. <Equation multiplier="0x2000" offset="0x08000000"/>
  897. </Bit>
  898. <Bit>
  899. <Name>SECWM1_END</Name>
  900. <Description>Bank 1 security WM area 1 end sector</Description>
  901. <BitOffset>0x10</BitOffset>
  902. <BitWidth>0x7</BitWidth>
  903. <Access>W</Access>
  904. <Equation multiplier="0x2000" offset="0x08000000"/>
  905. </Bit>
  906. </AssignedBits>
  907. </Field>
  908. </Category>
  909. <Category>
  910. <Name>Write sector group protection 1</Name>
  911. <Field>
  912. <Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
  913. <AssignedBits>
  914. <Bit>
  915. <Name>WRPSGn1</Name>
  916. <Description>Bank 1 sector group protection option status byte</Description>
  917. <BitOffset>0x0</BitOffset>
  918. <BitWidth>0x20</BitWidth>
  919. <Access>R</Access>
  920. <Equation multiplier="0x2000" offset="0x08000000"/>
  921. </Bit>
  922. </AssignedBits>
  923. </Field>
  924. <Field>
  925. <Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
  926. <AssignedBits>
  927. <Bit>
  928. <Name>WRPSGn1</Name>
  929. <Description>Bank 1 sector group protection option status byte</Description>
  930. <BitOffset>0x0</BitOffset>
  931. <BitWidth>0x20</BitWidth>
  932. <Access>W</Access>
  933. <Equation multiplier="0x2000" offset="0x08000000"/>
  934. </Bit>
  935. </AssignedBits>
  936. </Field>
  937. </Category>
  938. </Bank>
  939. <Bank interface="JTAG_SWD">
  940. <Parameters address="0x400221E0" name="Bank 5" size="0x10"/>
  941. <Category>
  942. <Name>Bank2 - Flash watermark area definition</Name>
  943. <Field>
  944. <Parameters address="0x400221E0" name="FLASH_SECWM_CUR2R" size="0x4"/>
  945. <AssignedBits>
  946. <Bit>
  947. <Name>SECWM2_STRT</Name>
  948. <Description>Bank 2 security WM area start sector</Description>
  949. <BitOffset>0x0</BitOffset>
  950. <BitWidth>0x7</BitWidth>
  951. <Access>R</Access>
  952. <Equation multiplier="0x2000" offset="0x08000000"/>
  953. </Bit>
  954. <Bit>
  955. <Name>SECWM2_END</Name>
  956. <Description>Bank 2 security WM area end sector</Description>
  957. <BitOffset>0x10</BitOffset>
  958. <BitWidth>0x7</BitWidth>
  959. <Access>R</Access>
  960. <Equation multiplier="0x2000" offset="0x08000000"/>
  961. </Bit>
  962. </AssignedBits>
  963. </Field>
  964. <Field>
  965. <Parameters address="0x400221E4" name="FLASH_SECWM_PRG2R" size="0x4"/>
  966. <AssignedBits>
  967. <Bit>
  968. <Name>SECWM2_STRT</Name>
  969. <Description>Bank 2 security WM area start sector</Description>
  970. <BitOffset>0x0</BitOffset>
  971. <BitWidth>0x7</BitWidth>
  972. <Access>W</Access>
  973. <Equation multiplier="0x2000" offset="0x08000000"/>
  974. </Bit>
  975. <Bit>
  976. <Name>SECWM2_END</Name>
  977. <Description>Bank 2 security WM area end sector</Description>
  978. <BitOffset>0x10</BitOffset>
  979. <BitWidth>0x7</BitWidth>
  980. <Access>W</Access>
  981. <Equation multiplier="0x2000" offset="0x08000000"/>
  982. </Bit>
  983. </AssignedBits>
  984. </Field>
  985. </Category>
  986. <Category>
  987. <Name>Write sector group protection 2</Name>
  988. <Field>
  989. <Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
  990. <AssignedBits>
  991. <Bit>
  992. <Name>WRPSGn2</Name>
  993. <Description>Bank 2 sector group protection option status byte</Description>
  994. <BitOffset>0x0</BitOffset>
  995. <BitWidth>0x20</BitWidth>
  996. <Access>R</Access>
  997. <Equation multiplier="0x2000" offset="0x08000000"/>
  998. </Bit>
  999. </AssignedBits>
  1000. </Field>
  1001. <Field>
  1002. <Parameters address="0x400221EC" name="FLASH_WRP2BR" size="0x4"/>
  1003. <AssignedBits>
  1004. <Bit>
  1005. <Name>WRPSGn2</Name>
  1006. <Description>Bank 2 sector group protection option status byte</Description>
  1007. <BitOffset>0x0</BitOffset>
  1008. <BitWidth>0x20</BitWidth>
  1009. <Access>W</Access>
  1010. <Equation multiplier="0x2000" offset="0x08000000"/>
  1011. </Bit>
  1012. </AssignedBits>
  1013. </Field>
  1014. </Category>
  1015. </Bank>
  1016. <Bank interface="JTAG_SWD">
  1017. <Parameters address="0x40022090" name="Bank 6" size="0x8"/>
  1018. <Category>
  1019. <Name>OTP write protection</Name>
  1020. <Field>
  1021. <Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
  1022. <AssignedBits>
  1023. <Bit>
  1024. <Name>LOCKBL</Name>
  1025. <Description>OTP Block Lock</Description>
  1026. <BitOffset>0x0</BitOffset>
  1027. <BitWidth>0x20</BitWidth>
  1028. <Access>R</Access>
  1029. <Equation multiplier="0x2000" offset="0x00000000"/>
  1030. </Bit>
  1031. </AssignedBits>
  1032. </Field>
  1033. <Field>
  1034. <Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
  1035. <AssignedBits>
  1036. <Bit>
  1037. <Name>LOCKBL</Name>
  1038. <Description>OTP Block Lock</Description>
  1039. <BitOffset>0x0</BitOffset>
  1040. <BitWidth>0x20</BitWidth>
  1041. <Access>W</Access>
  1042. <Equation multiplier="0x2000" offset="0x00000000"/>
  1043. </Bit>
  1044. </AssignedBits>
  1045. </Field>
  1046. </Category>
  1047. </Bank>
  1048. <Bank interface="JTAG_SWD">
  1049. <Parameters address="0x400220F0" name="Bank 7" size="0x8"/>
  1050. <Category>
  1051. <Name>Flash data bank 1 sectors</Name>
  1052. <Field>
  1053. <Parameters address="0x400220F0" name="FLASH_WRP2BR" size="0x4"/>
  1054. <AssignedBits>
  1055. <Bit>
  1056. <Name>EDATA1_EN</Name>
  1057. <Description>Bank1 Flash high-cycle data enable</Description>
  1058. <BitOffset>0xF</BitOffset>
  1059. <BitWidth>0x1</BitWidth>
  1060. <Access>R</Access>
  1061. <Values>
  1062. <Val value="0x0">No Flash high-cycle data area</Val>
  1063. <Val value="0x1">Flash high-cycle data is used</Val>
  1064. </Values>
  1065. </Bit>
  1066. <Bit>
  1067. <Name>EDATA1_STRT</Name>
  1068. <Description>EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  1069. <BitOffset>0x0</BitOffset>
  1070. <BitWidth>0x3</BitWidth>
  1071. <Access>R</Access>
  1072. <Equation multiplier="0x1" offset="0x0"/>
  1073. </Bit>
  1074. </AssignedBits>
  1075. </Field>
  1076. <Field>
  1077. <Parameters address="0x400220F4" name="FLASH_WRP2BR" size="0x4"/>
  1078. <AssignedBits>
  1079. <Bit>
  1080. <Name>EDATA1_EN</Name>
  1081. <Description>Bank1 Flash high-cycle data enable</Description>
  1082. <BitOffset>0xF</BitOffset>
  1083. <BitWidth>0x1</BitWidth>
  1084. <Access>W</Access>
  1085. <Values>
  1086. <Val value="0x0">No Flash high-cycle data area</Val>
  1087. <Val value="0x1">Flash high-cycle data is used</Val>
  1088. </Values>
  1089. </Bit>
  1090. <Bit>
  1091. <Name>EDATA1_STRT</Name>
  1092. <Description>EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  1093. <BitOffset>0x0</BitOffset>
  1094. <BitWidth>0x3</BitWidth>
  1095. <Access>W</Access>
  1096. <Equation multiplier="0x1" offset="0x0"/>
  1097. </Bit>
  1098. </AssignedBits>
  1099. </Field>
  1100. </Category>
  1101. </Bank>
  1102. <Bank interface="JTAG_SWD">
  1103. <Parameters address="0x400221F0" name="Bank 8" size="0x8"/>
  1104. <Category>
  1105. <Name>Flash data bank 2 sectors</Name>
  1106. <Field>
  1107. <Parameters address="0x400221F0" name="FLASH_WRP2BR" size="0x4"/>
  1108. <AssignedBits>
  1109. <Bit>
  1110. <Name>EDATA2_EN</Name>
  1111. <Description>Bank2 Flash high-cycle data enable</Description>
  1112. <BitOffset>0xF</BitOffset>
  1113. <BitWidth>0x1</BitWidth>
  1114. <Access>R</Access>
  1115. <Values>
  1116. <Val value="0x0">No Flash high-cycle data area</Val>
  1117. <Val value="0x1">Flash high-cycle data is used</Val>
  1118. </Values>
  1119. </Bit>
  1120. <Bit>
  1121. <Name>EDATA2_STRT</Name>
  1122. <Description>EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  1123. <BitOffset>0x0</BitOffset>
  1124. <BitWidth>0x3</BitWidth>
  1125. <Access>R</Access>
  1126. <Equation multiplier="0x1" offset="0x0"/>
  1127. </Bit>
  1128. </AssignedBits>
  1129. </Field>
  1130. <Field>
  1131. <Parameters address="0x400221F4" name="FLASH_WRP2BR" size="0x4"/>
  1132. <AssignedBits>
  1133. <Bit>
  1134. <Name>EDATA2_EN</Name>
  1135. <Description>Bank2 Flash high-cycle data enable</Description>
  1136. <BitOffset>0xF</BitOffset>
  1137. <BitWidth>0x1</BitWidth>
  1138. <Access>W</Access>
  1139. <Values>
  1140. <Val value="0x0">No Flash high-cycle data area</Val>
  1141. <Val value="0x1">Flash high-cycle data is used</Val>
  1142. </Values>
  1143. </Bit>
  1144. <Bit>
  1145. <Name>EDATA2_STRT</Name>
  1146. <Description>EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  1147. <BitOffset>0x0</BitOffset>
  1148. <BitWidth>0x3</BitWidth>
  1149. <Access>W</Access>
  1150. <Equation multiplier="0x1" offset="0x0"/>
  1151. </Bit>
  1152. </AssignedBits>
  1153. </Field>
  1154. </Category>
  1155. </Bank>
  1156. <Bank interface="JTAG_SWD">
  1157. <Parameters address="0x40022060" name="Bank 9" size="0x10"/>
  1158. <Category>
  1159. <Name>Flash EPOCH</Name>
  1160. <Field>
  1161. <Parameters address="0x40022060" name="FLASH_WRP2BR" size="0x4"/>
  1162. <AssignedBits>
  1163. <Bit>
  1164. <Name>NS_EPOCH</Name>
  1165. <Description>Non Volatile Non Secure EPOCH counter</Description>
  1166. <BitOffset>0x0</BitOffset>
  1167. <BitWidth>0x18</BitWidth>
  1168. <Access>R</Access>
  1169. <Equation multiplier="0x1" offset="0x00000000"/>
  1170. </Bit>
  1171. </AssignedBits>
  1172. </Field>
  1173. <Field>
  1174. <Parameters address="0x40022064" name="FLASH_WRP2BR" size="0x4"/>
  1175. <AssignedBits>
  1176. <Bit>
  1177. <Name>NS_EPOCH</Name>
  1178. <Description>Non Volatile Non Secure EPOCH counter</Description>
  1179. <BitOffset>0x0</BitOffset>
  1180. <BitWidth>0x18</BitWidth>
  1181. <Access>W</Access>
  1182. <Equation multiplier="0x1" offset="0x00000000"/>
  1183. </Bit>
  1184. </AssignedBits>
  1185. </Field>
  1186. <Field>
  1187. <Parameters address="0x40022068" name="FLASH_WRP2BR" size="0x4"/>
  1188. <AssignedBits>
  1189. <Bit>
  1190. <Name>SEC_EPOCH</Name>
  1191. <Description>Non Volatile Secure EPOCH counter</Description>
  1192. <BitOffset>0x0</BitOffset>
  1193. <BitWidth>0x18</BitWidth>
  1194. <Access>R</Access>
  1195. <Equation multiplier="0x1" offset="0x00000000"/>
  1196. </Bit>
  1197. </AssignedBits>
  1198. </Field>
  1199. <Field>
  1200. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  1201. <AssignedBits>
  1202. <Bit>
  1203. <Name>SEC_EPOCH</Name>
  1204. <Description>Non Volatile Secure EPOCH counter</Description>
  1205. <BitOffset>0x0</BitOffset>
  1206. <BitWidth>0x18</BitWidth>
  1207. <Access>W</Access>
  1208. <Equation multiplier="0x1" offset="0x00000000"/>
  1209. </Bit>
  1210. </AssignedBits>
  1211. </Field>
  1212. </Category>
  1213. </Bank>
  1214. <Bank interface="JTAG_SWD">
  1215. <Parameters address="0x400220F8" name="Bank 10" size="0x8"/>
  1216. <Category>
  1217. <Name>Flash HDP bank 1</Name>
  1218. <Field>
  1219. <Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
  1220. <AssignedBits>
  1221. <Bit>
  1222. <Name>HDP1_STRT</Name>
  1223. <Description>HDP barrier start set in number of 8kb sectors</Description>
  1224. <BitOffset>0x0</BitOffset>
  1225. <BitWidth>0x7</BitWidth>
  1226. <Access>R</Access>
  1227. <Equation multiplier="0x2000" offset="0x00000000"/>
  1228. </Bit>
  1229. <Bit>
  1230. <Name>HDP1_END</Name>
  1231. <Description>HDP barrier end set in number of 8kb sectors</Description>
  1232. <BitOffset>0x10</BitOffset>
  1233. <BitWidth>0x7</BitWidth>
  1234. <Access>R</Access>
  1235. <Equation multiplier="0x2000" offset="0x00000000"/>
  1236. </Bit>
  1237. </AssignedBits>
  1238. </Field>
  1239. <Field>
  1240. <Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
  1241. <AssignedBits>
  1242. <Bit>
  1243. <Name>HDP1_STRT</Name>
  1244. <Description>HDP barrier start set in number of 8kb sectors</Description>
  1245. <BitOffset>0x0</BitOffset>
  1246. <BitWidth>0x7</BitWidth>
  1247. <Access>W</Access>
  1248. <Equation multiplier="0x2000" offset="0x00000000"/>
  1249. </Bit>
  1250. <Bit>
  1251. <Name>HDP1_END</Name>
  1252. <Description>HDP barrier end set in number of 8kb sectors</Description>
  1253. <BitOffset>0x10</BitOffset>
  1254. <BitWidth>0x7</BitWidth>
  1255. <Access>W</Access>
  1256. <Equation multiplier="0x2000" offset="0x00000000"/>
  1257. </Bit>
  1258. </AssignedBits>
  1259. </Field>
  1260. </Category>
  1261. </Bank>
  1262. <Bank interface="JTAG_SWD">
  1263. <Parameters address="0x400221F8" name="Bank 11" size="0x8"/>
  1264. <Category>
  1265. <Name>Flash HDP bank 2</Name>
  1266. <Field>
  1267. <Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
  1268. <AssignedBits>
  1269. <Bit>
  1270. <Name>HDP2_STRT</Name>
  1271. <Description>HDP barrier start set in number of 8kb sectors</Description>
  1272. <BitOffset>0x0</BitOffset>
  1273. <BitWidth>0x7</BitWidth>
  1274. <Access>R</Access>
  1275. <Equation multiplier="0x2000" offset="0x00000000"/>
  1276. </Bit>
  1277. <Bit>
  1278. <Name>HDP2_END</Name>
  1279. <Description>HDP barrier end set in number of 8kb sectors</Description>
  1280. <BitOffset>0x10</BitOffset>
  1281. <BitWidth>0x7</BitWidth>
  1282. <Access>R</Access>
  1283. <Equation multiplier="0x2000" offset="0x00000000"/>
  1284. </Bit>
  1285. </AssignedBits>
  1286. </Field>
  1287. <Field>
  1288. <Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
  1289. <AssignedBits>
  1290. <Bit>
  1291. <Name>HDP2_STRT</Name>
  1292. <Description>HDP barrier start set in number of 8kb sectors</Description>
  1293. <BitOffset>0x0</BitOffset>
  1294. <BitWidth>0x7</BitWidth>
  1295. <Access>W</Access>
  1296. <Equation multiplier="0x2000" offset="0x00000000"/>
  1297. </Bit>
  1298. <Bit>
  1299. <Name>HDP2_END</Name>
  1300. <Description>HDP barrier end set in number of 8kb sectors</Description>
  1301. <BitOffset>0x10</BitOffset>
  1302. <BitWidth>0x7</BitWidth>
  1303. <Access>W</Access>
  1304. <Equation multiplier="0x2000" offset="0x00000000"/>
  1305. </Bit>
  1306. </AssignedBits>
  1307. </Field>
  1308. </Category>
  1309. </Bank>
  1310. </Configuration>
  1311. <Configuration config="1">
  1312. <Bank interface="JTAG_SWD">
  1313. <Parameters address="0x50022050" name="Bank 1" size="0x70"/>
  1314. <Category>
  1315. <Name>Product state</Name>
  1316. <Field>
  1317. <Parameters address="0x50022050" name="CUR" size="0x4"/>
  1318. <AssignedBits>
  1319. <Bit>
  1320. <Name>PRODUCT_STATE</Name>
  1321. <Description>Life state code.</Description>
  1322. <BitOffset>0x8</BitOffset>
  1323. <BitWidth>0x8</BitWidth>
  1324. <Access>R</Access>
  1325. <Values>
  1326. <Val value="0xED">Open</Val>
  1327. <Val value="0x17">Provisioning</Val>
  1328. <Val value="0x2E">iRoT-provisioned</Val>
  1329. <Val value="0xC6">TZ-Closed</Val>
  1330. <Val value="0x72">Closed</Val>
  1331. <Val value="0x5C">Locked</Val>
  1332. <Val value="0x9A">Regression</Val>
  1333. <Val value="0xA3">NS-Regression</Val>
  1334. </Values>
  1335. </Bit>
  1336. </AssignedBits>
  1337. </Field>
  1338. <Field>
  1339. <Parameters address="0x50022054" name="PRG" size="0x4"/>
  1340. <AssignedBits>
  1341. <Bit>
  1342. <Name>PRODUCT_STATE</Name>
  1343. <Description>Life state code.</Description>
  1344. <BitOffset>0x8</BitOffset>
  1345. <BitWidth>0x8</BitWidth>
  1346. <Access>W</Access>
  1347. <Values>
  1348. <Val value="0xED">Open</Val>
  1349. <Val value="0x17">Provisioning</Val>
  1350. <Val value="0x2E">iRoT-provisioned</Val>
  1351. <Val value="0xC6">TZ-Closed</Val>
  1352. <Val value="0x72">Closed</Val>
  1353. <Val value="0x5C">Locked</Val>
  1354. <Val value="0x9A">Regression</Val>
  1355. <Val value="0xA3">NS-Regression</Val>
  1356. </Values>
  1357. </Bit>
  1358. </AssignedBits>
  1359. </Field>
  1360. </Category>
  1361. <Category>
  1362. <Name>BOR Level</Name>
  1363. <Field>
  1364. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1365. <AssignedBits>
  1366. <Bit>
  1367. <Name>BOR_LEV</Name>
  1368. <Description>Brownout level option status bit.</Description>
  1369. <BitOffset>0x0</BitOffset>
  1370. <BitWidth>0x2</BitWidth>
  1371. <Access>R</Access>
  1372. <Values>
  1373. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1374. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1375. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1376. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1377. </Values>
  1378. </Bit>
  1379. </AssignedBits>
  1380. </Field>
  1381. <Field>
  1382. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1383. <AssignedBits>
  1384. <Bit>
  1385. <Name>BOR_LEV</Name>
  1386. <Description>Brownout level option status bit.</Description>
  1387. <BitOffset>0x0</BitOffset>
  1388. <BitWidth>0x2</BitWidth>
  1389. <Access>W</Access>
  1390. <Values>
  1391. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1392. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1393. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1394. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1395. </Values>
  1396. </Bit>
  1397. </AssignedBits>
  1398. </Field>
  1399. <Field>
  1400. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1401. <AssignedBits>
  1402. <Bit>
  1403. <Name>BORH_EN</Name>
  1404. <Description>Brownout high enable configuration bit</Description>
  1405. <BitOffset>0x2</BitOffset>
  1406. <BitWidth>0x1</BitWidth>
  1407. <Access>R</Access>
  1408. <Val value="0x0">disabled</Val>
  1409. <Val value="0x1">enabled</Val>
  1410. </Bit>
  1411. </AssignedBits>
  1412. </Field>
  1413. <Field>
  1414. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1415. <AssignedBits>
  1416. <Bit>
  1417. <Name>BORH_EN</Name>
  1418. <Description>Brownout high enable configuration bit</Description>
  1419. <BitOffset>0x2</BitOffset>
  1420. <BitWidth>0x1</BitWidth>
  1421. <Access>W</Access>
  1422. <Val value="0x0">disabled</Val>
  1423. <Val value="0x1">enabled</Val>
  1424. </Bit>
  1425. </AssignedBits>
  1426. </Field>
  1427. </Category>
  1428. <Category>
  1429. <Name>User Configuration</Name>
  1430. <Field>
  1431. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1432. <AssignedBits>
  1433. <Bit>
  1434. <Name>IO_VDD_HSLV</Name>
  1435. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  1436. <BitOffset>0x10</BitOffset>
  1437. <BitWidth>0x1</BitWidth>
  1438. <Access>R</Access>
  1439. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1440. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1441. </Bit>
  1442. </AssignedBits>
  1443. </Field>
  1444. <Field>
  1445. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1446. <AssignedBits>
  1447. <Bit>
  1448. <Name>IO_VDD_HSLV</Name>
  1449. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  1450. <BitOffset>0x10</BitOffset>
  1451. <BitWidth>0x1</BitWidth>
  1452. <Access>W</Access>
  1453. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1454. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1455. </Bit>
  1456. </AssignedBits>
  1457. </Field>
  1458. <Field>
  1459. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1460. <AssignedBits>
  1461. <Bit>
  1462. <Name>IO_VDDIO2_HSLV</Name>
  1463. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1464. <BitOffset>0x11</BitOffset>
  1465. <BitWidth>0x1</BitWidth>
  1466. <Access>R</Access>
  1467. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1468. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1469. </Bit>
  1470. </AssignedBits>
  1471. </Field>
  1472. <Field>
  1473. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1474. <AssignedBits>
  1475. <Bit>
  1476. <Name>IO_VDDIO2_HSLV</Name>
  1477. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1478. <BitOffset>0x11</BitOffset>
  1479. <BitWidth>0x1</BitWidth>
  1480. <Access>W</Access>
  1481. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1482. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1483. </Bit>
  1484. </AssignedBits>
  1485. </Field>
  1486. <Field>
  1487. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1488. <AssignedBits>
  1489. <Bit>
  1490. <Name>IWDG_STOP</Name>
  1491. <Description>Stop mode freeze option status bit.</Description>
  1492. <BitOffset>0x14</BitOffset>
  1493. <BitWidth>0x1</BitWidth>
  1494. <Access>R</Access>
  1495. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1496. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1497. </Bit>
  1498. </AssignedBits>
  1499. </Field>
  1500. <Field>
  1501. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1502. <AssignedBits>
  1503. <Bit>
  1504. <Name>IWDG_STOP</Name>
  1505. <Description>Stop mode freeze option status bit.</Description>
  1506. <BitOffset>0x14</BitOffset>
  1507. <BitWidth>0x1</BitWidth>
  1508. <Access>W</Access>
  1509. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1510. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1511. </Bit>
  1512. </AssignedBits>
  1513. </Field>
  1514. <Field>
  1515. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1516. <AssignedBits>
  1517. <Bit>
  1518. <Name>IWDG_STDBY</Name>
  1519. <Description>Standby mode freeze option status bit.</Description>
  1520. <BitOffset>0x15</BitOffset>
  1521. <BitWidth>0x1</BitWidth>
  1522. <Access>R</Access>
  1523. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1524. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  1525. </Bit>
  1526. </AssignedBits>
  1527. </Field>
  1528. <Field>
  1529. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1530. <AssignedBits>
  1531. <Bit>
  1532. <Name>IWDG_STDBY</Name>
  1533. <Description>Standby mode freeze option status bit.</Description>
  1534. <BitOffset>0x15</BitOffset>
  1535. <BitWidth>0x1</BitWidth>
  1536. <Access>W</Access>
  1537. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  1538. <Val value="0x1">Independent watchdog keep running in standby Stop mode.</Val>
  1539. </Bit>
  1540. </AssignedBits>
  1541. </Field>
  1542. <Field>
  1543. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1544. <AssignedBits>
  1545. <Bit>
  1546. <Name>BOOT_UBE</Name>
  1547. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  1548. <BitOffset>0x16</BitOffset>
  1549. <BitWidth>0x8</BitWidth>
  1550. <Access>R</Access>
  1551. <Values>
  1552. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  1553. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  1554. </Values>
  1555. </Bit>
  1556. </AssignedBits>
  1557. </Field>
  1558. <Field>
  1559. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1560. <AssignedBits>
  1561. <Bit>
  1562. <Name>BOOT_UBE</Name>
  1563. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  1564. <BitOffset>0x16</BitOffset>
  1565. <BitWidth>0x8</BitWidth>
  1566. <Access>W</Access>
  1567. <Values>
  1568. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  1569. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  1570. </Values>
  1571. </Bit>
  1572. </AssignedBits>
  1573. </Field>
  1574. <Field>
  1575. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1576. <AssignedBits>
  1577. <Bit>
  1578. <Name>SWAP_BANK</Name>
  1579. <Description>Bank swapping option status bit.</Description>
  1580. <BitOffset>0x1F</BitOffset>
  1581. <BitWidth>0x1</BitWidth>
  1582. <Access>R</Access>
  1583. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1584. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1585. </Bit>
  1586. </AssignedBits>
  1587. </Field>
  1588. <Field>
  1589. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1590. <AssignedBits>
  1591. <Bit>
  1592. <Name>SWAP_BANK</Name>
  1593. <Description>Bank swapping option status bit.</Description>
  1594. <BitOffset>0x1F</BitOffset>
  1595. <BitWidth>0x1</BitWidth>
  1596. <Access>W</Access>
  1597. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1598. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1599. </Bit>
  1600. </AssignedBits>
  1601. </Field>
  1602. <Field>
  1603. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1604. <AssignedBits>
  1605. <Bit>
  1606. <Name>IWDG_SW</Name>
  1607. <Description>IWDG control mode option status bit.</Description>
  1608. <BitOffset>0x3</BitOffset>
  1609. <BitWidth>0x1</BitWidth>
  1610. <Access>R</Access>
  1611. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1612. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1613. </Bit>
  1614. </AssignedBits>
  1615. </Field>
  1616. <Field>
  1617. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1618. <AssignedBits>
  1619. <Bit>
  1620. <Name>IWDG_SW</Name>
  1621. <Description>IWDG control mode option status bit.</Description>
  1622. <BitOffset>0x3</BitOffset>
  1623. <BitWidth>0x1</BitWidth>
  1624. <Access>W</Access>
  1625. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1626. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1627. </Bit>
  1628. </AssignedBits>
  1629. </Field>
  1630. <Field>
  1631. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1632. <AssignedBits>
  1633. <Bit>
  1634. <Name>WWDG_SW</Name>
  1635. <Description>WWDG control mode option status bit.</Description>
  1636. <BitOffset>0x4</BitOffset>
  1637. <BitWidth>0x1</BitWidth>
  1638. <Access>R</Access>
  1639. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1640. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1641. </Bit>
  1642. </AssignedBits>
  1643. </Field>
  1644. <Field>
  1645. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1646. <AssignedBits>
  1647. <Bit>
  1648. <Name>WWDG_SW</Name>
  1649. <Description>WWDG control mode option status bit.</Description>
  1650. <BitOffset>0x4</BitOffset>
  1651. <BitWidth>0x1</BitWidth>
  1652. <Access>W</Access>
  1653. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  1654. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  1655. </Bit>
  1656. </AssignedBits>
  1657. </Field>
  1658. <Field>
  1659. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1660. <AssignedBits>
  1661. <Bit>
  1662. <Name>NRST_STOP</Name>
  1663. <Description>Core domain Stop entry reset option status bit.</Description>
  1664. <BitOffset>0x6</BitOffset>
  1665. <BitWidth>0x1</BitWidth>
  1666. <Access>R</Access>
  1667. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  1668. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  1669. </Bit>
  1670. </AssignedBits>
  1671. </Field>
  1672. <Field>
  1673. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1674. <AssignedBits>
  1675. <Bit>
  1676. <Name>NRST_STOP</Name>
  1677. <Description>Core domain Stop entry reset option status bit.</Description>
  1678. <BitOffset>0x6</BitOffset>
  1679. <BitWidth>0x1</BitWidth>
  1680. <Access>W</Access>
  1681. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  1682. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  1683. </Bit>
  1684. </AssignedBits>
  1685. </Field>
  1686. <Field>
  1687. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1688. <AssignedBits>
  1689. <Bit>
  1690. <Name>NRST_STDBY</Name>
  1691. <Description>Core domain Standby entry reset option status bit.</Description>
  1692. <BitOffset>0x7</BitOffset>
  1693. <BitWidth>0x1</BitWidth>
  1694. <Access>R</Access>
  1695. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1696. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1697. </Bit>
  1698. </AssignedBits>
  1699. </Field>
  1700. <Field>
  1701. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1702. <AssignedBits>
  1703. <Bit>
  1704. <Name>NRST_STDBY</Name>
  1705. <Description>Core domain Standby entry reset option status bit.</Description>
  1706. <BitOffset>0x7</BitOffset>
  1707. <BitWidth>0x1</BitWidth>
  1708. <Access>W</Access>
  1709. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1710. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1711. </Bit>
  1712. </AssignedBits>
  1713. </Field>
  1714. </Category>
  1715. </Bank>
  1716. <Bank interface="JTAG_SWD">
  1717. <Parameters address="0x50022070" name="Bank 2" size="0x10"/>
  1718. <Category>
  1719. <Name>User Configuration 2</Name>
  1720. <Field>
  1721. <Parameters address="0x50022070" name="FLASH_WRP1AR" size="0x4"/>
  1722. <AssignedBits>
  1723. <Bit>
  1724. <Name>TZEN</Name>
  1725. <Description>Trust Zone Enable configuration bits</Description>
  1726. <BitOffset>0x18</BitOffset>
  1727. <BitWidth>0x8</BitWidth>
  1728. <Access>R</Access>
  1729. <Values>
  1730. <Val value="0xC3">Trust zone disabled</Val>
  1731. <Val value="0xB4">Trust zone enabled</Val>
  1732. </Values>
  1733. </Bit>
  1734. <Bit>
  1735. <Name>HUK_PUF</Name>
  1736. <Description>This bit configures the source and use of the unique key</Description>
  1737. <BitOffset>0xF</BitOffset>
  1738. <BitWidth>0x1</BitWidth>
  1739. <Access>R</Access>
  1740. <Values>
  1741. <Val value="0x0">The key is treated as HUK</Val>
  1742. <Val value="0x1">The key is treated as PUF</Val>
  1743. </Values>
  1744. </Bit>
  1745. <Bit>
  1746. <Name>USBPD_DIS</Name>
  1747. <Description>USB power delivery configuration option bit</Description>
  1748. <BitOffset>0x8</BitOffset>
  1749. <BitWidth>0x1</BitWidth>
  1750. <Access>R</Access>
  1751. <Values>
  1752. <Val value="0x0">Enabled</Val>
  1753. <Val value="0x1">Disabled</Val>
  1754. </Values>
  1755. </Bit>
  1756. <Bit>
  1757. <Name>SRAM2_ECC</Name>
  1758. <Description>ECC in SRAM2 region configuration bit</Description>
  1759. <BitOffset>0x6</BitOffset>
  1760. <BitWidth>0x1</BitWidth>
  1761. <Access>R</Access>
  1762. <Values>
  1763. <Val value="0x0">SRAM2 ECC check enabled </Val>
  1764. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1765. </Values>
  1766. </Bit>
  1767. <Bit>
  1768. <Name>SRAM3_ECC</Name>
  1769. <Description>ECC in SRAM3 region configuration bit</Description>
  1770. <BitOffset>0x5</BitOffset>
  1771. <BitWidth>0x1</BitWidth>
  1772. <Access>R</Access>
  1773. <Values>
  1774. <Val value="0x0">SRAM3 ECC check enabled </Val>
  1775. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1776. </Values>
  1777. </Bit>
  1778. <Bit>
  1779. <Name>BKPRAM_ECC</Name>
  1780. <Description>ECC in BKPRAM region configuration bit</Description>
  1781. <BitOffset>0x4</BitOffset>
  1782. <BitWidth>0x1</BitWidth>
  1783. <Access>R</Access>
  1784. <Values>
  1785. <Val value="0x0">BKPRAM ECC check enabled </Val>
  1786. <Val value="0x1">BKPRAM ECC check disabled</Val>
  1787. </Values>
  1788. </Bit>
  1789. <Bit>
  1790. <Name>SRAM2_RST</Name>
  1791. <Description>SRAM2 Erase when system reset</Description>
  1792. <BitOffset>0x3</BitOffset>
  1793. <BitWidth>0x1</BitWidth>
  1794. <Access>R</Access>
  1795. <Values>
  1796. <Val value="0x0">SRAM2 erase when system reset</Val>
  1797. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  1798. </Values>
  1799. </Bit>
  1800. <Bit>
  1801. <Name>SRAM1_3_RST</Name>
  1802. <Description>SRAM1 and SRAM3 erase upon system reset</Description>
  1803. <BitOffset>0x2</BitOffset>
  1804. <BitWidth>0x1</BitWidth>
  1805. <Access>R</Access>
  1806. <Values>
  1807. <Val value="0x0">SRAM1 and SRAM3 erased when a system reset occurs</Val>
  1808. <Val value="0x1">SRAM1 and SRAM3 not erased when a system reset occurs</Val>
  1809. </Values>
  1810. </Bit>
  1811. </AssignedBits>
  1812. </Field>
  1813. <Field>
  1814. <Parameters address="0x50022074" name="FLASH_WRP1AR" size="0x4"/>
  1815. <AssignedBits>
  1816. <Bit>
  1817. <Name>TZEN</Name>
  1818. <Description>Trust Zone Enable configuration bits</Description>
  1819. <BitOffset>0x18</BitOffset>
  1820. <BitWidth>0x8</BitWidth>
  1821. <Access>W</Access>
  1822. <Values>
  1823. <Val value="0xC3">Trust zone disabled</Val>
  1824. <Val value="0xB4">Trust zone enabled</Val>
  1825. </Values>
  1826. </Bit>
  1827. <Bit>
  1828. <Name>HUK_PUF</Name>
  1829. <Description>This bit configures the source and use of the unique key</Description>
  1830. <BitOffset>0xF</BitOffset>
  1831. <BitWidth>0x1</BitWidth>
  1832. <Access>W</Access>
  1833. <Values>
  1834. <Val value="0x0">The key is treated as HUK</Val>
  1835. <Val value="0x1">The key is treated as PUF</Val>
  1836. </Values>
  1837. </Bit>
  1838. <Bit>
  1839. <Name>USBPD_DIS</Name>
  1840. <Description>USB power delivery configuration option bit</Description>
  1841. <BitOffset>0x8</BitOffset>
  1842. <BitWidth>0x1</BitWidth>
  1843. <Access>W</Access>
  1844. <Values>
  1845. <Val value="0x0">Enabled</Val>
  1846. <Val value="0x1">Disabled</Val>
  1847. </Values>
  1848. </Bit>
  1849. <Bit>
  1850. <Name>SRAM2_ECC</Name>
  1851. <Description>ECC in SRAM2 region configuration bit</Description>
  1852. <BitOffset>0x6</BitOffset>
  1853. <BitWidth>0x1</BitWidth>
  1854. <Access>W</Access>
  1855. <Values>
  1856. <Val value="0x0">SRAM2 ECC check enabled </Val>
  1857. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1858. </Values>
  1859. </Bit>
  1860. <Bit>
  1861. <Name>SRAM3_ECC</Name>
  1862. <Description>ECC in SRAM3 region configuration bit</Description>
  1863. <BitOffset>0x5</BitOffset>
  1864. <BitWidth>0x1</BitWidth>
  1865. <Access>W</Access>
  1866. <Values>
  1867. <Val value="0x0">SRAM3 ECC check enabled </Val>
  1868. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1869. </Values>
  1870. </Bit>
  1871. <Bit>
  1872. <Name>BKPRAM_ECC</Name>
  1873. <Description>ECC in BKPRAM region configuration bit</Description>
  1874. <BitOffset>0x4</BitOffset>
  1875. <BitWidth>0x1</BitWidth>
  1876. <Access>W</Access>
  1877. <Values>
  1878. <Val value="0x0">BKPRAM ECC check enabled </Val>
  1879. <Val value="0x1">BKPRAM ECC check disabled</Val>
  1880. </Values>
  1881. </Bit>
  1882. <Bit>
  1883. <Name>SRAM2_RST</Name>
  1884. <Description>SRAM2 Erase when system reset</Description>
  1885. <BitOffset>0x3</BitOffset>
  1886. <BitWidth>0x1</BitWidth>
  1887. <Access>W</Access>
  1888. <Values>
  1889. <Val value="0x0">SRAM2 erase when system reset</Val>
  1890. <Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
  1891. </Values>
  1892. </Bit>
  1893. <Bit>
  1894. <Name>SRAM1_3_RST</Name>
  1895. <Description>SRAM1 and SRAM3 erase upon system reset</Description>
  1896. <BitOffset>0x2</BitOffset>
  1897. <BitWidth>0x1</BitWidth>
  1898. <Access>W</Access>
  1899. <Values>
  1900. <Val value="0x0">SRAM1 and SRAM3 erased when a system reset occurs</Val>
  1901. <Val value="0x1">SRAM1 and SRAM3 not erased when a system reset occurs</Val>
  1902. </Values>
  1903. </Bit>
  1904. </AssignedBits>
  1905. </Field>
  1906. </Category>
  1907. </Bank>
  1908. <Bank interface="JTAG_SWD">
  1909. <Parameters address="0x50022080" name="Bank 3" size="0x10"/>
  1910. <Category>
  1911. <Name>Boot Configuration</Name>
  1912. <Field>
  1913. <Parameters address="0x50022080" name="FLASH_WRP2AR" size="0x4"/>
  1914. <AssignedBits>
  1915. <Bit>
  1916. <Name>NSBOOTADD</Name>
  1917. <Description>Non secure unique boot entry address</Description>
  1918. <BitOffset>0x8</BitOffset>
  1919. <BitWidth>0x18</BitWidth>
  1920. <Access>R</Access>
  1921. <Equation multiplier="0x100" offset="0x00000000"/>
  1922. </Bit>
  1923. <Bit>
  1924. <Name>NSBOOT_LOCK</Name>
  1925. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings</Description>
  1926. <BitOffset>0x0</BitOffset>
  1927. <BitWidth>0x8</BitWidth>
  1928. <Access>R</Access>
  1929. <Values>
  1930. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  1931. <Val value="0xB4">The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  1932. </Values>
  1933. </Bit>
  1934. </AssignedBits>
  1935. </Field>
  1936. <Field>
  1937. <Parameters address="0x50022084" name="FLASH_WRP2AR" size="0x4"/>
  1938. <AssignedBits>
  1939. <Bit>
  1940. <Name>NSBOOTADD</Name>
  1941. <Description>Non secure unique boot entry address</Description>
  1942. <BitOffset>0x8</BitOffset>
  1943. <BitWidth>0x18</BitWidth>
  1944. <Access>W</Access>
  1945. <Equation multiplier="0x100" offset="0x00000000"/>
  1946. </Bit>
  1947. <Bit>
  1948. <Name>NSBOOT_LOCK</Name>
  1949. <Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings</Description>
  1950. <BitOffset>0x0</BitOffset>
  1951. <BitWidth>0x8</BitWidth>
  1952. <Access>W</Access>
  1953. <Values>
  1954. <Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
  1955. <Val value="0xB4">The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  1956. </Values>
  1957. </Bit>
  1958. </AssignedBits>
  1959. </Field>
  1960. <Field>
  1961. <Parameters address="0x50022088" name="FLASH_OPTR" size="0x4"/>
  1962. <AssignedBits>
  1963. <Bit>
  1964. <Name>SECBOOT_LOCK</Name>
  1965. <Description>A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.</Description>
  1966. <BitOffset>0x0</BitOffset>
  1967. <BitWidth>0x8</BitWidth>
  1968. <Access>R</Access>
  1969. <Values>
  1970. <Val value="0xC3">The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.</Val>
  1971. <Val value="0xB4">The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  1972. </Values>
  1973. </Bit>
  1974. <Bit>
  1975. <Name>SECBOOTADD</Name>
  1976. <Description>Unique Boot Entry Secure Adress</Description>
  1977. <BitOffset>0x8</BitOffset>
  1978. <BitWidth>0x18</BitWidth>
  1979. <Access>R</Access>
  1980. <Equation multiplier="0x100" offset="0x00000000"/>
  1981. </Bit>
  1982. </AssignedBits>
  1983. </Field>
  1984. <Field>
  1985. <Parameters address="0x5002208C" name="FLASH_OPTR" size="0x4"/>
  1986. <AssignedBits>
  1987. <Bit>
  1988. <Name>SECBOOT_LOCK</Name>
  1989. <Description>A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.</Description>
  1990. <BitOffset>0x0</BitOffset>
  1991. <BitWidth>0x8</BitWidth>
  1992. <Access>W</Access>
  1993. <Values>
  1994. <Val value="0xC3">The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.</Val>
  1995. <Val value="0xB4">The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).</Val>
  1996. </Values>
  1997. </Bit>
  1998. <Bit>
  1999. <Name>SECBOOTADD</Name>
  2000. <Description>Unique Boot Entry Secure Adress.</Description>
  2001. <BitOffset>0x8</BitOffset>
  2002. <BitWidth>0x18</BitWidth>
  2003. <Access>W</Access>
  2004. <Equation multiplier="0x100" offset="0x00000000"/>
  2005. </Bit>
  2006. </AssignedBits>
  2007. </Field>
  2008. </Category>
  2009. </Bank>
  2010. <Bank interface="JTAG_SWD">
  2011. <Parameters address="0x500220E0" name="Bank 4" size="0x10"/>
  2012. <Category>
  2013. <Name>Bank1 - Flash watermark area definition</Name>
  2014. <Field>
  2015. <Parameters address="0x500220E0" name="FLASH_SECWM_CUR1R" size="0x4"/>
  2016. <AssignedBits>
  2017. <Bit>
  2018. <Name>SECWM1_STRT</Name>
  2019. <Description>Bank 1 security WM area 1 start sector</Description>
  2020. <BitOffset>0x0</BitOffset>
  2021. <BitWidth>0x7</BitWidth>
  2022. <Access>R</Access>
  2023. <Equation multiplier="0x2000" offset="0x08000000"/>
  2024. </Bit>
  2025. <Bit>
  2026. <Name>SECWM1_END</Name>
  2027. <Description>Bank 1 security WM area 1 end sector</Description>
  2028. <BitOffset>0x10</BitOffset>
  2029. <BitWidth>0x7</BitWidth>
  2030. <Access>R</Access>
  2031. <Equation multiplier="0x2000" offset="0x08000000"/>
  2032. </Bit>
  2033. </AssignedBits>
  2034. </Field>
  2035. <Field>
  2036. <Parameters address="0x500220E4" name="FLASH_SECWM_PRG1R" size="0x4"/>
  2037. <AssignedBits>
  2038. <Bit>
  2039. <Name>SECWM1_STRT</Name>
  2040. <Description>Bank 1 security WM area 1 start sector</Description>
  2041. <BitOffset>0x0</BitOffset>
  2042. <BitWidth>0x7</BitWidth>
  2043. <Access>W</Access>
  2044. <Equation multiplier="0x2000" offset="0x08000000"/>
  2045. </Bit>
  2046. <Bit>
  2047. <Name>SECWM1_END</Name>
  2048. <Description>Bank 1 security WM area 1 end sector</Description>
  2049. <BitOffset>0x10</BitOffset>
  2050. <BitWidth>0x7</BitWidth>
  2051. <Access>W</Access>
  2052. <Equation multiplier="0x2000" offset="0x08000000"/>
  2053. </Bit>
  2054. </AssignedBits>
  2055. </Field>
  2056. </Category>
  2057. <Category>
  2058. <Name>Write sector group protection 1</Name>
  2059. <Field>
  2060. <Parameters address="0x500220E8" name="FLASH_WRP2BR" size="0x4"/>
  2061. <AssignedBits>
  2062. <Bit>
  2063. <Name>WRPSGn1</Name>
  2064. <Description>Bank 1 sector group protection option status byte</Description>
  2065. <BitOffset>0x0</BitOffset>
  2066. <BitWidth>0x20</BitWidth>
  2067. <Access>R</Access>
  2068. <Equation multiplier="0x2000" offset="0x08000000"/>
  2069. </Bit>
  2070. </AssignedBits>
  2071. </Field>
  2072. <Field>
  2073. <Parameters address="0x500220EC" name="FLASH_WRP2BR" size="0x4"/>
  2074. <AssignedBits>
  2075. <Bit>
  2076. <Name>WRPSGn1</Name>
  2077. <Description>Bank 1 sector group protection option status byte</Description>
  2078. <BitOffset>0x0</BitOffset>
  2079. <BitWidth>0x20</BitWidth>
  2080. <Access>W</Access>
  2081. <Equation multiplier="0x2000" offset="0x08000000"/>
  2082. </Bit>
  2083. </AssignedBits>
  2084. </Field>
  2085. </Category>
  2086. </Bank>
  2087. <Bank interface="JTAG_SWD">
  2088. <Parameters address="0x500221E0" name="Bank 5" size="0x10"/>
  2089. <Category>
  2090. <Name>Bank2 - Flash watermark area definition</Name>
  2091. <Field>
  2092. <Parameters address="0x500221E0" name="FLASH_SECWM_CUR2R" size="0x4"/>
  2093. <AssignedBits>
  2094. <Bit>
  2095. <Name>SECWM2_STRT</Name>
  2096. <Description>Bank 2 security WM area start sector</Description>
  2097. <BitOffset>0x0</BitOffset>
  2098. <BitWidth>0x7</BitWidth>
  2099. <Access>R</Access>
  2100. <Equation multiplier="0x2000" offset="0x08000000"/>
  2101. </Bit>
  2102. <Bit>
  2103. <Name>SECWM2_END</Name>
  2104. <Description>Bank 2 security WM area end sector</Description>
  2105. <BitOffset>0x10</BitOffset>
  2106. <BitWidth>0x7</BitWidth>
  2107. <Access>R</Access>
  2108. <Equation multiplier="0x2000" offset="0x08000000"/>
  2109. </Bit>
  2110. </AssignedBits>
  2111. </Field>
  2112. <Field>
  2113. <Parameters address="0x500221E4" name="FLASH_SECWM_PRG2R" size="0x4"/>
  2114. <AssignedBits>
  2115. <Bit>
  2116. <Name>SECWM2_STRT</Name>
  2117. <Description>Bank 2 security WM area start sector</Description>
  2118. <BitOffset>0x0</BitOffset>
  2119. <BitWidth>0x7</BitWidth>
  2120. <Access>W</Access>
  2121. <Equation multiplier="0x2000" offset="0x08000000"/>
  2122. </Bit>
  2123. <Bit>
  2124. <Name>SECWM2_END</Name>
  2125. <Description>Bank 2 security WM area end sector</Description>
  2126. <BitOffset>0x10</BitOffset>
  2127. <BitWidth>0x7</BitWidth>
  2128. <Access>W</Access>
  2129. <Equation multiplier="0x2000" offset="0x08000000"/>
  2130. </Bit>
  2131. </AssignedBits>
  2132. </Field>
  2133. </Category>
  2134. <Category>
  2135. <Name>Write sector group protection 2</Name>
  2136. <Field>
  2137. <Parameters address="0x500221E8" name="FLASH_WRP2BR" size="0x4"/>
  2138. <AssignedBits>
  2139. <Bit>
  2140. <Name>WRPSGn2</Name>
  2141. <Description>Bank 2 sector group protection option status byte</Description>
  2142. <BitOffset>0x0</BitOffset>
  2143. <BitWidth>0x20</BitWidth>
  2144. <Access>R</Access>
  2145. <Equation multiplier="0x2000" offset="0x08000000"/>
  2146. </Bit>
  2147. </AssignedBits>
  2148. </Field>
  2149. <Field>
  2150. <Parameters address="0x500221EC" name="FLASH_WRP2BR" size="0x4"/>
  2151. <AssignedBits>
  2152. <Bit>
  2153. <Name>WRPSGn2</Name>
  2154. <Description>Bank 2 sector group protection option status byte</Description>
  2155. <BitOffset>0x0</BitOffset>
  2156. <BitWidth>0x20</BitWidth>
  2157. <Access>W</Access>
  2158. <Equation multiplier="0x2000" offset="0x08000000"/>
  2159. </Bit>
  2160. </AssignedBits>
  2161. </Field>
  2162. </Category>
  2163. </Bank>
  2164. <Bank interface="JTAG_SWD">
  2165. <Parameters address="0x50022090" name="Bank 6" size="0x8"/>
  2166. <Category>
  2167. <Name>OTP write protection</Name>
  2168. <Field>
  2169. <Parameters address="0x50022090" name="FLASH_WRP2BR" size="0x4"/>
  2170. <AssignedBits>
  2171. <Bit>
  2172. <Name>LOCKBL</Name>
  2173. <Description>OTP Block Lock</Description>
  2174. <BitOffset>0x0</BitOffset>
  2175. <BitWidth>0x20</BitWidth>
  2176. <Access>R</Access>
  2177. <Equation multiplier="0x2000" offset="0x00000000"/>
  2178. </Bit>
  2179. </AssignedBits>
  2180. </Field>
  2181. <Field>
  2182. <Parameters address="0x50022094" name="FLASH_WRP2BR" size="0x4"/>
  2183. <AssignedBits>
  2184. <Bit>
  2185. <Name>LOCKBL</Name>
  2186. <Description>OTP Block Lock</Description>
  2187. <BitOffset>0x0</BitOffset>
  2188. <BitWidth>0x20</BitWidth>
  2189. <Access>W</Access>
  2190. <Equation multiplier="0x2000" offset="0x00000000"/>
  2191. </Bit>
  2192. </AssignedBits>
  2193. </Field>
  2194. </Category>
  2195. </Bank>
  2196. <Bank interface="JTAG_SWD">
  2197. <Parameters address="0x500220F0" name="Bank 7" size="0x8"/>
  2198. <Category>
  2199. <Name>Flash data bank 1 sectors</Name>
  2200. <Field>
  2201. <Parameters address="0x500220F0" name="FLASH_WRP2BR" size="0x4"/>
  2202. <AssignedBits>
  2203. <Bit>
  2204. <Name>EDATA1_EN</Name>
  2205. <Description>Bank1 Flash high-cycle data enable</Description>
  2206. <BitOffset>0xF</BitOffset>
  2207. <BitWidth>0x1</BitWidth>
  2208. <Access>R</Access>
  2209. <Values>
  2210. <Val value="0x0">No Flash high-cycle data area</Val>
  2211. <Val value="0x1">Flash high-cycle data is used</Val>
  2212. </Values>
  2213. </Bit>
  2214. <Bit>
  2215. <Name>EDATA1_STRT</Name>
  2216. <Description>EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  2217. <BitOffset>0x0</BitOffset>
  2218. <BitWidth>0x3</BitWidth>
  2219. <Access>R</Access>
  2220. <Equation multiplier="0x1" offset="0x0"/>
  2221. </Bit>
  2222. </AssignedBits>
  2223. </Field>
  2224. <Field>
  2225. <Parameters address="0x500220F4" name="FLASH_WRP2BR" size="0x4"/>
  2226. <AssignedBits>
  2227. <Bit>
  2228. <Name>EDATA1_EN</Name>
  2229. <Description>Bank1 Flash high-cycle data enable</Description>
  2230. <BitOffset>0xF</BitOffset>
  2231. <BitWidth>0x1</BitWidth>
  2232. <Access>W</Access>
  2233. <Values>
  2234. <Val value="0x0">No Flash high-cycle data area</Val>
  2235. <Val value="0x1">Flash high-cycle data is used</Val>
  2236. </Values>
  2237. </Bit>
  2238. <Bit>
  2239. <Name>EDATA1_STRT</Name>
  2240. <Description>EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  2241. <BitOffset>0x0</BitOffset>
  2242. <BitWidth>0x3</BitWidth>
  2243. <Access>W</Access>
  2244. <Equation multiplier="0x1" offset="0x0"/>
  2245. </Bit>
  2246. </AssignedBits>
  2247. </Field>
  2248. </Category>
  2249. </Bank>
  2250. <Bank interface="JTAG_SWD">
  2251. <Parameters address="0x500221F0" name="Bank 8" size="0x8"/>
  2252. <Category>
  2253. <Name>Flash data bank 2 sectors </Name>
  2254. <Field>
  2255. <Parameters address="0x500221F0" name="FLASH_WRP2BR" size="0x4"/>
  2256. <AssignedBits>
  2257. <Bit>
  2258. <Name>EDATA2_EN</Name>
  2259. <Description>Bank2 Flash high-cycle data enable</Description>
  2260. <BitOffset>0xF</BitOffset>
  2261. <BitWidth>0x1</BitWidth>
  2262. <Access>R</Access>
  2263. <Values>
  2264. <Val value="0x0">No Flash high-cycle data area</Val>
  2265. <Val value="0x1">Flash high-cycle data is used</Val>
  2266. </Values>
  2267. </Bit>
  2268. <Bit>
  2269. <Name>EDATA2_STRT</Name>
  2270. <Description>EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  2271. <BitOffset>0x0</BitOffset>
  2272. <BitWidth>0x3</BitWidth>
  2273. <Access>R</Access>
  2274. <Equation multiplier="0x1" offset="0x0"/>
  2275. </Bit>
  2276. </AssignedBits>
  2277. </Field>
  2278. <Field>
  2279. <Parameters address="0x500221F4" name="FLASH_WRP2BR" size="0x4"/>
  2280. <AssignedBits>
  2281. <Bit>
  2282. <Name>EDATA2_EN</Name>
  2283. <Description>Bank2 Flash high-cycle data enable</Description>
  2284. <BitOffset>0xF</BitOffset>
  2285. <BitWidth>0x1</BitWidth>
  2286. <Access>W</Access>
  2287. <Values>
  2288. <Val value="0x0">No Flash high-cycle data area</Val>
  2289. <Val value="0x1">Flash high-cycle data is used</Val>
  2290. </Values>
  2291. </Bit>
  2292. <Bit>
  2293. <Name>EDATA2_STRT</Name>
  2294. <Description>EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  2295. <BitOffset>0x0</BitOffset>
  2296. <BitWidth>0x3</BitWidth>
  2297. <Access>W</Access>
  2298. <Equation multiplier="0x1" offset="0x0"/>
  2299. </Bit>
  2300. </AssignedBits>
  2301. </Field>
  2302. </Category>
  2303. </Bank>
  2304. <Bank interface="JTAG_SWD">
  2305. <Parameters address="0x50022060" name="Bank 9" size="0x10"/>
  2306. <Category>
  2307. <Name>Flash EPOCH</Name>
  2308. <Field>
  2309. <Parameters address="0x50022060" name="FLASH_WRP2BR" size="0x4"/>
  2310. <AssignedBits>
  2311. <Bit>
  2312. <Name>NS_EPOCH</Name>
  2313. <Description>Non Volatile Non Secure EPOCH counter</Description>
  2314. <BitOffset>0x0</BitOffset>
  2315. <BitWidth>0x18</BitWidth>
  2316. <Access>R</Access>
  2317. <Equation multiplier="0x1" offset="0x00000000"/>
  2318. </Bit>
  2319. </AssignedBits>
  2320. </Field>
  2321. <Field>
  2322. <Parameters address="0x50022064" name="FLASH_WRP2BR" size="0x4"/>
  2323. <AssignedBits>
  2324. <Bit>
  2325. <Name>NS_EPOCH</Name>
  2326. <Description>Non Volatile Non Secure EPOCH counter</Description>
  2327. <BitOffset>0x0</BitOffset>
  2328. <BitWidth>0x18</BitWidth>
  2329. <Access>W</Access>
  2330. <Equation multiplier="0x1" offset="0x00000000"/>
  2331. </Bit>
  2332. </AssignedBits>
  2333. </Field>
  2334. <Field>
  2335. <Parameters address="0x50022068" name="FLASH_WRP2BR" size="0x4"/>
  2336. <AssignedBits>
  2337. <Bit>
  2338. <Name>SEC_EPOCH</Name>
  2339. <Description>Non Volatile Secure EPOCH counter</Description>
  2340. <BitOffset>0x0</BitOffset>
  2341. <BitWidth>0x18</BitWidth>
  2342. <Access>R</Access>
  2343. <Equation multiplier="0x1" offset="0x00000000"/>
  2344. </Bit>
  2345. </AssignedBits>
  2346. </Field>
  2347. <Field>
  2348. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  2349. <AssignedBits>
  2350. <Bit>
  2351. <Name>SEC_EPOCH</Name>
  2352. <Description>Non Volatile Secure EPOCH counter</Description>
  2353. <BitOffset>0x0</BitOffset>
  2354. <BitWidth>0x18</BitWidth>
  2355. <Access>W</Access>
  2356. <Equation multiplier="0x1" offset="0x00000000"/>
  2357. </Bit>
  2358. </AssignedBits>
  2359. </Field>
  2360. </Category>
  2361. </Bank>
  2362. <Bank interface="JTAG_SWD">
  2363. <Parameters address="0x500220F8" name="Bank 10" size="0x8"/>
  2364. <Category>
  2365. <Name>Flash HDP bank 1</Name>
  2366. <Field>
  2367. <Parameters address="0x500220F8" name="FLASH_WRP2BR" size="0x4"/>
  2368. <AssignedBits>
  2369. <Bit>
  2370. <Name>HDP1_STRT</Name>
  2371. <Description>HDP barrier start set in number of 8kb sectors</Description>
  2372. <BitOffset>0x0</BitOffset>
  2373. <BitWidth>0x7</BitWidth>
  2374. <Access>R</Access>
  2375. <Equation multiplier="0x2000" offset="0x00000000"/>
  2376. </Bit>
  2377. <Bit>
  2378. <Name>HDP1_END</Name>
  2379. <Description>HDP barrier end set in number of 8kb sectors</Description>
  2380. <BitOffset>0x10</BitOffset>
  2381. <BitWidth>0x7</BitWidth>
  2382. <Access>R</Access>
  2383. <Equation multiplier="0x2000" offset="0x00000000"/>
  2384. </Bit>
  2385. </AssignedBits>
  2386. </Field>
  2387. <Field>
  2388. <Parameters address="0x500220FC" name="FLASH_WRP2BR" size="0x4"/>
  2389. <AssignedBits>
  2390. <Bit>
  2391. <Name>HDP1_STRT</Name>
  2392. <Description>HDP barrier start set in number of 8kb sectors</Description>
  2393. <BitOffset>0x0</BitOffset>
  2394. <BitWidth>0x7</BitWidth>
  2395. <Access>W</Access>
  2396. <Equation multiplier="0x2000" offset="0x00000000"/>
  2397. </Bit>
  2398. <Bit>
  2399. <Name>HDP1_END</Name>
  2400. <Description>HDP barrier end set in number of 8kb sectors</Description>
  2401. <BitOffset>0x10</BitOffset>
  2402. <BitWidth>0x7</BitWidth>
  2403. <Access>W</Access>
  2404. <Equation multiplier="0x2000" offset="0x00000000"/>
  2405. </Bit>
  2406. </AssignedBits>
  2407. </Field>
  2408. </Category>
  2409. </Bank>
  2410. <Bank interface="JTAG_SWD">
  2411. <Parameters address="0x500221F8" name="Bank 11" size="0x8"/>
  2412. <Category>
  2413. <Name>Flash HDP bank 2</Name>
  2414. <Field>
  2415. <Parameters address="0x500221F8" name="FLASH_WRP2BR" size="0x4"/>
  2416. <AssignedBits>
  2417. <Bit>
  2418. <Name>HDP2_STRT</Name>
  2419. <Description>HDP barrier start set in number of 8kb sectors</Description>
  2420. <BitOffset>0x0</BitOffset>
  2421. <BitWidth>0x7</BitWidth>
  2422. <Access>R</Access>
  2423. <Equation multiplier="0x2000" offset="0x00000000"/>
  2424. </Bit>
  2425. <Bit>
  2426. <Name>HDP2_END</Name>
  2427. <Description>HDP barrier end set in number of 8kb sectors</Description>
  2428. <BitOffset>0x10</BitOffset>
  2429. <BitWidth>0x7</BitWidth>
  2430. <Access>R</Access>
  2431. <Equation multiplier="0x2000" offset="0x00000000"/>
  2432. </Bit>
  2433. </AssignedBits>
  2434. </Field>
  2435. <Field>
  2436. <Parameters address="0x500221FC" name="FLASH_WRP2BR" size="0x4"/>
  2437. <AssignedBits>
  2438. <Bit>
  2439. <Name>HDP2_STRT</Name>
  2440. <Description>HDP barrier start set in number of 8kb sectors</Description>
  2441. <BitOffset>0x0</BitOffset>
  2442. <BitWidth>0x7</BitWidth>
  2443. <Access>W</Access>
  2444. <Equation multiplier="0x2000" offset="0x00000000"/>
  2445. </Bit>
  2446. <Bit>
  2447. <Name>HDP2_END</Name>
  2448. <Description>HDP barrier end set in number of 8kb sectors</Description>
  2449. <BitOffset>0x10</BitOffset>
  2450. <BitWidth>0x7</BitWidth>
  2451. <Access>W</Access>
  2452. <Equation multiplier="0x2000" offset="0x00000000"/>
  2453. </Bit>
  2454. </AssignedBits>
  2455. </Field>
  2456. </Category>
  2457. </Bank>
  2458. </Configuration>
  2459. <Bank interface="Bootloader">
  2460. <Parameters address="0x40022050" name="Bank 1" size="0x8"/>
  2461. <Category>
  2462. <Name>Product state</Name>
  2463. <Field>
  2464. <Parameters address="0x40022050" name="CUR" size="0x4"/>
  2465. <AssignedBits>
  2466. <Bit>
  2467. <Name>PRODUCT_STATE</Name>
  2468. <Description>Life state code.</Description>
  2469. <BitOffset>0x8</BitOffset>
  2470. <BitWidth>0x8</BitWidth>
  2471. <Access>R</Access>
  2472. <Values>
  2473. <Val value="0xED">Open</Val>
  2474. <Val value="0x17">Provisioning</Val>
  2475. <Val value="0x2E">iRoT-provisioned</Val>
  2476. <Val value="0xC6">TZ-Closed</Val>
  2477. <Val value="0x72">Closed</Val>
  2478. <Val value="0x5C">Locked</Val>
  2479. <Val value="0x9A">Regression</Val>
  2480. <Val value="0xA3">NS-Regression</Val>
  2481. </Values>
  2482. </Bit>
  2483. </AssignedBits>
  2484. </Field>
  2485. <Field>
  2486. <Parameters address="0x40022054" name="PRG" size="0x4"/>
  2487. <AssignedBits>
  2488. <Bit>
  2489. <Name>PRODUCT_STATE</Name>
  2490. <Description>Life state code.</Description>
  2491. <BitOffset>0x8</BitOffset>
  2492. <BitWidth>0x8</BitWidth>
  2493. <Access>W</Access>
  2494. <Values>
  2495. <Val value="0xED">Open</Val>
  2496. <Val value="0x17">Provisioning</Val>
  2497. <Val value="0x2E">iRoT-provisioned</Val>
  2498. <Val value="0xC6">TZ-Closed</Val>
  2499. <Val value="0x72">Closed</Val>
  2500. <Val value="0x5C">Locked</Val>
  2501. <Val value="0x9A">Regression</Val>
  2502. <Val value="0xA3">NS-Regression</Val>
  2503. </Values>
  2504. </Bit>
  2505. </AssignedBits>
  2506. </Field>
  2507. </Category>
  2508. <Category>
  2509. <Name>BOR Level</Name>
  2510. <Field>
  2511. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2512. <AssignedBits>
  2513. <Bit>
  2514. <Name>BOR_LEV</Name>
  2515. <Description>Brownout level option status bit.</Description>
  2516. <BitOffset>0x0</BitOffset>
  2517. <BitWidth>0x2</BitWidth>
  2518. <Access>R</Access>
  2519. <Values>
  2520. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  2521. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  2522. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  2523. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  2524. </Values>
  2525. </Bit>
  2526. </AssignedBits>
  2527. </Field>
  2528. <Field>
  2529. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2530. <AssignedBits>
  2531. <Bit>
  2532. <Name>BOR_LEV</Name>
  2533. <Description>Brownout level option status bit.</Description>
  2534. <BitOffset>0x0</BitOffset>
  2535. <BitWidth>0x2</BitWidth>
  2536. <Access>W</Access>
  2537. <Values>
  2538. <Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  2539. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  2540. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  2541. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  2542. </Values>
  2543. </Bit>
  2544. </AssignedBits>
  2545. </Field>
  2546. <Field>
  2547. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2548. <AssignedBits>
  2549. <Bit>
  2550. <Name>BORH_EN</Name>
  2551. <Description>Brownout high enable configuration bit</Description>
  2552. <BitOffset>0x2</BitOffset>
  2553. <BitWidth>0x1</BitWidth>
  2554. <Access>R</Access>
  2555. <Val value="0x0">disabled</Val>
  2556. <Val value="0x1">enabled</Val>
  2557. </Bit>
  2558. </AssignedBits>
  2559. </Field>
  2560. <Field>
  2561. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2562. <AssignedBits>
  2563. <Bit>
  2564. <Name>BORH_EN</Name>
  2565. <Description>Brownout high enable configuration bit</Description>
  2566. <BitOffset>0x2</BitOffset>
  2567. <BitWidth>0x1</BitWidth>
  2568. <Access>W</Access>
  2569. <Val value="0x0">disabled</Val>
  2570. <Val value="0x1">enabled</Val>
  2571. </Bit>
  2572. </AssignedBits>
  2573. </Field>
  2574. </Category>
  2575. <Category>
  2576. <Name>User Configuration</Name>
  2577. <Field>
  2578. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2579. <AssignedBits>
  2580. <Bit>
  2581. <Name>IO_VDD_HSLV</Name>
  2582. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  2583. <BitOffset>0x10</BitOffset>
  2584. <BitWidth>0x1</BitWidth>
  2585. <Access>R</Access>
  2586. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  2587. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  2588. </Bit>
  2589. </AssignedBits>
  2590. </Field>
  2591. <Field>
  2592. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2593. <AssignedBits>
  2594. <Bit>
  2595. <Name>IO_VDD_HSLV</Name>
  2596. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  2597. <BitOffset>0x10</BitOffset>
  2598. <BitWidth>0x1</BitWidth>
  2599. <Access>W</Access>
  2600. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  2601. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  2602. </Bit>
  2603. </AssignedBits>
  2604. </Field>
  2605. <Field>
  2606. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2607. <AssignedBits>
  2608. <Bit>
  2609. <Name>IO_VDDIO2_HSLV</Name>
  2610. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  2611. <BitOffset>0x11</BitOffset>
  2612. <BitWidth>0x1</BitWidth>
  2613. <Access>R</Access>
  2614. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  2615. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  2616. </Bit>
  2617. </AssignedBits>
  2618. </Field>
  2619. <Field>
  2620. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2621. <AssignedBits>
  2622. <Bit>
  2623. <Name>IO_VDDIO2_HSLV</Name>
  2624. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  2625. <BitOffset>0x11</BitOffset>
  2626. <BitWidth>0x1</BitWidth>
  2627. <Access>W</Access>
  2628. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  2629. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  2630. </Bit>
  2631. </AssignedBits>
  2632. </Field>
  2633. <Field>
  2634. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2635. <AssignedBits>
  2636. <Bit>
  2637. <Name>IWDG_STOP</Name>
  2638. <Description>Stop mode freeze option status bit.</Description>
  2639. <BitOffset>0x14</BitOffset>
  2640. <BitWidth>0x1</BitWidth>
  2641. <Access>R</Access>
  2642. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  2643. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  2644. </Bit>
  2645. </AssignedBits>
  2646. </Field>
  2647. <Field>
  2648. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2649. <AssignedBits>
  2650. <Bit>
  2651. <Name>IWDG_STOP</Name>
  2652. <Description>Stop mode freeze option status bit.</Description>
  2653. <BitOffset>0x14</BitOffset>
  2654. <BitWidth>0x1</BitWidth>
  2655. <Access>W</Access>
  2656. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  2657. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  2658. </Bit>
  2659. </AssignedBits>
  2660. </Field>
  2661. <Field>
  2662. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2663. <AssignedBits>
  2664. <Bit>
  2665. <Name>IWDG_STDBY</Name>
  2666. <Description>Standby mode freeze option status bit.</Description>
  2667. <BitOffset>0x15</BitOffset>
  2668. <BitWidth>0x1</BitWidth>
  2669. <Access>R</Access>
  2670. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  2671. <Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
  2672. </Bit>
  2673. </AssignedBits>
  2674. </Field>
  2675. <Field>
  2676. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2677. <AssignedBits>
  2678. <Bit>
  2679. <Name>IWDG_STDBY</Name>
  2680. <Description>Standby mode freeze option status bit.</Description>
  2681. <BitOffset>0x15</BitOffset>
  2682. <BitWidth>0x1</BitWidth>
  2683. <Access>W</Access>
  2684. <Val value="0x0">Independent watchdog frozen in system standby mode</Val>
  2685. <Val value="0x1">Independent watchdog keep running in standby Stop mode.</Val>
  2686. </Bit>
  2687. </AssignedBits>
  2688. </Field>
  2689. <Field>
  2690. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2691. <AssignedBits>
  2692. <Bit>
  2693. <Name>BOOT_UBE</Name>
  2694. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  2695. <BitOffset>0x16</BitOffset>
  2696. <BitWidth>0x8</BitWidth>
  2697. <Access>R</Access>
  2698. <Values>
  2699. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  2700. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  2701. </Values>
  2702. </Bit>
  2703. </AssignedBits>
  2704. </Field>
  2705. <Field>
  2706. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2707. <AssignedBits>
  2708. <Bit>
  2709. <Name>BOOT_UBE</Name>
  2710. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  2711. <BitOffset>0x16</BitOffset>
  2712. <BitWidth>0x8</BitWidth>
  2713. <Access>W</Access>
  2714. <Values>
  2715. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  2716. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  2717. </Values>
  2718. </Bit>
  2719. </AssignedBits>
  2720. </Field>
  2721. <Field>
  2722. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2723. <AssignedBits>
  2724. <Bit>
  2725. <Name>SWAP_BANK</Name>
  2726. <Description>Bank swapping option status bit.</Description>
  2727. <BitOffset>0x1F</BitOffset>
  2728. <BitWidth>0x1</BitWidth>
  2729. <Access>R</Access>
  2730. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  2731. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  2732. </Bit>
  2733. </AssignedBits>
  2734. </Field>
  2735. <Field>
  2736. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2737. <AssignedBits>
  2738. <Bit>
  2739. <Name>SWAP_BANK</Name>
  2740. <Description>Bank swapping option status bit.</Description>
  2741. <BitOffset>0x1F</BitOffset>
  2742. <BitWidth>0x1</BitWidth>
  2743. <Access>W</Access>
  2744. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  2745. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  2746. </Bit>
  2747. </AssignedBits>
  2748. </Field>
  2749. <Field>
  2750. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2751. <AssignedBits>
  2752. <Bit>
  2753. <Name>IWDG_SW</Name>
  2754. <Description>IWDG control mode option status bit.</Description>
  2755. <BitOffset>0x3</BitOffset>
  2756. <BitWidth>0x1</BitWidth>
  2757. <Access>R</Access>
  2758. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  2759. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  2760. </Bit>
  2761. </AssignedBits>
  2762. </Field>
  2763. <Field>
  2764. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2765. <AssignedBits>
  2766. <Bit>
  2767. <Name>IWDG_SW</Name>
  2768. <Description>IWDG control mode option status bit.</Description>
  2769. <BitOffset>0x3</BitOffset>
  2770. <BitWidth>0x1</BitWidth>
  2771. <Access>W</Access>
  2772. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  2773. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  2774. </Bit>
  2775. </AssignedBits>
  2776. </Field>
  2777. <Field>
  2778. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2779. <AssignedBits>
  2780. <Bit>
  2781. <Name>WWDG_SW</Name>
  2782. <Description>WWDG control mode option status bit.</Description>
  2783. <BitOffset>0x4</BitOffset>
  2784. <BitWidth>0x1</BitWidth>
  2785. <Access>R</Access>
  2786. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  2787. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  2788. </Bit>
  2789. </AssignedBits>
  2790. </Field>
  2791. <Field>
  2792. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2793. <AssignedBits>
  2794. <Bit>
  2795. <Name>WWDG_SW</Name>
  2796. <Description>WWDG control mode option status bit.</Description>
  2797. <BitOffset>0x4</BitOffset>
  2798. <BitWidth>0x1</BitWidth>
  2799. <Access>W</Access>
  2800. <Val value="0x0">WWDG watchdog is controlled by hardware</Val>
  2801. <Val value="0x1">WWDG watchdog is controlled by software</Val>
  2802. </Bit>
  2803. </AssignedBits>
  2804. </Field>
  2805. <Field>
  2806. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2807. <AssignedBits>
  2808. <Bit>
  2809. <Name>NRST_STOP</Name>
  2810. <Description>Core domain Stop entry reset option status bit.</Description>
  2811. <BitOffset>0x6</BitOffset>
  2812. <BitWidth>0x1</BitWidth>
  2813. <Access>R</Access>
  2814. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  2815. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  2816. </Bit>
  2817. </AssignedBits>
  2818. </Field>
  2819. <Field>
  2820. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2821. <AssignedBits>
  2822. <Bit>
  2823. <Name>NRST_STOP</Name>
  2824. <Description>Core domain Stop entry reset option status bit.</Description>
  2825. <BitOffset>0x6</BitOffset>
  2826. <BitWidth>0x1</BitWidth>
  2827. <Access>W</Access>
  2828. <Val value="0x0">a reset is generated when entering Stop or Stop2 mode on core domain</Val>
  2829. <Val value="0x1">no reset generated when entering Stop or Stop2 mode on core domain</Val>
  2830. </Bit>
  2831. </AssignedBits>
  2832. </Field>
  2833. <Field>
  2834. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  2835. <AssignedBits>
  2836. <Bit>
  2837. <Name>NRST_STDBY</Name>
  2838. <Description>Core domain Standby entry reset option status bit.</Description>
  2839. <BitOffset>0x7</BitOffset>
  2840. <BitWidth>0x1</BitWidth>
  2841. <Access>R</Access>
  2842. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  2843. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  2844. </Bit>
  2845. </AssignedBits>
  2846. </Field>
  2847. <Field>
  2848. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  2849. <AssignedBits>
  2850. <Bit>
  2851. <Name>NRST_STDBY</Name>
  2852. <Description>Core domain Standby entry reset option status bit.</Description>
  2853. <BitOffset>0x7</BitOffset>
  2854. <BitWidth>0x1</BitWidth>
  2855. <Access>W</Access>
  2856. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  2857. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  2858. </Bit>
  2859. </AssignedBits>
  2860. </Field>
  2861. </Category>
  2862. </Bank>
  2863. </Peripheral>
  2864. </Peripherals>
  2865. </Device>
  2866. </Root>