STM32_Prog_DB_0x492.xml 64 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800
  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x492</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32WBA55/54</Name>
  9. <Series>STM32WBA</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- 1M non secure TZEN=0x0 -->
  15. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  16. </Configuration>
  17. <Configuration number="0x1"> <!-- 1M secure + RDP=0xAA + TZEN=0x1 -->
  18. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  19. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  20. </Configuration>
  21. <!-- <Configuration number="0x2"> -->
  22. <!-- <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x00000055"/> </RDP> -->
  23. <!-- <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN> -->
  24. <!-- </Configuration> -->
  25. <Configuration number="0x3"> <!-- 1M secure + TZEN=0x1 -->
  26. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  27. </Configuration>
  28. </Interface>
  29. <!-- Bootloader Interface -->
  30. <Interface name="Bootloader">
  31. <Configuration number="0x4"> <!-- 1M non Secure-->
  32. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  33. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  34. </Configuration>
  35. <Configuration number="0x5"> <!-- 1M Secure-->
  36. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  37. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  38. </Configuration>
  39. </Interface>
  40. </Configurations>
  41. <!-- Peripherals -->
  42. <Peripherals>
  43. <!-- Embedded SRAM -->
  44. <Peripheral>
  45. <Name>Embedded SRAM</Name>
  46. <Type>Storage</Type>
  47. <Description/>
  48. <ErasedValue>0xFF</ErasedValue>
  49. <Access>RWE</Access>
  50. <!-- 128 KB FOR 1M of flash Size -->
  51. <Configuration config="0">
  52. <Parameters address="0x20000000" name="SRAM" size="0x20000"/>
  53. <Description/>
  54. <Organization>Single</Organization>
  55. <Bank name="Bank 1">
  56. <Field>
  57. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x20000"/>
  58. </Field>
  59. </Bank>
  60. </Configuration>
  61. <Configuration config="1,3">
  62. <Parameters address="0x30000000" name="SRAM" size="0x20000"/>
  63. <Description/>
  64. <Organization>Single</Organization>
  65. <Bank name="Bank 1">
  66. <Field>
  67. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x20000"/>
  68. </Field>
  69. </Bank>
  70. </Configuration>
  71. </Peripheral>
  72. <!-- Embedded Flash -->
  73. <Peripheral>
  74. <Name>Embedded Flash</Name>
  75. <Type>Storage</Type>
  76. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  77. <ErasedValue>0xFF</ErasedValue>
  78. <Access>RWE</Access>
  79. <FlashSize address="0xBF907A0" default="0x100000"/>
  80. <BootloaderVersion address="0x0BF8FEFA"/>
  81. <ReconnectAfterOB value="1"/>
  82. <Configuration config="0,1,3"> <!-- 1 Mbyte non secure -->
  83. <Parameters address="0x08000000" name=" 1 Mbyte Embedded Flash" size="0x100000"/>
  84. <Description/>
  85. <Organization>Single</Organization>
  86. <Allignement>0x10</Allignement>
  87. <Bank name="Bank 1">
  88. <Field>
  89. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  90. </Field>
  91. </Bank>
  92. </Configuration>
  93. <!--<Configuration config="1,3">
  94. <Parameters address="0x0c000000" name=" 1 Mbyte Embedded Flash" size="0x100000"/>
  95. <Description/>
  96. <Organization>Single</Organization>
  97. <Allignement>0x10</Allignement>
  98. <Bank name="Bank 1">
  99. <Field>
  100. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  101. </Field>
  102. </Bank>
  103. </Configuration>-->
  104. </Peripheral>
  105. <!-- Data EEPROM -->
  106. <Peripheral>
  107. <Name>Data EEPROM</Name>
  108. <Type>Storage</Type>
  109. <Description>The Data EEPROM memory block. It contains user data.</Description>
  110. <ErasedValue>0xFF</ErasedValue>
  111. <Access>RWE</Access>
  112. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  113. <Configuration config="1,3,5">
  114. <Parameters address="0x0c000000" name=" 1 Mbyte Data EEPROM" size="0x100000"/>
  115. <Description/>
  116. <Organization>Single</Organization>
  117. <Allignement>0x4</Allignement>
  118. <Bank name="Bank 1">
  119. <Field>
  120. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  121. </Field>
  122. </Bank>
  123. </Configuration>
  124. </Peripheral>
  125. <!-- OTP -->
  126. <Peripheral>
  127. <Name>OTP</Name>
  128. <Type>Storage</Type>
  129. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  130. <ErasedValue>0xFF</ErasedValue>
  131. <Access>RW</Access>
  132. <!-- 512 Bytes single bank -->
  133. <Configuration>
  134. <Parameters address="0x0BF90000" name=" 512 Bytes Data OTP" size="0x200"/>
  135. <Description/>
  136. <Organization>Single</Organization>
  137. <Allignement>0x4</Allignement>
  138. <Bank name="OTP">
  139. <Field>
  140. <Parameters address="0x0BF90000" name="OTP" occurence="0x1" size="0x200"/>
  141. </Field>
  142. </Bank>
  143. </Configuration>
  144. </Peripheral>
  145. <!-- Option Bytes -->
  146. <Peripheral>
  147. <Name>Option Bytes</Name>
  148. <Type>Configuration</Type>
  149. <Description/>
  150. <Access>RW</Access>
  151. <Configuration config="0">
  152. <Bank interface="JTAG_SWD">
  153. <Parameters address="0x40022040" name="Bank 1" size="0xA0"/>
  154. <Category>
  155. <Name>Read Out Protection</Name>
  156. <Field>
  157. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  158. <AssignedBits>
  159. <Bit>
  160. <Name>RDP</Name>
  161. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  162. <BitOffset>0x0</BitOffset>
  163. <BitWidth>0x8</BitWidth>
  164. <Access>RW</Access>
  165. <Values>
  166. <Val value="0xAA">Level 0, no protection</Val>
  167. <Val value="0xDC">Level 1, read protection of memories</Val>
  168. <Val value="0xCC">Level 2, chip protection</Val>
  169. </Values>
  170. </Bit>
  171. </AssignedBits>
  172. </Field>
  173. </Category>
  174. <Category>
  175. <Name>BOR Level</Name>
  176. <Field>
  177. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  178. <AssignedBits>
  179. <Bit>
  180. <Name>BOR_LEV</Name>
  181. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  182. <BitOffset>0x8</BitOffset>
  183. <BitWidth>0x3</BitWidth>
  184. <Access>RW</Access>
  185. <Values>
  186. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  187. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  188. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  189. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  190. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  191. </Values>
  192. </Bit>
  193. </AssignedBits>
  194. </Field>
  195. </Category>
  196. <Category>
  197. <Name>User Configuration</Name>
  198. <Field>
  199. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  200. <AssignedBits>
  201. <Bit>
  202. <Name>nRST_STOP</Name>
  203. <Description/>
  204. <BitOffset>0xC</BitOffset>
  205. <BitWidth>0x1</BitWidth>
  206. <Access>RW</Access>
  207. <Values>
  208. <Val value="0x0">Reset generated when entering Stop mode</Val>
  209. <Val value="0x1">No reset generated when entering Stop mode</Val>
  210. </Values>
  211. </Bit>
  212. <Bit>
  213. <Name>nRST_STDBY</Name>
  214. <Description/>
  215. <BitOffset>0xD</BitOffset>
  216. <BitWidth>0x1</BitWidth>
  217. <Access>RW</Access>
  218. <Values>
  219. <Val value="0x0">Reset generated when entering Standby mode</Val>
  220. <Val value="0x1">No reset generated when entering Standby mode</Val>
  221. </Values>
  222. </Bit>
  223. <Bit>
  224. <Name>SRAM1_RST</Name>
  225. <Description>SRAM1 erase upon system reset</Description>
  226. <BitOffset>0xF</BitOffset>
  227. <BitWidth>0x1</BitWidth>
  228. <Access>RW</Access>
  229. <Values>
  230. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  231. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  232. </Values>
  233. </Bit>
  234. <Bit>
  235. <Name>IWDG_SW</Name>
  236. <Description/>
  237. <BitOffset>0x10</BitOffset>
  238. <BitWidth>0x1</BitWidth>
  239. <Access>RW</Access>
  240. <Values>
  241. <Val value="0x0">Hardware independant watchdog</Val>
  242. <Val value="0x1">Software independant watchdog</Val>
  243. </Values>
  244. </Bit>
  245. <Bit>
  246. <Name>IWDG_STOP</Name>
  247. <Description/>
  248. <BitOffset>0x11</BitOffset>
  249. <BitWidth>0x1</BitWidth>
  250. <Access>RW</Access>
  251. <Values>
  252. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  253. <Val value="0x1">IWDG counter active in stop mode</Val>
  254. </Values>
  255. </Bit>
  256. <Bit>
  257. <Name>IWDG_STDBY</Name>
  258. <Description/>
  259. <BitOffset>0x12</BitOffset>
  260. <BitWidth>0x1</BitWidth>
  261. <Access>RW</Access>
  262. <Values>
  263. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  264. <Val value="0x1">IWDG counter active in standby mode</Val>
  265. </Values>
  266. </Bit>
  267. <Bit>
  268. <Name>WWDG_SW</Name>
  269. <Description/>
  270. <BitOffset>0x13</BitOffset>
  271. <BitWidth>0x1</BitWidth>
  272. <Access>RW</Access>
  273. <Values>
  274. <Val value="0x0">Hardware window watchdog</Val>
  275. <Val value="0x1">Software window watchdog</Val>
  276. </Values>
  277. </Bit>
  278. <Bit>
  279. <Name>SRAM2_PE</Name>
  280. <Description>SRAM2 parity check enable </Description>
  281. <BitOffset>0x18</BitOffset>
  282. <BitWidth>0x1</BitWidth>
  283. <Access>RW</Access>
  284. <Values>
  285. <Val value="0x0">SRAM2 PE check enabled</Val>
  286. <Val value="0x1">SRAM2 PE check disabled</Val>
  287. </Values>
  288. </Bit>
  289. <Bit>
  290. <Name>SRAM2_RST</Name>
  291. <Description>SRAM2 Erase when system reset</Description>
  292. <BitOffset>0x19</BitOffset>
  293. <BitWidth>0x1</BitWidth>
  294. <Access>RW</Access>
  295. <Values>
  296. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  297. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  298. </Values>
  299. </Bit>
  300. <Bit>
  301. <Name>nSWBOOT0</Name>
  302. <Description>Software BOOT0</Description>
  303. <BitOffset>0x1A</BitOffset>
  304. <BitWidth>0x1</BitWidth>
  305. <Access>RW</Access>
  306. <Values>
  307. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  308. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  309. </Values>
  310. </Bit>
  311. <Bit>
  312. <Name>nBOOT0</Name>
  313. <Description>nBOOT0 option bit</Description>
  314. <BitOffset>0x1B</BitOffset>
  315. <BitWidth>0x1</BitWidth>
  316. <Access>RW</Access>
  317. <Values>
  318. <Val value="0x0">nBOOT0 = 0</Val>
  319. <Val value="0x1">nBOOT0 = 1</Val>
  320. </Values>
  321. </Bit>
  322. <Bit>
  323. <Name>TZEN</Name>
  324. <Description>Global TrustZone security enable</Description>
  325. <BitOffset>0x1F</BitOffset>
  326. <BitWidth>0x1</BitWidth>
  327. <Access>RW</Access>
  328. <Values>
  329. <Val value="0x0">Global TrustZone security disabled</Val>
  330. <Val value="0x1">Global TrustZone security enabled</Val>
  331. </Values>
  332. </Bit>
  333. </AssignedBits>
  334. </Field>
  335. </Category>
  336. <Category>
  337. <Name>Boot Configuration</Name>
  338. <Field>
  339. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  340. <AssignedBits>
  341. <Bit>
  342. <Name>NSBOOTADD0</Name>
  343. <Description>Non-secure Boot base address 0</Description>
  344. <BitOffset>0x7</BitOffset>
  345. <BitWidth>0x19</BitWidth>
  346. <Access>RW</Access>
  347. <Equation multiplier="0x80" offset="0x0000000"/>
  348. </Bit>
  349. </AssignedBits>
  350. </Field>
  351. <Field>
  352. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  353. <AssignedBits>
  354. <Bit>
  355. <Name>NSBOOTADD1</Name>
  356. <Description>Non-secure Boot base address 1</Description>
  357. <BitOffset>0x7</BitOffset>
  358. <BitWidth>0x19</BitWidth>
  359. <Access>RW</Access>
  360. <Equation multiplier="0x80" offset="0x0000000"/>
  361. </Bit>
  362. </AssignedBits>
  363. </Field>
  364. </Category>
  365. <Category>
  366. <Name>Write Protection</Name>
  367. <Field>
  368. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  369. <AssignedBits>
  370. <Bit config="0,2">
  371. <Name>WRPA_PSTRT</Name>
  372. <Description>WPR first area &quot;A&quot; start page</Description>
  373. <BitOffset>0x0</BitOffset>
  374. <BitWidth>0x7</BitWidth>
  375. <Access>RW</Access>
  376. <Equation multiplier="0x2000" offset="0x08000000"/>
  377. </Bit>
  378. <Bit config="0,2">
  379. <Name>WRPA_PEND</Name>
  380. <Description>WPR first area &quot;A&quot; end page</Description>
  381. <BitOffset>0x10</BitOffset>
  382. <BitWidth>0x7</BitWidth>
  383. <Access>RW</Access>
  384. <Equation multiplier="0x2000" offset="0x08000000"/>
  385. </Bit>
  386. <Bit>
  387. <Name>UNLOCK_A</Name>
  388. <Description>WPR first area A unlock</Description>
  389. <BitOffset>0x1F</BitOffset>
  390. <BitWidth>0x1</BitWidth>
  391. <Access>RW</Access>
  392. <Values>
  393. <Val value="0x0">WRPA start and end pages locked</Val>
  394. <Val value="0x1">WRPA start and end pages unlocked</Val>
  395. </Values>
  396. </Bit>
  397. </AssignedBits>
  398. </Field>
  399. <Field>
  400. <Parameters address="0x4002205C" name="FLASH_WRPBR" size="0x4"/>
  401. <AssignedBits>
  402. <Bit config="0,2">
  403. <Name>WRPB_PSTRT</Name>
  404. <Description>WPR second area &quot;B&quot; start page</Description>
  405. <BitOffset>0x0</BitOffset>
  406. <BitWidth>0x7</BitWidth>
  407. <Access>RW</Access>
  408. <Equation multiplier="0x2000" offset="0x08000000"/>
  409. </Bit>
  410. <Bit config="0,2">
  411. <Name>WRPB_PEND</Name>
  412. <Description>WPR second area &quot;B&quot; end page</Description>
  413. <BitOffset>0x10</BitOffset>
  414. <BitWidth>0x7</BitWidth>
  415. <Access>RW</Access>
  416. <Equation multiplier="0x2000" offset="0x08000000"/>
  417. </Bit>
  418. <Bit>
  419. <Name>UNLOCK_B</Name>
  420. <Description>WPR second area B unlock</Description>
  421. <BitOffset>0x1F</BitOffset>
  422. <BitWidth>0x1</BitWidth>
  423. <Access>RW</Access>
  424. <Values>
  425. <Val value="0x0">WRPB start and end pages locked</Val>
  426. <Val value="0x1">WRPB start and end pages unlocked</Val>
  427. </Values>
  428. </Bit>
  429. </AssignedBits>
  430. </Field>
  431. </Category>
  432. </Bank>
  433. </Configuration>
  434. <Configuration config="1">
  435. <Bank interface="JTAG_SWD">
  436. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  437. <Category>
  438. <Name>Read Out Protection</Name>
  439. <Field>
  440. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  441. <AssignedBits>
  442. <Bit>
  443. <Name>RDP</Name>
  444. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  445. <BitOffset>0x0</BitOffset>
  446. <BitWidth>0x8</BitWidth>
  447. <Access>RW</Access>
  448. <Values>
  449. <Val value="0xAA">Level 0, no protection</Val>
  450. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  451. <Val value="0xDC">Level 1, read protection of memories</Val>
  452. <Val value="0xCC">Level 2, chip protection</Val>
  453. </Values>
  454. </Bit>
  455. </AssignedBits>
  456. </Field>
  457. </Category>
  458. <Category>
  459. <Name>BOR Level</Name>
  460. <Field>
  461. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  462. <AssignedBits>
  463. <Bit>
  464. <Name>BOR_LEV</Name>
  465. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  466. <BitOffset>0x8</BitOffset>
  467. <BitWidth>0x3</BitWidth>
  468. <Access>RW</Access>
  469. <Values>
  470. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  471. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  472. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  473. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  474. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  475. </Values>
  476. </Bit>
  477. </AssignedBits>
  478. </Field>
  479. </Category>
  480. <Category>
  481. <Name>User Configuration</Name>
  482. <Field>
  483. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  484. <AssignedBits>
  485. <Bit>
  486. <Name>nRST_STOP</Name>
  487. <Description/>
  488. <BitOffset>0xC</BitOffset>
  489. <BitWidth>0x1</BitWidth>
  490. <Access>RW</Access>
  491. <Values>
  492. <Val value="0x0">Reset generated when entering Stop mode</Val>
  493. <Val value="0x1">No reset generated when entering Stop mode</Val>
  494. </Values>
  495. </Bit>
  496. <Bit>
  497. <Name>nRST_STDBY</Name>
  498. <Description/>
  499. <BitOffset>0xD</BitOffset>
  500. <BitWidth>0x1</BitWidth>
  501. <Access>RW</Access>
  502. <Values>
  503. <Val value="0x0">Reset generated when entering Standby mode</Val>
  504. <Val value="0x1">No reset generated when entering Standby mode</Val>
  505. </Values>
  506. </Bit>
  507. <Bit>
  508. <Name>SRAM1_RST</Name>
  509. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  510. <BitOffset>0xF</BitOffset>
  511. <BitWidth>0x1</BitWidth>
  512. <Access>RW</Access>
  513. <Values>
  514. <Val value="0x0">SRAM1 erased when a system reset occurs</Val>
  515. <Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
  516. </Values>
  517. </Bit>
  518. <Bit>
  519. <Name>IWDG_SW</Name>
  520. <Description/>
  521. <BitOffset>0x10</BitOffset>
  522. <BitWidth>0x1</BitWidth>
  523. <Access>RW</Access>
  524. <Values>
  525. <Val value="0x0">Hardware independant watchdog</Val>
  526. <Val value="0x1">Software independant watchdog</Val>
  527. </Values>
  528. </Bit>
  529. <Bit>
  530. <Name>IWDG_STOP</Name>
  531. <Description/>
  532. <BitOffset>0x11</BitOffset>
  533. <BitWidth>0x1</BitWidth>
  534. <Access>RW</Access>
  535. <Values>
  536. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  537. <Val value="0x1">IWDG counter active in stop mode</Val>
  538. </Values>
  539. </Bit>
  540. <Bit>
  541. <Name>IWDG_STDBY</Name>
  542. <Description/>
  543. <BitOffset>0x12</BitOffset>
  544. <BitWidth>0x1</BitWidth>
  545. <Access>RW</Access>
  546. <Values>
  547. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  548. <Val value="0x1">IWDG counter active in standby mode</Val>
  549. </Values>
  550. </Bit>
  551. <Bit>
  552. <Name>WWDG_SW</Name>
  553. <Description/>
  554. <BitOffset>0x13</BitOffset>
  555. <BitWidth>0x1</BitWidth>
  556. <Access>RW</Access>
  557. <Values>
  558. <Val value="0x0">Hardware window watchdog</Val>
  559. <Val value="0x1">Software window watchdog</Val>
  560. </Values>
  561. </Bit>
  562. <Bit>
  563. <Name>SRAM2_PE</Name>
  564. <Description>SRAM2 parity check enable</Description>
  565. <BitOffset>0x18</BitOffset>
  566. <BitWidth>0x1</BitWidth>
  567. <Access>RW</Access>
  568. <Values>
  569. <Val value="0x0">SRAM2 parity check enable</Val>
  570. <Val value="0x1">SRAM2 parity check disable</Val>
  571. </Values>
  572. </Bit>
  573. <Bit>
  574. <Name>SRAM2_RST</Name>
  575. <Description>SRAM2 Erase when system reset</Description>
  576. <BitOffset>0x19</BitOffset>
  577. <BitWidth>0x1</BitWidth>
  578. <Access>RW</Access>
  579. <Values>
  580. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  581. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  582. </Values>
  583. </Bit>
  584. <Bit>
  585. <Name>nSWBOOT0</Name>
  586. <Description>Software BOOT0</Description>
  587. <BitOffset>0x1A</BitOffset>
  588. <BitWidth>0x1</BitWidth>
  589. <Access>RW</Access>
  590. <Values>
  591. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  592. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  593. </Values>
  594. </Bit>
  595. <Bit>
  596. <Name>nBOOT0</Name>
  597. <Description>nBOOT0 option bit</Description>
  598. <BitOffset>0x1B</BitOffset>
  599. <BitWidth>0x1</BitWidth>
  600. <Access>RW</Access>
  601. <Values>
  602. <Val value="0x0">nBOOT0 = 0</Val>
  603. <Val value="0x1">nBOOT0 = 1</Val>
  604. </Values>
  605. </Bit>
  606. <Bit>
  607. <Name>TZEN</Name>
  608. <Description>Global TrustZone security enable</Description>
  609. <BitOffset>0x1F</BitOffset>
  610. <BitWidth>0x1</BitWidth>
  611. <Access>RW</Access>
  612. <Values>
  613. <Val value="0x0">Global TrustZone security disabled</Val>
  614. <Val value="0x1">Global TrustZone security enabled</Val>
  615. </Values>
  616. </Bit>
  617. </AssignedBits>
  618. </Field>
  619. </Category>
  620. <Category>
  621. <Name>Boot Configuration</Name>
  622. <Field>
  623. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  624. <AssignedBits>
  625. <Bit>
  626. <Name>NSBOOTADD0</Name>
  627. <Description>Non-secure Boot base address 0</Description>
  628. <BitOffset>0x7</BitOffset>
  629. <BitWidth>0x19</BitWidth>
  630. <Access>RW</Access>
  631. <Equation multiplier="0x80" offset="0x0000000"/>
  632. </Bit>
  633. </AssignedBits>
  634. </Field>
  635. <Field>
  636. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  637. <AssignedBits>
  638. <Bit>
  639. <Name>NSBOOTADD1</Name>
  640. <Description>Non-secure Boot base address 1</Description>
  641. <BitOffset>0x7</BitOffset>
  642. <BitWidth>0x19</BitWidth>
  643. <Access>RW</Access>
  644. <Equation multiplier="0x80" offset="0x0000000"/>
  645. </Bit>
  646. </AssignedBits>
  647. </Field>
  648. <Field>
  649. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  650. <AssignedBits>
  651. <Bit>
  652. <Name>SECBOOTADD0</Name>
  653. <Description>Secure boot base address 0</Description>
  654. <BitOffset>0x7</BitOffset>
  655. <BitWidth>0x19</BitWidth>
  656. <Access>RW</Access>
  657. <Equation multiplier="0x80" offset="0x0000000"/>
  658. </Bit>
  659. </AssignedBits>
  660. </Field>
  661. <Field>
  662. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  663. <AssignedBits>
  664. <Bit>
  665. <Name>BOOT_LOCK</Name>
  666. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  667. <BitOffset>0x0</BitOffset>
  668. <BitWidth>0x1</BitWidth>
  669. <Access>RW</Access>
  670. <Values>
  671. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  672. <Val value="0x1">Boot forced from base address memory</Val>
  673. </Values>
  674. </Bit>
  675. </AssignedBits>
  676. </Field>
  677. </Category>
  678. <Category>
  679. <Name>Secure Area</Name>
  680. <Field>
  681. <Parameters address="0x50022050" name="FLASH_SECWMR1" size="0x4"/>
  682. <AssignedBits>
  683. <Bit>
  684. <Name>SECWM1_PSTRT</Name>
  685. <Description>Start page of secure area</Description>
  686. <BitOffset>0x0</BitOffset>
  687. <BitWidth>0x7</BitWidth>
  688. <Access>RW</Access>
  689. <Equation multiplier="0x2000" offset="0x08000000"/>
  690. </Bit>
  691. <Bit >
  692. <Name>SECWM1_PEND</Name>
  693. <Description>End page of first secure area</Description>
  694. <BitOffset>0x10</BitOffset>
  695. <BitWidth>0x7</BitWidth>
  696. <Access>RW</Access>
  697. <Equation multiplier="0x2000" offset="0x08000000"/>
  698. </Bit>
  699. </AssignedBits>
  700. </Field>
  701. <Field>
  702. <Parameters address="0x50022054" name="FLASH_SECWMR2" size="0x4"/>
  703. <AssignedBits>
  704. <Bit>
  705. <Name>HDP1_PEND</Name>
  706. <Description>End page of secure hide protection area</Description>
  707. <BitOffset>0x10</BitOffset>
  708. <BitWidth>0x7</BitWidth>
  709. <Access>RW</Access>
  710. <Equation multiplier="0x2000" offset="0xC003fff"/>
  711. </Bit>
  712. <Bit>
  713. <Name>HDP1EN</Name>
  714. <Description>Secure Hide protection first area enable</Description>
  715. <BitOffset>0x1F</BitOffset>
  716. <BitWidth>0x1</BitWidth>
  717. <Access>RW</Access>
  718. <Values>
  719. <Val value="0x0">No secHDP area</Val>
  720. <Val value="0x1">HDP first area is enabled</Val>
  721. </Values>
  722. </Bit>
  723. </AssignedBits>
  724. </Field>
  725. </Category>
  726. <Category>
  727. <Name>Write Protection 1</Name>
  728. <Field>
  729. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  730. <AssignedBits>
  731. <Bit>
  732. <Name>WRPA_PSTRT</Name>
  733. <Description>WPR first area &quot;A&quot; start page</Description>
  734. <BitOffset>0x0</BitOffset>
  735. <BitWidth>0x7</BitWidth>
  736. <Access>RW</Access>
  737. <Equation multiplier="0x2000" offset="0x08000000"/>
  738. </Bit>
  739. <Bit>
  740. <Name>WRPA_PEND</Name>
  741. <Description>WPR first area &quot;A&quot; end page</Description>
  742. <BitOffset>0x10</BitOffset>
  743. <BitWidth>0x7</BitWidth>
  744. <Access>RW</Access>
  745. <Equation multiplier="0x2000" offset="0x08000000"/>
  746. </Bit>
  747. <Bit>
  748. <Name>UNLOCK_A</Name>
  749. <Description>WPR first area A unlock</Description>
  750. <BitOffset>0x1F</BitOffset>
  751. <BitWidth>0x1</BitWidth>
  752. <Access>RW</Access>
  753. <Values>
  754. <Val value="0x0">WRPA start and end pages locked</Val>
  755. <Val value="0x1">WRPA start and end pages unlocked</Val>
  756. </Values>
  757. </Bit>
  758. </AssignedBits>
  759. </Field>
  760. <Field>
  761. <Parameters address="0x5002205C" name="FLASH_WRPBR" size="0x4"/>
  762. <AssignedBits>
  763. <Bit>
  764. <Name>WRPB_PSTRT</Name>
  765. <Description>WPR second area &quot;B&quot; start page</Description>
  766. <BitOffset>0x0</BitOffset>
  767. <BitWidth>0x7</BitWidth>
  768. <Access>RW</Access>
  769. <Equation multiplier="0x2000" offset="0x08000000"/>
  770. </Bit>
  771. <Bit>
  772. <Name>WRPB_PEND</Name>
  773. <Description>WPR second area &quot;B&quot; end page</Description>
  774. <BitOffset>0x10</BitOffset>
  775. <BitWidth>0x7</BitWidth>
  776. <Access>RW</Access>
  777. <Equation multiplier="0x2000" offset="0x08000000"/>
  778. </Bit>
  779. <Bit>
  780. <Name>UNLOCK_B</Name>
  781. <Description>WPR second area B unlock</Description>
  782. <BitOffset>0x1F</BitOffset>
  783. <BitWidth>0x1</BitWidth>
  784. <Access>RW</Access>
  785. <Values>
  786. <Val value="0x0">WRPB start and end pages locked</Val>
  787. <Val value="0x1">WRPB start and end pages unlocked</Val>
  788. </Values>
  789. </Bit>
  790. </AssignedBits>
  791. </Field>
  792. </Category>
  793. </Bank>
  794. </Configuration>
  795. <Configuration config="3">
  796. <Bank interface="JTAG_SWD">
  797. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  798. <Category>
  799. <Name>Read Out Protection</Name>
  800. <Field>
  801. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  802. <AssignedBits>
  803. <Bit>
  804. <Name>RDP</Name>
  805. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  806. <BitOffset>0x0</BitOffset>
  807. <BitWidth>0x8</BitWidth>
  808. <Access>RW</Access>
  809. <Values>
  810. <Val value="0xAA">Level 0, no protection</Val>
  811. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  812. <Val value="0xDC">Level 1, read protection of memories</Val>
  813. <Val value="0xCC">Level 2, chip protection</Val>
  814. </Values>
  815. </Bit>
  816. </AssignedBits>
  817. </Field>
  818. </Category>
  819. <Category>
  820. <Name>BOR Level</Name>
  821. <Field>
  822. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  823. <AssignedBits>
  824. <Bit>
  825. <Name>BOR_LEV</Name>
  826. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  827. <BitOffset>0x8</BitOffset>
  828. <BitWidth>0x3</BitWidth>
  829. <Access>RW</Access>
  830. <Values>
  831. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  832. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  833. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  834. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  835. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  836. </Values>
  837. </Bit>
  838. </AssignedBits>
  839. </Field>
  840. </Category>
  841. <Category>
  842. <Name>User Configuration</Name>
  843. <Field>
  844. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  845. <AssignedBits>
  846. <Bit>
  847. <Name>nRST_STOP</Name>
  848. <Description/>
  849. <BitOffset>0xC</BitOffset>
  850. <BitWidth>0x1</BitWidth>
  851. <Access>RW</Access>
  852. <Values>
  853. <Val value="0x0">Reset generated when entering Stop mode</Val>
  854. <Val value="0x1">No reset generated when entering Stop mode</Val>
  855. </Values>
  856. </Bit>
  857. <Bit>
  858. <Name>nRST_STDBY</Name>
  859. <Description/>
  860. <BitOffset>0xD</BitOffset>
  861. <BitWidth>0x1</BitWidth>
  862. <Access>RW</Access>
  863. <Values>
  864. <Val value="0x0">Reset generated when entering Standby mode</Val>
  865. <Val value="0x1">No reset generated when entering Standby mode</Val>
  866. </Values>
  867. </Bit>
  868. <Bit>
  869. <Name>nRST_SHDW</Name>
  870. <Description/>
  871. <BitOffset>0xE</BitOffset>
  872. <BitWidth>0x1</BitWidth>
  873. <Access>RW</Access>
  874. <Values>
  875. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  876. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  877. </Values>
  878. </Bit>
  879. <Bit>
  880. <Name>SRAM1_RST</Name>
  881. <Description>SRAM1 erase upon system reset</Description>
  882. <BitOffset>0xF</BitOffset>
  883. <BitWidth>0x1</BitWidth>
  884. <Access>RW</Access>
  885. <Values>
  886. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  887. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  888. </Values>
  889. </Bit>
  890. <Bit>
  891. <Name>IWDG_SW</Name>
  892. <Description/>
  893. <BitOffset>0x10</BitOffset>
  894. <BitWidth>0x1</BitWidth>
  895. <Access>RW</Access>
  896. <Values>
  897. <Val value="0x0">Hardware independant watchdog</Val>
  898. <Val value="0x1">Software independant watchdog</Val>
  899. </Values>
  900. </Bit>
  901. <Bit>
  902. <Name>IWDG_STOP</Name>
  903. <Description/>
  904. <BitOffset>0x11</BitOffset>
  905. <BitWidth>0x1</BitWidth>
  906. <Access>RW</Access>
  907. <Values>
  908. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  909. <Val value="0x1">IWDG counter active in stop mode</Val>
  910. </Values>
  911. </Bit>
  912. <Bit>
  913. <Name>IWDG_STDBY</Name>
  914. <Description/>
  915. <BitOffset>0x12</BitOffset>
  916. <BitWidth>0x1</BitWidth>
  917. <Access>RW</Access>
  918. <Values>
  919. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  920. <Val value="0x1">IWDG counter active in standby mode</Val>
  921. </Values>
  922. </Bit>
  923. <Bit>
  924. <Name>WWDG_SW</Name>
  925. <Description/>
  926. <BitOffset>0x13</BitOffset>
  927. <BitWidth>0x1</BitWidth>
  928. <Access>RW</Access>
  929. <Values>
  930. <Val value="0x0">Hardware window watchdog</Val>
  931. <Val value="0x1">Software window watchdog</Val>
  932. </Values>
  933. </Bit>
  934. <Bit>
  935. <Name>SRAM2_PE</Name>
  936. <Description>SRAM2 parity check enable</Description>
  937. <BitOffset>0x18</BitOffset>
  938. <BitWidth>0x1</BitWidth>
  939. <Access>RW</Access>
  940. <Values>
  941. <Val value="0x0">SRAM2 parity check enable</Val>
  942. <Val value="0x1">SRAM2 parity check disable</Val>
  943. </Values>
  944. </Bit>
  945. <Bit>
  946. <Name>SRAM2_RST</Name>
  947. <Description>SRAM2 Erase when system reset</Description>
  948. <BitOffset>0x19</BitOffset>
  949. <BitWidth>0x1</BitWidth>
  950. <Access>RW</Access>
  951. <Values>
  952. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  953. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  954. </Values>
  955. </Bit>
  956. <Bit>
  957. <Name>nSWBOOT0</Name>
  958. <Description>Software BOOT0</Description>
  959. <BitOffset>0x1A</BitOffset>
  960. <BitWidth>0x1</BitWidth>
  961. <Access>RW</Access>
  962. <Values>
  963. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  964. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  965. </Values>
  966. </Bit>
  967. <Bit>
  968. <Name>nBOOT0</Name>
  969. <Description>nBOOT0 option bit</Description>
  970. <BitOffset>0x1B</BitOffset>
  971. <BitWidth>0x1</BitWidth>
  972. <Access>RW</Access>
  973. <Values>
  974. <Val value="0x0">nBOOT0 = 0</Val>
  975. <Val value="0x1">nBOOT0 = 1</Val>
  976. </Values>
  977. </Bit>
  978. <Bit>
  979. <Name>TZEN</Name>
  980. <Description>Global TrustZone security enable</Description>
  981. <BitOffset>0x1F</BitOffset>
  982. <BitWidth>0x1</BitWidth>
  983. <Access>RW</Access>
  984. <Values>
  985. <Val value="0x0">Global TrustZone security disabled</Val>
  986. <Val value="0x1">Global TrustZone security enabled</Val>
  987. </Values>
  988. </Bit>
  989. </AssignedBits>
  990. </Field>
  991. </Category>
  992. <Category>
  993. <Name>Boot Configuration</Name>
  994. <Field>
  995. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  996. <AssignedBits>
  997. <Bit>
  998. <Name>NSBOOTADD0</Name>
  999. <Description>Non-secure Boot base address 0</Description>
  1000. <BitOffset>0x7</BitOffset>
  1001. <BitWidth>0x19</BitWidth>
  1002. <Access>RW</Access>
  1003. <Equation multiplier="0x80" offset="0x0000000"/>
  1004. </Bit>
  1005. </AssignedBits>
  1006. </Field>
  1007. <Field>
  1008. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1009. <AssignedBits>
  1010. <Bit>
  1011. <Name>NSBOOTADD1</Name>
  1012. <Description>Non-secure Boot base address 1</Description>
  1013. <BitOffset>0x7</BitOffset>
  1014. <BitWidth>0x19</BitWidth>
  1015. <Access>RW</Access>
  1016. <Equation multiplier="0x80" offset="0x0000000"/>
  1017. </Bit>
  1018. </AssignedBits>
  1019. </Field>
  1020. <Field>
  1021. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1022. <AssignedBits>
  1023. <Bit>
  1024. <Name>SECBOOTADD0</Name>
  1025. <Description>Secure boot base address 0</Description>
  1026. <BitOffset>0x7</BitOffset>
  1027. <BitWidth>0x19</BitWidth>
  1028. <Access>RW</Access>
  1029. <Equation multiplier="0x80" offset="0x0000000"/>
  1030. </Bit>
  1031. </AssignedBits>
  1032. </Field>
  1033. <Field>
  1034. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1035. <AssignedBits>
  1036. <Bit>
  1037. <Name>BOOT_LOCK</Name>
  1038. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1039. <BitOffset>0x0</BitOffset>
  1040. <BitWidth>0x1</BitWidth>
  1041. <Access>RW</Access>
  1042. <Values>
  1043. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1044. <Val value="0x1">Boot forced from base address memory</Val>
  1045. </Values>
  1046. </Bit>
  1047. </AssignedBits>
  1048. </Field>
  1049. </Category>
  1050. <Category>
  1051. <Name>Secure Area </Name>
  1052. <Field>
  1053. <Parameters address="0x40022050" name="FLASH_SECWMR1" size="0x4"/>
  1054. <AssignedBits>
  1055. <Bit config="3">
  1056. <Name>SECWM1_PSTRT</Name>
  1057. <Description>Start page of first secure area</Description>
  1058. <BitOffset>0x0</BitOffset>
  1059. <BitWidth>0x7</BitWidth>
  1060. <Access>RW</Access>
  1061. <Equation multiplier="0x2000" offset="0x08000000"/>
  1062. </Bit>
  1063. <Bit config="3">
  1064. <Name>SECWM1_PEND</Name>
  1065. <Description>End page of first secure area</Description>
  1066. <BitOffset>0x10</BitOffset>
  1067. <BitWidth>0x7</BitWidth>
  1068. <Access>RW</Access>
  1069. <Equation multiplier="0x2000" offset="0x08000000"/>
  1070. </Bit>
  1071. </AssignedBits>
  1072. </Field>
  1073. <Field>
  1074. <Parameters address="0x40022054" name="FLASH_SECWMR2" size="0x4"/>
  1075. <AssignedBits>
  1076. <Bit config="4">
  1077. <Name>HDP1_PEND</Name>
  1078. <Description>End page of secure hide protection area</Description>
  1079. <BitOffset>0x10</BitOffset>
  1080. <BitWidth>0x7</BitWidth>
  1081. <Access>RW</Access>
  1082. <Equation multiplier="0x2000" offset="0xC003fff"/>
  1083. </Bit>
  1084. <Bit>
  1085. <Name>HDP1EN</Name>
  1086. <Description>Secure Hide protection area enable</Description>
  1087. <BitOffset>0x1F</BitOffset>
  1088. <BitWidth>0x1</BitWidth>
  1089. <Access>RW</Access>
  1090. <Values>
  1091. <Val value="0x0">No HDP area 1</Val>
  1092. <Val value="0x1">HDP first area is enabled</Val>
  1093. </Values>
  1094. </Bit>
  1095. </AssignedBits>
  1096. </Field>
  1097. </Category>
  1098. <Category>
  1099. <Name>Write Protection 1</Name>
  1100. <Field>
  1101. <Parameters address="0x40022058" name="FLASH_WRPAR" size="0x4"/>
  1102. <AssignedBits>
  1103. <Bit config="3">
  1104. <Name>WRPA_PSTRT</Name>
  1105. <Description>WPR area A &quot;A&quot; start page</Description>
  1106. <BitOffset>0x0</BitOffset>
  1107. <BitWidth>0x7</BitWidth>
  1108. <Access>RW</Access>
  1109. <Equation multiplier="0x2000" offset="0x08000000"/>
  1110. </Bit>
  1111. <Bit config="3">
  1112. <Name>WRPA_PEND</Name>
  1113. <Description>WPR area A &quot;A&quot; end page</Description>
  1114. <BitOffset>0x10</BitOffset>
  1115. <BitWidth>0x7</BitWidth>
  1116. <Access>RW</Access>
  1117. <Equation multiplier="0x2000" offset="0x08000000"/>
  1118. </Bit>
  1119. <Bit>
  1120. <Name>UNLOCK_A</Name>
  1121. <Description>WPR area A unlock</Description>
  1122. <BitOffset>0x1F</BitOffset>
  1123. <BitWidth>0x1</BitWidth>
  1124. <Access>RW</Access>
  1125. <Values>
  1126. <Val value="0x0">WRP1A start and end pages locked</Val>
  1127. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1128. </Values>
  1129. </Bit>
  1130. </AssignedBits>
  1131. </Field>
  1132. <Field>
  1133. <Parameters address="0x4002205C" name="FLASH_WRPBR" size="0x4"/>
  1134. <AssignedBits>
  1135. <Bit config="3">
  1136. <Name>WRPB_PSTRT</Name>
  1137. <Description>WPR area B &quot;B&quot; start page</Description>
  1138. <BitOffset>0x0</BitOffset>
  1139. <BitWidth>0x7</BitWidth>
  1140. <Access>RW</Access>
  1141. <Equation multiplier="0x4000" offset="0x08000000"/>
  1142. </Bit>
  1143. <Bit config="3">
  1144. <Name>WRPB_PEND</Name>
  1145. <Description>WPR area B &quot;B&quot; end page</Description>
  1146. <BitOffset>0x10</BitOffset>
  1147. <BitWidth>0x7</BitWidth>
  1148. <Access>RW</Access>
  1149. <Equation multiplier="0x4000" offset="0x08000000"/>
  1150. </Bit>
  1151. <Bit>
  1152. <Name>UNLOCK_B</Name>
  1153. <Description>WPR area B unlock</Description>
  1154. <BitOffset>0x1F</BitOffset>
  1155. <BitWidth>0x1</BitWidth>
  1156. <Access>RW</Access>
  1157. <Values>
  1158. <Val value="0x0">WRPB start and end pages locked</Val>
  1159. <Val value="0x1">WRPB start and end pages unlocked</Val>
  1160. </Values>
  1161. </Bit>
  1162. </AssignedBits>
  1163. </Field>
  1164. </Category>
  1165. </Bank>
  1166. </Configuration>
  1167. <Bank interface="Bootloader">
  1168. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  1169. <Category>
  1170. <Name>Read Out Protection</Name>
  1171. <Field>
  1172. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1173. <AssignedBits>
  1174. <Bit>
  1175. <Name>RDP</Name>
  1176. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1177. <BitOffset>0x0</BitOffset>
  1178. <BitWidth>0x8</BitWidth>
  1179. <Access>RW</Access>
  1180. <Values>
  1181. <Val value="0xAA">Level 0, no protection</Val>
  1182. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1183. <Val value="0xDC">Level 1, read protection of memories</Val>
  1184. <Val value="0xCC">Level 2, chip protection</Val>
  1185. </Values>
  1186. </Bit>
  1187. </AssignedBits>
  1188. </Field>
  1189. </Category>
  1190. <Category>
  1191. <Name>BOR Level</Name>
  1192. <Field>
  1193. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1194. <AssignedBits>
  1195. <Bit>
  1196. <Name>BOR_LEV</Name>
  1197. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  1198. <BitOffset>0x8</BitOffset>
  1199. <BitWidth>0x3</BitWidth>
  1200. <Access>RW</Access>
  1201. <Values>
  1202. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1203. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1204. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1205. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1206. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1207. </Values>
  1208. </Bit>
  1209. </AssignedBits>
  1210. </Field>
  1211. </Category>
  1212. <Category>
  1213. <Name>User Configuration</Name>
  1214. <Field>
  1215. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1216. <AssignedBits>
  1217. <Bit>
  1218. <Name>nRST_STOP</Name>
  1219. <Description/>
  1220. <BitOffset>0xC</BitOffset>
  1221. <BitWidth>0x1</BitWidth>
  1222. <Access>RW</Access>
  1223. <Values>
  1224. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1225. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1226. </Values>
  1227. </Bit>
  1228. <Bit>
  1229. <Name>nRST_STDBY</Name>
  1230. <Description/>
  1231. <BitOffset>0xD</BitOffset>
  1232. <BitWidth>0x1</BitWidth>
  1233. <Access>RW</Access>
  1234. <Values>
  1235. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1236. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1237. </Values>
  1238. </Bit>
  1239. <Bit>
  1240. <Name>nRST_SHDW</Name>
  1241. <Description/>
  1242. <BitOffset>0xE</BitOffset>
  1243. <BitWidth>0x1</BitWidth>
  1244. <Access>RW</Access>
  1245. <Values>
  1246. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1247. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1248. </Values>
  1249. </Bit>
  1250. <Bit>
  1251. <Name>IWDG_SW</Name>
  1252. <Description/>
  1253. <BitOffset>0x10</BitOffset>
  1254. <BitWidth>0x1</BitWidth>
  1255. <Access>RW</Access>
  1256. <Values>
  1257. <Val value="0x0">Hardware independant watchdog</Val>
  1258. <Val value="0x1">Software independant watchdog</Val>
  1259. </Values>
  1260. </Bit>
  1261. <Bit>
  1262. <Name>IWDG_STOP</Name>
  1263. <Description/>
  1264. <BitOffset>0x11</BitOffset>
  1265. <BitWidth>0x1</BitWidth>
  1266. <Access>RW</Access>
  1267. <Values>
  1268. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1269. <Val value="0x1">IWDG counter active in stop mode</Val>
  1270. </Values>
  1271. </Bit>
  1272. <Bit>
  1273. <Name>IWDG_STDBY</Name>
  1274. <Description/>
  1275. <BitOffset>0x12</BitOffset>
  1276. <BitWidth>0x1</BitWidth>
  1277. <Access>RW</Access>
  1278. <Values>
  1279. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1280. <Val value="0x1">IWDG counter active in standby mode</Val>
  1281. </Values>
  1282. </Bit>
  1283. <Bit>
  1284. <Name>WWDG_SW</Name>
  1285. <Description/>
  1286. <BitOffset>0x13</BitOffset>
  1287. <BitWidth>0x1</BitWidth>
  1288. <Access>RW</Access>
  1289. <Values>
  1290. <Val value="0x0">Hardware window watchdog</Val>
  1291. <Val value="0x1">Software window watchdog</Val>
  1292. </Values>
  1293. </Bit>
  1294. <Bit>
  1295. <Name>SWAP_BANK</Name>
  1296. <Description/>
  1297. <BitOffset>0x14</BitOffset>
  1298. <BitWidth>0x1</BitWidth>
  1299. <Access>RW</Access>
  1300. <Values>
  1301. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1302. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1303. </Values>
  1304. </Bit>
  1305. <Bit>
  1306. <Name>DB256</Name>
  1307. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  1308. <BitOffset>0x15</BitOffset>
  1309. <BitWidth>0x1</BitWidth>
  1310. <Access>RW</Access>
  1311. <Values>
  1312. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  1313. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  1314. </Values>
  1315. </Bit>
  1316. <Bit>
  1317. <Name>DBANK</Name>
  1318. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  1319. <BitOffset>0x16</BitOffset>
  1320. <BitWidth>0x1</BitWidth>
  1321. <Access>RW</Access>
  1322. <Values>
  1323. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1324. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1325. </Values>
  1326. </Bit>
  1327. <Bit>
  1328. <Name>SRAM2_PE</Name>
  1329. <Description>SRAM2 parity check enable</Description>
  1330. <BitOffset>0x18</BitOffset>
  1331. <BitWidth>0x1</BitWidth>
  1332. <Access>RW</Access>
  1333. <Values>
  1334. <Val value="0x0">SRAM2 parity check enable</Val>
  1335. <Val value="0x1">SRAM2 parity check disable</Val>
  1336. </Values>
  1337. </Bit>
  1338. <Bit>
  1339. <Name>SRAM2_RST</Name>
  1340. <Description>SRAM2 Erase when system reset</Description>
  1341. <BitOffset>0x19</BitOffset>
  1342. <BitWidth>0x1</BitWidth>
  1343. <Access>RW</Access>
  1344. <Values>
  1345. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1346. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1347. </Values>
  1348. </Bit>
  1349. <Bit>
  1350. <Name>nSWBOOT0</Name>
  1351. <Description>Software BOOT0</Description>
  1352. <BitOffset>0x1A</BitOffset>
  1353. <BitWidth>0x1</BitWidth>
  1354. <Access>RW</Access>
  1355. <Values>
  1356. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1357. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1358. </Values>
  1359. </Bit>
  1360. <Bit>
  1361. <Name>nBOOT0</Name>
  1362. <Description>nBOOT0 option bit</Description>
  1363. <BitOffset>0x1B</BitOffset>
  1364. <BitWidth>0x1</BitWidth>
  1365. <Access>RW</Access>
  1366. <Values>
  1367. <Val value="0x0">nBOOT0 = 0</Val>
  1368. <Val value="0x1">nBOOT0 = 1</Val>
  1369. </Values>
  1370. </Bit>
  1371. <Bit>
  1372. <Name>PA15_PUPEN</Name>
  1373. <Description>PA15 pull-up enable</Description>
  1374. <BitOffset>0x1C</BitOffset>
  1375. <BitWidth>0x1</BitWidth>
  1376. <Access>RW</Access>
  1377. <Values>
  1378. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1379. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1380. </Values>
  1381. </Bit>
  1382. <Bit>
  1383. <Name>TZEN</Name>
  1384. <Description>Global TrustZone security enable</Description>
  1385. <BitOffset>0x1F</BitOffset>
  1386. <BitWidth>0x1</BitWidth>
  1387. <Access>RW</Access>
  1388. <Values>
  1389. <Val value="0x0">Global TrustZone security disabled</Val>
  1390. <Val value="0x1">Global TrustZone security enabled</Val>
  1391. </Values>
  1392. </Bit>
  1393. </AssignedBits>
  1394. </Field>
  1395. </Category>
  1396. <Category>
  1397. <Name>Boot Configuration</Name>
  1398. <Field>
  1399. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1400. <AssignedBits>
  1401. <Bit>
  1402. <Name>NSBOOTADD0</Name>
  1403. <Description>Non-secure Boot base address 0</Description>
  1404. <BitOffset>0x7</BitOffset>
  1405. <BitWidth>0x19</BitWidth>
  1406. <Access>RW</Access>
  1407. <Equation multiplier="0x80" offset="0x0000000"/>
  1408. </Bit>
  1409. </AssignedBits>
  1410. </Field>
  1411. <Field>
  1412. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1413. <AssignedBits>
  1414. <Bit>
  1415. <Name>NSBOOTADD1</Name>
  1416. <Description>Non-secure Boot base address 1</Description>
  1417. <BitOffset>0x7</BitOffset>
  1418. <BitWidth>0x19</BitWidth>
  1419. <Access>RW</Access>
  1420. <Equation multiplier="0x80" offset="0x0000000"/>
  1421. </Bit>
  1422. </AssignedBits>
  1423. </Field>
  1424. <Field>
  1425. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1426. <AssignedBits>
  1427. <Bit config="6,7">
  1428. <Name>SECBOOTADD0</Name>
  1429. <Description>Secure boot base address 0</Description>
  1430. <BitOffset>0x7</BitOffset>
  1431. <BitWidth>0x19</BitWidth>
  1432. <Access>RW</Access>
  1433. <Equation multiplier="0x80" offset="0x0000000"/>
  1434. </Bit>
  1435. </AssignedBits>
  1436. </Field>
  1437. <Field>
  1438. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1439. <AssignedBits>
  1440. <Bit config="6,7">
  1441. <Name>BOOT_LOCK</Name>
  1442. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1443. <BitOffset>0x0</BitOffset>
  1444. <BitWidth>0x1</BitWidth>
  1445. <Access>RW</Access>
  1446. <Values>
  1447. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1448. <Val value="0x1">Boot forced from base address memory</Val>
  1449. </Values>
  1450. </Bit>
  1451. </AssignedBits>
  1452. </Field>
  1453. </Category>
  1454. <Category>
  1455. <Name>Secure Area </Name>
  1456. <Field>
  1457. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  1458. <AssignedBits>
  1459. <Bit config="6">
  1460. <Name>SECWM1_PSTRT</Name>
  1461. <Description>Start page of first secure area</Description>
  1462. <BitOffset>0x0</BitOffset>
  1463. <BitWidth>0x7</BitWidth>
  1464. <Access>RW</Access>
  1465. <Equation multiplier="0x4000" offset="0x08000000"/>
  1466. </Bit>
  1467. <Bit config="7">
  1468. <Name>SECWM1_PSTRT</Name>
  1469. <Description>Start page of first secure area</Description>
  1470. <BitOffset>0x0</BitOffset>
  1471. <BitWidth>0x7</BitWidth>
  1472. <Access>RW</Access>
  1473. <Equation multiplier="0x2000" offset="0x08000000"/>
  1474. </Bit>
  1475. <Bit config="6">
  1476. <Name>SECWM1_PEND</Name>
  1477. <Description>End page of first secure area</Description>
  1478. <BitOffset>0x10</BitOffset>
  1479. <BitWidth>0x7</BitWidth>
  1480. <Access>RW</Access>
  1481. <Equation multiplier="0x4000" offset="0x08000000"/>
  1482. </Bit>
  1483. <Bit config="7">
  1484. <Name>SECWM1_PEND</Name>
  1485. <Description>End page of first secure area</Description>
  1486. <BitOffset>0x10</BitOffset>
  1487. <BitWidth>0x7</BitWidth>
  1488. <Access>RW</Access>
  1489. <Equation multiplier="0x2000" offset="0x08000000"/>
  1490. </Bit>
  1491. </AssignedBits>
  1492. </Field>
  1493. <Field>
  1494. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  1495. <AssignedBits>
  1496. <Bit config="6">
  1497. <Name>HDP1_PEND</Name>
  1498. <Description>End page of first hide protection area</Description>
  1499. <BitOffset>0x10</BitOffset>
  1500. <BitWidth>0x7</BitWidth>
  1501. <Access>RW</Access>
  1502. <Equation multiplier="0x400" offset="0x08000000"/>
  1503. </Bit>
  1504. <Bit config="7">
  1505. <Name>HDP1_PEND</Name>
  1506. <Description>End page of first hide protection area</Description>
  1507. <BitOffset>0x10</BitOffset>
  1508. <BitWidth>0x7</BitWidth>
  1509. <Access>RW</Access>
  1510. <Equation multiplier="0x200" offset="0x08000000"/>
  1511. </Bit>
  1512. <Bit config="6,7">
  1513. <Name>HDP1EN</Name>
  1514. <Description>Hide protection first area enable</Description>
  1515. <BitOffset>0x1F</BitOffset>
  1516. <BitWidth>0x1</BitWidth>
  1517. <Access>RW</Access>
  1518. <Values>
  1519. <Val value="0x0">No HDP area 1</Val>
  1520. <Val value="0x1">HDP first area is enabled</Val>
  1521. </Values>
  1522. </Bit>
  1523. </AssignedBits>
  1524. </Field>
  1525. </Category>
  1526. <Category>
  1527. <Name>Write Protection 1</Name>
  1528. <Field>
  1529. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  1530. <AssignedBits>
  1531. <Bit config="6,8">
  1532. <Name>WRP1A_PSTRT</Name>
  1533. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1534. <BitOffset>0x0</BitOffset>
  1535. <BitWidth>0x7</BitWidth>
  1536. <Access>RW</Access>
  1537. <Equation multiplier="0x4000" offset="0x08000000"/>
  1538. </Bit>
  1539. <Bit config="7,9">
  1540. <Name>WRP1A_PSTRT</Name>
  1541. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1542. <BitOffset>0x0</BitOffset>
  1543. <BitWidth>0x7</BitWidth>
  1544. <Access>RW</Access>
  1545. <Equation multiplier="0x2000" offset="0x08000000"/>
  1546. </Bit>
  1547. <Bit config="6,8">
  1548. <Name>WRP1A_PEND</Name>
  1549. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1550. <BitOffset>0x10</BitOffset>
  1551. <BitWidth>0x7</BitWidth>
  1552. <Access>RW</Access>
  1553. <Equation multiplier="0x4000" offset="0x08000000"/>
  1554. </Bit>
  1555. <Bit config="7,9">
  1556. <Name>WRP1A_PEND</Name>
  1557. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1558. <BitOffset>0x10</BitOffset>
  1559. <BitWidth>0x7</BitWidth>
  1560. <Access>RW</Access>
  1561. <Equation multiplier="0x2000" offset="0x08000000"/>
  1562. </Bit>
  1563. <Bit>
  1564. <Name>UNLOCK_1A</Name>
  1565. <Description>Bank 1 WPR first area A unlock</Description>
  1566. <BitOffset>0x1F</BitOffset>
  1567. <BitWidth>0x1</BitWidth>
  1568. <Access>RW</Access>
  1569. <Values>
  1570. <Val value="0x0">WRP1A start and end pages locked</Val>
  1571. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1572. </Values>
  1573. </Bit>
  1574. </AssignedBits>
  1575. </Field>
  1576. <Field>
  1577. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  1578. <AssignedBits>
  1579. <Bit config="6,8">
  1580. <Name>WRP1B_PSTRT</Name>
  1581. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1582. <BitOffset>0x0</BitOffset>
  1583. <BitWidth>0x7</BitWidth>
  1584. <Access>RW</Access>
  1585. <Equation multiplier="0x4000" offset="0x08000000"/>
  1586. </Bit>
  1587. <Bit config="7,9">
  1588. <Name>WRP1B_PSTRT</Name>
  1589. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1590. <BitOffset>0x0</BitOffset>
  1591. <BitWidth>0x7</BitWidth>
  1592. <Access>RW</Access>
  1593. <Equation multiplier="0x2000" offset="0x08000000"/>
  1594. </Bit>
  1595. <Bit config="6,8">
  1596. <Name>WRP1B_PEND</Name>
  1597. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1598. <BitOffset>0x10</BitOffset>
  1599. <BitWidth>0x7</BitWidth>
  1600. <Access>RW</Access>
  1601. <Equation multiplier="0x4000" offset="0x08000000"/>
  1602. </Bit>
  1603. <Bit config="7,9">
  1604. <Name>WRP1B_PEND</Name>
  1605. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1606. <BitOffset>0x10</BitOffset>
  1607. <BitWidth>0x7</BitWidth>
  1608. <Access>RW</Access>
  1609. <Equation multiplier="0x2000" offset="0x08000000"/>
  1610. </Bit>
  1611. <Bit>
  1612. <Name>UNLOCK_1B</Name>
  1613. <Description>Bank 1 WPR second area B unlock</Description>
  1614. <BitOffset>0x1F</BitOffset>
  1615. <BitWidth>0x1</BitWidth>
  1616. <Access>RW</Access>
  1617. <Values>
  1618. <Val value="0x0">WRP1B start and end pages locked</Val>
  1619. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1620. </Values>
  1621. </Bit>
  1622. </AssignedBits>
  1623. </Field>
  1624. </Category>
  1625. <Category>
  1626. <Name>Secure area 2</Name>
  1627. <Field>
  1628. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  1629. <AssignedBits>
  1630. <Bit config="6">
  1631. <Name>SECWM2_PSTRT</Name>
  1632. <Description>Start page of second secure area</Description>
  1633. <BitOffset>0x0</BitOffset>
  1634. <BitWidth>0x7</BitWidth>
  1635. <Access>RW</Access>
  1636. <Equation multiplier="0x4000" offset="0x08000000"/>
  1637. </Bit>
  1638. <Bit config="7">
  1639. <Name>SECWM2_PSTRT</Name>
  1640. <Description>Start page of second secure area</Description>
  1641. <BitOffset>0x0</BitOffset>
  1642. <BitWidth>0x7</BitWidth>
  1643. <Access>RW</Access>
  1644. <Equation multiplier="0x2000" offset="0x08100000"/>
  1645. </Bit>
  1646. <Bit config="6">
  1647. <Name>SECWM2_PEND</Name>
  1648. <Description>End page of second secure area</Description>
  1649. <BitOffset>0x10</BitOffset>
  1650. <BitWidth>0x7</BitWidth>
  1651. <Access>RW</Access>
  1652. <Equation multiplier="0x4000" offset="0x08000000"/>
  1653. </Bit>
  1654. <Bit config="7">
  1655. <Name>SECWM2_PEND</Name>
  1656. <Description>End page of second secure area</Description>
  1657. <BitOffset>0x10</BitOffset>
  1658. <BitWidth>0x7</BitWidth>
  1659. <Access>RW</Access>
  1660. <Equation multiplier="0x2000" offset="0x08100000"/>
  1661. </Bit>
  1662. </AssignedBits>
  1663. </Field>
  1664. <Field>
  1665. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  1666. <AssignedBits>
  1667. <Bit config="6">
  1668. <Name>HDP2_PEND</Name>
  1669. <Description>End page of second hide protection area</Description>
  1670. <BitOffset>0x10</BitOffset>
  1671. <BitWidth>0x7</BitWidth>
  1672. <Access>RW</Access>
  1673. <Equation multiplier="0x400" offset="0x08000000"/>
  1674. </Bit>
  1675. <Bit config="7">
  1676. <Name>HDP2_PEND</Name>
  1677. <Description>End page of second hide protection area</Description>
  1678. <BitOffset>0x10</BitOffset>
  1679. <BitWidth>0x7</BitWidth>
  1680. <Access>RW</Access>
  1681. <Equation multiplier="0x200" offset="0x08000000"/>
  1682. </Bit>
  1683. <Bit config="6,7">
  1684. <Name>HDP2EN</Name>
  1685. <Description>Hide protection second area enable</Description>
  1686. <BitOffset>0x1F</BitOffset>
  1687. <BitWidth>0x1</BitWidth>
  1688. <Access>RW</Access>
  1689. <Values>
  1690. <Val value="0x0">No HDP area 2</Val>
  1691. <Val value="0x1">HDP second area is enabled</Val>
  1692. </Values>
  1693. </Bit>
  1694. </AssignedBits>
  1695. </Field>
  1696. </Category>
  1697. <Category>
  1698. <Name>Write Protection 2</Name>
  1699. <Field>
  1700. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  1701. <AssignedBits>
  1702. <Bit config="6,8">
  1703. <Name>WRP2A_PSTRT</Name>
  1704. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1705. <BitOffset>0x0</BitOffset>
  1706. <BitWidth>0x7</BitWidth>
  1707. <Access>RW</Access>
  1708. <Equation multiplier="0x4000" offset="0x08000000"/>
  1709. </Bit>
  1710. <Bit config="7,9">
  1711. <Name>WRP2A_PSTRT</Name>
  1712. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1713. <BitOffset>0x0</BitOffset>
  1714. <BitWidth>0x7</BitWidth>
  1715. <Access>RW</Access>
  1716. <Equation multiplier="0x2000" offset="0x08100000"/>
  1717. </Bit>
  1718. <Bit config="6,8">
  1719. <Name>WRP2A_PEND</Name>
  1720. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1721. <BitOffset>0x10</BitOffset>
  1722. <BitWidth>0x7</BitWidth>
  1723. <Access>RW</Access>
  1724. <Equation multiplier="0x4000" offset="0x08000000"/>
  1725. </Bit>
  1726. <Bit config="7,9">
  1727. <Name>WRP2A_PEND</Name>
  1728. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1729. <BitOffset>0x10</BitOffset>
  1730. <BitWidth>0x7</BitWidth>
  1731. <Access>RW</Access>
  1732. <Equation multiplier="0x2000" offset="0x08100000"/>
  1733. </Bit>
  1734. <Bit>
  1735. <Name>UNLOCK_2A</Name>
  1736. <Description>Bank 2 WPR first area A unlock</Description>
  1737. <BitOffset>0x1F</BitOffset>
  1738. <BitWidth>0x1</BitWidth>
  1739. <Access>RW</Access>
  1740. <Values>
  1741. <Val value="0x0">WRP2A start and end pages locked</Val>
  1742. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1743. </Values>
  1744. </Bit>
  1745. </AssignedBits>
  1746. </Field>
  1747. <Field>
  1748. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  1749. <AssignedBits>
  1750. <Bit config="6,8">
  1751. <Name>WRP2B_PSTRT</Name>
  1752. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1753. <BitOffset>0x0</BitOffset>
  1754. <BitWidth>0x7</BitWidth>
  1755. <Access>RW</Access>
  1756. <Equation multiplier="0x4000" offset="0x08000000"/>
  1757. </Bit>
  1758. <Bit config="7,9">
  1759. <Name>WRP2B_PSTRT</Name>
  1760. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1761. <BitOffset>0x0</BitOffset>
  1762. <BitWidth>0x7</BitWidth>
  1763. <Access>RW</Access>
  1764. <Equation multiplier="0x2000" offset="0x08100000"/>
  1765. </Bit>
  1766. <Bit config="6,8">
  1767. <Name>WRP2B_PEND</Name>
  1768. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1769. <BitOffset>0x10</BitOffset>
  1770. <BitWidth>0x7</BitWidth>
  1771. <Access>RW</Access>
  1772. <Equation multiplier="0x4000" offset="0x08000000"/>
  1773. </Bit>
  1774. <Bit config="7,9">
  1775. <Name>WRP2B_PEND</Name>
  1776. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1777. <BitOffset>0x10</BitOffset>
  1778. <BitWidth>0x7</BitWidth>
  1779. <Access>RW</Access>
  1780. <Equation multiplier="0x2000" offset="0x08100000"/>
  1781. </Bit>
  1782. <Bit>
  1783. <Name>UNLOCK_2B</Name>
  1784. <Description>Bank 2 WPR second area B unlock</Description>
  1785. <BitOffset>0x1F</BitOffset>
  1786. <BitWidth>0x1</BitWidth>
  1787. <Access>RW</Access>
  1788. <Values>
  1789. <Val value="0x0">WRP2B start and end pages locked</Val>
  1790. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1791. </Values>
  1792. </Bit>
  1793. </AssignedBits>
  1794. </Field>
  1795. </Category>
  1796. </Bank>
  1797. </Peripheral>
  1798. </Peripherals>
  1799. </Device>
  1800. </Root>