vd_a53x2_dap.cfg 751 B

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Cadence virtual debug interface
  3. # Arm Cortex A53x2 through DAP
  4. source [find interface/vdebug.cfg]
  5. set CORES 2
  6. set CHIPNAME a53
  7. set ACCESSPORT 0
  8. set MEMSTART 0x00000000
  9. set MEMSIZE 0x1000000
  10. set DBGBASE {0x80810000 0x80910000}
  11. set CTIBASE {0x80820000 0x80920000}
  12. # vdebug select transport
  13. transport select dapdirect_swd
  14. # JTAG reset config, frequency and reset delay
  15. adapter speed 50000
  16. adapter srst delay 5
  17. # BFM hierarchical path and input clk period
  18. vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
  19. # DMA Memories to access backdoor (up to 20)
  20. vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
  21. swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
  22. source [find target/vd_aarch64.cfg]