sdk-debugger-openocd-infineon/scripts/board/xtensa-palladium-vdebug-dual.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# for Palladium emulation systems
#

source [find interface/vdebug.cfg]

# vdebug select JTAG transport
transport select jtag

# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 50000
adapter srst delay 5

# Future improvement: Enable backdoor memory access
# set _MEMSTART 0x00000000
# set _MEMSIZE 0x100000

# BFM hierarchical path and input clk period
vdebug bfm_path Testbench.VJTAG 10ns

# DMA Memories to access backdoor (up to 4)
# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE

# Configure dual-core TAP chain
set XTENSA_NUM_CORES 2

# Create Xtensa target first
source [find target/xtensa.cfg]

# Configure Xtensa core parameters next
# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"