esi32xx.cfg 952 B

1234567891011121314151617181920212223242526272829303132333435363738
  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. #
  3. # EnSilica eSi-32xx SoC (eSi-RISC Family)
  4. # http://www.ensilica.com/risc-ip/
  5. #
  6. if { [info exists CHIPNAME] } {
  7. set _CHIPNAME $CHIPNAME
  8. } else {
  9. set _CHIPNAME esi32xx
  10. }
  11. if { [info exists CPUTAPID] } {
  12. set _CPUTAPID $CPUTAPID
  13. } else {
  14. set _CPUTAPID 0x11234001
  15. }
  16. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  17. set _TARGETNAME $_CHIPNAME.cpu
  18. target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
  19. # Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
  20. # CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
  21. if { [info exists CACHEARCH] } {
  22. $_TARGETNAME esirisc cache_arch $CACHEARCH
  23. }
  24. adapter speed 2000
  25. reset_config none
  26. # The default linker scripts provided by the eSi-RISC toolchain do not
  27. # specify attributes on memory regions, which results in incorrect
  28. # application of software breakpoints by GDB.
  29. gdb_breakpoint_override hard