sdk-debugger-openocd-infineon/scripts/target/stm32mp15x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
# http://www.st.com/stm32mp1

# HLA does not support multi-cores nor custom CSW nor AP other than 0
if { [using_hla] } {
	echo "ERROR: HLA transport cannot work with this target."
	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
	shutdown
}

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32mp15x
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		set _CPUTAPID 0x6ba00477
	} else {
		set _CPUTAPID 0x6ba02477
	}
}

# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
	set _CLCTAPID $CLCTAPID
} else {
	set _CLCTAPID 0x06500041
}

swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
if { [using_jtag] } {
	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack

# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
# so defer-examine it until the reset framework get merged
# NOTE: keep ap-num and dbgbase to speed-up examine after reset
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine

targets $_CHIPNAME.cpu0

target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
$_CHIPNAME.cpu0 cortex_a maskisr on
$_CHIPNAME.cpu1 cortex_a maskisr on
$_CHIPNAME.cpu0 cortex_a dacrfixup on
$_CHIPNAME.cpu1 cortex_a dacrfixup on

cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000

swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000

# interface does not work while srst is asserted
# this is target specific, valid for every board
# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
# debug unit, behavior equivalent to "srst_pulls_trst"
reset_config srst_gates_jtag srst_pulls_trst

adapter speed 5000
adapter srst pulse_width 200
# bootrom has an internal timeout of 1 second for detecting the boot flash.
# wait at least 1 second to guarantee we are out of bootrom
adapter srst delay 1100

add_help_text axi_secure "Set secure mode for following AXI accesses"
proc axi_secure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x10006000
}

add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
proc axi_nsecure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x30006000
}

axi_secure

proc dbgmcu_enable_debug {} {
	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
	# freeze watchdog 1 and 2 on cores halted
	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
}

proc toggle_cpu0_dbg_claim0 {} {
	# toggle CPU0 DBG_CLAIM[0]
	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
}

proc detect_cpu1 {} {
	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
	set dual_core [expr {$cpu1_prsr & 1}]
	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}

proc rcc_enable_traceclk {} {
	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
}

# FIXME: most of handler below will be removed once reset framework get merged
$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
$_CHIPNAME.ap1  configure -event examine-start       {dap init}
$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}