sdk-debugger-openocd-infineon/scripts/target/mxs40/traveo2_68m_common.cfg

#
# Copyright (C) <2019-2021>
#   <Cypress Semiconductor Corporation (an Infineon company)>
#
# Common configuration for TRAVEO™II family of microcontrollers.
#

source [find target/swj-dp.tcl]
source [find target/mxs40/mxs40_common.cfg]

if { [info exists WORKAREAADDR] } {
	set _WA_ADDR $WORKAREAADDR
	unset WORKAREAADDR
} else {
	set _WA_ADDR 0x28000800
}

if { [info exists WORKAREASIZE] } {
	set _WA_SIZE $WORKAREASIZE
	unset WORKAREASIZE
} else {
	set _WA_SIZE 0x8000
}

# (large_sector_num << 16) | small_sector_num
set ${_CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE [ expr {($MAIN_LARGE_SECTOR_NUM << 16) |  $MAIN_SMALL_SECTOR_NUM} ]
set ${_CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE [ expr {($WORK_LARGE_SECTOR_NUM << 16) |  $WORK_SMALL_SECTOR_NUM} ]

if { $_ENABLE_ACQUIRE } {
	kitprog3 acquire_config on 3 0 2
}

global TARGET
set TARGET $_CHIPNAME.cpu
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apsel 2
$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]
$_CHIPNAME.dap apsel 3
$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]

proc enable_cm7x {} {
	mww 0x40261244 0x80000000
	mww 0x40261248 0x80000000
	mww 0x4020040C 15
	mww 0x4020000C 15
	mww 0x40201200 0x05FA0001
	mww 0x40201200 0x05FA0003
	mww 0x40201210 0x05FA0001
	mww 0x40201210 0x05FA0003
}

global _TRAVEO_VARIANT_C2D_4M
if { ![info exists _TRAVEO_VARIANT_C2D_4M] } {
	set _TRAVEO_VARIANT_C2D_4M 0
}

if { $_TRAVEO_VARIANT_C2D_4M } {
	set _FLASH_DRIVER_NAME traveo21
} else {
	set _FLASH_DRIVER_NAME traveo22
}

target create ${TARGET}.cm0  cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
${TARGET}.cm0 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
${TARGET}.cm0 cortex_m reset_config sysresetreq
${TARGET}.cm0 configure -event examine-end "cy_get_set_device_param ${_FLASH_DRIVER_NAME} ${_CHIPNAME}_main_cm0 ${_CHIPNAME}_work_cm0; enable_cm7x"
${TARGET}.cm0 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm0; enable_cm7x"

target create ${TARGET}.cm70 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
${TARGET}.cm70 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
${TARGET}.cm70 configure -event reset-assert {}
${TARGET}.cm70 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm70"

flash bank ${_CHIPNAME}_main_cm0		${_FLASH_DRIVER_NAME} 0x10000000 0 0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_work_cm0		${_FLASH_DRIVER_NAME} 0x14000000 0 0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_super_cm0		${_FLASH_DRIVER_NAME} 0x17000000 0 0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_efuse_cm0		${_FLASH_DRIVER_NAME}_efuse 0x90700000 1024 1 1 ${TARGET}.cm0 external

flash bank ${_CHIPNAME}_main_cm70		virtual 0x10000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_main_cm0
flash bank ${_CHIPNAME}_work_cm70		virtual 0x14000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_work_cm0
flash bank ${_CHIPNAME}_super_cm70		virtual 0x17000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_super_cm0
flash bank ${_CHIPNAME}_efuse_cm70		virtual 0x90700000 1024 1 1 ${TARGET}.cm70 ${_CHIPNAME}_efuse_cm0 external

if { $_TRAVEO_VARIANT_C2D_4M == 0} {
	target create ${TARGET}.cm71 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -coreid 2
	${TARGET}.cm71 configure -work-area-phys $_WA_ADDR -work-area-size $_WA_SIZE -work-area-backup 0
	${TARGET}.cm71 configure -event reset-assert {}
	${TARGET}.cm71 configure -event reset-deassert-post "mxs40_reset_deassert_post traveo2 ${TARGET}.cm71"

	flash bank ${_CHIPNAME}_main_cm71		virtual 0x10000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_main_cm0
	flash bank ${_CHIPNAME}_work_cm71		virtual 0x14000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_work_cm0
	flash bank ${_CHIPNAME}_super_cm71		virtual 0x17000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_super_cm0
	flash bank ${_CHIPNAME}_efuse_cm71		virtual 0x90700000 1024 1 1 ${TARGET}.cm71 ${_CHIPNAME}_efuse_cm0 external
}

unset _TRAVEO_VARIANT_C2D_4M

targets ${TARGET}.cm0

if {[using_jtag]} {
	jtag newtap $_CHIPNAME bs -irlen 4 -expected-id 0
}