sdk-debugger-openocd-infineon/scripts/board/atmel_at91sam9rl-ek.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

################################################################################
#
# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
#
# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
#                     OSCSEL configured for external 32.768 kHz crystal
#
# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
#
################################################################################

# We add to the minimal configuration.
source [find target/at91sam9rl.cfg]

$_TARGETNAME configure -event reset-start {
        # At reset CPU runs at 32.768 kHz.
        # JTAG Frequency must be 6 times slower if RCLK is not supported.
        jtag_rclk 5
        halt
        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
        mww phys 0xfffffd08 0xa5000501
}

$_TARGETNAME configure -event reset-init {
        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog

	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
        sleep 20                          ;# wait 20 ms
        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
        sleep 10                          ;# wait 10 ms
        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz
        sleep 20                          ;# wait 20 ms
        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
        sleep 10                          ;# wait 10 ms
        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
        sleep 10                          ;# wait 10 ms

	# Increase JTAG Speed to 6 MHz if RCLK is not supported
        jtag_rclk 6000

	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads

	mww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)

        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory

	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)

	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
	mww 0x20000000 0
	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
	mww 0x20000000 0
	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
	mww 0x20000000 0
	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
	mww 0x20000000 0
	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
}