eir.cfg 2.3 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Elector Internet Radio board
  3. # http://www.ethernut.de/en/hardware/eir/index.html
  4. source [find target/at91sam7se512.cfg]
  5. $_TARGETNAME configure -event reset-init {
  6. # WDT_MR, disable watchdog
  7. mww 0xFFFFFD44 0x00008000
  8. # RSTC_MR, enable user reset
  9. mww 0xfffffd08 0xa5000001
  10. # CKGR_MOR
  11. mww 0xFFFFFC20 0x00000601
  12. sleep 10
  13. # CKGR_PLLR
  14. mww 0xFFFFFC2C 0x00481c0e
  15. sleep 10
  16. # PMC_MCKR
  17. mww 0xFFFFFC30 0x00000007
  18. sleep 10
  19. # PMC_IER
  20. mww 0xFFFFFF60 0x00480100
  21. #
  22. # Enable SDRAM interface.
  23. #
  24. # Enable SDRAM control at PIO A.
  25. mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
  26. mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
  27. # Enable address bus (A0, A2-A11, A13-A17) at PIO B
  28. mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
  29. mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
  30. # Enable 16 bit data bus at PIO C
  31. mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
  32. mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
  33. # Enable SDRAM chip select
  34. mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
  35. # Set SDRAM characteristics in configuration register.
  36. # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
  37. mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
  38. sleep 10
  39. # Issue 16 bit SDRAM command: NOP
  40. mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
  41. mww 0x20000000 0x00000000
  42. # Issue 16 bit SDRAM command: Precharge all
  43. mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
  44. mww 0x20000000 0x00000000
  45. # Issue 8 auto-refresh cycles
  46. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  47. mww 0x20000000 0x00000000
  48. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  49. mww 0x20000000 0x00000000
  50. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  51. mww 0x20000000 0x00000000
  52. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  53. mww 0x20000000 0x00000000
  54. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  55. mww 0x20000000 0x00000000
  56. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  57. mww 0x20000000 0x00000000
  58. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  59. mww 0x20000000 0x00000000
  60. mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  61. mww 0x20000000 0x00000000
  62. # Issue 16 bit SDRAM command: Set mode register
  63. mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
  64. mww 0x20000014 0xcafedede
  65. # Set refresh rate count ???
  66. mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
  67. # Issue 16 bit SDRAM command: Normal mode
  68. mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
  69. mww 0x20000000 0x00000180
  70. #
  71. # Enable external reset key.
  72. #
  73. mww 0xfffffd08 0xa5000001
  74. }