imx27lnst.cfg 1.4 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # The Linuxstamp-mx27 is board has a single IMX27 chip
  3. # For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
  4. source [find target/imx27.cfg]
  5. $_TARGETNAME configure -event gdb-attach { reset init }
  6. $_TARGETNAME configure -event reset-init { imx27lnst_init }
  7. proc imx27lnst_init { } {
  8. # This setup puts RAM at 0xA0000000
  9. # reset the board correctly
  10. adapter speed 500
  11. reset run
  12. reset halt
  13. mww 0x10000000 0x20040304
  14. mww 0x10020000 0x00000000
  15. mww 0x10000004 0xDFFBFCFB
  16. mww 0x10020004 0xFFFFFFFF
  17. sleep 100
  18. # ========================================
  19. # Configure DDR on CSD0 -- initial reset
  20. # ========================================
  21. mww 0xD8001010 0x00000008
  22. sleep 100
  23. # ========================================
  24. # Configure DDR on CSD0 -- wait 5000 cycle
  25. # ========================================
  26. mww 0x10027828 0x55555555
  27. mww 0x10027830 0x55555555
  28. mww 0x10027834 0x55555555
  29. mww 0x10027838 0x00005005
  30. mww 0x1002783C 0x15555555
  31. mww 0xD8001010 0x00000004
  32. mww 0xD8001004 0x00795729
  33. #mww 0xD8001000 0x92200000
  34. mww 0xD8001000 0x91120000
  35. mww 0xA0000F00 0x0
  36. #mww 0xD8001000 0xA2200000
  37. mww 0xD8001000 0xA1120000
  38. mww 0xA0000F00 0x0
  39. mww 0xA0000F00 0x0
  40. #mww 0xD8001000 0xB2200000
  41. mww 0xD8001000 0xB1120000
  42. mwb 0xA0000033 0xFF
  43. mwb 0xA1000000 0xAA
  44. #mww 0xD8001000 0x82228085
  45. mww 0xD8001000 0x81128080
  46. }