lubbock.cfg 2.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Intel "Lubbock" Development Board with PXA255 (dbpxa255)
  3. # Obsolete; this was Intel's original PXA255 development system
  4. # Board also had CPU cards for SA1100, PXA210, PXA250, and more.
  5. source [find target/pxa255.cfg]
  6. adapter srst delay 250
  7. jtag_ntrst_delay 250
  8. # NOTE: until after pinmux and such are set up, only CS0 is
  9. # available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
  10. # CS0, CS1 -- two banks of CFI flash, 32 MBytes each
  11. # each bank is 32-bits wide, two 16-bit chips in parallel
  12. set _FLASHNAME $_CHIPNAME.flash0
  13. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  14. set _FLASHNAME $_CHIPNAME.flash1
  15. flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
  16. # CS2 low -- FPGA registers
  17. # CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
  18. $_TARGETNAME configure -work-area-phys 0x0a0f0000
  19. $_TARGETNAME configure -event reset-assert-pre \
  20. "$_TARGETNAME configure -work-area-size 0"
  21. # Make the hex led display a number, assuming CS2 is set up
  22. # and all digits have been enabled through the FPGA.
  23. proc hexled {u32} {
  24. mww 0x08000010 $u32
  25. }
  26. # CS3 -- Ethernet
  27. # CS4 -- SA1111
  28. # CS5 -- PCMCIA
  29. # NOTE: system console normally uses the FF UART connector
  30. proc lubbock_init {target} {
  31. echo "Initialize PXA255 Lubbock board"
  32. # (1) pinmux
  33. # GPSR0..GPSR2
  34. mww 0x40e00018 0x00008000
  35. mww 0x40e0001c 0x00FC0382
  36. mww 0x40e00020 0x0001FFFF
  37. # GPDR0..GPDR2
  38. mww 0x40e0000c 0x0060A800
  39. mww 0x40e00010 0x00FF0382
  40. mww 0x40e00014 0x0001C000
  41. # GAFR0_[LU]..GAFR2_[LU]
  42. mww 0x40e00054 0x98400000
  43. mww 0x40e00058 0x00002950
  44. mww 0x40e0005c 0x000A9558
  45. mww 0x40e00060 0x0005AAAA
  46. mww 0x40e00064 0xA0000000
  47. mww 0x40e00068 0x00000002
  48. # write PSSR, enable GPIOs
  49. mww 0x40f00000 0x00000020
  50. # write LED ctrl register ... ones disable
  51. # high byte, 8 hex leds; low byte, 8 discretes
  52. mwh 0x08000040 0xf0ff
  53. hexled 0x0000
  54. # (2) Address space setup
  55. # MSC0/MSC1/MSC2
  56. mww 0x48000008 0x23f223f2
  57. mww 0x4800000c 0x3ff1a441
  58. mww 0x48000010 0x7ff97ff1
  59. # pcmcia/cf
  60. mww 0x48000014 0x00000000
  61. mww 0x48000028 0x00010504
  62. mww 0x4800002c 0x00010504
  63. mww 0x48000030 0x00010504
  64. mww 0x48000034 0x00010504
  65. mww 0x48000038 0x00004715
  66. mww 0x4800003c 0x00004715
  67. hexled 0x1111
  68. # (3) SDRAM setup
  69. # REVISIT this looks dubious ... no refresh cycles
  70. mww 0x48000004 0x03CA4018
  71. mww 0x48000004 0x004B4018
  72. mww 0x48000004 0x000B4018
  73. mww 0x48000004 0x000BC018
  74. mww 0x48000000 0x00001AC8
  75. mww 0x48000000 0x00001AC9
  76. mww 0x48000040 0x00000000
  77. # FIXME -- setup:
  78. # CLOCKS (and faster JTAG)
  79. # enable icache
  80. # FIXME SRAM isn't working
  81. # $target configure -work-area-size 0x10000
  82. hexled 0x2222
  83. flash probe 0
  84. flash probe 1
  85. hexled 0xcafe
  86. }
  87. $_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"