صفحهٔ اصلی گشت‌و‌گذار راهنما
ورود
RT-Thread-Studio
/
sdk-debugger-openocd-infineon
mirrorاز https://github-proxy.rt-thread.io/RT-Thread-Studio/sdk-debugger-openocd-infineon.git
2
0
انشعاب 0
پرونده‌ها مشکلات 0 ویکی
شاخه: main
شاخه‌ها تگ‌ها
sdk-debugger-op...
/
scripts
/
board
/
nxp_imx7sabre.cfg

nxp_imx7sabre.cfg 3.2 KB
لینک دائمی تاريخچه خام

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116 
  1. # SPDX-License-Identifier: GPL-2.0-or-later
    2. 

  2. 

  3. # NXP IMX7SABRE board
    4. 

  4. # use on-board JTAG header
    5. 

  5. transport select jtag
    6. 

  6. 

  7. # set a safe speed, can be overridden
    8. 

  8. adapter speed 1000
    9. 

  9. 

  10. # reset configuration has TRST and SRST support
    11. 

  11. reset_config trst_and_srst srst_push_pull
    12. 

  12. # need at least 100ms delay after SRST release for JTAG
    13. 

  13. adapter srst delay 100
    14. 

  14. 

  15. # source the target file
    16. 

  16. source [find target/imx7.cfg]
    17. 

  17. # import mrw proc
    18. 

  18. source [find mem_helper.tcl]
    19. 

  19. 

  20. # function to disable the on-chip watchdog
    21. 

  21. proc imx7_disable_wdog { } {
    22. 

  22.         # echo "disable watchdog power-down counter"
    23. 

  23.         mwh phys 0x30280008 0x00
    24. 

  24. }
    25. 

  25. 

  26. proc imx7_uart_dbgconf { } {
    27. 

  27. 	# disable response to debug_req signal for uart1
    28. 

  28. 	mww phys 0x308600b4 0x0a60
    29. 

  29. }
    30. 

  30. 

  31. proc check_bits_set_32 { addr mask } {
    32. 

  32.     while { [expr {[mrw $addr] & $mask} == 0] } { }
    33. 

  33. }
    34. 

  34. 

  35. proc apply_dcd { } {
    36. 

  36.     # echo "apply dcd"
    37. 

  37. 

  38.     mww phys 0x30340004 0x4F400005
    39. 

  39.     # Clear then set bit30 to ensure exit from DDR retention
    40. 

  40.     mww phys 0x30360388 0x40000000
    41. 

  41.     mww phys 0x30360384 0x40000000
    42. 

  42. 

  43.     mww phys 0x30391000 0x00000002
    44. 

  44.     mww phys 0x307a0000 0x01040001
    45. 

  45.     mww phys 0x307a01a0 0x80400003
    46. 

  46.     mww phys 0x307a01a4 0x00100020
    47. 

  47.     mww phys 0x307a01a8 0x80100004
    48. 

  48.     mww phys 0x307a0064 0x00400046
    49. 

  49.     mww phys 0x307a0490 0x00000001
    50. 

  50.     mww phys 0x307a00d0 0x00020083
    51. 

  51.     mww phys 0x307a00d4 0x00690000
    52. 

  52.     mww phys 0x307a00dc 0x09300004
    53. 

  53.     mww phys 0x307a00e0 0x04080000
    54. 

  54.     mww phys 0x307a00e4 0x00100004
    55. 

  55.     mww phys 0x307a00f4 0x0000033f
    56. 

  56.     mww phys 0x307a0100 0x09081109
    57. 

  57.     mww phys 0x307a0104 0x0007020d
    58. 

  58.     mww phys 0x307a0108 0x03040407
    59. 

  59.     mww phys 0x307a010c 0x00002006
    60. 

  60.     mww phys 0x307a0110 0x04020205
    61. 

  61.     mww phys 0x307a0114 0x03030202
    62. 

  62.     mww phys 0x307a0120 0x00000803
    63. 

  63.     mww phys 0x307a0180 0x00800020
    64. 

  64.     mww phys 0x307a0184 0x02000100
    65. 

  65.     mww phys 0x307a0190 0x02098204
    66. 

  66.     mww phys 0x307a0194 0x00030303
    67. 

  67.     mww phys 0x307a0200 0x00000016
    68. 

  68.     mww phys 0x307a0204 0x00171717
    69. 

  69.     mww phys 0x307a0214 0x04040404
    70. 

  70.     mww phys 0x307a0218 0x0f040404
    71. 

  71.     mww phys 0x307a0240 0x06000604
    72. 

  72.     mww phys 0x307a0244 0x00000001
    73. 

  73.     mww phys 0x30391000 0x00000000
    74. 

  74.     mww phys 0x30790000 0x17420f40
    75. 

  75.     mww phys 0x30790004 0x10210100
    76. 

  76.     mww phys 0x30790010 0x00060807
    77. 

  77.     mww phys 0x307900b0 0x1010007e
    78. 

  78.     mww phys 0x3079009c 0x00000d6e
    79. 

  79.     mww phys 0x30790020 0x08080808
    80. 

  80.     mww phys 0x30790030 0x08080808
    81. 

  81.     mww phys 0x30790050 0x01000010
    82. 

  82.     mww phys 0x30790050 0x00000010
    83. 

  83. 

  84.     mww phys 0x307900c0 0x0e407304
    85. 

  85.     mww phys 0x307900c0 0x0e447304
    86. 

  86.     mww phys 0x307900c0 0x0e447306
    87. 

  87. 

  88.     check_bits_set_32 0x307900c4 0x1
    89. 

  89. 

  90.     mww phys 0x307900c0 0x0e447304
    91. 

  91.     mww phys 0x307900c0 0x0e407304
    92. 

  92. 

  93. 

  94.     mww phys 0x30384130 0x00000000
    95. 

  95.     mww phys 0x30340020 0x00000178
    96. 

  96.     mww phys 0x30384130 0x00000002
    97. 

  97.     mww phys 0x30790018 0x0000000f
    98. 

  98. 

  99.     check_bits_set_32 0x307a0004 0x1
    100. 

  100. }
    101. 

  101. 

  102. # disable internal reset-assert handling to
    103. 

  103. # allow reset-init to work
    104. 

  104. $_TARGETNAME.0 configure -event reset-assert ""
    105. 

  105. $_TARGETNAME.1 configure -event reset-assert ""
    106. 

  106. $_TARGETNAME_2 configure -event reset-assert ""
    107. 

  107. 

  108. $_TARGETNAME.0 configure -event reset-init {
    109. 

  109.     global _CHIPNAME
    110. 

  110.     imx7_disable_wdog
    111. 

  111.     imx7_uart_dbgconf
    112. 

  112.     apply_dcd
    113. 

  113.     $_CHIPNAME.dap memaccess 0
    114. 

  114. }
    115. 

  115. 

  116. target smp $_TARGETNAME.0 $_TARGETNAME.1
    117.