topas910.cfg 2.8 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. ######################################
  3. # Target: Toshiba TOPAS910 -- TMPA910 Starterkit
  4. #
  5. ######################################
  6. # We add to the minimal configuration.
  7. source [find target/tmpa910.cfg]
  8. ######################
  9. # Target configuration
  10. ######################
  11. #$_TARGETNAME configure -event gdb-attach { reset init }
  12. $_TARGETNAME configure -event reset-init { topas910_init }
  13. proc topas910_init { } {
  14. # Init PLL
  15. # my settings
  16. mww 0xf005000c 0x00000007
  17. mww 0xf0050010 0x00000065
  18. mww 0xf005000c 0x000000a7
  19. sleep 10
  20. mdw 0xf0050008
  21. mww 0xf0050008 0x00000002
  22. mww 0xf0050004 0x00000000
  23. # NEW: set CLKCR5
  24. mww 0xf0050054 0x00000040
  25. #
  26. sleep 10
  27. # Init SDRAM
  28. # _PMCDRV = 0x00000071;
  29. # //
  30. # // Initialize SDRAM timing parameter
  31. # //
  32. # _DMC_CAS_LATENCY = 0x00000006;
  33. # _DMC_T_DQSS = 0x00000000;
  34. # _DMC_T_MRD = 0x00000002;
  35. # _DMC_T_RAS = 0x00000007;
  36. #
  37. # _DMC_T_RC = 0x0000000A;
  38. # _DMC_T_RCD = 0x00000013;
  39. #
  40. # _DMC_T_RFC = 0x0000010A;
  41. #
  42. # _DMC_T_RP = 0x00000013;
  43. # _DMC_T_RRD = 0x00000002;
  44. # _DMC_T_WR = 0x00000002;
  45. # _DMC_T_WTR = 0x00000001;
  46. # _DMC_T_XP = 0x0000000A;
  47. # _DMC_T_XSR = 0x0000000B;
  48. # _DMC_T_ESR = 0x00000014;
  49. #
  50. # //
  51. # // Configure SDRAM type parameter
  52. # _DMC_MEMORY_CFG = 0x00008011;
  53. # _DMC_USER_CONFIG = 0x00000011;
  54. # // 32 bit memory interface
  55. #
  56. #
  57. # _DMC_REFRESH_PRD = 0x00000A60;
  58. # _DMC_CHIP_0_CFG = 0x000140FC;
  59. #
  60. # _DMC_DIRECT_CMD = 0x000C0000;
  61. # _DMC_DIRECT_CMD = 0x00000000;
  62. #
  63. # _DMC_DIRECT_CMD = 0x00040000;
  64. # _DMC_DIRECT_CMD = 0x00040000;
  65. # _DMC_DIRECT_CMD = 0x00080031;
  66. # //
  67. # // Finally start SDRAM
  68. # //
  69. # _DMC_MEMC_CMD = MEMC_CMD_GO;
  70. # */
  71. mww 0xf0020260 0x00000071
  72. mww 0xf4300014 0x00000006
  73. mww 0xf4300018 0x00000000
  74. mww 0xf430001C 0x00000002
  75. mww 0xf4300020 0x00000007
  76. mww 0xf4300024 0x0000000A
  77. mww 0xf4300028 0x00000013
  78. mww 0xf430002C 0x0000010A
  79. mww 0xf4300030 0x00000013
  80. mww 0xf4300034 0x00000002
  81. mww 0xf4300038 0x00000002
  82. mww 0xf430003C 0x00000001
  83. mww 0xf4300040 0x0000000A
  84. mww 0xf4300044 0x0000000B
  85. mww 0xf4300048 0x00000014
  86. mww 0xf430000C 0x00008011
  87. mww 0xf4300304 0x00000011
  88. mww 0xf4300010 0x00000A60
  89. mww 0xf4300200 0x000140FC
  90. mww 0xf4300008 0x000C0000
  91. mww 0xf4300008 0x00000000
  92. mww 0xf4300008 0x00040000
  93. mww 0xf4300008 0x00040000
  94. mww 0xf4300008 0x00080031
  95. mww 0xf4300004 0x00000000
  96. sleep 10
  97. # adapter speed NNNN
  98. # remap off in case of IROM boot
  99. mww 0xf0000004 0x00000001
  100. }
  101. # comment the following out if usinf J-Link, it soes not support DCC
  102. arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
  103. #####################
  104. # Flash configuration
  105. #####################
  106. #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
  107. set _FLASHNAME $_CHIPNAME.flash
  108. flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME