sdk-debugger-openocd-infineon/scripts/board/topasa900.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# Thanks to Pieter Conradie for this script!
# Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
######################################

# We add to the minimal configuration.
source [find target/tmpa900.cfg]

######################
# Target configuration
######################

#$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { topasa900_init }

proc topasa900_init { } {
# Init PLL
# my settings
	mww 0xf005000c 0x00000007
	mww 0xf0050010 0x00000065
	mww 0xf005000c 0x000000a7
	sleep 10
	mdw 0xf0050008
	mww 0xf0050008 0x00000002
	mww 0xf0050004 0x00000000
# NEW: set CLKCR5
	mww 0xf0050054 0x00000040
#
# bplan settings
#	mww 0xf0050004 0x00000000
#	mww 0xf005000c 0x000000a7
#	sleep 10
#	mdw 0xf0050008
#	mww 0xf0050008 0x00000002
#	mww 0xf0050010 0x00000065
#	mww 0xf0050054 0x00000040
	sleep 10
# Init SDRAM
#  _PMCDRV          = 0x00000071;
#  //
#  // Initialize SDRAM timing parameter
#  //
#  _DMC_CAS_LATENCY = 0x00000006;
#  _DMC_T_DQSS      = 0x00000000;
#  _DMC_T_MRD       = 0x00000002;
#  _DMC_T_RAS       = 0x00000007;
#
#  _DMC_T_RC        = 0x0000000A;
#  _DMC_T_RCD       = 0x00000013;
#
#  _DMC_T_RFC       = 0x0000010A;
#
#  _DMC_T_RP        = 0x00000013;
#  _DMC_T_RRD       = 0x00000002;
#  _DMC_T_WR        = 0x00000002;
#  _DMC_T_WTR       = 0x00000001;
#  _DMC_T_XP        = 0x0000000A;
#  _DMC_T_XSR       = 0x0000000B;
#  _DMC_T_ESR       = 0x00000014;
#
#  //
#  // Configure SDRAM type parameter
#  _DMC_MEMORY_CFG  = 0x00008011;
#  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
#
#
#  _DMC_REFRESH_PRD = 0x00000A60;
#  _DMC_CHIP_0_CFG  = 0x000140FC;
#
#  _DMC_DIRECT_CMD  = 0x000C0000;
#  _DMC_DIRECT_CMD  = 0x00000000;
#
#  _DMC_DIRECT_CMD  = 0x00040000;
#  _DMC_DIRECT_CMD  = 0x00040000;
#  _DMC_DIRECT_CMD  = 0x00080031;
#  //
#  // Finally start SDRAM
#  //
#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
#  */

	mww 0xf0020260 0x00000071
	mww 0xf4300014 0x00000006
	mww 0xf4300018 0x00000000
	mww 0xf430001C 0x00000002
	mww 0xf4300020 0x00000007
	mww 0xf4300024 0x0000000A
	mww 0xf4300028 0x00000013
	mww 0xf430002C 0x0000010A
	mww 0xf4300030 0x00000013
	mww 0xf4300034 0x00000002
	mww 0xf4300038 0x00000002
	mww 0xf430003C 0x00000001
	mww 0xf4300040 0x0000000A
	mww 0xf4300044 0x0000000B
	mww 0xf4300048 0x00000014
	mww 0xf430000C 0x00008011
	mww 0xf4300304 0x00000011
	mww 0xf4300010 0x00000A60
	mww 0xf4300200 0x000140FC
	mww 0xf4300008 0x000C0000
	mww 0xf4300008 0x00000000
	mww 0xf4300008 0x00040000
	mww 0xf4300008 0x00040000
	mww 0xf4300008 0x00080031
	mww 0xf4300004 0x00000000

	sleep 10
#	adapter speed NNNN

# remap off in case of IROM boot
	mww 0xf0000004 0x00000001

}

# comment the following out if usinf J-Link, it soes not support DCC
arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads


#####################
# Flash configuration
#####################

#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME