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tp-link_wdr4300.cfg

tp-link_wdr4300.cfg 3.4 KB
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  1. # SPDX-License-Identifier: GPL-2.0-or-later
    2. 

  2. 

  3. source [find target/atheros_ar9344.cfg]
    4. 

  4. 

  5. reset_config trst_only separate
    6. 

  6. 

  7. proc ar9344_40mhz_pll_init {} {
    8. 

  8. 	# QCA_PLL_SRIF_CPU_DPLL2_REG
    9. 

  9. 	mww 0xb81161C4 0x13210f00
    10. 

  10. 	# QCA_PLL_SRIF_CPU_DPLL3_REG
    11. 

  11. 	mww 0xb81161C8 0x03000000
    12. 

  12. 	# QCA_PLL_SRIF_DDR_DPLL2_REG
    13. 

  13. 	mww 0xb8116244 0x13210f00
    14. 

  14. 	# QCA_PLL_SRIF_DDR_DPLL3_REG
    15. 

  15. 	mww 0xb8116248 0x03000000
    16. 

  16. 	# QCA_PLL_SRIF_BB_DPLL_BASE_REG
    17. 

  17. 	mww 0xb8116188 0x03000000
    18. 

  18. 

  19. 	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
    20. 

  20. 	mww 0xb8050008 0x0130001C
    21. 

  21. 	mww 0xb8050008 0x0130001C
    22. 

  22. 	mww 0xb8050008 0x0130001C
    23. 

  23. 

  24. 	# QCA_PLL_CPU_PLL_CFG_REG
    25. 

  25. 	mww 0xb8050000 0x40021380
    26. 

  26. 	# QCA_PLL_DDR_PLL_CFG_REG
    27. 

  27. 	mww 0xb8050004 0x40815800
    28. 

  28. 	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
    29. 

  29. 	mww 0xb8050008 0x0130801C
    30. 

  30. 

  31. 	# QCA_PLL_SRIF_CPU_DPLL2_REG
    32. 

  32. 	mww 0xb81161C4 0x10810F00
    33. 

  33. 	mww 0xb81161C0 0x41C00000
    34. 

  34. 	# QCA_PLL_SRIF_CPU_DPLL2_REG
    35. 

  35. 	mww 0xb81161C4 0xD0810F00
    36. 

  36. 	# QCA_PLL_SRIF_CPU_DPLL3_REG
    37. 

  37. 	mww 0xb81161C8 0x03000000
    38. 

  38. 	# QCA_PLL_SRIF_CPU_DPLL2_REG
    39. 

  39. 	mww 0xb81161C4 0xD0800F00
    40. 

  40. 

  41. 	# QCA_PLL_SRIF_CPU_DPLL3_REG
    42. 

  42. 	mww 0xb81161C8 0x03000000
    43. 

  43. 	# QCA_PLL_SRIF_CPU_DPLL3_REG
    44. 

  44. 	mww 0xb81161C8 0x43000000
    45. 

  45. 	# QCA_PLL_SRIF_CPU_DPLL3_REG
    46. 

  46. 	mww 0xb81161C8 0x030003E8
    47. 

  47. 

  48. 	# QCA_PLL_SRIF_DDR_DPLL2_REG
    49. 

  49. 	mww 0xb8116244 0x10810F00
    50. 

  50. 	mww 0xb8116240 0x41680000
    51. 

  51. 	# QCA_PLL_SRIF_DDR_DPLL2_REG
    52. 

  52. 	mww 0xb8116244 0xD0810F00
    53. 

  53. 	# QCA_PLL_SRIF_DDR_DPLL3_REG
    54. 

  54. 	mww 0xb8116248 0x03000000
    55. 

  55. 	# QCA_PLL_SRIF_DDR_DPLL2_REG
    56. 

  56. 	mww 0xb8116244 0xD0800F00
    57. 

  57. 

  58. 	# QCA_PLL_SRIF_DDR_DPLL3_REG
    59. 

  59. 	mww 0xb8116248 0x03000000
    60. 

  60. 	# QCA_PLL_SRIF_DDR_DPLL3_REG
    61. 

  61. 	mww 0xb8116248 0x43000000
    62. 

  62. 	# QCA_PLL_SRIF_DDR_DPLL3_REG
    63. 

  63. 	mww 0xb8116248 0x03000718
    64. 

  64. 

  65. 	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
    66. 

  66. 	mww 0xb8050008 0x01308018
    67. 

  67. 	mww 0xb8050008 0x01308010
    68. 

  68. 	mww 0xb8050008 0x01308000
    69. 

  69. 

  70. 	# QCA_PLL_DDR_PLL_DITHER_REG
    71. 

  71. 	mww 0xb8050044 0x78180200
    72. 

  72. 	# QCA_PLL_CPU_PLL_DITHER_REG
    73. 

  73. 	mww 0xb8050048 0x41C00000
    74. 

  74. 

  75. }
    76. 

  76. 

  77. proc ar9344_ddr_init {} {
    78. 

  78. 	# QCA_DDR_CTRL_CFG_REG
    79. 

  79. 	mww 0xb8000108 0x40
    80. 

  80. 	# QCA_DDR_RD_DATA_THIS_CYCLE_REG
    81. 

  81. 	mww 0xb8000018 0xFF
    82. 

  82. 	# QCA_DDR_BURST_REG
    83. 

  83. 	mww 0xb80000C4 0x74444444
    84. 

  84. 	# QCA_DDR_BURST2_REG
    85. 

  85. 	mww 0xb80000C8 0x0222
    86. 

  86. 	# QCA_AHB_MASTER_TOUT_MAX_REG
    87. 

  87. 	mww 0xb80000CC 0xFFFFF
    88. 

  88. 

  89. 	# QCA_DDR_CFG_REG
    90. 

  90. 	mww 0xb8000000 0xC7D48CD0
    91. 

  91. 	# QCA_DDR_CFG2_REG
    92. 

  92. 	mww 0xb8000004 0x9DD0E6A8
    93. 

  93. 

  94. 	# QCA_DDR_DDR2_CFG_REG
    95. 

  95. 	mww 0xb80000B8 0x0E59
    96. 

  96. 	# QCA_DDR_CFG2_REG
    97. 

  97. 	mww 0xb8000004 0x9DD0E6A8
    98. 

  98. 

  99. 	# QCA_DDR_CTRL_REG
    100. 

  100. 	mww 0xb8000010 0x08
    101. 

  101. 	mww 0xb8000010 0x08
    102. 

  102. 	mww 0xb8000010 0x10
    103. 

  103. 	mww 0xb8000010 0x20
    104. 

  104. 	# QCA_DDR_EMR_REG
    105. 

  105. 	mww 0xb800000C 0x02
    106. 

  106. 	# QCA_DDR_CTRL_REG
    107. 

  107. 	mww 0xb8000010 0x02
    108. 

  108. 

  109. 	# QCA_DDR_MR_REG
    110. 

  110. 	mww 0xb8000008 0x0133
    111. 

  111. 	# QCA_DDR_CTRL_REG
    112. 

  112. 	mww 0xb8000010 0x1
    113. 

  113. 	mww 0xb8000010 0x8
    114. 

  114. 	mww 0xb8000010 0x8
    115. 

  115. 	mww 0xb8000010 0x4
    116. 

  116. 	mww 0xb8000010 0x4
    117. 

  117. 

  118. 	# QCA_DDR_MR_REG
    119. 

  119. 	mww 0xb8000008 0x33
    120. 

  120. 	# QCA_DDR_CTRL_REG
    121. 

  121. 	mww 0xb8000010 0x1
    122. 

  122. 

  123. 	# QCA_DDR_EMR_REG
    124. 

  124. 	mww 0xb800000C 0x0382
    125. 

  125. 	# QCA_DDR_CTRL_REG
    126. 

  126. 	mww 0xb8000010 0x2
    127. 

  127. 	# QCA_DDR_EMR_REG
    128. 

  128. 	mww 0xb800000C 0x0402
    129. 

  129. 	# QCA_DDR_CTRL_REG
    130. 

  130. 	mww 0xb8000010 0x2
    131. 

  131. 

  132. 	# QCA_DDR_REFRESH_REG
    133. 

  133. 	mww 0xb8000014 0x4270
    134. 

  134. 

  135. 	# QCA_DDR_TAP_CTRL_0_REG
    136. 

  136. 	mww 0xb800001C 0x0e
    137. 

  137. 	# QCA_DDR_TAP_CTRL_1_REG
    138. 

  138. 	mww 0xb8000020 0x0e
    139. 

  139. 	# QCA_DDR_TAP_CTRL_2_REG
    140. 

  140. 	mww 0xb8000024 0x0e
    141. 

  141. 	# QCA_DDR_TAP_CTRL_3_REG
    142. 

  142. 	mww 0xb8000028 0x0e
    143. 

  143. }
    144. 

  144. 

  145. $_TARGETNAME configure -event reset-init {
    146. 

  146. 

  147. 	# mww 0xb806001c 0x1000000
    148. 

  148. 	ar9344_40mhz_pll_init
    149. 

  149. 	sleep 100
    150. 

  150. 

  151. 	# flash remap
    152. 

  152. 	# SPI_CONTROL_ADDR
    153. 

  153. 	mww 0xbF000004 0x43
    154. 

  154. 

  155. 	ar9344_ddr_init
    156. 

  156. 	sleep 100
    157. 

  157. }
    158. 

  158. 

  159. set ram_boot_address 0xa0000000
    160. 

  160. $_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
    161. 

  161. 

  162. flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
    163.