tx25_stk5.cfg 4.6 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # -------------------------------------------------------------------------
  3. # KaRo TX25 CPU Module on a StarterkitV base board
  4. # http://www.karo-electronics.com/tx25.html
  5. # -------------------------------------------------------------------------
  6. source [find target/imx25.cfg]
  7. #-------------------------------------------------------------------------
  8. # Declare Nand
  9. #-------------------------------------------------------------------------
  10. nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
  11. $_TARGETNAME configure -event gdb-attach { reset init }
  12. $_TARGETNAME configure -event reset-init { tx25_init }
  13. proc tx25_init { } {
  14. #-------------------------------------------------------------------------
  15. # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
  16. # Set all MPROTx to be non-bufferable, trusted for R/W,
  17. # not forced to user-mode.
  18. #-------------------------------------------------------------------------
  19. mww 0x43f00000 0x77777777
  20. mww 0x43f00004 0x77777777
  21. mww 0x53f00000 0x77777777
  22. mww 0x53f00004 0x77777777
  23. sleep 100
  24. #-------------------------------------------------------------------------
  25. # MAX (Multi-Layer AHB Crossbar Switch) setup
  26. # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
  27. #-------------------------------------------------------------------------
  28. mww 0x43f04000 0x00043210
  29. mww 0x43f04100 0x00043210
  30. mww 0x43f04200 0x00043210
  31. mww 0x43f04300 0x00043210
  32. mww 0x43f04400 0x00043210
  33. # SGPCR - always park on last master
  34. mww 0x43f04010 0x10
  35. mww 0x43f04110 0x10
  36. mww 0x43f04210 0x10
  37. mww 0x43f04310 0x10
  38. mww 0x43f04410 0x10
  39. # MGPCR - restore default values
  40. mww 0x43f04800 0x0
  41. mww 0x43f04900 0x0
  42. mww 0x43f04a00 0x0
  43. mww 0x43f04b00 0x0
  44. mww 0x43f04c00 0x0
  45. # Configure M3IF registers
  46. # M3IF Control Register (M3IFCTL) for MX25
  47. # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
  48. # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
  49. # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
  50. # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
  51. # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
  52. # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
  53. # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
  54. # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
  55. # ----------
  56. # 0x00000001
  57. mww 0xb8003000 0x00000001
  58. #-------------------------------------------------------------------------
  59. # configure ARM CLK
  60. #-------------------------------------------------------------------------
  61. # Set the Clock CTL (HRM p. 355)
  62. mww 0x53F80008 0x20034000
  63. # Setup Clock Gating CTL 0-2 (HRM p. 357)
  64. mww 0x53F8000C 0x1fffffff
  65. mww 0x53F80010 0xffffffff
  66. mww 0x53F80014 0x000fdfff
  67. #-------------------------------------------------------------------------
  68. # SDRAM initialization
  69. #-------------------------------------------------------------------------
  70. # set to 3.3v SDRAM
  71. mww 0x43FAC454 0x00000800
  72. # reset (set up ESDMISC)
  73. mww 0xB8001010 0x00000002
  74. # Setup for SDRAM Bank 0
  75. #-------------------------------------------------------------------------
  76. # Write ESDCFG0
  77. mww 0xB8001004 0x00095728
  78. # CTL SMode = Precharge command
  79. mww 0xB8001000 0x92116480
  80. mww 0x80000400 0x00000000
  81. # CTL SMode = Auto Refresh command
  82. mww 0xB8001000 0xA2116480
  83. mww 0x80000000 0x0
  84. mww 0x80000000 0x0
  85. mww 0x80000000 0x0
  86. mww 0x80000000 0x0
  87. mww 0x80000000 0x0
  88. mww 0x80000000 0x0
  89. mww 0x80000000 0x0
  90. mww 0x80000000 0x0
  91. # CTL SMode = Load Mode Register command
  92. mww 0xB8001000 0xB2116480
  93. mwb 0x80000033 0x00
  94. # CTL SMode = normal
  95. mww 0xB8001000 0x82116480
  96. # Setup for SDRAM Bank 1
  97. #-------------------------------------------------------------------------
  98. # Write ESDCFG1
  99. mww 0xB800100C 0x00095728
  100. # CTL SMode = Precharge command
  101. mww 0xB8001008 0x92116480
  102. mww 0x90000400 0x00000000
  103. # CTL SMode = Auto Refresh command
  104. mww 0xB8001008 0xA2116480
  105. mww 0x90000000 0x00000000
  106. mww 0x90000000 0x00000000
  107. mww 0x90000000 0x00000000
  108. mww 0x90000000 0x00000000
  109. mww 0x90000000 0x00000000
  110. mww 0x90000000 0x00000000
  111. mww 0x90000000 0x00000000
  112. mww 0x90000000 0x00000000
  113. # CTL SMode = Load Mode Register command
  114. mww 0xB8001008 0xB2116480
  115. mwb 0x90000033 0x00
  116. # CTL SMode = normal
  117. mww 0xB8001008 0x82116480
  118. # GPIO configuration
  119. #-------------------------------------------------------------------------
  120. mww 0x43FAC02C 0x00000015
  121. mww 0x53FD0000 0x01000000
  122. mww 0x53FD0004 0x00000080
  123. }