vd_a75x4_dap.cfg 810 B

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Cadence virtual debug interface
  3. # Arm Cortex A53x2 through DAP
  4. source [find interface/vdebug.cfg]
  5. set CORES 4
  6. set CHIPNAME a75
  7. set ACCESSPORT 0x00040000
  8. set MEMSTART 0x00000000
  9. set MEMSIZE 0x1000000
  10. set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
  11. set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
  12. # vdebug select transport
  13. transport select dapdirect_swd
  14. # JTAG reset config, frequency and reset delay
  15. adapter speed 200000
  16. adapter srst delay 5
  17. # BFM hierarchical path and input clk period
  18. vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
  19. # DMA Memories to access backdoor (up to 20)
  20. #vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
  21. swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
  22. source [find target/vd_aarch64.cfg]