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- # SPDX-License-Identifier: GPL-2.0-or-later
- # Cadence virtual debug interface
- # Arm Cortex A53x2 through DAP
- source [find interface/vdebug.cfg]
- set CORES 4
- set CHIPNAME a75
- set ACCESSPORT 0x00040000
- set MEMSTART 0x00000000
- set MEMSIZE 0x1000000
- set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
- set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
- # vdebug select transport
- transport select dapdirect_swd
- # JTAG reset config, frequency and reset delay
- adapter speed 200000
- adapter srst delay 5
- # BFM hierarchical path and input clk period
- vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
- # DMA Memories to access backdoor (up to 20)
- #vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
- swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
- source [find target/vd_aarch64.cfg]
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