altera_fpgasoc_arria10.cfg 1.9 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Intel (Altera) Arria10 FPGA SoC
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME arria10
  7. }
  8. # ARM CoreSight Debug Access Port (dap HPS)
  9. if { [info exists DAP_TAPID] } {
  10. set _DAP_TAPID $DAP_TAPID
  11. } else {
  12. set _DAP_TAPID 0x4ba00477
  13. }
  14. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
  15. # Subsidiary TAP: fpga (tap)
  16. # See Intel Arria 10 Handbook
  17. # https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
  18. # Intel Arria 10 GX 160 0x02ee20dd
  19. # Intel Arria 10 GX 220 0x02e220dd
  20. # Intel Arria 10 GX 270 0x02ee30dd
  21. # Intel Arria 10 GX 320 0x02e230dd
  22. # Intel Arria 10 GX 480 0x02e240dd
  23. # Intel Arria 10 GX 570 0x02ee50dd
  24. # Intel Arria 10 GX 660 0x02e250dd
  25. # Intel Arria 10 GX 900 0x02ee60dd
  26. # Intel Arria 10 GX 1150 0x02e660dd
  27. # Intel Arria 10 GT 900 0x02e260dd
  28. # Intel Arria 10 GT 1150 0x02e060dd
  29. # Intel Arria 10 SX 160 0x02e620dd
  30. # Intel Arria 10 SX 220 0x02e020dd
  31. # Intel Arria 10 SX 270 0x02e630dd
  32. # Intel Arria 10 SX 320 0x02e030dd
  33. # Intel Arria 10 SX 480 0x02e040dd
  34. # Intel Arria 10 SX 570 0x02e650dd
  35. # Intel Arria 10 SX 660 0x02e050dd
  36. jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
  37. -expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
  38. -expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
  39. -expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
  40. -expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
  41. -expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
  42. -expected-id 0x02e050dd
  43. set _TARGETNAME $_CHIPNAME.cpu
  44. #
  45. # Cortex-A9 target
  46. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  47. target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
  48. target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
  49. -defer-examine
  50. target smp $_TARGETNAME.0 $_TARGETNAME.1