sdk-debugger-openocd-infineon/scripts/target/atsame5x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

#
# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices
# with a Cortex-M4 core
#

#
# Devices only support SWD transports.
#
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME atsame5
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

# Work-area is a space in RAM used for flash programming
# By default use 32kB (the smallest RAM size is 128kB)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x8000
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x4ba00477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# SAM DSU will hold the CPU in reset if TCK is low when RESET_N
# deasserts
#
# dsu_reset_deassert configures whether we want to run or halt out of reset,
# then instruct the DSU to let us out of reset.
$_TARGETNAME configure -event reset-deassert-post {
        atsame5 dsu_reset_deassert
}

# SRST (wired to RESET_N) resets debug circuitry
# srst_pulls_trst is not configured here to avoid an error raised in reset halt
reset_config srst_gates_jtag

# Do not use a reset button with other SWD adapter than Atmel's EDBG.
# DSU usually locks MCU in reset state until you issue a reset command
# in OpenOCD.

# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset.
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at clock speed over 5000 khz. Atmel recommends
# adapter speed less than 10 * CPU clock.
adapter speed 2000

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME