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- # SPDX-License-Identifier: GPL-2.0-or-later
- # Freescale i.MX53
- if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
- } else {
- set _CHIPNAME imx53
- }
- # CoreSight Debug Access Port
- if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
- } else {
- set _DAP_TAPID 0x1ba00477
- }
- jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID
- # SDMA / no IDCODE
- jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
- # SJC
- if { [info exists SJC_TAPID] } {
- set _SJC_TAPID SJC_TAPID
- } else {
- set _SJC_TAPID 0x0190d01d
- }
- jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
- -expected-id $_SJC_TAPID -ignore-version
- # GDB target: Cortex-A8, using DAP
- set _TARGETNAME $_CHIPNAME.cpu
- dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
- target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
- # some TCK tycles are required to activate the DEBUG power domain
- jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
- proc imx53_dbginit {target} {
- # General Cortex-A8 debug initialisation
- cortex_a dbginit
- }
- $_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"
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