max32620.cfg 1.2 KB

1234567891011121314151617181920212223242526272829303132
  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Maxim Integrated MAX32620 OpenOCD target configuration file
  3. # www.maximintegrated.com
  4. # adapter speed
  5. adapter speed 4000
  6. # reset pin configuration
  7. reset_config srst_only
  8. if {[using_jtag]} {
  9. jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
  10. jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
  11. } else {
  12. swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
  13. }
  14. dap create max32620.dap -chain-position max32620.cpu
  15. # target configuration
  16. target create max32620.cpu cortex_m -dap max32620.dap
  17. max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
  18. # Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
  19. # flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
  20. # max32620 flash base address 0x00000000
  21. # max32620 flash size 0x200000 (2MB)
  22. # max32620 FLC base address 0x40002000
  23. # max32620 sector (page) size 0x2000 (8kB)
  24. # max32620 clock speed 96 (MHz)
  25. flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96