sdk-debugger-openocd-infineon/scripts/target/omap3530.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# TI OMAP3530
# http://focus.ti.com/docs/prod/folders/print/omap3530.html
# Other OMAP3 chips remove DSP and/or the OpenGL support

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME omap3530
}

# ICEpick-C ... used to route Cortex, DSP, and more not shown here
source [find target/icepick.cfg]

# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable

# Subsidiary TAP: CoreSight Debug Access Port (DAP)
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x0b6d602f
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
	-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
	"icepick_c_tapenable $_CHIPNAME.jrc 3"

# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
   set _JRC_TAPID $JRC_TAPID
} else {
   set _JRC_TAPID 0x0b7ae02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
	-expected-id $_JRC_TAPID

# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap

# SRAM: 64K at 0x4020.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000

###################

# the reset sequence is event-driven
# and kind of finicky...

# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"

# have the DAP "always" be active
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"

proc omap3_dbginit {target} {
     # General Cortex-A8 debug initialisation
     cortex_a dbginit
     # Enable DBGU signal for OMAP353x
     $target mww phys 0x5401d030 0x00002000
}

# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
adapter speed 1000
$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }

# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
# would issue.  RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"

$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"