sdk-debugger-openocd-infineon/scripts/target/psoc5lp.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

#
# Cypress PSoC 5LP
#

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME psoc5lp
}

if { [info exists CPUTAPID] } {
	set _CPU_TAPID $CPUTAPID
} else {
	set _CPU_TAPID 0x4BA00477
}

if { [using_jtag] } {
	set _CPU_DAP_ID $_CPU_TAPID
} else {
	set _CPU_DAP_ID 0x2ba01477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

if { [info exists WORKAREASIZE] } {
	set _WORKAREASIZE $WORKAREASIZE
} else {
	set _WORKAREASIZE 0x2000
}

$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
                       -work-area-size $_WORKAREASIZE -work-area-backup 0

source [find mem_helper.tcl]

$_TARGETNAME configure -event reset-init {
	# Configure Target Device (PSoC 5LP Device Programming Specification 5.2)

	set PANTHER_DBG_CFG 0x4008000C
	set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
	mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0

	set PM_ACT_CFG0 0x400043A0
	mww $PM_ACT_CFG0 0xBF

	set FASTCLK_IMO_CR 0x40004200
	set FASTCLK_IMO_CR_F_RANGE_2    [expr {2 << 0}]
	set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
	mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
}

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME

if {![using_hla]} {
	cortex_m reset_config sysresetreq
}