ti_calypso.cfg 1.2 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859
  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. #
  3. # TI Calypso (lite) G2 C035 Digital Base Band chip
  4. #
  5. # ARM7TDMIE + DSP subchip (S28C128)
  6. #
  7. # 512K SRAM Calypso
  8. # 256K SRAM Calypso lite
  9. #
  10. if { [info exists CHIPNAME] } {
  11. set _CHIPNAME $CHIPNAME
  12. } else {
  13. set _CHIPNAME calypso
  14. }
  15. if { [info exists ENDIAN] } {
  16. set _ENDIAN $ENDIAN
  17. } else {
  18. set _ENDIAN little
  19. }
  20. if { [info exists CPUTAPID] } {
  21. set _CPUTAPID $CPUTAPID
  22. } else {
  23. set _CPUTAPID 0x3100e02f
  24. }
  25. # Work-area is a space in RAM used for flash programming
  26. # By default use 64kB
  27. if { [info exists WORKAREASIZE] } {
  28. set _WORKAREASIZE $WORKAREASIZE
  29. } else {
  30. set _WORKAREASIZE 0x10000
  31. }
  32. adapter speed 1000
  33. reset_config trst_and_srst
  34. jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8
  35. jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  36. # target
  37. set _TARGETNAME $_CHIPNAME.arm
  38. target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME
  39. # workarea
  40. $_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1
  41. arm7_9 dcc_downloads enable
  42. arm7_9 fast_memory_access enable
  43. $_TARGETNAME configure -event examine-start {
  44. irscan calypso.arm 0x0b -endstate DRPAUSE
  45. drscan calypso.arm 2 2 -endstate RUN/IDLE
  46. }