sdk-debugger-openocd-infineon/scripts/target/ti_dm6446.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

#
# Texas Instruments DaVinci family: TMS320DM6446
#
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME dm6446
}

# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
set EMU01 "-disable"

# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
#set EMU01 "-enable"

source [find target/icepick.cfg]

# Subsidiary TAP: unknown ... must enable via ICEpick
jtag newtap $_CHIPNAME unknown -irlen 8 -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
	"icepick_c_tapenable $_CHIPNAME.jrc 3"

# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
jtag configure $_CHIPNAME.dsp -event tap-enable \
	"icepick_c_tapenable $_CHIPNAME.jrc 2"

# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
   set _ETB_TAPID $ETB_TAPID
} else {
   set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
	"icepick_c_tapenable $_CHIPNAME.jrc 1"

# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
   set _CPU_TAPID $CPU_TAPID
} else {
   set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
	"icepick_c_tapenable $_CHIPNAME.jrc 0"

# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
   set _JRC_TAPID $JRC_TAPID
} else {
   set _JRC_TAPID 0x0b70002f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID

jtag configure $_CHIPNAME.jrc -event setup \
	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"

################
# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
set _TARGETNAME $_CHIPNAME.arm

target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000

# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it.  OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }

arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable

# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb