sdk-debugger-openocd-infineon/scripts/target/traveo2_6m.cfg

#
# Copyright (C) <2019-2024>
#   <Cypress Semiconductor Corporation (an Infineon company)>
#
# Configuration script for Cypress TRAVEO™II C-2D family of microcontrollers.
# TRAVEO™II C-2D is a triple-core device with CM0+ and 2xCM7 cores. All cores share
# the same Flash/RAM/MMIO address space.
#
source [find target/infineon/common/common_ifx.cfg]
namespace import ifx::*

# The following four lines can be used to override Flash Geometry of the target device
# In this case configuration scripts will not perform any auto-detection and will use
# predefined values.
# If all these variables are set to zero, configuration scripts will attempt to detect
# the type of target device by reading SiliconID from SFlash and matching it with MPN
# database, see cympn.cfg file.
set MAIN_LARGE_SECTOR_NUM 190
set MAIN_SMALL_SECTOR_NUM 32
set WORK_LARGE_SECTOR_NUM 48
set WORK_SMALL_SECTOR_NUM 256

# Reset configuration - use hardware XRES pin
# If this line is commented-out OpenOCD will use SYSRESETREQ to reset the CM0+ core and
# all peripherals. This will also reset CM4/CM7 cores.
# reset_config srst_only srst_pulls_trst

# Defines the name of the Target and allows to override it from the command line
set_or_global CHIPNAME traveo2_6m
set TARGET_VARIANT TVIIC2D6M

echo "** Supported Flash Loaders: ***********************"
echo "** SMIF0_LOADER: TV2_6M_SI_A0_SemperFlash.elf"
echo "**               TV2_6M_SI_A0_HyperFlash.elf"
echo "**               TV2_6M_SI_A0_DualQuadSPI.elf"
echo "***************************************************"

# External Memory configuration
# The following variables can be set to '1' in the command line to enable corresponding
# external memory banks:
# set ENABLE_SEMPERFLASH_0 1
# set ENABLE_HYPERFLASH_0  1
# set ENABLE_DUALQUADSPI_0 1
set_or_global ENABLE_SEMPERFLASH_0  0
set_or_global ENABLE_HYPERFLASH_0   0
set_or_global ENABLE_DUALQUADSPI_0  0

# Default flash loaders, can be overriden from the command line
set_or_global SEMPERFLASH_LOADER_0  TV2_6M_SI_A0_SemperFlash.elf
set_or_global HYPERFLASH_LOADER_0   TV2_6M_SI_A0_HyperFlash.elf
set_or_global DUALQUADSPI_LOADER_0  TV2_6M_SI_A0_DualQuadSPI.elf
set_or_global HYPERRAM_LOADER_0     TV2_6M_SI_A0_HyperRAM.elf

# Include common functionality script
source [find target/infineon/cat1c/base_cytxxx.cfg]

# Procedure to enable external HyperRAM
# Script loads initialization code to target RAM and executes it
# Initialization code is responsible for enabling external RAM and
# mapping it to the CPU address space
proc enable_hyperram_0 { {xip_base 0x64000000} } {
	global HYPERRAM_LOADER_0

	catch {
		load_image ../flm/cypress/traveo2/${HYPERRAM_LOADER_0} 0x28000800
		reg pc 0x28000800
		reg sp 0x28010000
		reg r0 $xip_base
		reg r1 0
		reg r2 3
		reg r9 0x28002800
		resume 0x28000800
		wait_halt
		mrw $xip_base
		echo "** HyperRAM mapped to address [format 0x%08X $xip_base]"
	}
}