sdk-debugger-openocd-infineon/scripts/target/traveo2_8m_psvp.cfg

#
# Copyright (C) <2019-2021>
#   <Cypress Semiconductor Corporation (an Infineon company)>
#
# Configuration script for Cypress TRAVEO™II B-H family of microcontrollers.
# TRAVEO™II B-H is a triple-core device with CM0+ and 2xCM7 cores. All cores share
# the same Flash/RAM/MMIO address space.
#

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
source [find target/infineon/common/common_ifx.cfg]
source [find target/infineon/cat1/func_mxs40.cfg]
namespace import ifx::*
namespace import mxs40::*

if {[using_jtag]} {
   adapter speed 1000
} else {
   adapter speed 2000
}

adapter srst delay 25
adapter srst pulse_width 5

global _CHIPNAME
if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME traveo2_8m
}

set TARGET_VARIANT TVIIBH8M

# (large_sector_num << 16) | small_sector_num
set ${_CHIPNAME}::MAIN_FLASH_SIZE_OVERRIDE [ expr {(30 << 16) | 8} ]
set ${_CHIPNAME}::WORK_FLASH_SIZE_OVERRIDE [ expr {(96 << 16) | 512} ]

if { ![info exists HYPERFLASH_FLASHLOADER] } {
	set HYPERFLASH_FLASHLOADER {../flm/cypress/traveo2/TV2BH_8M_HyperFlash.elf}
}

if { ![info exists HYPERRAM_FLASHLOADER] } {
	set HYPERRAM_FLASHLOADER {../flm/cypress/traveo2/TV2BH_8M_HyperRAM.elf}
}

if { ![info exists DUALQUADSPI_FLASHLOADER] } {
	set DUALQUADSPI_FLASHLOADER {../flm/cypress/traveo2/TV2BH_8M_DualQuadSPI.elf}
}

global _ENABLE_ACQUIRE
global _ENABLE_POWER_SUPPLY
if { [adapter name] eq "kitprog3" } {
	if { [info exists ENABLE_ACQUIRE] } {
		set _ENABLE_ACQUIRE $ENABLE_ACQUIRE
	} else {
		if {[using_jtag]} {
			set _ENABLE_ACQUIRE 0
			echo "** Test Mode acquire disabled (not supported in JTAG mode)"
		} else {
			set _ENABLE_ACQUIRE 1
		}
	}

	if { [info exists ENABLE_POWER_SUPPLY] } {
		set _ENABLE_POWER_SUPPLY $ENABLE_POWER_SUPPLY
	} else {
		set _ENABLE_POWER_SUPPLY 0
	}
} else {
	set _ENABLE_ACQUIRE	 0
	set _ENABLE_POWER_SUPPLY 0
	echo "** Test Mode acquire not supported by selected adapter"
}

if { $_ENABLE_ACQUIRE } {
	echo "** Auto-acquire enabled, use \"set ENABLE_ACQUIRE 0\" to disable"
	kitprog3 acquire_config on 3 0 2
}

if { $_ENABLE_POWER_SUPPLY } {
	echo "** Enabling target power ($_ENABLE_POWER_SUPPLY mV) \"set ENABLE_POWER_SUPPLY 0\" to disable"
	kitprog3 power_config on $_ENABLE_POWER_SUPPLY
}


global TARGET
set TARGET $_CHIPNAME.cpu
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apsel 2
$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]
$_CHIPNAME.dap apsel 3
$_CHIPNAME.dap apcsw [expr {(1 << 24) | (1 << 25) | (1 << 27) | (1 << 29) | (1 << 31)}]

proc init_reset { mode } {
	global RESET_MODE
	set RESET_MODE $mode

	if {[using_jtag]} {
		jtag arp_init-reset
	}
}

#proc chip_protection {} {
#	set protection [ expr [mrw 0x402020C4]]
#	set ret "X"
#
#	switch $protection {
#		1 { set ret "VIRGIN" }
#		2 { set ret "NORMAL" }
#		3 { set ret "SECURE" }
#		4 { set ret "DEAD" }
#		default { set ret "UNKNOWN" }
#	}
#
#	return $ret
#}

proc enable_cm7x {} {
	mww 0x40261244 0x80000000
	mww 0x40261248 0x80000000
	mww 0x4020040C 15
	mww 0x4020000C 15
	mww 0x40201200 0x05FA0001
	mww 0x40201200 0x05FA0003
	mww 0x40201210 0x05FA0001
	mww 0x40201210 0x05FA0003
}

# Utility to make 'reset halt' work as reset;halt on a target
# It does not prevent running code after reset
proc reset_deassert_post { target } {
	global _ENABLE_ACQUIRE
	global RESET_MODE

	if { $RESET_MODE ne "run" } {
		if { [string match "*cm0" $target] } {
			if { $_ENABLE_ACQUIRE } {
				catch { acquire traveo2_8m.cpu.cm0 }
			}

#			catch {
#				echo "** SFlash SiliconID:	 0x[format %08X [mrw 0x17000000]]"
#				echo "** Flash Boot version: 0x[format %08X [mrw 0x17002004]]"
#				echo "** Chip Protection: [chip_protection]"
#			}
		}

		# TRAVEO™II cleared AP registers including TAR during reset
		# Force examine to synchronize OpenOCD target status
		$target arp_examine
		$target arp_poll
		$target arp_poll
		set st [$target curstate]

		if { $st eq "reset" } {
			# we assume running state follows
			# if reset accidentally halts, waiting is useless
			catch { $target arp_waitstate running 100 }
			set st [$target curstate]
		}

		if { $st eq "running" } {
			echo "** $target: Ran after reset and before halt..."
			if [string match "*cm0" $target ] {
				if { $_ENABLE_ACQUIRE == 0 } {
					sleep 100
					traveo2 reset_halt
				} else {
					$target arp_halt
				}

			} else {
				$target arp_halt
			}
			$target arp_waitstate halted 100
		}
	}
}

proc acquire { target } {
	global _ENABLE_ACQUIRE
	if { $_ENABLE_ACQUIRE == 0 } {
		echo "----------------------------------------------------------------"
		echo "Test Mode acquire disabled. Use 'set ENABLE_ACQUIRE 1' to enable"
		echo "----------------------------------------------------------------"
		error
	}

	# acquire will leave CPU in running state
	# openocd does not expect this
	kitprog3 acquire_psoc

	# we need to re-examine and halt target manually
	${target} arp_examine
	${target} arp_poll
	${target} arp_poll

	# Ensure target has stopped on WFI instruction
	set loops 200
	while { $loops } {
		set sleeping [ expr {[mrw 0xE000EDF0] & 0x00040000} ]
		if { $sleeping } break
		set loops [ expr {$loops - 1} ]
		sleep 10
	}

	if { $sleeping } {
		${target} arp_halt
		${target} arp_waitstate halted 100
		echo "** Device acquired successfully"
		return
	}

	echo "-----------------------------------------------"
	echo "Failed to acquire Traveo-II device in Test Mode"
	echo "-----------------------------------------------"
	error
}

target create ${TARGET}.cm0  cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
${TARGET}.cm0 configure -work-area-phys 0x28000800 -work-area-size 0x8000 -work-area-backup 0
${TARGET}.cm0 cortex_m reset_config sysresetreq
${TARGET}.cm0 configure -event examine-end "display_info traveo22 ${_CHIPNAME}_main0_cm0 ${_CHIPNAME}_work_cm0; enable_cm7x"
${TARGET}.cm0 configure -event reset-deassert-post "catch {reset_deassert_post ${TARGET}.cm0}; enable_cm7x"

target create ${TARGET}.cm70 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
${TARGET}.cm70 configure -work-area-phys 0x28000800 -work-area-size 0x8000 -work-area-backup 0
${TARGET}.cm70 cortex_m reset_config vectreset
${TARGET}.cm70 configure -event reset-deassert-post "catch {reset_deassert_post ${TARGET}.cm70}"

target create ${TARGET}.cm71 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -coreid 2
${TARGET}.cm71 configure -work-area-phys 0x28000800 -work-area-size 0x8000 -work-area-backup 0
${TARGET}.cm71 cortex_m reset_config vectreset
${TARGET}.cm71 configure -event reset-deassert-post "catch {reset_deassert_post ${TARGET}.cm71}"

flash bank ${_CHIPNAME}_main0_cm0       traveo22 0x10000000             0           0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_main1_cm0       traveo22 0x10400000 [ expr {(30 << 16) | 8} ] 0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_work_cm0        traveo22 0x14000000             0           0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_super_cm0       traveo22 0x17000000             0           0 0 ${TARGET}.cm0
flash bank ${_CHIPNAME}_efuse_cm0       traveo22_efuse 0x90700000 1024 1 1 ${TARGET}.cm0 external

flash bank ${_CHIPNAME}_main0_cm70      virtual 0x10000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_main0_cm0
flash bank ${_CHIPNAME}_main1_cm70      virtual 0x10400000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_main1_cm0
flash bank ${_CHIPNAME}_work_cm70       virtual 0x14000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_work_cm0
flash bank ${_CHIPNAME}_super_cm70      virtual 0x17000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_super_cm0
flash bank ${_CHIPNAME}_efuse_cm70      virtual 0x90700000 1024 1 1 ${TARGET}.cm70 ${_CHIPNAME}_efuse_cm0 external

flash bank ${_CHIPNAME}_main0_cm71      virtual 0x10000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_main0_cm0
flash bank ${_CHIPNAME}_main1_cm71      virtual 0x10400000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_main1_cm0
flash bank ${_CHIPNAME}_work_cm71       virtual 0x14000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_work_cm0
flash bank ${_CHIPNAME}_super_cm71      virtual 0x17000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_super_cm0
flash bank ${_CHIPNAME}_efuse_cm71      virtual 0x90700000 1024 1 1 ${TARGET}.cm71 ${_CHIPNAME}_efuse_cm0 external

if { [info exists ENABLE_HYPERFLASH] } {
	set _ENABLE_HYPERFLASH $ENABLE_HYPERFLASH
} else {
	set _ENABLE_HYPERFLASH 0
}

if { $_ENABLE_HYPERFLASH } {
	flash bank ${_CHIPNAME}_hyperflash_cm0	cmsis_flash 0x60000000 0x1000000 4 4 ${TARGET}.cm0 $HYPERFLASH_FLASHLOADER 0x1000
	flash bank ${_CHIPNAME}_hyperflash_cm70 virtual 0x60000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_hyperflash_cm0
	flash bank ${_CHIPNAME}_hyperflash_cm71 virtual 0x60000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_hyperflash_cm0
}

if { [info exists ENABLE_DUALQUADSPI] } {
	set _ENABLE_DUALQUADSPI $ENABLE_DUALQUADSPI
} else {
	set _ENABLE_DUALQUADSPI 0
}

if { $_ENABLE_DUALQUADSPI } {
	flash bank ${_CHIPNAME}_qspi_cm0	cmsis_flash 0x60000000 0x4000000 4 4 ${TARGET}.cm0 $DUALQUADSPI_FLASHLOADER 0x1000
	flash bank ${_CHIPNAME}_qspi_cm70	virtual 0x60000000 0 0 0 ${TARGET}.cm70 ${_CHIPNAME}_qspi_cm0
	flash bank ${_CHIPNAME}_qspi_cm71	virtual 0x60000000 0 0 0 ${TARGET}.cm71 ${_CHIPNAME}_qspi_cm0
}

proc enable_hyperram { {xip_base 0x64000000} } {
	global HYPERRAM_FLASHLOADER
	catch {
		load_image $HYPERRAM_FLASHLOADER 0x28000800
		reg pc 0x28000800
		reg sp 0x28010000
		reg r0 $xip_base
		reg r1 0
		reg r2 3
		resume 0x28000800
		wait_halt
		mrw $xip_base
		echo "** HyperRAM mapped to address [format 0x%08X $xip_base]"
	}
}

targets ${TARGET}.cm0

proc erase_all {} {
	lset banks [flash list]

	for {set i [expr {[llength $banks] - 1}]} { $i >= 0 } { set i [expr {$i - 1}]} {
		set bank [lindex $banks $i]
		if { $bank(name) != "virtual" } {
			flash erase_sector $i 0 last
		}
	}
}