em357.cfg 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677
  1. #
  2. # Target configuration for the Silicon Labs EM357 chips
  3. #
  4. #
  5. # em357 family supports JTAG and SWD transports
  6. #
  7. source [find target/swj-dp.tcl]
  8. if { [info exists CHIPNAME] } {
  9. set _CHIPNAME $CHIPNAME
  10. } else {
  11. set _CHIPNAME em357
  12. }
  13. # Work-area is a space in RAM used for flash programming
  14. # By default use 4kB
  15. if { [info exists WORKAREASIZE] } {
  16. set _WORKAREASIZE $WORKAREASIZE
  17. } else {
  18. set _WORKAREASIZE 0x1000
  19. }
  20. if { [info exists CPUTAPID] } {
  21. set _CPUTAPID $CPUTAPID
  22. } else {
  23. if { [using_jtag] } {
  24. set _CPUTAPID 0x3ba00477
  25. } else {
  26. set _CPUTAPID 0x1ba00477
  27. }
  28. }
  29. if { [info exists BSTAPID] } {
  30. set _BSTAPID $BSTAPID
  31. } else {
  32. set _BSTAPID 0x069a962b
  33. }
  34. if { [info exists CHIPNAME] } {
  35. set _CHIPNAME $CHIPNAME
  36. } else {
  37. set _CHIPNAME em358
  38. }
  39. if { [info exists FLASHSIZE] } {
  40. set _FLASHSIZE $FLASHSIZE
  41. } else {
  42. set _FLASHSIZE 0x30000
  43. }
  44. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  45. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  46. if { [using_jtag] } {
  47. jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
  48. }
  49. set _TARGETNAME $_CHIPNAME.cpu
  50. target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  51. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  52. set _FLASHNAME $_CHIPNAME.flash
  53. flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME
  54. if { ![using_hla]} {
  55. # according to errata, we need to use vectreset rather than sysresetreq to avoid lockup
  56. # There is a bug in the chip, which means that when using external debuggers the chip
  57. # may lock up in certain CPU clock modes. Affected modes are operating the CPU at
  58. # 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC
  59. # oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and
  60. # require a pin reset or power cycle.
  61. #
  62. # for details, refer to:
  63. # http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf
  64. cortex_m reset_config vectreset
  65. }