npcx.cfg 1.4 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # script for Nuvoton NPCX Cortex-M4 Series
  3. # Adapt based on what transport is active.
  4. source [find target/swj-dp.tcl]
  5. # Set Chipname
  6. if { [info exists CHIPNAME] } {
  7. set _CHIPNAME $CHIPNAME
  8. } else {
  9. set _CHIPNAME NPCX_M4
  10. }
  11. # SWD DAP ID of Nuvoton NPCX Cortex-M4.
  12. if { [info exists CPUDAPID ] } {
  13. set _CPUDAPID $CPUDAPID
  14. } else {
  15. set _CPUDAPID 0x4BA00477
  16. }
  17. # Work-area is a space in RAM used for flash programming
  18. # By default use 32kB
  19. if { [info exists WORKAREASIZE] } {
  20. set _WORKAREASIZE $WORKAREASIZE
  21. } else {
  22. set _WORKAREASIZE 0x8000
  23. }
  24. # Debug Adapter Target Settings
  25. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
  26. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  27. set _TARGETNAME $_CHIPNAME.cpu
  28. target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  29. $_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  30. # Initial JTAG/SWD speed
  31. # For safety purposes, set for the lowest cpu clock configuration
  32. # 4MHz / 6 = 666KHz, so use 600KHz for it
  33. adapter speed 600
  34. # For safety purposes, set for the lowest cpu clock configuration
  35. $_TARGETNAME configure -event reset-start {adapter speed 600}
  36. # use sysresetreq to perform a system reset
  37. cortex_m reset_config sysresetreq
  38. # flash configuration
  39. set _FLASHNAME $_CHIPNAME.flash
  40. flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME