pic32mm.cfg 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566
  1. if { [info exists CHIPNAME] } {
  2. set _CHIPNAME $CHIPNAME
  3. } else {
  4. set _CHIPNAME pic32mm
  5. }
  6. if { [info exists ENDIAN] } {
  7. set _ENDIAN $ENDIAN
  8. } else {
  9. set _ENDIAN little
  10. }
  11. if { [info exists CPUTAPID] } {
  12. set _CPUTAPID $CPUTAPID
  13. } else {
  14. set _CPUTAPID 0x3771e053
  15. }
  16. adapter srst delay 100
  17. jtag_ntrst_delay 100
  18. #jtag scan chain
  19. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  20. jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID -expected-id 0x4771e053
  21. set _TARGETNAME $_CHIPNAME.cpu
  22. target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
  23. #We initially set the work area size to the size of RAM of the smallest device. The 'pic32mm find_work_area' command executed during 'reset init' will extend it later.
  24. $_TARGETNAME configure -work-area-phys 0xa0000000 -work-area-size 4096 -work-area-backup 0
  25. $_TARGETNAME configure -event reset-init {
  26. #
  27. # Set system clock to 8Mhz if the default clock configuration is set
  28. #
  29. global _TARGETNAME
  30. set _SYSKEY 0xbf803670
  31. set _OSCCON_CLR 0xbf802684
  32. # SYSKEY register, make sure OSCCON is locked
  33. mww $_SYSKEY 0x0
  34. # SYSKEY register, write unlock sequence
  35. mww $_SYSKEY 0xaa996655
  36. mww $_SYSKEY 0x556699aa
  37. # OSCCON register + 4, clear OSCCON FRCDIV and NOSC bits, configuring the clock to run from FRC divided by 1
  38. mww $_OSCCON_CLR 0x07000700
  39. # SYSKEY register, relock OSCCON
  40. mww $_SYSKEY 0x0
  41. pic32mm find_work_area
  42. }
  43. #This disables the mips_m4k_bulk_write_memory() optimization that does not properly work on PIC32 targets.
  44. $_TARGETNAME mips_m4k disable_bulk_memory_write
  45. set _FLASHNAME $_CHIPNAME.flash0
  46. flash bank $_FLASHNAME pic32mm 0x1fc00000 0 0 0 $_TARGETNAME
  47. # add virtual banks for kseg0 and kseg1
  48. flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  49. flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  50. set _FLASHNAME $_CHIPNAME.flash1
  51. flash bank $_FLASHNAME pic32mm 0x1d000000 0 0 0 $_TARGETNAME
  52. # add virtual banks for kseg0 and kseg1
  53. flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
  54. flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME