vd_aarch64.cfg 1.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0-or-later
  2. # Cadence virtual debug interface
  3. # Arm v8 64b Cortex A
  4. if {![info exists _CORES]} {
  5. set _CORES 1
  6. }
  7. if {![info exists _CHIPNAME]} {
  8. set _CHIPNAME aarch64
  9. }
  10. set _TARGETNAME $_CHIPNAME.cpu
  11. set _CTINAME $_CHIPNAME.cti
  12. set DBGBASE {0x80810000 0x80910000}
  13. set CTIBASE {0x80820000 0x80920000}
  14. dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
  15. $_CHIPNAME.dap apsel 1
  16. for { set _core 0 } { $_core < $_CORES } { incr _core } \
  17. {
  18. cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
  19. set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
  20. -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
  21. if { $_core != 0 } {
  22. # non-boot core examination may fail
  23. set _command "$_command -defer-examine"
  24. set _smp_command "$_smp_command $_TARGETNAME.$_core"
  25. } else {
  26. set _smp_command "target smp $_TARGETNAME.$_core"
  27. }
  28. eval $_command
  29. }
  30. eval $_smp_command
  31. # default target is core 0
  32. targets $_TARGETNAME.0