【增加】版本控制。

Signed-off-by: armink <armink.ztl@gmail.com>

.gitattributes

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+* text=auto
+
+*.S text
+*.asm text
+*.c text
+*.cc text
+*.cpp text
+*.cxx text
+*.h text
+*.htm text
+*.html text
+*.in text
+*.ld text
+*.m4 text
+*.mak text
+*.mk text
+*.py text
+*.rb text
+*.s text
+*.sct text
+*.sh text
+*.txt text
+*.xml text
+SConscript text
+Makefile text
+AUTHORS text
+COPYING text
+
+*.LZO -text
+*.Opt -text
+*.Uv2 -text
+*.ewp -text
+*.eww -text
+*.vcproj -text
+*.bat -text
+*.dos -text
+*.icf -text
+*.inf -text
+*.ini -text
+*.sct -text
+*.xsd -text
+Jamfile -text

.gitignore

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+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+*~
+*.o
+*.obj
+*.bak
+*.dep
+*.lib
+*.a
+*.i
+*.d
+tools/kconfig-frontends/kconfig-mconf
+packages
+cconfig.h
+GPUCache
+
+#cscope files
+cscope.*
+ncscope.*
+
+#ctag files
+tags
+

.travis.yml

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+language: c
+
+notifications:
+  email: false
+
+before_script:
+# travis has changed to 64-bit and we require 32-bit compatibility libraries
+  - sudo apt-get update
+  # clang
+  - "sudo apt-get -qq install gcc-multilib libc6:i386 libgcc1:i386 gcc-4.6-base:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev || true"
+  # - sudo apt-get -qq install gcc-arm-none-eabi
+  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true"
+  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true"
+  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true"
+  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/mips-sde-elf/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true"
+  # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
+  # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
+  - export RTT_ROOT=`pwd`
+  - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
+
+env:
+#  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
+  - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
+#  - RTT_BSP='bf533' # no scons
+  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='es32f0334' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
+#  - RTT_BSP='es32f0654' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
+  - RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt/imxrt1050-evk' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='lpc824' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
+  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc54114-lite' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
+  - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
+  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='m16c62p' # m32c
+  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='microblaze' # no scons
+  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='mini4020' # no scons
+#  - RTT_BSP='nios_ii' # no scons
+  - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='pic32ethernet' # no scons
+  - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='simulator' # x86
+  - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-dofly-M3S' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f469-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
+#  - RTT_BSP='upd70f3454' # iar
+#  - RTT_BSP='x86' # x86
+  - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
+  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
+
+stage: compile
+script:
+  - scons -C bsp/$RTT_BSP

AUTHORS

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+Kernel Design & Implementation
+- Bernard Xiong <bernard.xiong@gmail.com>
+
+LwIP 1.3.0/1.3.1/1.3.2/1.4.0
+- Porting
+  Qiu Yi
+  Mbbill
+- Testing
+  Bernard Xiong
+
+Filesystem
+- Porting and Add Virtual Filesystem
+- Testing
+  Qiu Yi
+  prife
+
+RTGUI
+- Design and Implemenation
+  Bernard Xiong
+  Grissiom
+
+BSP
+Bernard Xiong
+- ATMEL AT91SAM7S64 & AT91SAM7X256 Porting
+- STM32 Porting
+- S3C4510 Porting
+
+Mbbill
+- ATMEL AT91SAM7X256
+
+Xulong Cao
+- QEMU/x86
+
+Aozima
+- LPC 2148 Porting
+- STM32 Porting
+
+Jing Lee
+- LPC 2478 Porting
+
+Qiu Yi
+- S3C2410 & S3C2440 Porting
+- TI LM3S
+
+others...

ChangeLog.md

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+# RT-Thread v3.1.3 Change Log
+
+## Kernel
+
+* Fix the `rt_tick_from_millisecond()` compilation warning issue;
+* Fix the issue that the system object is not detached when handling defunct threads. 
+* Add the value checking of semaphore (the maximum value of semaphore is up to 65535)
+* Add the checking and assertion of re-initialization of object.
+* In the rt_enter_critical/rt_exit_critical function, add the checking of whether scheduler is startup or not.
+* Fix the definition issue of `ENOTSUP` in libc_errno.h.
+* Simplify the rtdbg.h file and use ulog to make log/debug system easier to use.
+* Add the configuration of RT_USING_ARCH_DATA_TYPE, `rt_int8_t/.../rt_uint32_t` and other basic data types can be defined by BSP itself. (It is recommended to put them into the rtconfig_project.h file, so that this file can be automatically included in rtconfig.h when menuconfig generates it.)
+* Add `RT_Device_Class_Sensor` type devices;
+* In the case of single core, the definition of `rt_hw_spin_lock/rt_hw_spin_unlock` is redefined as the disable/enable interrupt.
+* Add the `rt_strnlen()` function in kservice.c.
+* Support the long long type in rt_kprintf (HubertXie);
+
+## Components
+
+* Remove CMSIS and move to software package as CMSIS package.
+* Remove logtrace component. The system log system switches to ulog;
+* Add more code to support AC6 tool chain in some BSP and components;
+* In DFS file system component, clean up the log and fix the mkfs issue when index may be out of range.
+* Split the running mode from sleep mode in power management, and the frequency change should be clearer. Power management is not use idle hook but execute the sleep action in idle thread directly. (How to use power management, please visit programming document for details)
+* Cleanup the log of MMC/SD driver framework;
+* Rewrite Sensor Framework, replace the original C++ implementation with C version, and add some corresponding sensor software packages; To use the sensor packages, please use this release;
+* Add the DMA transmission operation in the serial driver framework;
+* Add the consistency protection to tc_flush routine of serial driver (loogg).
+* Add rt_sfud_flash_find_by_dev_name API in SFUD.
+* When the Pipe device closed, if it is an unnamed Pipe device and the open count is 0, this Pipe device will be deleted.
+* The delayed work implementation is added to workqueue, and the workqueue of the system is added as an option.
+* Fix the data loss issue when using DMA transmission in USB CDC.
+* Change the return type of finsh_getchar to int;
+* Fix the errno issue in newlib/GCC tool chain.
+* Change the management of pthreads to POSIX thread array instead of mapping pthread_t directly to rt_thread_t; Change the fields definition more similar with newlib/glibc in pthreads.
+* Fix the thread name output in ulog.
+* Add loop parameter in utest, then executes test cases repeatedly; Add thread parameter in utest to execute testcase in a new thread.
+* Add delay in handshake phase to protect incomplete data reception in YModem component.
+* Add netdev component, abstract netdev concept, used to management and control network interface device, and provide netdev operation commands, including ping/ifconfig/dns/netstat etc;
+* Modify SAL for netdev, that is, adds the judgment of netdev status and information when the socket creating and data transmitting;
+* Add options and types for UDP multicast traffic handling and IPPROTO_IP in SAL;
+* Fix `itctrol()` function not support to control socketfd issues in SAL;
+* Improve error log processing in AT socket;
+* Fix serial receive data failed issues when AT client initialization is not completed;
+
+## BSP
+
+* Add IMXRT1021-EVK BSP (NXP provides maintenance and support);
+* Add the ETH hardware checksum option in IMXRT1052 ETH driver;
+* Cleanup the LPC 4088 BSP to use main function entry and support menuconfig;
+* The double Frame Buffer mechanism and touch screen driver are added in Godson 1C BSP, then it can better to support Persimmon UI (sundm75).
+* Add watchdog driver in Godson 1C BSP(sundm75);
+* Fix the SysTick interrupt handling issue in nRF52832 and add menuconfig configuration file.
+* Add QSPI and SPI flash driver to Nuvoton M487 BSP (bluebear 233)
+* Change the CPU porting to libcpu/arm/cortex-a folder in QEMU-VExpress A9/IMX6UL BSP;
+* In QEMU-VExpress A9 BSP, the MAC address associated with the local MAC address is used for a unified MAC address in the network.
+* remove stm32f0x, stm32f7-disco, stm32f107, stm32f40x, stm32l072, stm32l475-iot-disco, stm32l476-nucleo BSP (when the new STM32 BSP can completely replace these old BSP, these BSP will be removed);
+* For the new STM32 BSP:
+  * Add CAN driver (ylz0923)
+  * Add CAN driver to stm32f103-fire-arbitrary (ylz0923)
+  * stm32f746-st-disco with LCD, watchdog, SDCard, ethernet, Flash and other drivers (Jinsheng)
+* More board support is added to the new STM32 BSP:
+  * stm32f103-atk-warship V3 ATK Warship V3 (daizhiwang)
+  * STm32f103-dofly-M3S Dofly STM32F103 Development Board
+  * stm32f103-mini-system, the minimum system board for STM32F103 (daizhiwang)
+  * stm32f401-st-nucleo
+  * stm32f405-smdz-breadfruit sanmu electronic stm32405 development board (sunlichao)
+  * stm32f469-st-disco
+  * stm32h743-atk-apollo (whj4674672)
+  * stm32l4r9-st-eval
+  * stm32l053-st-nucleo (sun_shine)
+  * stm32l475-st-discovery
+  * stm32l476-st-nucleo (Vincent-VG)
+  * stm32l496-ali-developer
+* The SCI driver is added to the TMS320F28379D BSP (xuzuoyi).
+* Add W60X Wi-Fi SoC chip BSP from Winner Microelectronics Co.,Ltd. (Winner Micro and RealThread provide maintenance and support);
+* Fix the UART2 IO configuration issue in X1000 UART driver (Zhou Yanjie);
+* Cleanup the libcpu/arm/cortex-a code;
+* The _rt_hw_context_switch_interrupt/_rt_hw_context_switch is separated in TI DSP TMS320F28379D BSP (xuzuoyi);
+
+## Tool
+
+* Add Makefile generation feature in scons with command `scons –target=makefile -s`. Then developer can use make to build RT-Thread under Linux or Windows.
+* Add Eclipse project generation feature in scons with command `scons –target=eclipse -s`, which will put the necessary information in `.cproject` and `.project` files in current BSP folder. The developer can use Eclipse to build RT-Thread.
+* Fix the multi-group same name issue when generating Keil MDK project file and add a library file into the SConscript (Eric Qiang);
+* Fix the GCC Version Comparing issue
+* ENV version updated to v1.1.2
+  * Update scons version to 3.0.5
+  * Fix VC++ warning issue
+  * Fix Unicode error issue
+
+# RT-Thread v3.1.2 Change Log
+
+## Kernel
+
+* nothing
+
+## Components
+
+* When formatting the file system, adds FM_SFD option to create a volume in SFD format for FatFs; (HubretXie)
+* Add file system handle pointer in `struct dfs_fd' structure;
+* Fix stdio fd issue when POSIX api is used; (gbcwbz)
+* Fix the `fd_is_open()` issue: when the sub-path is the same in different mounted filesystem. 
+* Change the critical lock/unlock to dfs_lock/unlock in `getcwd()` function of DFS (the critical lock/unlock is different in SMP environment);
+* Fix the `aio_result` issue, which is returned by `aio_read_work` in AIO; (fullhan)
+* Fix the mmap issue when the addr parameter is NULL; (fullhan)
+* Modify the `_sys_istty` function in armlibc to correctly handle STDIN/STDOUT/STDERR; (gbcwbz)
+* Modify the `_write_r` function in newlib to correctly handle stdout.
+* Fix the at_socket issue when socket is a null pointer; (thomas onegd)
+* Fix the select event issue in `at_recvfrom()` function in at_socket;
+* Divide SAL into `sal_socket_ops/sal_proto_ops` and sal_proto_ops is implemented with gethostbyname/getaddrinfo ops etc.
+* Add socket TLS layer in SAL, that is, upper application can be supported by encrypted transmission without considering lowlevel TLS at all.
+* Fix the length issue of `ulog_strcpy`, which should be not exceed `ULOG_LINE_BUF_SIZE`;
+* Add the macro definition of hexadecimal log output to ulog; (HubretXie)
+* Add uTest component. The uTest is a unit test framework on RT-Thread, and can also be used for automatic testing on board with external Python scripts.
+* Fix some compilation warnings and enumeration mismatches in drivers/audio;
+* Fix the `can_rx/can_tx` issue, which is not cleared to NULL when CAN device is closed in drivers/can; (xeonxu)
+* Fix drivers/hwtimer, time acquisition issue with counting down mode;
+* Add drivers/adc driver framework;
+* Fix the tick compensation issue when enable interrupt too early; (geniusgogo)
+* Add `RT_SERIAL_USING_DMA` option in drivers/serial;
+* Add QSPI support in drivers/spi framework;
+* Add QSPI support in SFUD (based on the QSPI peripheral of stm32); SFUD is upgraded to version 1.1.0;
+* Optimize SPI take/release function call in spi_msd;
+* Fix the `blk_size` issue in `rt_rbb_blk_alloc()`;
+* Fix the FS USB issue in `_get_descriptor` function;
+* Fix the empty password issue in AP mode of drivers/wlan;
+* Fix the return type issue in drivers/wlan;
+* Remove the duplicate opening file check when open a file;
+
+# BSP
+
+* Change the name parameter to `cosnt char *` in `rt_hw_interrupt_install` function; (liruncong)
+* Fix `$` warning issue in Kconfig files of each BSP;
+* Add the LPC54114-lite BSP, including GPIO, I2C, SDCard, SPI, SPI Flash, UART driver;
+* Add Nuvoton-M487 BSP, including UART, EMAC driver; (Bluebear 233)
+* Fix the CAN driver issue in STM32F4XX-HAL BSP; (xeonxu)
+* Fix UART DMA settings issue in STM32F10x/STM32F40x BSP; (zhouchuanfu)
+* Fix the HEAP_BEGIN definition issue in STM32H743-Nucleo BSP; (nongxiaoming)
+* Fix GPIO configuration issue in stm32f10x-HAL; (Wu Han)
+* Change stm32f107 BSP as main function entry; (whj4674672)
+* Fix the serial interrupt handling issue in stm32f10x BSP;
+* Add PWM, RTC and watchdog drivers to stm32f10x-HAL BSP; (XXXXzzzz000)
+* Fix the watchdog driver issue in stm32f4xx-HAL BSP; (XXXXzzzz000)
+* Use lwIP version 2.x in stm32f40x/stm32f107 BSP.
+* Fix the link issue when enable CmBacktrace package in stm32f4xx-HAL BSP; (xeonxu)
+* Support Audio and microphones features in stm32f429-apollo BSP;
+* Enable dlmodule support in x86 BSP; (SASANO Takayoshi)
+* Addd uTest section in the link script of qemu-vexpress-a9/stm32f429-atk-apollo BSP for automatic testing;
+* Change the license to Apache License v2.0 in Godson 1C BSP; (sundm75)
+* Add the new BSP framework for STM32 serial chip, such as STM32 G0/F0/L0/F1/F4/F7/H7. In new BSP framework, the SoC drivers is reused. And in same time, lots of STM32 boards are supportted with new BSP framework:
+  * STM32F091-Nucleo Development Board BSP
+  * STM32F411-Nucleo Development Board BSP
+  * STM32L432-Nucleo Development Board BSP; (sun_shine)
+  * STM32F407-Discovery Development Board BSP
+  * STM32F446-Nucleo Development Board BSP; (andeyqi)
+  * STM32F746-Discovery Development Board BSP; (jinsheng)
+  * STM32F767-Nucleo Development Board BSP; (e31207077)
+  * STM32G071-Nucleo Development Board BSP;
+  * ATK STM32F103 NANO Development Board BSP
+  * ATK STM32F407 Explorer Development Board BSP
+  * ATK STM32F429 Apollo Development Board BSP
+  * ATK STM32F767 Apollo Development Board BSP
+  * ATK STM32L475 Pandora IoT Development Board BSP
+  * Fire STM32F103 Arbitrary Development Board BSP
+  * Fire STM32F429 Challenger Development Board BSP
+  * Fire STM32F767 Challenger Development Board BSP; (Hao Zhu)
+  * ArmFly STM32F429-v6 Development Board BSP
+  * STM32F103 iBox development board BSP; (dingo1688)
+  * Dofly STM32F103 Development Board; (FindYGL)
+  * STM32F107 uC/Eval Development Board BSP; (whj4674672)
+  * and more, there are more developers involved for stm32 BSP framework, they are HubretXie, Hao Zhu, e190, etc. to improve the STM32 public driver.
+* Add SWM320 BSP of Synwit.cn, including GPIO, HW Timer, I2C, Watchdog, PWM, RTC, SPI, UART, etc.; (provided and maintained by Synwit)
+* Add TI TMS320F28379D BSP, the first DSP chip supported on RT-Thread; (xuzhuoyi)
+* Fix USB driver issue in X1000; (Zhou YanJie)
+
+# Tool
+
+* Provide more inforamtion when the tool chain does not exist;
+* Add a draft Segger Embedded Studio project file generation command. Note that the tool chain in SES is a special version not the newlib.
+* Fix the IAR library link command issue when use scons command line under;
+* Fix the BSP path issue in scons `str(Dir('#'))`;
+* Add `scons --pyconfig-silent` command to add some Kconfig configurations and to generate `.config` and `rtconfig.h` files;
+* Update the `scons --dist` command to adapt to the new BSP framework;
+* Modify the mkromfs.py script. Fix the corresponding C code generation When the romfs contains empty files or empty folders;
+* Fix the issue of version string comparison issue for GNU GCC version in utils.py;
+* ENV updated to V1.1.0
+  * Provide better prompt information to improve user experience;
+  * Add `system32` path to environment variables to avoid the `cmd` command cannot be found;
+  * Add `PYTHONHOME` variable to environment variables to avoid PYTHON environment issue;
+
+# RT-Thread v3.1.1 Change Log
+
+## Kernel
+
+* Support the configuration of the upward growth stack which is defined by the `ARCH_CPU_STACK_GROWS_UPWARD` macro. Because there are fewer ARCH for stacks growing upward, this configuration item does not display directly in menuconfig. When a CPU ARCH needs stacks growing upward, the configuration of `ARCH_CPU_STACK_GROWS_UPWARD` can be selected by BSP Kconfig file in default.
+* Support for ARMCC V6 and later compiler (LLVM-based Compiler); currently it's mainly used in Keil MDK IDE. Please notes that the "Warnings" needs to use `Moderate Warnings` in project configuration in C/C++ (AC6) TAB; After using ARMCC v6, RT-Thread will add an additional `CLANG_ARM` macro definition; (liruncong, nongxiaoming, bernard)
+* The `RT_USING_IDLE_HOOK` configuration in Kconfig becomes a separate configuration item, not limited to `RT_USING_HOOK`; (geniusgogo)
+
+## Components
+
+* Improve the PWM driver framework and add more interfaces.
+* Fix the F_SETFL handling in ioctrl function; Fix the return value issue of fcntl function which is always 0 value.
+* Fix the memheap object type issue when creating a ramfs object.
+* Add power management framework for low power applications.
+* Add multi-segment support for read and write operations in MC/SDIO driver framework (for stm32, you can choose a separate stm32_sdio package); (weety)
+* Add ringblk_buf component for the block mode but in ringbuffer applications;
+* Improve WLAN management framework with unified interfaces, management, commands, to provide more friendly support to developers and users;
+* Add the conditional macro in the finsh when the MSH component is not enabled, even if the code files are compiled.
+* Remove gdbstub and move to rt-thread packages.
+* Upgrade and improve SAL and AT components: (linuxhan, eddylin83, slyant, luofanlu, Hubert Xie, Lawlieta, zhaojuntao, armink)
+  * Fix the none cleared issue when closing socket in SAL, which lead to the socket is always holding.
+  * Fix the `select()` issue for UDP communication in AT component. Add the receiving data handling to complete the clearing of received event;
+  * Add the errno value when receive data timeout in at_recvfrom function in the AT component.
+  * Add the receive data timeout handling in at_client_recv function in the AT component.
+* Fix a possible issue in fputc function implementation when using microlib;
+* Add gmtime_r implementation for ARMCC, IAR tool chain;
+* Improve time function support in IAR and support 64bit time; (hichard)
+* DHCPD's support for IPv6;
+* Remove lwIP-1.3.2 porting and add lwIP-2.1.0 porting; lwIP-2.0.2 is still the default version.
+* Add a lightweight ulog component and automatically replace the debug macro of the original rtdbg.h when it's enable.
+* USB stack update
+  * HOST, optimize the USB HOST timeout mechanism; fix the un-alignment visit issue in F4xx-HAL USB host driver;
+  * Device: Add the check when class drivers are illegally registered; Fix the un-aligned access issue in some platforms; optimize CDC VCOM classes, add the timeout mechanism and ID definition.
+
+## BSP
+
+* Upgrade the wlan adaptor to the new version of Wi-Fi management framework in amebaz BSP.
+* Add airkiss wifi configuration code to amebaz BSP.
+* Update Apollo2 BSP with ADC, GPIO, I2C, PDM, SPI, UART and other drivers; (Haleyl)
+* BeagleBone BSP is changed to main function mode, and adds Kconfig configuration file.
+* DM365 BSP adds Kconfig configuration file;
+* Update HiFive1 BSP and add more documentation.
+* Update imx6sx BSP to main function mode, and add Kconfig configuration file.
+* Change the old imxrt1052-evk BSP. The imxrt1052-related BSPs are classified into the `bsp/imxrt` directory; A touch framework is added to `bsp/imxrt`, and later will be moved into `components/drivers` directory;
+* Improve stm32f4xx-HAL BSP with PWM, I2C, USB Host driver; (XuanZe, xuzhuoyi)
+* Improve stm32f10x BSP with CAN driver and increase I2C driver; (wuhanstudio, AubrCool)
+* Improve stm32f10x-HAL BSP with I2C, IWG, PWM, RTC and other drivers, improve UART driver; (XuanZe)
+* Improve stm32f429-disco BSP and add I2C, LCD, Touch driver; (xuzhuoyi)
+* Improve x86 BSP, support dlmodule function; (SASANO Takayoshi, parai)
+
+## Tool
+
+* Modify the building script to support Python 3; <Python 3 patches have been submitted to scons and need to wait for next scons release，maybe scons-3.0.2> (Arda)
+* Add `scons --pyconfig` mode, which has a TK UI configurator; (weety)
+* Support for GNU GCC 7/8 version toolchains (The `-std=c99` is not added into C-compiler flags), but please note: PThreads component failed in 2.5 and new version of newlib.
+
+# RT-Thread 3.1.0 Change Log
+
+## Kernel
+
+* The main thread priority can be configured by Kconfig;
+* Add the checking of kernel object type, which can effectively avoid the problem of continuing to use kernel objects after they are destroyed.
+* Add the idle hook list to mount multiple idle hook, and can be configured by Kconfig.
+* Add the device_ops operation set to reduce the footprint of device object.
+* Remove the special memory operation in application module when using SLAB memory management algorithm.
+* Move application module from the kernel to `libc/libdl`.
+* Enhance the debug information output of `rtdbg.h` file.
+* In Keil/IAR tool chain, the `RT_USED` is used to keep symbols and avoid to add more argument or section in link phrase.
+
+## Components
+
+* Remove all of external codes, which will be moved to packages in the future.
+* Add initialization flag for shell, file system, network protocol stack etc to prevent repeated initialization;
+* Enable the long file name feature of ELM FatFs in default.
+* Change DFS FD to dynamic allocation mode. The maximum number of allocation is still DFS_FD_MAX.
+* Add dfs_fdtable_get() function to get different fdtable;
+* Add more DFS error messages, and provide easy to understand log when abnormal.
+* Fix the disk format issue of FatFs file system when multiple FatFs file systems are mounted.
+* Remove the folder enter feature in msh when input a folder name;
+* Add `int finsh_set_prompt (const char * prompt);` routine for setting a custom prompt for msh;
+* Add the VBUS configuration in Kconfig.
+* Move the application module from kernel to `libc/libdl` component;
+* Rewrite most of the management code for application module: replace the original object container with the object list; split the symbol resolution code into different processor architecture etc.
+* Update the application module chapter in the programming guide, and change it into dynamic module chapter.
+* Overwrite the exit() function of newlib to take over the processing of exit for a dlmodule.
+* Add SAL (Socket Abstraction Layer) component for adapting different protocol stacks and network implementations, and update the relevant sections of the programming guide;
+* Add AT component, including AT client, AT server and AT Socket function;
+* Remove the poll/select API of DFS_NET and move them to SAL component.
+* Remove the strong dependence of lwIP component for DFS_NET and replace it with Kconfig configuration in SAL.
+* Add the DHCP server function with lwIP raw API;
+* Fix the wait queue none-initialization issue in socket allocation of lwIP.
+* When a thread is about to block on a wait queue, fix the wake up issue for `rt_wqueue_wakeup' is executed to wake up that thread;
+* Add the PWM driver framework;
+* Fix the sdio_irq_wakeup release issue in the MMC/SD framework.
+* Fix the problem of DMA handling in the serial driver framework.
+* Update SFUD to v1.0.6 version;
+
+## BSP
+
+* Fix the SP issue when hard fault occurs for ARM Cortex-M arch;
+* Add C-Sky CK802 architecture porting;
+* Add Realtek amebaz WiFi SOC (rtl8710bn) BSP;
+* Update imxrt1052-evk firmware SDK to support B model chip.
+* Fix the copying packets issue in the Godson 1C BSP when sending message.
+* The Nuvoton m05x/m451 BSP are changed into the main() entry mode, and supports GCC compilation;
+* Fix the inconsistency issue between touch range and LCD resolution in qemu-vexpress-a9.
+* Add qemu-vexpress-gemini BSP for dual core A9 (RT-Thread + Linux) arch;
+* Add the basic porting for Raspberry Pi 2B ;
+* Add CAN and PWM drivers in stm32f4xx-HAL BSP;
+* Optimize the GPIO driver in stm32f4xx-HAL BSP;
+* Add UART3 driver in stm32f4xx-HAL BSP;
+* Fix the I2C1 driver clock in stm32f10x BSP and WDG control interface.
+* Add rt_hw_us_delay interface in stm32f10x-HAL BSP;
+* Optimize the GPIO driver in stm32f10x-HAL BSP;
+* Add GPIO driver and RTC driver in stm32f107 BSP;
+
+## Tool
+
+* ENV update to v1.0.0 final version.
+* ENV added the China mirror for software package, which can speed up the software package download, update  etc.
+* Fix the ENV known bugs and enhance the interaction with users.
+* Add building script to detect the version of GCC & newlib;
+* Add building script to detect the version of armcc;
+* Add `scons --dist` function to make distribution for a BSP.
+* Add `scons - dist - strip' function to make a minimal files of distribution for a BSP.
+* Add `ASFLAGS/LOCAL_ASFLAGS' parameters for defined a group and pass them to assembler;
+* Fix some errors in building script under the Linux environment.
+* Add the C-Sky CDK IDE project generation.
+* Add `scons --target=vsc -s` to generate friendly configuration files for VSCode;
+
+# RT-Thread 3.0.4 Change Log
+
+## Kernel
+
+* Change the location of hook invoking in rt_event_send, which can better reflect the event value to the system view.
+* Fix the rt_realloc() issue in memheap;
+* Fix the vstart_addr issue in the dynamic library.
+* Ensure that signal is more standardized and remove si_errno members from siginfo_t;
+* Add rt_thread_mdelay() API for millisecond delay in thread.
+
+## Components
+
+* Fix the DFS mkfs issue of FatFs (which is a merge issue introduced in RT-Thread V3.0 upgrade).
+* Fix dfs_net poll issue, if there is already received data, the upper layer can not wake up and deal with data.
+* Fix the socket issue in dfs_net if lwip_socket failed(Bluebear233);
+* If the dfs_net/socket feature is used within lwIP 1.x version, a compiler error will be returned.
+* Fix the DFS df() information issue;
+* Fix the audio device write issue while the interrupt is not properly recovered.
+* Fix the one-shot timeout issue in the hardware timer driver framework.
+* In ENC28J60 driver, the "link change interrupt" is enable in initialization.
+* Fix the data issue in put data into ringbuffer.
+* Add UDP information display in netstat command;
+* Fix the USB HS issue when sending 1 bytes of data will cause two times of transmission.
+* Change the registration mechanism of USB Class Driver and Class Driver can be registered in package.
+* Add USB Device driver framework for HS USB.
+* Enhance the compatibility of time() function for different compilers;
+* Add more configuration items for DHCPD in menuconfig.
+
+## BSP
+
+* Temporarily remove the Andes AE210P transplant because of the mistakenly use SVC for context switching.
+* Add SD/MMC drive in Allwinner ARM9 BSP;
+* Add SPI and SPI Flash drivers to Allwinner ARM9 BSP.
+* Add GD32's gd32303e-eval development board support;
+* gd32450z-eval supports GNU GCC compilation;
+* Rewriting the hifive1 board level support package for the risc-v architecture;
+* About i.MX RT1052, we have completed various development board support: ATK, Fire, seeed studio;
+* On i.MX RT1052, add the cache-ops functions;
+* On i.MX RT1052, add I2S driver and WM8960 codec driver support;
+* Improve ETH driver support (including support for Fire development board) on i.MX RT1052.
+* Add Hardware Timer driver support on i.MX RT1052.
+* On i.MX RT1052, add GPIO driver;
+* On i.MX RT1052, add RTC driver;
+* On i.MX RT1052, improve SD/MMC driver;
+* On i.MX RT1052, add SPI driver and SPI Flash driver (connect to SFUD component);
+* Add USB Device driver on i.MX RT1052.
+* Add README files and KConfig files in LPC408x BSP;
+* Add README documents in LPC5460x-LPCXpresso BSP;
+* Add the display controller driver (Sundm75) in Godson 1C BSP.
+* Add CAN driver in Loongson 1C BSP(Sundm75);
+* In GPIO driver of Loongson 1C BSP, add (external) interrupt feature (Zhuangwei);
+* Use SPI automatic initialization in Loongson 1C BSP.
+* Add I2C driver in Loongson1C BSP(Sundm75);
+* Add resistive touch screen driver in Loongson 1C BSP(Sundm75);
+* In Loongson 1C BSP, the components initiliazation and main function is enable(Zhuangwei).
+* Add self bootup in Loongson1C BSP (Zhuangwei);
+* Add README files and KConfig files to Loongson 1C BSP(Zhuangwei).
+* Fix the rx descriptor issue in init_rx_desc function in NUC472 BSP (Bluebear233);
+* Add AC97 Audio driver in QEMU-VExpress-A9 BSP;
+* Add README description file in QEMU-VExpress-A9;
+* Add I2C driver in stm32f4xx-HAL BSP, and README description file;
+* Add cache-ops in stm32f7-disco BSP, and README description file;
+* Add README description file in stm32f10x/stm32f10x-HAL;
+* Add README specification files and KConfig configuration files in stm32f40x BSP;
+* Add KConfig configuration file in stm32f20x BSP;
+* Add README description file to stm32f411-nucleo BSP and enable GNU GCC tool chain support;
+* Add GPIO driver and README description file in stm32f429-apollo BSP;
+* Add KConfig configuration files in stm32f429-armfly BSP;
+* Add README description file in stm32l476-nucleo BSP;
+* Because V2M-MPS2 does not support in 32-bit machine simulation operation, temporarily remove this BSP.
+* Add README description file and some firmware file, such as u-boot.bin, wifi firmware etc, in X1000 BSP;
+Tools
+* Add detection feature for the version of GNU GCC tool chain and libc function feature.
+* Add the function of VSCode editor assistance, and support scons --target=vsc -s under BSP folder to generate configuration files for VSCode.
+* Add the detection of verson of IAR;
+* Add the ProjectInfo (Env) function to get information about target: all source files should be compiled, all header files, all macro definitions, the search paths for header file etc.
+
+# RT-Thread 3.0.3 Change Log
+
+## Kernel
+
+* Add scheduler protection when do cleanup for a detached thread;
+* Fix the object_find issue when enable module feature;
+* Improve POSIX signal support and add rt_signal_wait function and POSIX sigwait interface;
+* When enable finsh shell, rtthread.h header file includes the API file of finsh. Therefore, the application code can use command export feature without finsh.h file;
+* Improve the comments of rtdbg.h file. In RT-Thread, just use following code to add debug log feature:
+
+```c
+    #define DBG_ENABLE
+
+    #define DBG_SECTION_NAME    "[ MOD]"
+    #define DBG_LEVEL           DBG_INFO
+    #define DBG_COLOR
+    #include <rtdbg.h>
+```
+
+When close the DBG_ENABLE definition, the debug log will be closed. Otherwise, the `dbg_log(level, fmt, ...)` can be used to print debug information. 
+
+DBG_SECTION_NAME - The prefix information for each log line;
+DBG_LEVEL - The debug log level;
+DBG_COLOR - Whether use color log in console.
+
+## Components
+
+* Fix the flag issue of fopen in GNU GCC;
+* Fix the pthread_detach issue when used for a detached pthread;
+* Fix the _TIMESPEC_DEFINED issue in IAR 8;
+* Add libc_stdio_get_console() interface for returns the fd of console;
+* Move UI engine component as a standalone package;
+* Add a unify TF/SD card driver on SPI device bus;
+* Add soft-RTC device, therefore device can synchronize with network time and maintains the time with OS tick later;
+* Change the open/fcntl/ioctl API to POSIX standard  interface;
+* Fix ramfs issue when update with RTT 3.0.x;
+* Fix the elm fatfs umount issue; (liu2guang)
+* ignore the O_CREAT flag when open a device file;
+* Improve VCOM class driver in USB stack; (ChunfengMu, Aubr.Cool)
+
+## BSP
+
+* Fix the potential issue when enable Cortex-M hardware FPU;
+* Add v2m-mps2 bsp, which is used in Keil MDK5 for Cortex-M4/M7/M23/M33 simulation;
+* Add sdcard driver for stm32f10x-HAL;(liu2guang)
+* Improve GNU GCC support for stm32f10x-HAL;(Xeon Xu)
+* simulator bsp can be used in Windows/Visual C++ and update SDL to v2.0.7;
+* Add gk7102 bsp by gokemicro;(gokemicro)
+* Add allwinner F1C100s ARM9 bsp;(uestczyh222)
+* Fix some issues in peripherals drive library of NXP LPC54608/i.MX RT; (Valeriy Van)
+
+## Tools
+
+* scons building script will automatically add `_REENT_SMALL` macro when enable newlib nanao;
+* Modify building script for Python 3.x and scons 3.0
+
+# RT-Thread v3.0.2 Change log
+
+## Platform
+
+* Make sure the Object_Class to a fixed value
+* Add `rt_device_create/destroy` API
+* Add memory trace for small memory management algorithm for memory leak and overwritten.
+* Add a first version of asynchronous I/O API
+* Add cputime for high resolution counter
+* Add pipe device functions in DeviceDrivers
+* USB Host available in stm32f4 with mass storage class
+* Add 'df' command in msh
+* Update UI engine and add an example
+* Split `clock_time` from pthreads and add a new clock id: `CLOCK_CPUTIME_ID`
+* Enable IPv6 in lwIP 2.0.2 version
+* Add memlog in logtrace
+* Fix closesocket issue in dfs_net
+* Fix IPv6 issue in NFS
+* Update JFFS2 file system with new DFS API
+* Fix the issue of stat "/.." of lwext4 (parai)
+* Fix the fs type search issue in mkfs
+* Fix the select issue in dfs_net
+
+## Tools
+
+* scons: add '--useconfig' command to use an exist config file
+* scons: force to use g++ for link when enable `RT_USING_CPLUSPLUS` in GNU GCC configuration
+* Enable package feature in Linux/MacOS host
+
+## BSP
+
+* Add NUC472 bsp (bluebear)
+* Update SD/MMC driver for qemu-vexpress-A9
+* Add keyboard/mouse driver for qemu-vexpress-a9
+* Add ADC/I2C/Flash/PWM/RTC/smbus/SPI driver for apollo2 (Haleyl)
+* Add I2C/LCD/Touch driver for i.MXRT1052-EVK
+* Update SD/MMC driver for mini2440 (kuangdazzidd)
+* Update simulator to adapt VC++ compiler
+* Add USB host driver in stm32f4xx-HAL (uestczyh222)
+* Update EMAC driver for IPv6 in stm32f40x/stm32f107
+* Add stm32h743-nucleo bsp (polariss)
+
+# RT-Thread v3.0.1 Change log
+
+## Platform:
+
+* Add mmap()/munmap() API for POSIX compatibility.
+* Fix the filesystem_operation_table issue.
+* Enhance USB stack for USB slave (HID/ECM/RNDIS/WINUSB or composite device);
+* Enhance USB stack for USB host (HID/MSC etc);
+* Fix memory leak issue when close a pipe.  
+* Fix the romfs open issue;
+* Add SoftAP device in Wi-Fi framework;
+* Re-order the lwIP/ETH initialization;
+* Add IPv6 options in Kconfig;
+* Fix the module_id issue in _rt_thread_init;
+
+## Tools:
+
+* Add menuconfig for Linux/Mac platform: use `scons --memuconfig` to enable it;
+* Add LIBS feature for IAR project;
+
+## BSP:
+
+* Enhance LPC54608 BSP for kinds of compiler;
+* Add GPIO/I2C/SPI driver for Loongson 1C;
+* Add csd cmd in sdcard driver of mini2440;
+* Add SDIO/EMAC driver for qemu-vexpress-a9 bsp;
+* Enable VC++ to compile simulator bsp;
+* Add stm32f4xx-HAL bsp for kinds of STM32F4 series <User can use menuconfig to select chip>;
+* Fix the PHY reset in stm32f429-apollo bsp;
+* Add Audio/MMC/SLCD/Touch/USB slave/RTC/SPI/SFC Flash driver in Ingenic X1000 bsp;
+
+# RT-Thread v3.0.0 Change log
+## Platform:
+
+* Add more POSIX features, for example poll/select, signal, termios etc.
+* Add waitqueue for poll feature.
+* Use fops for file operation. There are two ways to visit device object: rt_device_* API, the file API(open/read/write/close etc).
+* Change the type of cmd from uint8_t to int in control interface.
+* Add more C++ object for RT-Thread Kernel Object.
+* Add wlan driver framework for wlan device operation.
+* Integrate SFUD into RT-Thread to unify the operations of spi flash.
+* Update lwIP to v2.0.2 version.
+
+## Tools:
+
+* Enable packages, with ENV tool.
+* menuconfig & Kconfig.
+* Add scons --dist for make a distribution for specified BSP.
+
+## BSP:
+
+* more MCU porting.
+
+## IoT:
+
+* put more IoT components as packages, for example, MQTT, CoAP, HTTP, TLS etc.
+
+# RT-Thread v2.1.0 Change log
+
+This release is the final release for RT-Thread v2.1.0 branch. This release has been delayed many time. After committed fh8620 and x1000 bsp, we are proud to announce this branch release of the official version.
+
+The change log since last stable version:
+
+## Kernel:
+
+* Move the init component to the kernel.
+* Fix the device open flag issue.
+* Add assertion hook.
+* Better application module support.
+* Does not lock scheduler when invoking soft-timer timeout function.
+
+## Board Support Package:
+
+* fh8620, which is provided by Shanghai Fullhan Microelectronics Co., Ltd. It's a IP camera chip with ARM1176, 300MHz, 16KB I-Cache and 16kB D-Cache.
+* x1000 bsp. The CPU is a XBurst CPU 1.0GHz, MIPS-based, from Ingenic Semiconductor Co.,Ltd.
+* imx6sx bsp, only the Cortex-A9 core porting in the NXP i.MX6 solox. BTW, another full Kinetis series porting was created in rt-thread_fsl, which is maintained by NXP employee.
+* lpc5410x bsp, only the Cortex-M4 core porting.
+* ls1cdev bsp for Loogson1C board.
+* dm365 bsp.
+* nRF51822/nRF52832 bsp.
+* stm32f7-disco bsp, the first ARM Cortex-M7 porting in RT-Thread.
+* stm32f411-nucleo bsp.
+* Add IAR compiler support in beaglebone bsp.
+
+## Components:
+
+* Add more socket fd operators in DFS with a virtual lwIP file system ops.
+* Add CAN/Hardware Timer device drivers.
+* Fix the SDIO issue to support sdio wifi device.
+* Add eMMC support in SD/MMC device drivers;
+* Fix the NAT configured enter reset issue in lwIP NAT.
+* RTGUI come back, but as a UI engine for blend point/line/rect and bitmap etc.
+* Add nanopb porting, a small code-size Protocol Buffers implementation;
+* Add paho-mqtt porting, the Eclipse Paho MQTT C/C++ client for Embedded platforms;
+* Update freetype to 2.5.4 version.
+* Enhance msh for file operations.
+* Split the exported commands of finsh shell to a standalone section: ".rodata.name"
+
+# RT-Thread v2.1.0 beta版本更改说明
+
+## BSP部分
+
+* BeagleBone加入GPIO驱动；
+* 京微雅格M7，更新驱动库并改进EMAC驱动程序；
+* 新加入dm365移植（包括EMAC、GPIO、I2C、MMC/SD、SPI等驱动）；
+* LPC4088加入EMC、硬件定时器、CAN驱动；
+* 新加入龙芯1C，智龙v2开发板移植（包括多串口驱动）；
+* 更改mini2440移植为applications/drivers等的目录方式；
+* 更新simulator在MS VC++上的移植，处理好初始化代码工作，完善UART控制台驱动；
+* 新加入stm32f7-disco移植；
+* 在stm32f10x中新加入CAN驱动及应用代码示例；
+* 在stm32f40x中加入硬件定时器驱动，RTC驱动；
+* 调整stm32f107为新的串口驱动框架；
+
+## 组件
+
+* DFS的struct stat定义中移除st_blksize成员（可以兼容于VC++中的stat定义）；
+* 修正DFS中select实现的问题；
+* 修正DFS中文件操作出错、关闭时的fd处理问题；
+* 修正DFS中mkdir和lseek出错时的fd处理问题；
+* 修正lwIP中SYS_ARCH_PROTECT/SYS_ARCH_UNPROTECT保护的问题；
+* 增加CAN驱动框架；
+* 增加硬件定时器驱动框架；
+* SD/MMC驱动框架中增加eMMC支持；
+* 修正注册SDIO驱动时驱动关联的问题；
+* 修正串口驱动框架DMA发送时激活标志的问题；
+* SPI Flash驱动中加入对GD25Q spi flash芯片支持；
+* 增加paho-mqtt组件移植；
+* 增加msh的脚本执行能力，可以在msh下执行*.sh脚本；
+* 增加msh下的mkfs命令；
+* 修正在Linux Telnet下使用finsh shell回车符处理的问题；
+* 增加应用模块在使用armcc、gnu gcc编译器时的libc符号导出；
+* 在以太网网卡驱动框架中增加ETHIF_LINK_AUTOUP/PHYUP参数用于指定初始时的链路Up/Down状态；
+* 在组件初始化中导出log_trace组件；
+
+## 内核
+
+* 更改UNUSED/USED等更改成RT_UNUSED/RT_USED；
+* 链接时增加.rodata.name section，当空间资源受限时可以把它放到性能低的内存区域；
+* 完善IAR编译器下的组件自动初始化；
+* 增加rt_assert_hook，在触发断言时可以执行这个钩子函数；
+* 修正应用模块分散加载情况下的问题；
+
+## 工具
+
+* scons中定义Group时加入了本Group内的编译参数定义；
+* 修正了如果Group中即包含代码，也包含二进制库时，生成的Keil MDK工程文件有两个重名Group的问题；
+
+版本: RT-Threadv2.0.1及v2.1.0 alpha
+
+RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前开发主干的一个技术预览版本，它给出了v2.1.0这个版本系列的技术预览情况，不建议用于实际产品中，因为它可能存在大量的一些bug。
+
+# RT-Thread v2.0.1更改说明
+
+*  IAR用的dlib，加入THREAD_SUPPORT 和 FILE_DESCRIPTOR的支持；
+*  修正finsh中echo回显模式的问题；
+*  修正USB host代码的编译错误；
+*  修正sensor框架回调函数的问题；
+*  修正pin设备注册时的设备名称问题；
+
+而v2.1.0 alpha这个技术预览版则沿着最初设定的roadmap技术路线进行，这其中主要包括：
+
+*  lwip更深度的集成：把它集成到RT-Thread的文件系统接口中，这样Linux/Unix下的一些socket网络应用能够更顺利的移植到RT-Thread上，也为以后可以应用到更多地方的select接口铺路。
+
+*  这部分是和RT-Thread发布本身无关，但也是这个版本系列设定的目标之一：开启一个云端集成开发环境的时代！云端会是什么样的，请用现代化的浏览器打开[CloudIDE](http://lab.rt-thread.org/cloudide/simulator/index.html)
+
+# RT-Thread 2.0.0正式版更改说明
+
+经历了大约1年的时间，RT-Thread v2.0.0的最终版本终于发布出来了。自这个版本开发以来，引入了多项功能、修改、增强等。感谢参与的诸位开发人员！
+以下是自v2.0.0 RC版本以来的详细更改记录。后续我还会给出v2.0.0版本自v1.2.x版本的主要不同、看点，以及给出下一个版本的roadmap规划。
+
+## 内核
+
+*  console以RT_DEVICE_FLAG_STREAM参数打开字符设备；
+*  在rt_memheap_free中加入更多的断言检查；
+
+## 组件
+
+*  更新RW009驱动以支持Wi-Fi SoftAP模式（aozima）；
+*  修正sensor框架的一些问题，并加入C API接口（睿赛德服务公司提供）；
+*  加入MPU6050 sensor的代码（bernard, Coing）；
+*  加入BMI055 sensor的代码（Coing）；
+*  当未使能heap时，修正finsh/msh中list_memheap的问题；
+*  修正LIBC编译的警告；
+*  加入IAR dlib相关的移植，使得应用能够使用标准的API接口；
+*  修正YMode握手时可能引起的竞争问题（grissiom）；
+*  更新FreeType版本到2.5.4
+*  单独把C++的全局对象初始化放到cplusplus_system_init函数中，并在初始化线程中调用；
+*  finsh中以RT_DEVICE_FLAG_STREAM参数打开字符设备；
+*  添加VBUS组件用于Linux与RT-Thread系统之间，RT-Thread与RT-Thread系统之间通信（睿赛德服务公司捐赠）；
+*  增加lwIP/NAT组件，可以做多个网口间的地址转换（Hicard）；
+*  增加lwIP/DHCP服务端，用于向客户端分配IP地址（睿赛德服务公司提供）；
+
+## BSP
+
+*  修正LPC4357串口驱动初始化时过早打开中断的问题（nongxiaoming）；
+*  重写LPC4357串口驱动，并让芯片上M4/M0核心分别都执行RT-Thread系统，两核心之间以VBUS组件进行系统间通信（睿赛德服务公司捐赠）；
+*  新增RX移植（limxuzheng）；
+*  新增NuMicro M051 Series移植，支持GCC、Keil MDK编译器（bright-pan）；
+*  新增LPC54102移植（Coing）；
+*  移除STM32F4 BSP中不需要的RT_TIMER_TICK_PER_SECOND配置（pangweishen）；
+*  在Linux Clang编译分析中，强制以32位模式进行编译（grissiom）；
+*  修正STM32F103中串口驱动中断过早打开的问题（armink）；
+
+## 工具
+
+*  增加scons中的MD5支持（bright-pan）；
+
+# RT-Thread 2.0.0 RC 更改说明
+
+发布时间:2014/11/4
+
+随着RT-Thread功能越来越多，如何发布版本也成为一件头疼的事情，因为需要仔细对比最近三个月来的修改记录。这次的发布距离上一次beta版本依然是三个月的时间，但按照发布计划已然推迟了一个月进行发布。 
+
+在这三个月中，开源社区上也发生了很多有趣的事情：
+
+阿嘉的使用RT-Thread的四轴飞行器毕业设计惊艳亮相，采用了1个STM32F4 + 8个STM32F1进行飞行控制，总计9个MCU的另类实现方式；沿循四轴飞行器的路线，与国内匿名团队合作，采用RW009 Wi-Fi控制的迷你四轴飞行器也在稳步推进过程中。
+
+RT-Thread做为一个开源组织参与的CSDN开源夏令营结出了丰硕的果实：
+由hduffddybz参与的IPv6协议栈移植（最新版本的lwIP-head版本移植）在这次发布中已经包括进来，从而能够在使用RT-Thread的小型设备上实现TCP/IP v4/v6双栈的支持；
+由wzyy2参与的GDB stub实现，也完美的支持BeagleBoneBlack开发板和STM32F4平台；
+CSDN开源夏令营其他的成果，例如bluedroid移植也有了初步的成果，希望能够在后续的版本（可能会是2.1.0系列版本？）包含进来。CSDN开源夏令营是一次非常棒的活动，能够让学生提前进入实战，了解软件开发的初步知识。对开源社区来说，也是一次非常有益的社区互动活动。希望明年这个活动可以继续，关注RT-Thread、嵌入式开发的同学可以关注明年的动向。
+
+当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相应的做出了积极的响应，所以这个版本开始加入sensor的应用框架（APP/算法 <--> sensor framework <--> RT-Thread device driver <--> 硬件外设）。希望在小型化的RT-Thread操作系统基础上融合智能化相关的技术，让RT-Thread成为这方面可选的OS系统之一。RT-Thread操作系统的sensor框架也尝试新的实现方式，即采用C++的方式来实现（当然也会考虑C方面的兼容，无疑C++的面向对象特性会更好，所以最终选择了C++），在这个基础上也可能融合其他的一些生态技术，例如ARM mbed平台上的一些社区组件技术。所以这个发布版本中既包括sensor框架，也包括了C++底层的一些基础支撑。
+
+这个版本是RT-Thread 2.0.0系列正式版本的候选版本，正式版本预计会在年底正式发布，距离正式版本还会加入更完善的一些支撑（例如各种传感器驱动）。也计划2014年11月22日，在上海浦东举行RT-Thread嵌入式系统沙龙活动，欢迎大家关注并参与进行RT-Thread方方面面的技术交流。
+
+以下是这个版本的更改记录:
+
+## 内核
+
+* 修正当采用高级别优化编译时，idle任务中查询是否有僵尸线程的潜在bug；
+
+* 修正memory pool中的竞争问题；
+
+* 在console中打开设备时，加入流标志进行打开；
+
+## 组件
+
+* 加入C++基础支撑组件。C++组件依赖于RT_USING_LIBC库，当使用GCC编译器时请注意查看其中的说明文档并更改ld script；
+* 修正DFS中NFS打开目录的bug；
+* 更改DFS ROMFS默认romfs_root为弱化符号；
+* 添加DFS中dfs_file_lseek接口中关于fs的检查；
+* 移除I2C core中无用的core lock锁；
+* 添加sensor framework（采用C++的方式支持各种sensor）；
+* 修正serial框架中DMA发送的bug（heyuanjie87）；
+* 移除SPI框架中不必要的device初始化代码；
+* 完善SPI Wi-Fi网卡RW009驱动并提供RSSI相关的命令；
+* 修正MSH中未定义DFS_USING_WORKDIR时更改当前目录的bug；
+* 修正MSH中未定义RT_LWIP_TCP时依然定义了netstat命令的bug；
+* 修正MSH中未定义RT_USING_HEAP时依然定义了free命令的bug；
+* 修正finsh中FINSH_USING_HISTORY相关的裁剪；
+* 加入gdb stub组件，当前支持ARM Cortex-A8和Cortex-M3/4（wzyy2）；
+* 统一不同编译器下使用LIBC的宏为RT_USING_LIBC，原有的宏定义RT_USING_NEWLIB/RT_USING_ARM_LIBC需要从rtconfig.h中移除，并替换成RT_USING_LIBC；
+* 加入最新的lwIP分支：lwip-head，以提供IPv4/v6双栈的功能（hduffddybz）；
+* YMode中打开串口设备时，添加open flag（armink）；
+
+## bsp
+
+* 加入北京京微雅格的M7（华山）低功耗FPGA的ARM Cortex-M3移植（aozima）；
+* 加入北京京微雅格的M7 EMAC以太网驱动（aozima）；
+* AT91SAM9260分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
+* BeagleBoneBlack分支中加入gdb stub支持（wzyy2）；
+* LPC176x分支中加入C++支持；
+* LPC176x分支中修正SD卡驱动返回卡信息的bug；
+* 修正LPC408x分支中GCC编译时的问题；
+* LPC408x分支中加入C++支持；
+* 龙芯1B分支中加入UART3驱动；
+* 加入飞索半导体的MB9BF568 FM4分支移植（yangfasheng）；
+* mini2440分支中更改RT_USING_NEWLIB为 RT_USING_LIBC；
+* stm32f0x分支中移除不同编译器下的LIBC定义，统一更改为RT_USING_LIBC；
+* stm32f0x分支中加入串口接收溢出中断处理（armink）；
+* stm32f40x分支中加入gdb stub支持并添加UART6驱动（wzzy2）；
+* zynq7000分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
+* 加入ARM Cortex-M4芯片指令级的ffs实现；
+* 修正MB0BF618S分支中缺少timer初始化的bug（mike mao）；
+
+## 工具
+
+* 移除Python 2.6中未支持的语法（xfguo）；
+* 移除Windows平台中的startupinfo信息（对Python版本兼容性更好）；
+* 修正CPPPATH被打乱的bug；
+
+# RT-Thread 2.0.0 Beta更改说明
+
+发布时间:2014/8/1
+
+v2.0.0这个版本系列是RT-Thread当前的开发分支，如果要上新项目，建议使用这个版本来进行，预计这个版本的正式版会在年底发布。欢迎对这个版本进行测试、并反馈问题，能够早日进入到稳定版。
+
+v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持：如Arda贡献的TM4C129x移植，Romeo贡献的frdm-k64f移植，xiaonong的LPC4300移植等，以及睿赛德服务公司捐赠的Zynq7000移植，MB9BF618S移植，以及SPI WiFi网卡的驱动代码等。
+
+更改记录
+
+## 内核
+
+* 移除rt_device_init_all()函数：在系统启动时不需要再调用这个函数来初始化驱动，而是由上层应用执行rt_device_open时自动进行设备初始化；
+* 修正设备对象引用计数在打开设备失败依然递增的问题；
+* 增加WEAK宏用于定义/声明弱符号；
+* 在执行静态内存块分配前，重置线程的errno；
+* 修正timer未打开调试选项时，无用的静态函数定义（导致编译警告）；
+* 启动timer前，对timer进行强制移除；
+* 在执行soft timer超时函数时，打开调度器锁；
+* 新增块设备的自动刷新参数，RT_DEVICE_CTRL_BLK_AUTOREFRESH；
+
+## 工具
+
+* 修正scons命令编译时，选择keil mdk (armcc)编译器时，命令行太长编译失败的问题；
+
+## 移植
+
+* 移除rt_device_init_all()相关的调用；
+* 根据串口框架调整相关的驱动代码；
+* 新增frdm-k64f移植（FreeScale K64芯片）；
+* 移除K60Fxxxx移植；
+* 新增LPC43xx移植（NXP LPC4357芯片）；
+* 移除LPC176x中的组件初始化配置；
+* 修正龙芯1B移植（ls1bdev）中链接脚本关于组件初始化部分的配置；
+* 修正STM32F40x中UART3的配置；
+* 修正STM32F40x中GNU GCC连接脚本中ROM/RAM大小的配置；
+* 移除STM32F107中的组件初始化配置；
+* 增强STM32F107 EMAC驱动性能，同时加入自动查找PHY芯片地址功能；
+* 重写xplorer4330（NXP LPC4330芯片）移植（xiaonong完成）；
+* 新增Zynq7000 ARM Dual Cortex-A9移植；
+* 新增MB9BF618S移植；
+* 新增tm4c129x移植，并加入相应的EMAC以太网驱动；
+
+## 组件
+
+* DFS: 新增根据设备对象获得其上装载文件系统路径的函数：dfs_filesystem_get_mounted_path(struct rt_device* device);
+* DFS: 修正readdir在GNU GCC下的编译警告；
+* DeviceDrivers：新增workqueue实现；
+* DeviceDrivers: 修正USB Device栈中的一些拼写错误；
+* DeviceDrivers: 重写serial框架，能够让串口设备驱动同时支持三种模式：poll、interrupt、DMA。模式选择需要在执行rt_device_open时，由open flags指定；
+* DeviceDrivers: 加入更多的SPI设备驱动，例如RW009的SPI WiFi网口驱动（2.4G 802.11 b/g/n，WEP/WPA/WPA2，SoftAP/Station），SPI NorFlash块设备驱动，ENC28J60以太网网卡驱动；
+* Finsh: list_device()命令中增加refcount的信息；
+* Finsh: 修正'0'零常量无法识别的错误；
+* Finsh: mv命令，实现把一个文件移动到一个目录中；
+* Finsh: ifconfig命令支持对一个网络接口的基本配置；
+* Finsh: 新增netstat命令，用于显示当前系统中TCP连接的状态；
+* Finsh: 修正当命令行太长导致的缓冲区移除的问题；
+* libc: 修正arm libc中未使用DFS时的编译警告；
+* libc: 修正newlib中使用DFS时的系统调用编译警告（GNU GCC下）；
+* lwIP 1.4.1: 默认打开LWIP_SO_SNDTIMEO以支持连接发送超时；
+* lwIP 1.4.1: 修正MEMP_NUM_TCP_SEG定义错误的问题；
+* lwIP 1.4.1: 加入RT_LWIP_REASSEMBLY_FRAG选项定义以支持IP分组及合并；
+* lwIP 1.4.1: ethnet网络接口支持定义LWIP_NO_TX_THREAD/LWIP_NO_RX_THREAD，以关闭etx/erx线程；
+* lwIP 1.4.1: 用户可以重新定义RT_LWIP_ETH_MTU，以修改网络中的MTU值；
+* lwIP 1.4.1: 修正LWIP_NETIF_LINK_CALLBACK条件编译的问题；
+* lwIP 1.4.1: 完善移植相关的注释；
+* log trace: 增加log_session_lvl接口；
+* log trace: log trace中的session引用更改成常量形式；
+* ymodem: 增强数据接收的稳定性；
+
+# RT-Thread 2.0.0 Alpha更改说明
+
+发布时间:2014/4/8
+​	
+RT-Thread 2.0.0分支的第一个技术预览版本，仅用于展示2.0.0发展分支的演化动向(按照roadmap，2.0.0这个分支会有一部分RT-Thread和Linux互补性的技术，为Linux增加更好的实时性，为RT-Thread增加更多的功能性，这份技术预览版正是朝着这个目标而努力)，欢迎反馈建议和问题。
+
+## 组件
+
+* msh： bugfix 和功能性增强。新的 msh 在调用外部模块方面更加方便。
+* DFS： nfs 的 bugfix 和内置命令的增强。ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题。
+* JS：新添了轻量级Javascript引擎，可以在RT-Thread中直接运行javascript脚本。
+* VMM：可以在qemu中运行的 Virtual Machine Module 组件。暂时只支持 realview-pb-a8 的 bsp。
+* CMSIS：版本更新至 3.20
+* drivers：USB 协议栈的重构。新的框架中编写驱动变得更加容易了。
+
+## BSP
+
+* beaglebone：串口驱动更新
+* realview-a8：添加了 VMM 组件
+
+## 工具
+
+* 固件加入scons --target=ua -s，用于准备用户应用环境；
+
+[发布后记]
+
+RT-Thread 2.0.0. Alpha版本相比于RT-Thread 1.2.1，新的特性主要有两部分：
+- RT-Thread + Linux双系统，这部分以RealView-A8处理器(ARM Cortex-A8单核)为蓝本，给出一个简单的双系统并行运行的demo；在没有硬件的环境下，可以使用QEMU软件虚拟方式的执行。这个链接中包含一个编译好的Linux及RT-Thread二进制包，可以直接下载进行体验。
+
+目录中有 Linux 的内核镜像 zImage，ramdisk rootfs.cpio.gz。可以用
+qemu-system-arm -M realview-pb-a8 -kernel zImage -initrd rootfs.cpio.gz -serial vc -serial vc
+来启动。启动之后 Linux 的控制台在第一个串口上(Atl + Ctrl + 3)，可以直接无密码以 root 用户登录。登录之后加载内核模块：
+insmod rtvmm.ko
+来启动 RT-Thread。RT-Thread 启动之后控制台在第二个串口上(Atl + Ctrl + 4)。第一个串口Linux shell依然可以使用，第二个串口则是RT-Thread的shell。
+- JavaScript解析器，这个是由牛头哥移植的，可以在一个非常小资料的MCU上以JavaScript脚本方式进行编程、开发。根据这种方式，也提供了RN001JS的以太网硬件模块：以JavaScript脚本语言作为二次开发，提供在线web(即WebIDE)进行编程并运行JavaScript程序。JavaScript作为一门轻量级、解释型的语言，更容易上手，配合WebIDE、及提供的一些example可以使得开发变得非常的轻松，也包括一些传感器的JavaScript例子，让做网页的人也可以玩硬件了！
+
+# RT-Thread 1.2.1更改说明
+
+发布时间: 2014/4/8
+​	
+在原有的1.2.0版本的bug修正版本，也是1.2.0系列的第一个修正版本，原则上不添加任何的新功能，我们尽量会按照每个季度一个修订版本的方式推进。大家在使用的过程中有什么问题还请反馈给我们，这些问题很可能会在下个版本中修正！
+
+以下是更改记录：
+
+## 内核
+
+* 用户应用，增加用户应用命令行参数支持；
+* 在挂起一个任务时，把相应的定时器也关闭；
+
+## BSP
+
+* BeagleBone，加入更多串口驱动支持；
+* 移除BSP中rt_device_init_all函数调用，改成打开设备时自动进行初始化；
+* LPC176x，移除components初始化管理器；
+* LPC4088，修正LED驱动的问题；
+* STM32F107，移除components初始化管理器；
+
+## 组件
+
+* 文件系统，ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题；
+* 文件系统，NFS网络文件系统修正相关的一些编译警告信息；
+* 文件系统，copy命令加入文件夹方式复制功能；
+* 文件系统，RAMFS，加入到components初始化管理器中；
+* 文件系统，ROMFS，用于转换文件的工具mkromfs.py，增加Linux主机的支持；
+* CMSIS更新到3.2.0版本；
+* 串口驱动框架加入serial->ops->control的调用；
+* 命令行系统，优化msh，支持用户应用的命令行参数；
+* 命令行系统，当使用msh时，默认使用msh >的命令行提示符；
+* TCP/IP协议栈，导出更多的lwIP接口给用户应用；
+* POSIX thread，修正了同时使用lwIP组件时的编译警告；
+* 第三方组件，加入TJPGD的移植，加入libpng的移植；
+
+## 工具
+
+* 固件加入scons --target=ua -s，用于准备用户应用环境；
+
+[发布后记]
+* RT-Thread携带了众多的BSP，不一定能够一一保证每个分支上把RT-Thread上相应的功能使用起来。所以针对这种情况，我们有一款评估用的硬件开发板：RealBoard 4088，在上面力求把一些相关例程都添加上，这样在一个基本的BSP基础上，可以对照着把其他的组件、功能添加进去；
+* RealBoard 4088使用的RT-Thread版本主要以RT-Thread 1.2.1版本为主。
+
+# RT-Thread 1.2.0正式版本更改说明
+
+发布时间: 2014/1/6 
+
+实现roadmap中提到的大部分内容
+​	
+1，文档方面已完成《RT-Thread编程手册》，同时还有论坛上jiezhi童鞋的《一起来学RT-Thread系列连载教程》
+2，BSP分支方面新增cortext-A8(beaglebone)，cortext-R4(rm48x50)，UNITY-2(SEP6200),lpc408x的移植
+3，组件方面：
+- 加入msh(类似linux shell的风格)，能够直接执行应用程序
+- 新增freemodbus 1.6.0的移植
+- 新增开源的嵌入式关系数据库SQLite 3.8.1的移植
+- 新增Ymodem协议
+- 默认使用lwIP 1.4.1
+
+下面是自RT-Thread 1.2.0 RC版本发布以来具体的变更履历：
+
+## 内核
+
+* timer.c - 使用跳跃表(skip list)实现系统定时器链表，并在bsp中的startup.c中重新加入定时器初始化函数rt_system_timer_init()
+* rtdebug.h - 新增宏定义RT_DEBUG_IN_THREAD_CONTEXT
+* idle.c - 在函数rt_thread_idle_excute()中一次清除所有的死线程
+* scheduler.c - 新增API rt_critical_level()返回调度器上锁次数
+
+## 移植
+
+* cortex-m0 - 修正 cortex-m0 GCC移植中hardfault的问题点
+* cortex-r4 - 在startup后释放IRQ堆栈空间
+* cortex-r4 - 按字节长度分配堆栈空间
+
+## BSP分支
+
+* 新增lpc408x移植
+* bsp/stm32f0x - 增加USART1，USART2驱动，支持finsh，支持组件初始化
+* bsp/simulator - 当RTGUI配置无效时打印错误信息
+* bsp/simulator - 默认情况下关闭RTGUI选项
+* bsp/simulator - 增加createdef.py文件来生成VS的def文件
+* bsp/simulator - 当使用VC++编译时去除_TIME_T_DEFINED的定义
+* bsp/xplorer4330 - 重命名文件Retarget.c为retarget.c,否则linux系统中编译会报错
+* bsp/xplorer4330 - 修正GCC编译链接时关于ENTRY的警告
+* bsp/rm48x50 - 新增GCC的移植
+* bsp/K60Fxxxx - 修正一个编译错误
+
+## 组件
+
+* dfs - 正确处理mkfs未实现的情况
+* dfs - 使用指针代替index变量
+* dfs - 在函数dfs_filesystem_lookup()将含义模糊的指针变量名称empty重命名为fs
+* dfs - 修正dfs_unmount问题点
+* dfs - 在设备打开错误时令挂载失败
+* dfs/elmfat - 令elmfatfs每次都检查扇区大小
+* net - 新增freemodbus 1.6.0的移植
+* finsh - 新增FINSH_USING_MSH_ONLY选项
+* finsh - 只有当shell设备为空时调用rt_console_get_device()
+* finsh - 修正FINSH_USING_SYMTAB未定义的错误
+* finsh - 重构control按键的处理
+* msh - 增加文件和路径名称自动补全的功能
+* msh - msh内增加执行module的功能
+* msh - msh内增加更多的命令
+* libc - 修正 _sys_read()/_sys_write()问题点
+* external - 增加开源的嵌入式关系数据库SQLite 3.8.1的移植
+* pthreads - 避免ESHUTDOWN重复定义
+* mtd_nand - 在MTD nand中增加更多的调试措施
+* mtd_nand - 修正操作MTD nand时起始块错误的问题
+* lwip-1.4.1 - 在lwIP内加入更多的RT-Thread选项设置
+* log_trace - 修正函数memmove()参数使用错误的问题
+* drivers/pipe - 增加一个control命令来获得pipe剩余的空间
+* drivers/serial - 如果读写长度为0，则立即返回
+
+## 例程
+
+* examples - 用rt_sem_control()中的RT_IPC_CMD_RESET命令rt_sem_trytake()来清除信号量
+* examples - 始终打印输出测试结果
+* examples - 在所有的测试结束后打印输出简报
+* examples - 在TC线程中清除变量_tc_stat的TC_STAT_RUNNING状态
+* examples - 重新实现loop功能，并新增finsh命令tc_loop
+* examples - 在tc_stop中增加延时，由原来的延时RT_TICK_PER_SECOND/2调整为10 * RT_TICK_PER_SECOND
+* examples - 在SConscript中判断TC如果被使能，在CPPPATH中增加TC路径
+* examples - 新增一个in-mem-log的例子
+* semaphore_priority.c - 在cleanup时释放信号量
+* heap_realloc.c - 检查调用realloc(ptr, 0)是否成功
+* thread_delete.c - tc线程的延时应该比tid2的延时长，保证其测试过程中正常运行
+* thread_delay.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
+* semaphore_static.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
+* semaphore_dynamic.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
+
+其他：
+* 更新README.md
+	
+# RT-Thread 1.2.0RC更改说明
+
+发布时间: 2013/10/10/ 10:19
+​	 
+主要说明: 该版本新增ARM Cortex-A8的支持(BeagleBone)，新增UNITY-2内核的支持(SEP6200)，新增Ymodem协议。
+
+变更履历
+========
+
+[内核]
+
+* 修正rtdef.h中的拼写错误(_MSC_VER_ -> _MSC_VER)
+* 修正scheduler.c中的调试打印输出错误
+* ipc - 在函数rt_event_recv()中增加对参数option有效性的检查
+* device - 增加统计设备引用次数的变量ref_count
+* memheap - 修正内存块分割问题点
+* memheap - 优化函数rt_memheap_realloc()
+* kservice - 函数声明使用rt_vsnprintf代替vsnprintf
+
+
+[组件]
+
+* dfs - 修正dfs_file.c中一处变量参数类型错误的问题
+* dfs - 增加mount table
+* dfs - 在building脚本中加入ramfs的支持
+* dfs - 修正ramfs中O_APPEND write的问题
+* dfs/elm - 在mkfs中加入device_open/close
+* dfs/jffs2 - 修正jffs2_opn/opendir中的f_flag初始化问题
+* dfs/jffs2 - 修正jffs2卸载问题
+* pthread - 修正一处编译警告
+* drivers/pipe - 增加rt_pipe_init/rt_pipe_detach
+* drivers/pipe - 增加非阻塞读写和强制写模式
+* drivers/pipe - 当恢复读的时候调用函数rx_indicate()
+* drivers/pipe - 增加一个设备类型(pipe类型)
+* drivers/portal - 实现portal设备类型
+* drivers/ringbuffer - 修改一些模糊不清的函数名称
+* drivers/ringbuffer - 新增put_force和putchar_force接口函数
+* finsh - 当set_device时增加设备检查
+* finsh - 在rx_ind中增加对shell设备的自动设置
+* finsh - 增加pipe和portal设备的描述
+* finsh - 在变量定义时使用别名
+* finsh - 当关闭设备时注销rx_indicate
+* finsh - 修正命令行太长的问题
+* finsh/msh - 只有当DFS_USING_WORKDIR使能时才声明cd/pwd
+* init - 为新的组件初始化机制更新连接脚本
+* init - 增加组件初始化调试代码
+* logtrace - 整理代码，去除编译警告
+* logtrace - 增加LOG_TRACE_VERBOSE
+* logtrace - 调整log values
+* logtrace - 只有当finsh使能的时候才声明cmd
+* libc/minilibc - 在sys/time.h中增加gettimeofday的声明
+* utilities - 新增ymodem
+
+工具:
+
+* building.py - 增加clang静态缝隙器的支持
+* building.py - 为Keil MDK增加buildlib功能
+* building.py - 在clang-analyze中执行'clang -Wall -fsyntas-only'
+* clang-analyze.py - 增加一个定制工具实现clang静态分析
+
+分支:
+
+* 新增BeagleBone的移植
+* 新增SEP6200的移植
+* 新增K60Fxxxx的移植
+* 修正Linux中的编译错误(lm4f232, stm32f40x, xplorer4330)
+* cortex-m3 - 加强hard fault的异常处理函数
+* at91sam9260 - 更新串口驱动，使用组件中的通用串口驱动
+* at91sam9260 - 更新工程目录结构
+* at91sam9260 - 修正编译错误
+* at91sam9260 - 内嵌GPLv2许可
+* stm32f10x - 删除无用的文件
+* stm32f10x - 更新工程目录结构
+* stm32f10x - 更新工程文件
+* stm32f10x - 为使用新的组件初始化更新连接脚本
+* stm32f10x - 为使用新的组件初始化更新SD card驱动
+* stm32f10x - 为使用新的组件初始化更新DM9000驱动
+* stm32f10x - 更新串口驱动，使用组件中的通用串口驱动
+* stm32f10x - 修正rtgui初始化问题
+* simulator - 为使用新的组件初始化更新代码，以便支持mingw
+* simulator - 支持Linux系统
+* simulator - 修正Linux系统中的SDL初始化问题
+* simulator - 在rt_components_init之后初始化SDL
+* simulator - 将对SDL设置的内容移入drivers/SConstruct
+* simulator - 在env中获得CORSS_TOOL和EXEC_PATH的值
+* simulator - 支持clang-analyze
+* simulator - 增加tap netif driver
+
+//----------------------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------------------
+
+
+版本: RT-Thread 1.2.0 Beta 版本
+
+发布时间: 2013/6/30
+​		
+进过开发人员三个月的努力，RT-Thread 1.2.0 Beta 版本如期发布。
+该版本默认采用lwIP 1.4.1协议栈，USB device stack也进一步完善。加入 log_trace 子系统，加入组件初始化升级版本，加入 ARM Cortex-R 的移植。
+
+主要变化：
+
+* 1，新增组件初始化功能
+- 详情请看论坛帖子[新功能] 组件初始化
+* 2，支持ARM Cortex-R系列处理器
+- Grissiom 完成 ARM Cortex-R 的移植，目前BSP中已有TI RM48x50分支（仅支持TI CCS开发环境）
+* 3，文件系统中新增 RAMFS
+* 4，加入 log_trace 子系统
+* 5，优化Cortex-M4线程上下文切换，使用了浮点运算的线程才保存及恢复FPU寄存器
+- 详情请看论坛帖子[优化]cortex-m4f线程切换，优化FPU寄存器
+* 6，新增API rt_memheap_realloc()
+* 7，重新实现ringbuffer，采用镜像的方法区分“满”和“空”，同时支持任意大小的buffer
+* 8，内核中加入RT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOC宏。
+如果用户未定义这些宏，将默认指向rt_malloc/rt_free/rt_realloc。
+同时内核仅局限于使用这些宏来使用动态内存
+* 9，在 building.py 中新增生成 cscope database 的选项
+* 10，USB组件新增reset函数，支持热插拔
+* 11，scons编译系统支持CCS开发环境
+* 12，USB组件新增状态信息（USB_STATE_NOTATTACHED，USB_STATE_ATTACHED，USB_STATE_POWERED...）
+
+修复问题点：
+
+* 1，USB组件HOST可以挂起endpoints
+* 2，simulator分支，修复 serial_write 问题
+* 3，udisk可以被弹出
+* 4，iar.py中修复绝对路径的问题
+* 5，dfs_fs.h内增加dfs_mkfs()函数的申明
+* 6，生成MDK工程文件的时候加入library文件
+* 7，当PC不再接受数据的时候，重置VCOM相应的状态
+* 8，USB组件：返回正确的LangID字符串长度给HOST
+* 9，Cortex-M0，Cortex-M3，Cortex-M4上下文切换时，回收系统初始化时用到的栈空间
+
+//----------------------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------------------
+
+
+
+版本: RT-Thread 1.2.0 Alpha版本
+
+发布时间: 2013/4/10
+​	
+遵循2013年RT-Thread roadmap，RT-Thread 1.2.0 Alpha版本发布，Alpha意味着此版本为技术预览版，仅用于展示RT-Thread 1.2.0未来的发展方向，并不适合于开发正式产品。RT-Thread 1.2.0版本是1.1.x系列的下一个分支，这个分支主要体现的是RT-Thread 1.x系列的文档情况。当然也有一些功能、代码方面的增强。
+
+伴随着新版本的到来，RT-Thread有几个重大的转变：
+1，代码托管从google code(SVN)迁移到github(GIT)
+2，RT-Thread与RTGUI区分开来，并成为两个独立的开发分支
+3，重视文档，将文档建设作为1.2.0版本的首要任务来抓
+
+内核主要变化：
+1，加入__rt_ffs函数用于实现32位整数中获取第一个置1的位；同时调度器中位图相关算法直接使用__rt_ffs函数；CPU移植时，可定义RT_USING_CPU_FFS，使用芯片指令完成。
+
+2，新的中断注册机制
+weety加入interrupt description功能，用于为interrupt增加更多的信息，同时中断服务例程也可以携带用户自定义的参数类型。
+* 这部分对ARM7、ARM9、MIPS等影响很大，需要对CPU移植做相应的一些修改。
+* 这部分对ARM Cortex-M系列芯片没有影响。
+
+3，调整定时器插入位置，为相同超时定时的后面。
+
+组件主要变化：
+1，添加lwIP 1.4.1。
+2，在finsh shell中加入module shell功能。finsh shell本身是一个C语言表达式的shell命令行，而module shell更类似于一个传统的命令行，由命令，参数等方式构成。
+
+分支主要变化：
+1，完善simulator分支，支持RTGUI，支持应用模块。
+2，完善at91sam9260分支的移植及驱动更新。
+
+编译系统主要变化：
+1，开启省略编译时长命令特性，如果需要查看编译时命令行，可以使用scons --verbose查看。
+2，加入生成CodeBlocks工程特性。
+3，修正当系统安装使用Keil MDK 4.6+版本的问题。
+
+github主要提交履历:
+5646189b29: elm fatfs支持mkfs，并且无需提前执行dfs_mount; mount/umount/mkfs操作也不会引起reset
+22786f8817: 允许用户自定义PID和VID
+0001344105: 更明确的定时器运行机制，如果两个定时器在同一个时刻发生超时，那么先开始的定时器先处理
+5d68ef8ec1: 修正使用64位GCC时编译finsh过程中发生错误的问题
+a4d661dcf1: 修正dfs_elm.c中一处内存泄露，并且在mount fatfs失败时执行 umount fatfs操作
+43228aeb9c: 修正list_tcps问题：ipaddr_ntoa不是可重入的函数。
+3de4b92a68: 修正AT91SAM9260分支中PHY link状态错误的问题。
+1abaa0492d

Kconfig

@@ -0,0 +1,3 @@
+source "$RTT_DIR/src/Kconfig"
+source "$RTT_DIR/libcpu/Kconfig"
+source "$RTT_DIR/components/Kconfig"

LICENSE

@@ -0,0 +1,201 @@
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README.md

@@ -0,0 +1,84 @@
+# RT-Thread #
+
+[中文页](README_zh.md) |
+
+[![GitHub](https://img.shields.io/github/license/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE)
+[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
+[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
+[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
+[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
+[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
+
+RT-Thread is an open source IoT operating system from China, which has strong scalability: from a tiny kernel running on a tiny core, for example ARM Cortex-M0, or Cortex-M3/4/7, to a rich feature system running on MIPS32, ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
+
+## Overview ##
+
+RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue, signal etc. However, it has three different things:
+
+* Device Driver;
+* Component;
+* Dynamic Module
+
+The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
+
+The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
+
+The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
+
+## Board Support Package ##
+
+RT-Thread RTOS can support many architectures:
+
+* ARM Cortex-M0
+* ARM Cortex-M3/M4/7
+* ARM Cortex-R4
+* ARM Cortex-A8/A9
+* ARM920T/ARM926 etc
+* MIPS32
+* x86
+* Andes
+* C-Sky
+* RISC-V
+* PowerPC
+
+## License ##
+
+RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code.
+
+    /*
+     * Copyright (c) 2006-2018, RT-Thread Development Team
+     *
+     * SPDX-License-Identifier: Apache-2.0
+     */
+
+Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).
+
+## Usage ##
+
+RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly. 
+So far, the RT-Thread scons building system support the command line compile or generate some IDE's project. There are some option varaibles in the scons building script (rtconfig.py):
+
+* ```CROSS_TOOL``` the compiler which you want to use, gcc/keil/iar. 
+* ```EXEC_PATH``` the path of compiler. 
+
+In SConstruct file:
+
+```RTT_ROOT``` This variable is the root directory of RT-Thread RTOS. If you build the porting in the bsp directory, you can use the default setting. Also, you can set the root directory in ```RTT_ROOT``` environment variable and not modify SConstruct files.
+
+When you set these variables correctly, you can use command:
+
+    scons
+
+under BSP directory to simplely compile RT-Thread RTOS.
+
+If you want to generate the IDE's project file, you can use command:
+
+    scons --target=mdk/mdk4/mdk5/iar/cb -s
+
+to generate the project file.
+
+NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files.
+
+## Contribution ##
+
+Please refer the contributors in the github. Thank all of RT-Thread Developers.

README_zh.md

@@ -0,0 +1,97 @@
+# RT-Thread #
+
+[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
+[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
+[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
+[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
+[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
+
+RT-Thread是一个来自中国的开源物联网操作系统，它提供了非常强的可伸缩能力：从一个可以运行在ARM Cortex-M0芯片上的极小内核，到中等的ARM Cortex-M3/4/7系统，甚至是运行于MIPS32、ARM Cortex-A系列处理器上功能丰富系统。
+
+## 简介 ##
+
+RT-Thread包含了一个自有的、传统的硬实时内核：可抢占的多任务实时调度器，信号量，互斥量，邮箱，消息队列，信号等。当然，它和传统的实时操作系统还存在着三种不同：
+
+* 设备驱动框架；
+* 软件组件；
+* 应用模块
+
+设备驱动框架更类似一套驱动框架，涉及到UART，IIC，SPI，SDIO，USB从设备/主设备，EMAC，NAND闪存设备等。它会把这些设备驱动中的共性抽象/抽取出来，而驱动工程师只需要按照固定的模式实现少量的底层硬件操作及板级配置。通过这样的方式，让一个硬件外设更容易地对接到RT-Thread系统中，并获得RT-Thread平台上的完整软件栈功能。
+
+软件组件是位于RT-Thread内核上的软件单元，例如命令行（finsh/msh shell），虚拟文件系统（FAT，YAFFS，UFFS，ROM/RAM文件系统等），TCP/IP网络协议栈（lwIP），Libc/POSIX标准层等。一般的，一个软件组件放置于一个目录下，例如RT-Thread/components目录下的文件夹，并且每个软件组件通过一个 SConscript文件来描述并被添加到RT-Thread的构建系统中。当系统配置中开启了这一软件组件时，这个组件将被编译并链接到最终的RT-Thread固件中。
+
+注：随着RT-Thread 3.0中的包管理器开启，越来越多的软件组件将以package方式出现在RT-Thread平台中。而RT-Thread平台更多的是指：
+
+* RT-Thread内核；
+* shell命令行；
+* 虚拟文件系统；
+* TCP/IP网络协议栈；
+* 设备驱动框架；
+* Libc/POSIX标准层。
+
+更多的IoT软件包则以package方式被添加到RT-Thread系统中。
+
+应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象链表，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。
+
+## 支持的芯片架构 ##
+
+RT-Thread支持数种芯片体系架构，已经覆盖当前应用中的主流体系架构：
+
+* ARM Cortex-M0
+* ARM Cortex-M3/M4/7
+* ARM Cortex-R4
+* ARM Cortex-A8/A9
+* ARM920T/ARM926 etc
+* MIPS32
+* x86
+* Andes
+* C-Sky
+* RISC-V
+* PowerPC
+
+## 许可证 ##
+
+RT-Thread从v3.1.1版本开始，是一个以Apache许可证2.0版本授权的开源软件，许可证信息以及版权信息一般的可以在代码首部看到：
+
+    /*
+     * Copyright (c) 2006-2018, RT-Thread Development Team
+     *
+     * SPDX-License-Identifier: Apache-2.0
+     */
+
+从2018/09/09开始，开发者提交PR需要签署贡献者许可协议（CLA）。
+
+注意：
+
+以Apache许可协议v2.0版本授权仅在RT-Thread v3.1.1正式版发布之后才正式实施，当前依然在准备阶段（准备所有原有开发者签署CLA协议）。
+
+## 编译 ##
+
+RT-Thread使用了[scons](http://www.scons.org)做为自身的编译构建系统，并进行一定的定制以满足自身的需求（可以通过scons --help查看RT-Thread中额外添加的命令）。在编译RT-Thread前，请先安装Python 2.7.x及scons。
+
+截至目前，RT-Thread scons构建系统可以使用命令行方式编译代码，或者使用scons来生成不同IDE的工程文件。在使用scons时，需要对构建配置文件（rtconfig.py）中如下的变量进行配置：
+
+* ```CROSS_TOOL``` 指定希望使用的工具链，例如gcc/keil/iar. 
+* ```EXEC_PATH``` 工具链的路径. 
+
+注：在SConstruct文件中：
+
+```RTT_ROOT``` 这个变量指向了RT-Thread的发布源代码根目录。如果你仅计划编译bsp目录下的target，这个`RTT_ROOT`可以使用默认配置。另外，你也可以设置同名的环境变量来指向不同的RT-Thread源代码根目录。
+
+当你把相关的配置都配置正确后，你可以在具有目标目录下（这个目录应包括rtconfig.py、SContruct文件）执行以下命令：
+
+    scons 
+
+从而简单地就编译好RT-Thread。
+
+如果你希望使用IDE来编译RT-Thread，你也可以使用命令行：
+
+    scons --target=mdk/mdk4/mdk5/iar/cb -s 
+
+来生成mdk/iar等的工程文件。而后在IDE中打开project前缀的工程文件来编译RT-Thread。
+
+注意：RT-Thread的scons构建系统会根据配置头文件rtconfig.h来裁剪系统。例如，如果你关闭了rtconfig.h中的lwIP定义（通过注释掉```#define RT_USING_LWIP```的方式），则scons生成的IDE工程文件中将自动不包括lwIP相关的文件。而在RT-Thread 3.0版本中，可以通过menuconfig的方式来配置整个系统，而不需要再手工更改rtconfig.h配置头文件。
+
+## 贡献者 ##
+
+请访问github上RT-Thread项目上的contributors了解已经为RT-Thread提交过代码，PR的贡献者。感谢所有为RT-Thread付出的开发者们！

bsp/stm32/libraries/HAL_Drivers/Kconfig

@@ -0,0 +1,48 @@
+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif
+
+config BSP_USING_CRC
+    bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRC
+    # "Crypto device frame dose not support above 8-bits granularity"
+    # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7)
+    default n 
+
+config BSP_USING_RNG
+    bool "Enable RNG (Random Number Generator)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_RNG
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
+                SOC_SERIES_STM32H7)
+    default n
+    
+config BSP_USING_UDID
+    bool "Enable UDID (Unique Device Identifier)"
+    select RT_USING_HWCRYPTO
+    default n
+

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,101 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
+    src += ['drv_pm.c']
+    src += ['drv_lptim.c']
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+
+if GetDepend('BSP_USING_LCD_MIPI'):
+    src += ['drv_lcd_mipi.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
+    src += ['drv_flash/drv_flash_f0.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
+    src += ['drv_flash/drv_flash_f1.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
+    src += ['drv_flash/drv_flash_f2.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
+    src += ['drv_flash/drv_flash_f4.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
+    src += ['drv_flash/drv_flash_f7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
+    src += ['drv_flash/drv_flash_l4.c']
+	
+if GetDepend('RT_USING_HWCRYPTO'):
+    src += ['drv_crypto.c']
+	
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['BSP_USING_USBD']):
+    src += ['drv_usbd.c']
+
+if GetDepend(['BSP_USING_PULSE_ENCODER']):
+    src += ['drv_pulse_encoder.c']
+
+src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    path += [cwd + '/drv_flash']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel2-3 DMA2 channel1-2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
+#define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+
+#if  defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+/* DMA1 channel2-3 DMA2 channel1-2 */
+
+/* DMA1 channel4-7 DMA2 channel3-5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#endif
+/* DMA1 channel4-7 DMA2 channel3-5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM14,         \
+       .tim_irqn                = TIM14_IRQn,    \
+       .name                    = "timer14",     \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM16,         \
+       .tim_irqn                = TIM16_IRQn,    \
+       .name                    = "timer16",     \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM17,         \
+       .tim_irqn                = TIM17_IRQn,    \
+       .name                    = "timer17",     \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+    
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC1,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC2,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC3,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-02     SummerGift   first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler         DMA1_Channel2_IRQHandler
+#define UART3_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE           DMA1_Channel2
+#define UART3_TX_DMA_IRQ                DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE           DMA1_Channel7
+#define UART2_TX_DMA_IRQ                DMA1_Channel7_IRQn
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
+#define SPI3_RX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_RX_DMA_INSTANCE            DMA2_Channel1
+#define SPI3_RX_DMA_IRQ                 DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
+#define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART4_RX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_RX_DMA_INSTANCE           DMA2_Channel3
+#define UART4_RX_DMA_IRQ                DMA2_Channel3_IRQn
+#endif
+/* DMA2 channel4 */
+/* DMA2 channel5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler         DMA2_Channel4_5_IRQHandler
+#define UART4_TX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_TX_DMA_INSTANCE           DMA2_Channel5
+#define UART4_TX_DMA_IRQ                DMA2_Channel4_5_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                     \
+    {                                             \
+       .tim_handler.Instance     = TIM1,          \
+       .encoder_irqn             = TIM1_UP_IRQn,  \
+       .name                     = "pulse1"       \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM2,       \
+       .encoder_irqn             = TIM2_IRQn,  \
+       .name                     = "pulse2"    \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM3,       \
+       .encoder_irqn             = TIM3_IRQn,  \
+       .name                     = "pulse3"    \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM4,       \
+       .encoder_irqn             = TIM4_IRQn,  \
+       .name                     = "pulse4"    \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f1xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel4,                \
+        .dma_tx.dma_irq = DMA2_Channel4_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     BalanceTWK   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-07-29     Chinese66    change from f4 to f1
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#define USBD_IRQ_TYPE        USB_LP_CAN1_RX0_IRQn
+#define USBD_IRQ_HANDLER     USB_LP_CAN1_RX0_IRQHandler
+#define USBD_INSTANCE        USB
+#define USBD_PCD_SPEED       PCD_SPEED_FULL
+#define USBD_PCD_PHY_MODULE  PCD_PHY_EMBEDDED
+
+#ifndef BSP_USB_CONNECT_PIN
+#define BSP_USB_CONNECT_PIN  -1
+#endif
+
+#ifndef BSP_USB_PULL_UP_STATUS
+#define BSP_USB_PULL_UP_STATUS  1
+#endif
+#endif

bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART6_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART6_RX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+/* DMA2 stream3 */
+
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)	
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+
+/* DMA2 stream7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f2xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef BSP_USING_TIM7
+#ifndef TIM7_CONFIG
+#define TIM7_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM7,         \
+       .tim_irqn                = TIM7_IRQn,    \
+       .name                    = "timer7",     \
+    }
+#endif /* TIM7_CONFIG */
+#endif /* BSP_USING_TIM7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
+#define UART8_DMA_TX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART8_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_TX_DMA_INSTANCE            DMA1_Stream0
+#define UART8_TX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_TX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE            DMA1_Stream3
+#define UART3_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_TX_DMA_IRQ                 DMA1_Stream3_IRQn
+#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream3
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_TX_DMA_INSTANCE            DMA1_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_TX_DMA_IRQ                 DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream6
+#define UART2_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_TX_DMA_IRQ                 DMA1_Stream6_IRQn
+#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
+#define UART8_DMA_RX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART8_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_RX_DMA_INSTANCE            DMA1_Stream6
+#define UART8_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_RX_DMA_IRQ                 DMA1_Stream6_IRQn
+#endif
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_TX_DMA_INSTANCE            DMA1_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler          DMA2_Stream1_IRQHandler
+#define UART6_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE            DMA2_Stream1
+#define UART6_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                 DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_DMA_TX_IRQHandler         DMA2_Stream6_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_TX_DMA_INSTANCE           DMA2_Stream6
+#define UART6_TX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_TX_DMA_IRQ                DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Stream7_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Stream7
+#define UART1_TX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_TX_DMA_IRQ                DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM1,                \
+       .encoder_irqn            = TIM1_UP_TIM10_IRQn,  \
+       .name                    = "pulse1"             \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM2,                \
+       .encoder_irqn            = TIM2_IRQn,           \
+       .name                    = "pulse2"             \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM3,                \
+       .encoder_irqn            = TIM3_IRQn,           \
+       .name                    = "pulse3"             \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM4,                \
+       .encoder_irqn            = TIM4_IRQn,           \
+       .name                    = "pulse4"             \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef BSP_USING_PWM12
+#ifndef PWM12_CONFIG
+#define PWM12_CONFIG                            \
+    {                                           \
+       .tim_handle.Instance     = TIM12,        \
+       .name                    = "pwm12",      \
+       .channel                 = 0             \
+    }
+#endif /* PWM12_CONFIG */
+#endif /* BSP_USING_PWM12 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-03     zylx         modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h

@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .Instance = UART7,                                         \
+        .irq_type = UART7_IRQn,                                    \
+    }
+#endif /* UART7_CONFIG */
+
+#if defined(BSP_UART7_RX_USING_DMA)
+#ifndef UART7_DMA_RX_CONFIG
+#define UART7_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART7_RX_DMA_INSTANCE,                         \
+        .channel = UART7_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART7_RX_DMA_RCC,                               \
+        .dma_irq = UART7_RX_DMA_IRQ,                               \
+    }
+#endif /* UART7_DMA_RX_CONFIG */
+#endif /* BSP_UART7_RX_USING_DMA */
+		
+#if defined(BSP_UART7_TX_USING_DMA)
+#ifndef UART7_DMA_TX_CONFIG
+#define UART7_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART7_TX_DMA_INSTANCE,                         \
+        .channel = UART7_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART7_TX_DMA_RCC,                               \
+        .dma_irq = UART7_TX_DMA_IRQ,                               \
+    }
+#endif /* UART7_DMA_TX_CONFIG */
+#endif /* BSP_UART7_TX_USING_DMA */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .Instance = UART8,                                         \
+        .irq_type = UART8_IRQn,                                    \
+    }
+#endif /* UART8_CONFIG */
+
+#if defined(BSP_UART8_RX_USING_DMA)
+#ifndef UART8_DMA_RX_CONFIG
+#define UART8_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART8_RX_DMA_INSTANCE,                         \
+        .channel = UART8_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART8_RX_DMA_RCC,                               \
+        .dma_irq = UART8_RX_DMA_IRQ,                               \
+    }
+#endif /* UART8_DMA_RX_CONFIG */
+#endif /* BSP_UART8_RX_USING_DMA */
+		
+#if defined(BSP_UART8_TX_USING_DMA)
+#ifndef UART8_DMA_TX_CONFIG
+#define UART8_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART8_TX_DMA_INSTANCE,                         \
+        .channel = UART8_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART8_TX_DMA_RCC,                               \
+        .dma_irq = UART8_TX_DMA_IRQ,                               \
+    }
+#endif /* UART8_DMA_TX_CONFIG */
+#endif /* BSP_UART8_TX_USING_DMA */
+#endif /* BSP_USING_UART8 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA1_Channel1_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE             DMA1_Channel1
+#define SPI1_RX_DMA_REQUEST              DMA_REQUEST_SPI1_RX
+#define SPI1_RX_DMA_IRQ                  DMA1_Channel1_IRQn
+#ifdef BSP_UART1_RX_USING_DMA
+#undef BSP_UART1_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel1
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#define UART1_RX_DMA_IRQ                DMA1_Channel1_IRQn
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel1_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel1
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel1_IRQn
+#endif
+
+/* DMA1 channle2-3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#ifdef BSP_UART2_RX_USING_DMA
+#undef BSP_UART2_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel2_3_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel2
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                DMA1_Channel2_3_IRQn
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#endif
+
+#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHBENR_DMA1EN
+#define LPUART1_RX_DMA_INSTANCE         DMA1_Channel5
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#define LPUART1_RX_DMA_IRQ              DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .request = SPI1_TX_DMA_REQUEST,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .request = SPI1_RX_DMA_REQUEST,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .request = SPI2_TX_DMA_REQUEST,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .request = SPI2_RX_DMA_REQUEST,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#define LPUART1_IRQHandler      USART3_4_LPUART1_IRQHandler
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request =  LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request =  UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request =  UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#else
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request =  UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#else
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = USART4,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* UART4_CONFIG */
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request =  UART4_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
+#define UART8_DMA_TX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART8_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_TX_DMA_INSTANCE            DMA1_Stream0
+#define UART8_TX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_TX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE            DMA1_Stream3
+#define UART3_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_TX_DMA_IRQ                 DMA1_Stream3_IRQn
+#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream3
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_TX_DMA_INSTANCE            DMA1_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_TX_DMA_IRQ                 DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream6
+#define UART2_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_TX_DMA_IRQ                 DMA1_Stream6_IRQn
+#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
+#define UART8_DMA_RX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART8_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_RX_DMA_INSTANCE            DMA1_Stream6
+#define UART8_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_RX_DMA_IRQ                 DMA1_Stream6_IRQn
+#endif
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_TX_DMA_INSTANCE            DMA1_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler          DMA2_Stream1_IRQHandler
+#define UART6_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE            DMA2_Stream1
+#define UART6_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                 DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_DMA_TX_IRQHandler         DMA2_Stream6_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_TX_DMA_INSTANCE           DMA2_Stream6
+#define UART6_TX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_TX_DMA_IRQ                DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Stream7_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Stream7
+#define UART1_TX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_TX_DMA_IRQ                DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM1,                \
+       .encoder_irqn            = TIM1_UP_TIM10_IRQn,  \
+       .name                    = "pulse1"             \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM2,                \
+       .encoder_irqn            = TIM2_IRQn,           \
+       .name                    = "pulse2"             \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM3,                \
+       .encoder_irqn            = TIM3_IRQn,           \
+       .name                    = "pulse3"             \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM4,                \
+       .encoder_irqn            = TIM4_IRQn,           \
+       .name                    = "pulse4"             \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef BSP_USING_PWM12
+#ifndef PWM12_CONFIG
+#define PWM12_CONFIG                            \
+    {                                           \
+       .tim_handle.Instance     = TIM12,        \
+       .name                    = "pwm12",      \
+       .channel                 = 0             \
+    }
+#endif /* PWM12_CONFIG */
+#endif /* BSP_USING_PWM12 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32g4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-03     zylx         modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ * 2019-10-03     xuzhuoyi     modify for STM32G4
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32h7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Channel4_5_6_7_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART1_RX_DMA_IRQ                 DMA1_Channel4_5_6_7_IRQn
+#endif
+/* DMA1 channel5 */
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Channel4_5_6_7_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel6
+#define UART2_RX_DMA_IRQ                 DMA1_Channel4_5_6_7_IRQn
+#endif
+/* DMA1 channel6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+    
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h

@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
+#define QSPI_DMA_INSTANCE               DMA1_Channel5
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
+#define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_TX_DMA_INSTANCE           DMA2_Channel1
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_RX_DMA_INSTANCE           DMA2_Channel2
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
+#endif
+
+/* DMA2 channel5 */
+
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE               DMA2_Channel7
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
+#define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
+#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA2_Channel7_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHB1ENR_DMA2EN
+#define LPUART1_RX_DMA_INSTANCE         DMA2_Channel7
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_4
+#define LPUART1_RX_DMA_IRQ              DMA2_Channel7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+    
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32l4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.request = DMA_REQUEST_7,                 \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel5,                \
+        .dma_tx.request = DMA_REQUEST_7,                 \
+        .dma_tx.dma_irq = DMA2_Channel5_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI2,                                   \
+        .bus_name = "spi2",                                 \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI3,                                   \
+        .bus_name = "spi3",                                 \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_TX_DMA_RCC,                         \
+        .Instance = SPI3_TX_DMA_INSTANCE,                   \
+        .request = SPI3_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_RX_DMA_RCC,                         \
+        .Instance = SPI3_RX_DMA_INSTANCE,                   \
+        .request = SPI3_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-12     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */  
+   
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_adc.c

@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-05     zylx         first version
+ * 2018-12-12     greedyhao    Porting for stm32f7xx
+ * 2019-02-01     yuneizhilin   fix the stm32_adc_init function initialization issue
+ */
+
+#include <board.h>
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.adc"
+#include <drv_log.h>
+
+static ADC_HandleTypeDef adc_config[] =
+{
+#ifdef BSP_USING_ADC1
+    ADC1_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC2
+    ADC2_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC3
+    ADC3_CONFIG,
+#endif
+};
+
+struct stm32_adc
+{
+    ADC_HandleTypeDef ADC_Handler;
+    struct rt_adc_device stm32_adc_device;
+};
+
+static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
+
+static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    ADC_HandleTypeDef *stm32_adc_handler;
+    RT_ASSERT(device != RT_NULL);
+    stm32_adc_handler = device->parent.user_data;
+
+    if (enabled)
+    {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+        ADC_Enable(stm32_adc_handler);
+#else
+        __HAL_ADC_ENABLE(stm32_adc_handler);
+#endif
+    }
+    else
+    {
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+        ADC_Disable(stm32_adc_handler);
+#else
+        __HAL_ADC_DISABLE(stm32_adc_handler);
+#endif
+    }
+
+    return RT_EOK;
+}
+
+static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t stm32_channel = 0;
+
+    switch (channel)
+    {
+    case  0:
+        stm32_channel = ADC_CHANNEL_0;
+        break;
+    case  1:
+        stm32_channel = ADC_CHANNEL_1;
+        break;
+    case  2:
+        stm32_channel = ADC_CHANNEL_2;
+        break;
+    case  3:
+        stm32_channel = ADC_CHANNEL_3;
+        break;
+    case  4:
+        stm32_channel = ADC_CHANNEL_4;
+        break;
+    case  5:
+        stm32_channel = ADC_CHANNEL_5;
+        break;
+    case  6:
+        stm32_channel = ADC_CHANNEL_6;
+        break;
+    case  7:
+        stm32_channel = ADC_CHANNEL_7;
+        break;
+    case  8:
+        stm32_channel = ADC_CHANNEL_8;
+        break;
+    case  9:
+        stm32_channel = ADC_CHANNEL_9;
+        break;
+    case 10:
+        stm32_channel = ADC_CHANNEL_10;
+        break;
+    case 11:
+        stm32_channel = ADC_CHANNEL_11;
+        break;
+    case 12:
+        stm32_channel = ADC_CHANNEL_12;
+        break;
+    case 13:
+        stm32_channel = ADC_CHANNEL_13;
+        break;
+    case 14:
+        stm32_channel = ADC_CHANNEL_14;
+        break;
+    case 15:
+        stm32_channel = ADC_CHANNEL_15;
+        break;
+    case 16:
+        stm32_channel = ADC_CHANNEL_16;
+        break;
+    case 17:
+        stm32_channel = ADC_CHANNEL_17;
+        break;
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+    case 18:
+        stm32_channel = ADC_CHANNEL_18;
+        break;
+#endif
+    }
+
+    return stm32_channel;
+}
+
+static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    ADC_ChannelConfTypeDef ADC_ChanConf;
+    ADC_HandleTypeDef *stm32_adc_handler;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    stm32_adc_handler = device->parent.user_data;
+
+    rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
+
+#if defined(SOC_SERIES_STM32F1)
+    if (channel <= 17)
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2)  || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+    if (channel <= 18)
+#endif
+    {
+        /* set stm32 ADC channel */
+        ADC_ChanConf.Channel =  stm32_adc_get_channel(channel);
+    }
+    else
+    {
+#if defined(SOC_SERIES_STM32F1)
+        LOG_E("ADC channel must be between 0 and 17.");
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2)  || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
+        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+        LOG_E("ADC channel must be between 0 and 18.");
+#endif
+        return -RT_ERROR;
+    }
+    ADC_ChanConf.Rank = 1;
+#if defined(SOC_SERIES_STM32F0)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
+#elif defined(SOC_SERIES_STM32F1)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
+#elif defined(SOC_SERIES_STM32L4)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
+#endif
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+    ADC_ChanConf.Offset = 0;
+#endif
+#ifdef SOC_SERIES_STM32L4
+    ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
+    ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
+#endif
+    HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
+
+    /* start ADC */
+    HAL_ADC_Start(stm32_adc_handler);
+
+    /* Wait for the ADC to convert */
+    HAL_ADC_PollForConversion(stm32_adc_handler, 100);
+
+    /* get ADC value */
+    *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops stm_adc_ops =
+{
+    .enabled = stm32_adc_enabled,
+    .convert = stm32_get_adc_value,
+};
+
+static int stm32_adc_init(void)
+{
+    int result = RT_EOK;
+    /* save adc name */
+    char name_buf[5] = {'a', 'd', 'c', '0', 0};
+    int i = 0;
+
+    for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
+    {
+        /* ADC init */
+        name_buf[3] = '0';
+        stm32_adc_obj[i].ADC_Handler = adc_config[i];
+#if defined(ADC1)
+        if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
+        {
+            name_buf[3] = '1';
+        }
+#endif
+#if defined(ADC2)
+        if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
+        {
+            name_buf[3] = '2';
+        }
+#endif
+#if defined(ADC3)
+        if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
+        {
+            name_buf[3] = '3';
+        }
+#endif
+        if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
+        {
+            LOG_E("%s init failed", name_buf);
+            result = -RT_ERROR;
+        }
+        else
+        {
+            /* register ADC device */
+            if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
+            {
+                LOG_D("%s init success", name_buf);
+            }
+            else
+            {
+                LOG_E("%s register failed", name_buf);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(stm32_adc_init);
+
+#endif /* BSP_USING_ADC */

bsp/stm32/libraries/HAL_Drivers/drv_can.c

@@ -0,0 +1,911 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-05     Xeon Xu      the first version
+ * 2019-01-22     YLZ          port from stm324xx-HAL to bsp stm3210x-HAL
+ * 2019-02-19     YLZ          add support EXTID RTR Frame. modify send, recv functions.
+ *                             fix bug.port to BSP [stm32]
+ * 2019-03-27     YLZ          support double can channels, support stm32F4xx (only Legacy mode).
+ * 2019-06-17     YLZ          port to new STM32F1xx HAL V1.1.3.
+ */
+
+#include "drv_can.h"
+#ifdef BSP_USING_CAN
+
+#define LOG_TAG    "drv_can"
+#include <drv_log.h>
+
+/* attention !!! baud calculation example: Tclk / ((ss + bs1 + bs2) * brp)  36 / ((1 + 8 + 3) * 3) = 1MHz*/
+#if defined (SOC_SERIES_STM32F1)/* APB1 36MHz(max) */
+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 3)},
+    {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ  | CAN_BS2_3TQ | 5)},
+    {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 6)},
+    {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 12)},
+    {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 24)},
+    {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 30)},
+    {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 60)},
+    {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 150)},
+    {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_3TQ | 300)}
+};
+#elif defined (SOC_SERIES_STM32F4)/* APB1 45MHz(max) */
+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 3)},
+    {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ  | CAN_BS2_5TQ | 4)},
+    {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 6)},
+    {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 12)},
+    {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 24)},
+    {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 30)},
+    {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 60)},
+    {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 150)},
+    {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_5TQ | 300)}
+};
+#elif defined (SOC_SERIES_STM32F7)/* APB1 54MHz(max) */
+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 3)},
+    {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ  | CAN_BS2_7TQ | 4)},
+    {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 6)},
+    {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 12)},
+    {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 24)},
+    {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 30)},
+    {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 60)},
+    {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 150)},
+    {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 300)}
+};
+#endif
+
+#ifdef BSP_USING_CAN1
+static struct stm32_can drv_can1 =
+{
+    .name = "can1",
+    .CanHandle.Instance = CAN1,
+};
+#endif
+
+#ifdef BSP_USING_CAN2
+static struct stm32_can drv_can2 =
+{
+    "can2",
+    .CanHandle.Instance = CAN2,
+};
+#endif
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+    rt_uint32_t len, index;
+
+    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+    for (index = 0; index < len; index++)
+    {
+        if (can_baud_rate_tab[index].baud_rate == baud)
+            return index;
+    }
+
+    return 0; /* default baud is CAN1MBaud */
+}
+
+static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
+{
+    struct stm32_can *drv_can;
+    rt_uint32_t baud_index;
+
+    RT_ASSERT(can);
+    RT_ASSERT(cfg);
+    drv_can = (struct stm32_can *)can->parent.user_data;
+    RT_ASSERT(drv_can);
+
+    drv_can->CanHandle.Init.TimeTriggeredMode = DISABLE;
+    drv_can->CanHandle.Init.AutoBusOff = ENABLE;
+    drv_can->CanHandle.Init.AutoWakeUp = DISABLE;
+    drv_can->CanHandle.Init.AutoRetransmission = DISABLE;
+    drv_can->CanHandle.Init.ReceiveFifoLocked = DISABLE;
+    drv_can->CanHandle.Init.TransmitFifoPriority = ENABLE;
+
+    switch (cfg->mode)
+    {
+    case RT_CAN_MODE_NORMAL:
+        drv_can->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+        break;
+    case RT_CAN_MODE_LISEN:
+        drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT;
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        drv_can->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
+        break;
+    case RT_CAN_MODE_LOOPBACKANLISEN:
+        drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
+        break;
+    }
+
+    baud_index = get_can_baud_index(cfg->baud_rate);
+    drv_can->CanHandle.Init.SyncJumpWidth = BAUD_DATA(SJW, baud_index);
+    drv_can->CanHandle.Init.TimeSeg1 = BAUD_DATA(BS1, baud_index);
+    drv_can->CanHandle.Init.TimeSeg2 = BAUD_DATA(BS2, baud_index);
+    drv_can->CanHandle.Init.Prescaler = BAUD_DATA(RRESCL, baud_index);
+    /* init can */
+    if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
+    {
+        return -RT_ERROR;
+    }
+
+    /* default filter config */
+    HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
+    /* can start */
+    HAL_CAN_Start(&drv_can->CanHandle);
+
+    return RT_EOK;
+}
+
+static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+    rt_uint32_t argval;
+    struct stm32_can *drv_can;
+    struct rt_can_filter_config *filter_cfg;
+
+    RT_ASSERT(can != RT_NULL);
+    drv_can = (struct stm32_can *)can->parent.user_data;
+    RT_ASSERT(drv_can != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
+                HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
+                HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
+            }
+#endif
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
+            }
+#endif
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                NVIC_DisableIRQ(CAN1_SCE_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                NVIC_DisableIRQ(CAN2_SCE_IRQn);
+            }
+#endif
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
+            __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
+        }
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
+
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
+                HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
+                HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
+            }
+#endif
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
+
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN1_TX_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN2_TX_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
+            }
+#endif
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
+            __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
+
+            if (CAN1 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
+            }
+#ifdef CAN2
+            if (CAN2 == drv_can->CanHandle.Instance)
+            {
+                HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 1, 0);
+                HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
+            }
+#endif
+        }
+        break;
+    case RT_CAN_CMD_SET_FILTER:
+        if (RT_NULL == arg)
+        {
+            /* default filter config */
+            HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
+        }
+        else
+        {
+            filter_cfg = (struct rt_can_filter_config *)arg;
+            /* get default filter */
+            for (int i = 0; i < filter_cfg->count; i++)
+            {
+                drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
+                drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
+                drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) | 
+                                                    (filter_cfg->items[i].ide << 2) | 
+                                                    (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+                drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
+                drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF;
+                drv_can->FilterConfig.FilterMode = filter_cfg->items[i].mode;
+                /* Filter conf */
+                HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
+            }
+        }
+        break;
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL &&
+                argval != RT_CAN_MODE_LISEN &&
+                argval != RT_CAN_MODE_LOOPBACK &&
+                argval != RT_CAN_MODE_LOOPBACKANLISEN)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.mode)
+        {
+            drv_can->device.config.mode = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud &&
+                argval != CAN800kBaud &&
+                argval != CAN500kBaud &&
+                argval != CAN250kBaud &&
+                argval != CAN125kBaud &&
+                argval != CAN100kBaud &&
+                argval != CAN50kBaud  &&
+                argval != CAN20kBaud  &&
+                argval != CAN10kBaud)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.baud_rate)
+        {
+            drv_can->device.config.baud_rate = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_PRIV:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_PRIV &&
+                argval != RT_CAN_MODE_NOPRIV)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.privmode)
+        {
+            drv_can->device.config.privmode = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+    {
+        rt_uint32_t errtype;
+        errtype = drv_can->CanHandle.Instance->ESR;
+        drv_can->device.status.rcverrcnt = errtype >> 24;
+        drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
+        drv_can->device.status.lasterrtype = errtype & 0x70;
+        drv_can->device.status.errcode = errtype & 0x07;
+
+        rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
+    }
+    break;
+    }
+
+    return RT_EOK;
+}
+
+static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+    CAN_HandleTypeDef *hcan;
+    hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    CAN_TxHeaderTypeDef txheader = {0};
+    HAL_CAN_StateTypeDef state = hcan->State;
+
+    /* Check the parameters */
+    RT_ASSERT(IS_CAN_DLC(pmsg->len));
+
+    if ((state == HAL_CAN_STATE_READY) ||
+            (state == HAL_CAN_STATE_LISTENING))
+    {
+        /*check select mailbox  is empty */
+        switch (1 << box_num)
+        {
+        case CAN_TX_MAILBOX0:
+            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0) != SET)
+            {
+                /* Change CAN state */
+                hcan->State = HAL_CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        case CAN_TX_MAILBOX1:
+            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1) != SET)
+            {
+                /* Change CAN state */
+                hcan->State = HAL_CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        case CAN_TX_MAILBOX2:
+            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2) != SET)
+            {
+                /* Change CAN state */
+                hcan->State = HAL_CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        default:
+            RT_ASSERT(0);
+            break;
+        }
+
+        if (RT_CAN_STDID == pmsg->ide)
+        {
+            txheader.IDE = CAN_ID_STD;
+            RT_ASSERT(IS_CAN_STDID(pmsg->id));
+            txheader.StdId = pmsg->id;
+        }
+        else
+        {
+            txheader.IDE = CAN_ID_EXT;
+            RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+            txheader.ExtId = pmsg->id;
+        }
+
+        if (RT_CAN_DTR == pmsg->rtr)
+        {
+            txheader.RTR = CAN_RTR_DATA;
+        }
+        else
+        {
+            txheader.RTR = CAN_RTR_REMOTE;
+        }
+        /* clear TIR */
+        hcan->Instance->sTxMailBox[box_num].TIR &= CAN_TI0R_TXRQ;
+        /* Set up the Id */
+        if (RT_CAN_STDID == pmsg->ide)
+        {
+            hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.StdId << CAN_TI0R_STID_Pos) | txheader.RTR;
+        }
+        else
+        {
+            hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.ExtId << CAN_TI0R_EXID_Pos) | txheader.IDE | txheader.RTR;
+        }
+        /* Set up the DLC */
+        hcan->Instance->sTxMailBox[box_num].TDTR = pmsg->len & 0x0FU;
+        /* Set up the data field */
+        WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDHR,
+                  ((uint32_t)pmsg->data[7] << CAN_TDH0R_DATA7_Pos) |
+                  ((uint32_t)pmsg->data[6] << CAN_TDH0R_DATA6_Pos) |
+                  ((uint32_t)pmsg->data[5] << CAN_TDH0R_DATA5_Pos) |
+                  ((uint32_t)pmsg->data[4] << CAN_TDH0R_DATA4_Pos));
+        WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDLR,
+                  ((uint32_t)pmsg->data[3] << CAN_TDL0R_DATA3_Pos) |
+                  ((uint32_t)pmsg->data[2] << CAN_TDL0R_DATA2_Pos) |
+                  ((uint32_t)pmsg->data[1] << CAN_TDL0R_DATA1_Pos) |
+                  ((uint32_t)pmsg->data[0] << CAN_TDL0R_DATA0_Pos));
+        /* Request transmission */
+        SET_BIT(hcan->Instance->sTxMailBox[box_num].TIR, CAN_TI0R_TXRQ);
+
+        return RT_EOK;
+    }
+    else
+    {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+        return -RT_ERROR;
+    }
+}
+
+static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+    HAL_StatusTypeDef status;
+    CAN_HandleTypeDef *hcan;
+    struct rt_can_msg *pmsg;
+    CAN_RxHeaderTypeDef rxheader = {0};
+
+    RT_ASSERT(can);
+
+    hcan = &((struct stm32_can *)can->parent.user_data)->CanHandle;
+    pmsg = (struct rt_can_msg *) buf;
+
+    /* get data */
+    status = HAL_CAN_GetRxMessage(hcan, fifo, &rxheader, pmsg->data);
+    if (HAL_OK != status)
+        return -RT_ERROR;
+    /* get id */
+    if (CAN_ID_STD == rxheader.IDE)
+    {
+        pmsg->ide = RT_CAN_STDID;
+        pmsg->id = rxheader.StdId;
+    }
+    else
+    {
+        pmsg->ide = RT_CAN_EXTID;
+        pmsg->id = rxheader.ExtId;
+    }
+    /* get type */
+    if (CAN_RTR_DATA == rxheader.RTR)
+    {
+        pmsg->rtr = RT_CAN_DTR;
+    }
+    else
+    {
+        pmsg->rtr = RT_CAN_RTR;
+    }
+    /* get len */
+    pmsg->len = rxheader.DLC;
+    /* get hdr */
+    if (hcan->Instance == CAN1)
+    {
+        pmsg->hdr = (rxheader.FilterMatchIndex + 1) >> 1;
+    }
+#ifdef CAN2
+    else if (hcan->Instance == CAN2)
+    {
+       pmsg->hdr = (rxheader.FilterMatchIndex >> 1) + 14;
+    }
+#endif
+
+    return RT_EOK;
+}
+
+
+static const struct rt_can_ops _can_ops =
+{
+    _can_config,
+    _can_control,
+    _can_sendmsg,
+    _can_recvmsg,
+};
+
+static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
+{
+    CAN_HandleTypeDef *hcan;
+    RT_ASSERT(can);
+    hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
+
+    switch (fifo)
+    {
+    case CAN_RX_FIFO0:
+        /* save to user list */
+        if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_MSG_PENDING))
+        {
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+        }
+        /* Check FULL flag for FIFO0 */
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_FULL))
+        {
+            /* Clear FIFO0 FULL Flag */
+            __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+        }
+
+        /* Check Overrun flag for FIFO0 */
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_OVERRUN))
+        {
+            /* Clear FIFO0 Overrun Flag */
+            __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        break;
+    case CAN_RX_FIFO1:
+        /* save to user list */
+        if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_MSG_PENDING))
+        {
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+        }
+        /* Check FULL flag for FIFO1 */
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_FULL))
+        {
+            /* Clear FIFO1 FULL Flag */
+            __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+        }
+
+        /* Check Overrun flag for FIFO1 */
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_OVERRUN))
+        {
+            /* Clear FIFO1 Overrun Flag */
+            __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        break;
+    }
+}
+
+#ifdef BSP_USING_CAN1
+/**
+ * @brief This function handles CAN1 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
+ */
+void CAN1_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    CAN_HandleTypeDef *hcan;
+    hcan = &drv_can1.CanHandle;
+    if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
+    }
+    else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
+    }
+    else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 RX0 interrupts.
+ */
+void CAN1_RX0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&drv_can1.device, CAN_RX_FIFO0);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 RX1 interrupts.
+ */
+void CAN1_RX1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&drv_can1.device, CAN_RX_FIFO1);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN1 SCE interrupts.
+ */
+void CAN1_SCE_IRQHandler(void)
+{
+    rt_uint32_t errtype;
+    CAN_HandleTypeDef *hcan;
+
+    hcan = &drv_can1.CanHandle;
+    errtype = hcan->Instance->ESR;
+
+    rt_interrupt_enter();
+    HAL_CAN_IRQHandler(hcan);
+
+    switch ((errtype & 0x70) >> 4)
+    {
+    case RT_CAN_BUS_BIT_PAD_ERR:
+        drv_can1.device.status.bitpaderrcnt++;
+        break;
+    case RT_CAN_BUS_FORMAT_ERR:
+        drv_can1.device.status.formaterrcnt++;
+        break;
+    case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
+        drv_can1.device.status.ackerrcnt++;
+        if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        break;
+    case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+    case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+        drv_can1.device.status.biterrcnt++;
+        break;
+    case RT_CAN_BUS_CRC_ERR:
+        drv_can1.device.status.crcerrcnt++;
+        break;
+    }
+
+    drv_can1.device.status.lasterrtype = errtype & 0x70;
+    drv_can1.device.status.rcverrcnt = errtype >> 24;
+    drv_can1.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+    drv_can1.device.status.errcode = errtype & 0x07;
+    hcan->Instance->MSR |= CAN_MSR_ERRI;
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+/**
+ * @brief This function handles CAN2 TX interrupts.
+ */
+void CAN2_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    CAN_HandleTypeDef *hcan;
+    hcan = &drv_can2.CanHandle;
+    if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
+    }
+    else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
+    }
+    else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
+    {
+        if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        }
+        /* Write 0 to Clear transmission status flag RQCPx */
+        SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 RX0 interrupts.
+ */
+void CAN2_RX0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&drv_can2.device, CAN_RX_FIFO0);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 RX1 interrupts.
+ */
+void CAN2_RX1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&drv_can2.device, CAN_RX_FIFO1);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN2 SCE interrupts.
+ */
+void CAN2_SCE_IRQHandler(void)
+{
+    rt_uint32_t errtype;
+    CAN_HandleTypeDef *hcan;
+
+    hcan = &drv_can2.CanHandle;
+    errtype = hcan->Instance->ESR;
+
+    rt_interrupt_enter();
+    HAL_CAN_IRQHandler(hcan);
+
+    switch ((errtype & 0x70) >> 4)
+    {
+    case RT_CAN_BUS_BIT_PAD_ERR:
+        drv_can2.device.status.bitpaderrcnt++;
+        break;
+    case RT_CAN_BUS_FORMAT_ERR:
+        drv_can2.device.status.formaterrcnt++;
+        break;
+    case RT_CAN_BUS_ACK_ERR:
+        drv_can2.device.status.ackerrcnt++;
+        if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+            rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        break;
+    case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+    case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+        drv_can2.device.status.biterrcnt++;
+        break;
+    case RT_CAN_BUS_CRC_ERR:
+        drv_can2.device.status.crcerrcnt++;
+        break;
+    }
+
+    drv_can2.device.status.lasterrtype = errtype & 0x70;
+    drv_can2.device.status.rcverrcnt = errtype >> 24;
+    drv_can2.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+    drv_can2.device.status.errcode = errtype & 0x07;
+    hcan->Instance->MSR |= CAN_MSR_ERRI;
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_CAN2 */
+
+/**
+ * @brief  Error CAN callback.
+ * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+ *         the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERROR_WARNING |
+                        CAN_IT_ERROR_PASSIVE |
+                        CAN_IT_BUSOFF |
+                        CAN_IT_LAST_ERROR_CODE |
+                        CAN_IT_ERROR |
+                        CAN_IT_RX_FIFO0_MSG_PENDING |
+                        CAN_IT_RX_FIFO0_OVERRUN |
+                        CAN_IT_RX_FIFO0_FULL |
+                        CAN_IT_RX_FIFO1_MSG_PENDING |
+                        CAN_IT_RX_FIFO1_OVERRUN |
+                        CAN_IT_RX_FIFO1_FULL |
+                        CAN_IT_TX_MAILBOX_EMPTY);
+}
+
+int rt_hw_can_init(void)
+{
+    struct can_configure config = CANDEFAULTCONFIG;
+    config.privmode = RT_CAN_MODE_NOPRIV;
+    config.ticks = 50;
+#ifdef RT_CAN_USING_HDR
+    config.maxhdr = 14;
+#ifdef CAN2
+    config.maxhdr = 28;
+#endif
+#endif
+    /* config default filter */
+    CAN_FilterTypeDef filterConf = {0};
+    filterConf.FilterIdHigh = 0x0000;
+    filterConf.FilterIdLow = 0x0000;
+    filterConf.FilterMaskIdHigh = 0x0000;
+    filterConf.FilterMaskIdLow = 0x0000;
+    filterConf.FilterFIFOAssignment = CAN_FILTER_FIFO0;
+    filterConf.FilterBank = 0;
+    filterConf.FilterMode = CAN_FILTERMODE_IDMASK;
+    filterConf.FilterScale = CAN_FILTERSCALE_32BIT;
+    filterConf.FilterActivation = ENABLE;
+    filterConf.SlaveStartFilterBank = 14;
+
+#ifdef BSP_USING_CAN1
+    filterConf.FilterBank = 0;
+
+    drv_can1.FilterConfig = filterConf;
+    drv_can1.device.config = config;
+    /* register CAN1 device */
+    rt_hw_can_register(&drv_can1.device,
+                       drv_can1.name,
+                       &_can_ops,
+                       &drv_can1);
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+    filterConf.FilterBank = filterConf.SlaveStartFilterBank;
+
+    drv_can2.FilterConfig = filterConf;
+    drv_can2.device.config = config;
+    /* register CAN2 device */
+    rt_hw_can_register(&drv_can2.device,
+                       drv_can2.name,
+                       &_can_ops,
+                       &drv_can2);
+#endif /* BSP_USING_CAN2 */
+
+    return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+#endif /* BSP_USING_CAN */
+
+/************************** end of file ******************/

bsp/stm32/libraries/HAL_Drivers/drv_can.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-05     Xeon Xu      the first version
+ * 2019-01-22     YLZ          port from stm324xx-HAL to bsp stm3210x-HAL
+ * 2019-01-26     YLZ          redefine `struct stm32_drv_can` add member `Rx1Message`
+ * 2019-02-19     YLZ          port to BSP [stm32]
+ * 2019-06-17     YLZ          modify struct stm32_drv_can.
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#define BS1SHIFT        16
+#define BS2SHIFT        20
+#define RRESCLSHIFT     0
+#define SJWSHIFT        24
+#define BS1MASK         ((0x0F) << BS1SHIFT )
+#define BS2MASK         ((0x07) << BS2SHIFT )
+#define RRESCLMASK      (0x3FF << RRESCLSHIFT )
+#define SJWMASK         (0x3 << SJWSHIFT )
+
+struct stm32_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t config_data;
+};
+#define BAUD_DATA(TYPE,NO)       ((can_baud_rate_tab[NO].config_data & TYPE##MASK))
+
+/* stm32 can device */
+struct stm32_can
+{
+    char *name;
+    CAN_HandleTypeDef CanHandle;
+    CAN_FilterTypeDef FilterConfig;
+    struct rt_can_device device;     /* inherit from can device */
+};
+
+int rt_hw_can_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_CAN_H__ */
+
+/************************** end of file ******************/

bsp/stm32/libraries/HAL_Drivers/drv_common.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#include "drv_common.h"
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+#include "drv_usart.h"
+#endif
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+#if defined (SOC_SERIES_STM32H7)
+    HAL_SYSTICK_Config((HAL_RCCEx_GetD1SysClockFreq()) / RT_TICK_PER_SECOND);
+#else
+    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
+#endif
+    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+    HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    HAL_IncTick();
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+uint32_t HAL_GetTick(void)
+{
+    return rt_tick_get() * 1000 / RT_TICK_PER_SECOND;
+}
+
+void HAL_SuspendTick(void)
+{
+}
+
+void HAL_ResumeTick(void)
+{
+}
+
+void HAL_Delay(__IO uint32_t Delay)
+{
+}
+
+/* re-implement tick interface for STM32 HAL */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+    /* Return function status */
+    return HAL_OK;
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void _Error_Handler(char *s, int num)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while(1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = SystemCoreClock / 1000000UL;
+    do {
+        now = SysTick->VAL;
+        delta = start > now ? start - now : reload + start - now;
+    } while(delta < us_tick * us);
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+#ifdef SCB_EnableICache
+    /* Enable I-Cache---------------------------------------------------------*/
+    SCB_EnableICache();
+#endif
+
+#ifdef SCB_EnableDCache
+    /* Enable D-Cache---------------------------------------------------------*/
+    SCB_EnableDCache();
+#endif
+
+    /* HAL_Init() function is called at the beginning of the program */
+    HAL_Init();
+
+    /* enable interrupt */
+    __set_PRIMASK(0);
+    /* System clock initialization */
+    SystemClock_Config();
+    /* disbale interrupt */
+    __set_PRIMASK(1);
+
+    rt_hw_systick_init();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/stm32/libraries/HAL_Drivers/drv_common.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-10-30     SummerGift        first version
+ */
+ 
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_STM32F0)
+#include "f0/dma_config.h"
+#include "f0/uart_config.h"
+#include "f0/spi_config.h"
+#include "f0/tim_config.h"
+#include "f0/pwm_config.h"
+#include "f0/adc_config.h"
+#elif defined(SOC_SERIES_STM32F1)
+#include "f1/dma_config.h"
+#include "f1/uart_config.h"
+#include "f1/spi_config.h"
+#include "f1/adc_config.h"
+#include "f1/tim_config.h"
+#include "f1/sdio_config.h"
+#include "f1/pwm_config.h"
+#include "f1/usbd_config.h"
+#include "f1/pulse_encoder_config.h"
+#elif  defined(SOC_SERIES_STM32F2)
+#include "f2/dma_config.h"
+#include "f2/uart_config.h"
+#include "f2/spi_config.h"
+#include "f2/adc_config.h"
+#include "f2/tim_config.h"
+#include "f2/sdio_config.h"
+#include "f2/pwm_config.h"	
+#elif  defined(SOC_SERIES_STM32F4)
+#include "f4/dma_config.h"
+#include "f4/uart_config.h"
+#include "f4/spi_config.h"
+#include "f4/qspi_config.h"
+#include "f4/usbd_config.h"
+#include "f4/adc_config.h"
+#include "f4/tim_config.h"
+#include "f4/sdio_config.h"
+#include "f4/pwm_config.h"
+#include "f4/pulse_encoder_config.h"
+#elif  defined(SOC_SERIES_STM32F7)
+#include "f7/dma_config.h"
+#include "f7/uart_config.h"
+#include "f7/spi_config.h"
+#include "f7/qspi_config.h"
+#include "f7/adc_config.h"
+#include "f7/tim_config.h"
+#include "f7/sdio_config.h"
+#include "f7/pwm_config.h"
+#elif  defined(SOC_SERIES_STM32L0)
+#include "l0/dma_config.h"
+#include "l0/uart_config.h"
+#elif  defined(SOC_SERIES_STM32L4)
+#include "l4/dma_config.h"
+#include "l4/uart_config.h"
+#include "l4/spi_config.h"
+#include "l4/qspi_config.h"
+#include "l4/adc_config.h"
+#include "l4/tim_config.h"
+#include "l4/sdio_config.h"
+#include "l4/pwm_config.h"
+#include "l4/usbd_config.h"
+#elif  defined(SOC_SERIES_STM32G0)
+#include "g0/dma_config.h"
+#include "g0/uart_config.h"
+#include "g0/spi_config.h"
+#include "g0/adc_config.h"
+#include "g0/tim_config.h"
+#include "g0/pwm_config.h"
+#elif  defined(SOC_SERIES_STM32G4)
+#include "g4/dma_config.h"
+#include "g4/uart_config.h"
+#include "g4/spi_config.h"
+#include "g4/qspi_config.h"
+#include "g4/usbd_config.h"
+#include "g4/adc_config.h"
+#include "g4/tim_config.h"
+#include "g4/sdio_config.h"
+#include "g4/pwm_config.h"
+#include "g4/pulse_encoder_config.h"
+#elif  defined(SOC_SERIES_STM32H7)
+#include "h7/dma_config.h"
+#include "h7/uart_config.h"
+#include "h7/spi_config.h"
+#include "h7/qspi_config.h"
+#include "h7/adc_config.h"
+#include "h7/tim_config.h"
+#include "h7/sdio_config.h"
+#include "h7/pwm_config.h"
+#include "h7/usbd_config.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_crypto.c

@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-10     Ernest       1st version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <stdlib.h>
+#include <string.h>
+#include "drv_crypto.h"
+#include "board.h"
+
+struct stm32_hwcrypto_device
+{
+    struct rt_hwcrypto_device dev;
+    struct rt_mutex mutex;
+};
+
+#if defined(BSP_USING_CRC)
+
+struct hash_ctx_des
+{
+    CRC_HandleTypeDef contex;
+};
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+static struct hwcrypto_crc_cfg  crc_backup_cfg;
+
+static int reverse_bit(rt_uint32_t n)
+{
+    n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xaaaaaaaa);
+    n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xcccccccc);
+    n = ((n >> 4) & 0x0f0f0f0f) | ((n << 4) & 0xf0f0f0f0);
+    n = ((n >> 8) & 0x00ff00ff) | ((n << 8) & 0xff00ff00);
+    n = ((n >> 16) & 0x0000ffff) | ((n << 16) & 0xffff0000);
+
+    return n;
+}
+#endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
+
+static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_uint32_t result = 0;
+    struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
+
+#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+    CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex);
+#endif
+
+    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+    if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
+    {
+        if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE)
+        {
+            HW_TypeDef->Init.GeneratingPolynomial = ctx ->crc_cfg.poly;
+        }
+        else
+        {
+            HW_TypeDef->Init.GeneratingPolynomial = DEFAULT_CRC32_POLY;
+        }
+
+        switch (ctx ->crc_cfg.flags)
+        {
+        case 0:
+            HW_TypeDef->Init.InputDataInversionMode   = CRC_INPUTDATA_INVERSION_NONE;
+            HW_TypeDef->Init.OutputDataInversionMode   = CRC_OUTPUTDATA_INVERSION_DISABLE;
+            break;
+        case CRC_FLAG_REFIN:
+            HW_TypeDef->Init.InputDataInversionMode   = CRC_INPUTDATA_INVERSION_BYTE;
+            break;
+        case CRC_FLAG_REFOUT:
+            HW_TypeDef->Init.OutputDataInversionMode   = CRC_OUTPUTDATA_INVERSION_ENABLE;
+            break;
+        case CRC_FLAG_REFIN|CRC_FLAG_REFOUT:
+            HW_TypeDef->Init.InputDataInversionMode   = CRC_INPUTDATA_INVERSION_BYTE;
+            HW_TypeDef->Init.OutputDataInversionMode   = CRC_OUTPUTDATA_INVERSION_ENABLE;
+            break;
+        default :
+            goto _exit;
+        }
+
+        HW_TypeDef->Init.CRCLength = ctx ->crc_cfg.width;
+        if (HW_TypeDef->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_DISABLE)
+        {
+            HW_TypeDef->Init.InitValue = ctx ->crc_cfg.last_val;
+        }
+
+        if (HAL_CRC_Init(HW_TypeDef) != HAL_OK)
+        {
+            goto _exit;
+        }
+        memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
+    }
+
+    if (HAL_CRC_STATE_READY != HAL_CRC_GetState(HW_TypeDef))
+    {
+        goto _exit;
+    }
+#else
+    if (ctx->crc_cfg.flags != 0 || ctx->crc_cfg.last_val != 0xFFFFFFFF || ctx->crc_cfg.xorout != 0 || length % 4 != 0)
+    {
+        goto _exit;
+    }
+    length /= 4;
+#endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
+
+    result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length);
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+    if (HW_TypeDef->Init.OutputDataInversionMode)
+    {
+        ctx ->crc_cfg.last_val = reverse_bit(result);
+    }
+    else
+    {
+        ctx ->crc_cfg.last_val = result;
+    }
+    crc_backup_cfg.last_val = ctx ->crc_cfg.last_val;
+    result = (result ? result ^ (ctx ->crc_cfg.xorout) : result);
+#endif /* defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
+
+_exit:
+    rt_mutex_release(&stm32_hw_dev->mutex);
+
+    return result;
+}
+
+static const struct hwcrypto_crc_ops crc_ops =
+{
+    .update = _crc_update,
+};
+#endif /* BSP_USING_CRC */
+
+#if defined(BSP_USING_RNG)
+static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
+{
+    rt_uint32_t gen_random = 0;
+
+    RNG_HandleTypeDef *HW_TypeDef = (RNG_HandleTypeDef *)(ctx->parent.contex);
+
+    if (HAL_OK ==  HAL_RNG_GenerateRandomNumber(HW_TypeDef, &gen_random))
+    {
+        return gen_random ;
+    }
+
+    return 0;
+}
+
+static const struct hwcrypto_rng_ops rng_ops =
+{
+    .update = _rng_rand,
+};
+#endif /* BSP_USING_RNG */
+
+static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_RNG)
+    case HWCRYPTO_TYPE_RNG:
+    {
+        RNG_HandleTypeDef *hrng = rt_calloc(1, sizeof(RNG_HandleTypeDef));
+
+        hrng->Instance = RNG;
+        HAL_RNG_Init(hrng);
+        ctx->contex = hrng;
+        ((struct hwcrypto_rng *)ctx)->ops = &rng_ops;
+
+        break;
+    }
+#endif /* BSP_USING_RNG */
+
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+    {
+        CRC_HandleTypeDef *hcrc = rt_calloc(1, sizeof(CRC_HandleTypeDef));
+        if (RT_NULL == hcrc)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+
+        hcrc->Instance = CRC;
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+        hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
+        hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;
+        hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE;
+        hcrc->Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE;
+        hcrc->InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
+#else
+        if (HAL_CRC_Init(hcrc) != HAL_OK)
+        {
+            res = -RT_ERROR;
+        }
+#endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
+        ctx->contex = hcrc;
+        ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
+        break;
+    }
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_RNG)
+    case HWCRYPTO_TYPE_RNG:
+        break;
+#endif /* BSP_USING_RNG */
+
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);			
+        HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex));
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+
+    rt_free(ctx->contex);
+}
+
+static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_RNG)
+    case HWCRYPTO_TYPE_RNG:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+        }    
+        break;
+#endif /* BSP_USING_RNG */
+
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+        }
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_RNG)
+    case HWCRYPTO_TYPE_RNG:
+        break;
+#endif /* BSP_USING_RNG */
+
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+}
+
+static const struct rt_hwcrypto_ops _ops =
+{
+    .create = _crypto_create,
+    .destroy = _crypto_destroy,
+    .copy = _crypto_clone,
+    .reset = _crypto_reset,
+};
+
+int stm32_hw_crypto_device_init(void)
+{
+    static struct stm32_hwcrypto_device _crypto_dev;
+    rt_uint32_t cpuid[3] = {0};
+
+    _crypto_dev.dev.ops = &_ops;
+#if defined(BSP_USING_UDID)
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+    cpuid[0] = HAL_GetUIDw0();
+    cpuid[1] = HAL_GetUIDw1();
+#elif defined(SOC_SERIES_STM32H7)
+    cpuid[0] = HAL_GetREVID();
+    cpuid[1] = HAL_GetDEVID();
+#endif
+
+#endif /* BSP_USING_UDID */
+
+    _crypto_dev.dev.id = 0;
+    rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
+
+    _crypto_dev.dev.user_data = &_crypto_dev;
+
+    if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+    {
+        return -1;
+    }
+    rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO);
+    return 0;
+}
+INIT_DEVICE_EXPORT(stm32_hw_crypto_device_init);

bsp/stm32/libraries/HAL_Drivers/drv_crypto.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-10     Ernest       1st version
+ */
+
+#ifndef __DRV_CRYPTO_H__
+#define __DRV_CRYPTO_H__
+
+int l4_hw_crypto_device_init(void);
+
+#endif /* __DRV_CRYPTO_H__ */

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-10     SummerGift   first version
+ */
+
+#ifndef __DRV_DMA_H_
+#define __DRV_DMA_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
+	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+#define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
+	|| defined(SOC_SERIES_STM32H7)
+#define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
+#endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
+
+struct dma_config {
+    DMA_INSTANCE_TYPE *Instance;
+    rt_uint32_t dma_rcc;
+    IRQn_Type dma_irq;
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+    rt_uint32_t channel;
+#endif
+
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+    rt_uint32_t request;
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_DMA_H_ */

bsp/stm32/libraries/HAL_Drivers/drv_eth.c

@@ -0,0 +1,659 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-19     SummerGift   first version
+ * 2018-12-25     zylx         fix some bugs
+ * 2019-06-10     SummerGift   optimize PHY state detection process
+ * 2019-09-03     xiaofan      optimize link change detection process
+ */
+
+#include "board.h"
+#include "drv_config.h"
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+/*
+* Emac driver uses CubeMX tool to generate emac and phy's configuration,
+* the configuration files can be found in CubeMX_Config floder.
+*/
+
+/* debug option */
+//#define ETH_RX_DUMP
+//#define ETH_TX_DUMP
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.emac"
+#include <drv_log.h>
+
+#define MAX_ADDR_LEN 6
+
+struct rt_stm32_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+#ifndef PHY_USING_INTERRUPT_MODE
+    rt_timer_t poll_link_timer;
+#endif
+
+    /* interface address info, hw address */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];
+    /* ETH_Speed */
+    uint32_t    ETH_Speed;
+    /* ETH_Duplex_Mode */
+    uint32_t    ETH_Mode;
+};
+
+static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
+static rt_uint8_t *Rx_Buff, *Tx_Buff;
+static  ETH_HandleTypeDef EthHandle;
+static struct rt_stm32_eth stm32_eth_device;
+
+#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    int i, j;
+
+    for (i = 0; i < buflen; i += 16)
+    {
+        rt_kprintf("%08X: ", i);
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen)
+                rt_kprintf("%02X ", buf[i + j]);
+            else
+                rt_kprintf("   ");
+        rt_kprintf(" ");
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen)
+                rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+        rt_kprintf("\n");
+    }
+}
+#endif
+
+extern void phy_reset(void);
+/* EMAC initialization function */
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+    __HAL_RCC_ETH_CLK_ENABLE();
+
+    phy_reset();
+
+    /* ETHERNET Configuration */
+    EthHandle.Instance = ETH;
+    EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
+    EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
+    EthHandle.Init.Speed = ETH_SPEED_100M;
+    EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
+    EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
+    EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
+#ifdef RT_LWIP_USING_HW_CHECKSUM
+    EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
+#else
+    EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
+#endif
+
+    HAL_ETH_DeInit(&EthHandle);
+
+    /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
+    if (HAL_ETH_Init(&EthHandle) != HAL_OK)
+    {
+        LOG_E("eth hardware init failed");
+    }
+    else
+    {
+        LOG_D("eth hardware init success");
+    }
+
+    /* Initialize Tx Descriptors list: Chain Mode */
+    HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, Tx_Buff, ETH_TXBUFNB);
+
+    /* Initialize Rx Descriptors list: Chain Mode  */
+    HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
+
+    /* ETH interrupt Init */
+    HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
+    HAL_NVIC_EnableIRQ(ETH_IRQn);
+
+    /* Enable MAC and DMA transmission and reception */
+    if (HAL_ETH_Start(&EthHandle) == HAL_OK)
+    {
+        LOG_D("emac hardware start");
+    }
+    else
+    {
+        LOG_E("emac hardware start faild");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    LOG_D("emac open");
+    return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+    LOG_D("emac close");
+    return RT_EOK;
+}
+
+static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    LOG_D("emac read");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    LOG_D("emac write");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
+{
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit data*/
+rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+    rt_err_t ret = RT_ERROR;
+    HAL_StatusTypeDef state;
+    struct pbuf *q;
+    uint8_t *buffer = (uint8_t *)(EthHandle.TxDesc->Buffer1Addr);
+    __IO ETH_DMADescTypeDef *DmaTxDesc;
+    uint32_t framelength = 0;
+    uint32_t bufferoffset = 0;
+    uint32_t byteslefttocopy = 0;
+    uint32_t payloadoffset = 0;
+
+    DmaTxDesc = EthHandle.TxDesc;
+    bufferoffset = 0;
+
+    /* copy frame from pbufs to driver buffers */
+    for (q = p; q != NULL; q = q->next)
+    {
+        /* Is this buffer available? If not, goto error */
+        if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+        {
+            LOG_D("buffer not valid");
+            ret = ERR_USE;
+            goto error;
+        }
+
+        /* Get bytes in current lwIP buffer */
+        byteslefttocopy = q->len;
+        payloadoffset = 0;
+
+        /* Check if the length of data to copy is bigger than Tx buffer size*/
+        while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
+        {
+            /* Copy data to Tx buffer*/
+            memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
+
+            /* Point to next descriptor */
+            DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
+
+            /* Check if the buffer is available */
+            if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+            {
+                LOG_E("dma tx desc buffer is not valid");
+                ret = ERR_USE;
+                goto error;
+            }
+
+            buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
+
+            byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
+            payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
+            framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
+            bufferoffset = 0;
+        }
+
+        /* Copy the remaining bytes */
+        memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
+        bufferoffset = bufferoffset + byteslefttocopy;
+        framelength = framelength + byteslefttocopy;
+    }
+
+#ifdef ETH_TX_DUMP
+    dump_hex(buffer, p->tot_len);
+#endif
+
+    /* Prepare transmit descriptors to give to DMA */
+    /* TODO Optimize data send speed*/
+    LOG_D("transmit frame lenth :%d", framelength);
+
+    /* wait for unlocked */
+    while (EthHandle.Lock == HAL_LOCKED);
+
+    state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
+    if (state != HAL_OK)
+    {
+        LOG_E("eth transmit frame faild: %d", state);
+    }
+
+    ret = ERR_OK;
+
+error:
+
+    /* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
+    if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
+    {
+        /* Clear TUS ETHERNET DMA flag */
+        EthHandle.Instance->DMASR = ETH_DMASR_TUS;
+
+        /* Resume DMA transmission*/
+        EthHandle.Instance->DMATPDR = 0;
+    }
+
+    return ret;
+}
+
+/* receive data*/
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+
+    struct pbuf *p = NULL;
+    struct pbuf *q = NULL;
+    HAL_StatusTypeDef state;
+    uint16_t len = 0;
+    uint8_t *buffer;
+    __IO ETH_DMADescTypeDef *dmarxdesc;
+    uint32_t bufferoffset = 0;
+    uint32_t payloadoffset = 0;
+    uint32_t byteslefttocopy = 0;
+    uint32_t i = 0;
+
+    /* Get received frame */
+    state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
+    if (state != HAL_OK)
+    {
+        LOG_D("receive frame faild");
+        return NULL;
+    }
+
+    /* Obtain the size of the packet and put it into the "len" variable. */
+    len = EthHandle.RxFrameInfos.length;
+    buffer = (uint8_t *)EthHandle.RxFrameInfos.buffer;
+
+    LOG_D("receive frame len : %d", len);
+
+    if (len > 0)
+    {
+        /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
+        p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+    }
+
+#ifdef ETH_RX_DUMP
+    dump_hex(buffer, p->tot_len);
+#endif
+
+    if (p != NULL)
+    {
+        dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
+        bufferoffset = 0;
+        for (q = p; q != NULL; q = q->next)
+        {
+            byteslefttocopy = q->len;
+            payloadoffset = 0;
+
+            /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
+            while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
+            {
+                /* Copy data to pbuf */
+                memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
+
+                /* Point to next descriptor */
+                dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
+                buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
+
+                byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
+                payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
+                bufferoffset = 0;
+            }
+            /* Copy remaining data in pbuf */
+            memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
+            bufferoffset = bufferoffset + byteslefttocopy;
+        }
+    }
+
+    /* Release descriptors to DMA */
+    /* Point to first descriptor */
+    dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
+    /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
+    for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++)
+    {
+        dmarxdesc->Status |= ETH_DMARXDESC_OWN;
+        dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
+    }
+
+    /* Clear Segment_Count */
+    EthHandle.RxFrameInfos.SegCount = 0;
+
+    /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+    if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+    {
+        /* Clear RBUS ETHERNET DMA flag */
+        EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
+        /* Resume DMA reception */
+        EthHandle.Instance->DMARPDR = 0;
+    }
+
+    return p;
+}
+
+/* interrupt service routine */
+void ETH_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    HAL_ETH_IRQHandler(&EthHandle);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+    rt_err_t result;
+    result = eth_device_ready(&(stm32_eth_device.parent));
+    if (result != RT_EOK)
+        LOG_I("RxCpltCallback err = %d", result);
+}
+
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+    LOG_E("eth err");
+}
+
+enum {
+    PHY_LINK        = (1 << 0),
+    PHY_100M        = (1 << 1),
+    PHY_FULL_DUPLEX = (1 << 2),
+};
+
+static void phy_linkchange()
+{
+    static rt_uint8_t phy_speed = 0;
+    rt_uint8_t phy_speed_new = 0;
+    rt_uint32_t status;
+
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
+    LOG_D("phy basic status reg is 0x%X", status);
+
+    if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
+    {
+        rt_uint32_t SR;
+
+        phy_speed_new |= PHY_LINK;
+
+        SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
+        LOG_D("phy control status reg is 0x%X", SR);
+
+        if (PHY_Status_SPEED_100M(SR))
+        {
+            phy_speed_new |= PHY_100M;
+        }
+
+        if (PHY_Status_FULL_DUPLEX(SR))
+        {
+            phy_speed_new |= PHY_FULL_DUPLEX;
+        }
+    }
+
+    if (phy_speed != phy_speed_new)
+    {
+        phy_speed = phy_speed_new;
+        if (phy_speed & PHY_LINK)
+        {
+            LOG_D("link up");
+            if (phy_speed & PHY_100M)
+            {
+                LOG_D("100Mbps");
+                stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
+            }
+            else
+            {
+                stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
+                LOG_D("10Mbps");
+            }
+
+            if (phy_speed & PHY_FULL_DUPLEX)
+            {
+                LOG_D("full-duplex");
+                stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
+            }
+            else
+            {
+                LOG_D("half-duplex");
+                stm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX;
+            }
+
+            /* send link up. */
+            eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+        }
+        else
+        {
+            LOG_I("link down");
+            eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
+        }
+    }
+}
+
+#ifdef PHY_USING_INTERRUPT_MODE
+static void eth_phy_isr(void *args)
+{
+    rt_uint32_t status = 0;
+
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
+    LOG_D("phy interrupt status reg is 0x%X", status);
+
+    phy_linkchange();
+}
+#endif /* PHY_USING_INTERRUPT_MODE */
+
+static void phy_monitor_thread_entry(void *parameter)
+{
+    uint8_t phy_addr = 0xFF;
+    uint8_t detected_count = 0;
+
+    while(phy_addr == 0xFF)
+    {
+        /* phy search */
+        rt_uint32_t i, temp;
+        for (i = 0; i <= 0x1F; i++)
+        {
+            EthHandle.Init.PhyAddress = i;
+            HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp);
+
+            if (temp != 0xFFFF && temp != 0x00)
+            {
+                phy_addr = i;
+                break;
+            }
+        }
+
+        detected_count++;
+        rt_thread_mdelay(1000);
+
+        if (detected_count > 10)
+        {
+            LOG_E("No PHY device was detected, please check hardware!");
+        }
+    }
+
+    LOG_D("Found a phy, address:0x%02X", phy_addr);
+
+    /* RESET PHY */
+    LOG_D("RESET PHY!");
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
+    rt_thread_mdelay(2000);
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
+
+    phy_linkchange();
+#ifdef PHY_USING_INTERRUPT_MODE
+    /* configuration intterrupt pin */
+    rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
+    rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
+
+    /* enable phy interrupt */
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
+#if defined(PHY_INTERRUPT_CTRL_REG)
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
+#endif
+#else /* PHY_USING_INTERRUPT_MODE */
+    stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
+                                        NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
+    if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
+    {
+        LOG_E("Start link change detection timer failed");
+    }
+#endif /* PHY_USING_INTERRUPT_MODE */
+}
+
+/* Register the EMAC device */
+static int rt_hw_stm32_eth_init(void)
+{
+    rt_err_t state = RT_EOK;
+
+    /* Prepare receive and send buffers */
+    Rx_Buff = (rt_uint8_t *)rt_calloc(ETH_RXBUFNB, ETH_MAX_PACKET_SIZE);
+    if (Rx_Buff == RT_NULL)
+    {
+        LOG_E("No memory");
+        state = -RT_ENOMEM;
+        goto __exit;
+    }
+
+    Tx_Buff = (rt_uint8_t *)rt_calloc(ETH_TXBUFNB, ETH_MAX_PACKET_SIZE);
+    if (Tx_Buff == RT_NULL)
+    {
+        LOG_E("No memory");
+        state = -RT_ENOMEM;
+        goto __exit;
+    }
+
+    DMARxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
+    if (DMARxDscrTab == RT_NULL)
+    {
+        LOG_E("No memory");
+        state = -RT_ENOMEM;
+        goto __exit;
+    }
+
+    DMATxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
+    if (DMATxDscrTab == RT_NULL)
+    {
+        LOG_E("No memory");
+        state = -RT_ENOMEM;
+        goto __exit;
+    }
+
+    stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
+    stm32_eth_device.ETH_Mode  = ETH_MODE_FULLDUPLEX;
+
+    /* OUI 00-80-E1 STMICROELECTRONICS. */
+    stm32_eth_device.dev_addr[0] = 0x00;
+    stm32_eth_device.dev_addr[1] = 0x80;
+    stm32_eth_device.dev_addr[2] = 0xE1;
+    /* generate MAC addr from 96bit unique ID (only for test). */
+    stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
+    stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
+    stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
+
+    stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
+    stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
+    stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
+    stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
+    stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
+    stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
+    stm32_eth_device.parent.parent.user_data  = RT_NULL;
+
+    stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
+    stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;
+
+    /* register eth device */
+    state = eth_device_init(&(stm32_eth_device.parent), "e0");
+    if (RT_EOK == state)
+    {
+        LOG_D("emac device init success");
+    }
+    else
+    {
+        LOG_E("emac device init faild: %d", state);
+        state = -RT_ERROR;
+        goto __exit;
+    }
+
+    /* start phy monitor */
+    rt_thread_t tid;
+    tid = rt_thread_create("phy",
+                           phy_monitor_thread_entry,
+                           RT_NULL,
+                           1024,
+                           RT_THREAD_PRIORITY_MAX - 2,
+                           2);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        state = -RT_ERROR;
+    }
+__exit:
+    if (state != RT_EOK)
+    {
+        if (Rx_Buff)
+        {
+            rt_free(Rx_Buff);
+        }
+
+        if (Tx_Buff)
+        {
+            rt_free(Tx_Buff);
+        }
+
+        if (DMARxDscrTab)
+        {
+            rt_free(DMARxDscrTab);
+        }
+
+        if (DMATxDscrTab)
+        {
+            rt_free(DMATxDscrTab);
+        }
+    }
+
+    return state;
+}
+INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);

bsp/stm32/libraries/HAL_Drivers/drv_eth.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-25     zylx         first version
+ */
+
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG       0x00U
+#define PHY_RESET_MASK              (1<<15)
+#define PHY_AUTO_NEGOTIATION_MASK   (1<<12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG        0x01U
+#define PHY_LINKED_STATUS_MASK      (1<<2)
+#define PHY_AUTONEGO_COMPLETE_MASK  (1<<5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG                 0x02U
+
+/* The PHY ID two register */
+#define PHY_ID2_REG                 0x03U
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG   0x04U
+
+#ifdef PHY_USING_LAN8720A
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x1DU
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x1EU
+#define PHY_LINK_DOWN_MASK          (1<<4)
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
+
+/*  The PHY status register. */
+#define PHY_Status_REG              0x1FU
+#define PHY_10M_MASK                (1<<2)
+#define PHY_100M_MASK               (1<<3)
+#define PHY_FULL_DUPLEX_MASK        (1<<4)
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   ((sr) & PHY_100M_MASK)
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+#endif /* PHY_USING_LAN8720A */
+
+#ifdef PHY_USING_DM9161CEP
+#define PHY_Status_REG              0x11U
+#define PHY_10M_MASK                ((1<<12) || (1<<13))
+#define PHY_100M_MASK               ((1<<14) || (1<<15))
+#define PHY_FULL_DUPLEX_MASK        ((1<<15) || (1<<13))
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   ((sr) & PHY_100M_MASK)
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x15U
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x15U
+#define PHY_LINK_CHANGE_FLAG        (1<<2)
+#define PHY_LINK_CHANGE_MASK        (1<<9)
+#define PHY_INT_MASK                0
+
+#endif /* PHY_USING_DM9161CEP */
+
+#ifdef PHY_USING_DP83848C
+#define PHY_Status_REG              0x10U
+#define PHY_10M_MASK                (1<<1)
+#define PHY_FULL_DUPLEX_MASK        (1<<2)
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   (!PHY_Status_SPEED_10M(sr))
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x12U
+#define PHY_LINK_CHANGE_FLAG        (1<<13)
+/*  The PHY interrupt control register. */
+#define PHY_INTERRUPT_CTRL_REG      0x11U
+#define PHY_INTERRUPT_EN            ((1<<0)|(1<<1))
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x12U
+#define PHY_INT_MASK                (1<<5)
+#endif /* PHY_USING_DP83848C */
+
+#endif /* __DRV_ETH_H__ */

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int stm32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c

@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t addr)
+{
+    uint32_t page = 0;
+    page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result        = RT_EOK;
+    rt_uint32_t end_addr   = addr + size;
+
+    if (addr % 4 != 0)
+    {
+        LOG_E("write addr must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    while (addr < end_addr)
+    {
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
+        {
+            if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            addr += 4;
+            buf  += 4;
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(rt_uint32_t addr, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    uint32_t PAGEError = 0;
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = GetPage(addr);
+    EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+    return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
+}
+
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */