entry_gcc.S 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-05-29 tanek first implementation
  9. */
  10. .section .text.entry
  11. .align 2
  12. .global trap_entry
  13. trap_entry:
  14. // save all from thread context
  15. addi sp, sp, -32 * 4
  16. sw x1, 1 * 4(sp)
  17. li t0, 0x80
  18. sw t0, 2 * 4(sp)
  19. sw x4, 4 * 4(sp)
  20. sw x5, 5 * 4(sp)
  21. sw x6, 6 * 4(sp)
  22. sw x7, 7 * 4(sp)
  23. sw x8, 8 * 4(sp)
  24. sw x9, 9 * 4(sp)
  25. sw x10, 10 * 4(sp)
  26. sw x11, 11 * 4(sp)
  27. sw x12, 12 * 4(sp)
  28. sw x13, 13 * 4(sp)
  29. sw x14, 14 * 4(sp)
  30. sw x15, 15 * 4(sp)
  31. sw x16, 16 * 4(sp)
  32. sw x17, 17 * 4(sp)
  33. sw x18, 18 * 4(sp)
  34. sw x19, 19 * 4(sp)
  35. sw x20, 20 * 4(sp)
  36. sw x21, 21 * 4(sp)
  37. sw x22, 22 * 4(sp)
  38. sw x23, 23 * 4(sp)
  39. sw x24, 24 * 4(sp)
  40. sw x25, 25 * 4(sp)
  41. sw x26, 26 * 4(sp)
  42. sw x27, 27 * 4(sp)
  43. sw x28, 28 * 4(sp)
  44. sw x29, 29 * 4(sp)
  45. sw x30, 30 * 4(sp)
  46. sw x31, 31 * 4(sp)
  47. // switch to interrupt stack
  48. move s0, sp
  49. la sp, _sp
  50. // interrupt handle
  51. call rt_interrupt_enter
  52. csrr a0, mcause
  53. csrr a1, mepc
  54. mv a2, sp
  55. call handle_trap
  56. call rt_interrupt_leave
  57. // switch to from thread stack
  58. move sp, s0
  59. // need to switch new thread
  60. la s0, rt_thread_switch_interrupt_flag
  61. lw s2, 0(s0)
  62. beqz s2, spurious_interrupt
  63. sw zero, 0(s0)
  64. csrr a0, mepc
  65. sw a0, 0 * 4(sp)
  66. la s0, rt_interrupt_from_thread
  67. lw s1, 0(s0)
  68. sw sp, 0(s1)
  69. la s0, rt_interrupt_to_thread
  70. lw s1, 0(s0)
  71. lw sp, 0(s1)
  72. lw a0, 0 * 4(sp)
  73. csrw mepc, a0
  74. spurious_interrupt:
  75. lw x1, 1 * 4(sp)
  76. // Remain in M-mode after mret
  77. li t0, 0x00001800
  78. csrs mstatus, t0
  79. lw t0, 2 * 4(sp)
  80. csrs mstatus, t0
  81. lw x4, 4 * 4(sp)
  82. lw x5, 5 * 4(sp)
  83. lw x6, 6 * 4(sp)
  84. lw x7, 7 * 4(sp)
  85. lw x8, 8 * 4(sp)
  86. lw x9, 9 * 4(sp)
  87. lw x10, 10 * 4(sp)
  88. lw x11, 11 * 4(sp)
  89. lw x12, 12 * 4(sp)
  90. lw x13, 13 * 4(sp)
  91. lw x14, 14 * 4(sp)
  92. lw x15, 15 * 4(sp)
  93. lw x16, 16 * 4(sp)
  94. lw x17, 17 * 4(sp)
  95. lw x18, 18 * 4(sp)
  96. lw x19, 19 * 4(sp)
  97. lw x20, 20 * 4(sp)
  98. lw x21, 21 * 4(sp)
  99. lw x22, 22 * 4(sp)
  100. lw x23, 23 * 4(sp)
  101. lw x24, 24 * 4(sp)
  102. lw x25, 25 * 4(sp)
  103. lw x26, 26 * 4(sp)
  104. lw x27, 27 * 4(sp)
  105. lw x28, 28 * 4(sp)
  106. lw x29, 29 * 4(sp)
  107. lw x30, 30 * 4(sp)
  108. lw x31, 31 * 4(sp)
  109. addi sp, sp, 32 * 4
  110. mret
  111. .weak handle_trap
  112. handle_trap:
  113. 1:
  114. j 1b