update to 3.1.5

.github/workflows/action.yml

@@ -0,0 +1,140 @@
+name: RT-Thread
+
+# Controls when the action will run. Triggers the workflow on push or pull request
+# events but only for the lts-v3.1.x branch
+on:
+  # Runs at 16:00 UTC (BeiJing 00:00) on the 1st of every month
+  schedule:
+    - cron:  '0 16 1 * *'
+  push:
+    branches:
+      - lts-v3.1.x
+    paths-ignore:
+      - documentation/**
+      - '**/README.md'
+      - '**/README_zh.md'
+  pull_request:
+    branches:
+      - lts-v3.1.x
+    paths-ignore:
+      - documentation/**
+      - '**/README.md'
+      - '**/README_zh.md'
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    name: ${{ matrix.legs.RTT_BSP }}
+    strategy:
+      fail-fast: false
+      matrix:
+       legs:
+         - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}         
+         - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm4f232", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc43xx/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc178x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc408x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-lyc8", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f427-robomaster-a", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
+
+    steps:
+      - uses: actions/checkout@v2
+      - name: Set up Python
+        uses: actions/setup-python@master
+        with:
+          python-version: 3.8
+
+      - name: Install Tools
+        shell: bash
+        run: |
+          sudo apt-get update
+          sudo apt-get -qq install gcc-multilib libsdl-dev scons
+          echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
+          echo "RTT_CC=gcc" >> $GITHUB_ENV
+    
+      - name: Install Arm ToolChains
+        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
+        shell: bash
+        run: |
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 
+          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt  
+          /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
+          echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
+
+      - name: Install Mips ToolChains
+        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
+        shell: bash
+        run: |
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 
+          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt  
+          /opt/mips-2016.05/bin/mips-sde-elf-gcc --version
+          echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
+
+      - name: Bsp Scons Compile
+        if: ${{ success() }}
+        shell: bash
+        env:
+          RTT_BSP: ${{ matrix.legs.RTT_BSP }}
+          RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }}
+        run: |
+          scons -C bsp/$RTT_BSP

.travis.yml

@@ -1,125 +0,0 @@
-language: c
-
-notifications:
-  email: false
-
-before_script:
-# travis has changed to 64-bit and we require 32-bit compatibility libraries
-  - sudo apt-get update
-  # clang
-  - "sudo apt-get -qq install gcc-multilib libc6:i386 libgcc1:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev scons || true"
-  # - sudo apt-get -qq install gcc-arm-none-eabi
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 && sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
-  - export RTT_ROOT=`pwd`
-  - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
-
-env:
-#  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
-  - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
-#  - RTT_BSP='bf533' # no scons
-  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='es32f0334' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-#  - RTT_BSP='es32f0654' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-atk-commander' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-fire-pro' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-nxp-evk' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc824' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc54114-lite' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-#  - RTT_BSP='m16c62p' # m32c
-  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='microblaze' # no scons
-  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='mini4020' # no scons
-#  - RTT_BSP='mm32l07x' # not support gcc
-#  - RTT_BSP='nios_ii' # no scons
-  - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='pic32ethernet' # no scons
-  - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='simulator' # x86
-  - RTT_BSP='stm32/stm32f072-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-M3S' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-yf-ufun' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f427-robomaster-a' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f469-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g431-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
-#  - RTT_BSP='upd70f3454' # iar
-#  - RTT_BSP='x86' # x86
-  - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
-
-stage: compile
-script:
-  - scons -C bsp/$RTT_BSP

ChangeLog.md

@@ -1,3 +1,89 @@
+# RT-Thread v3.1.5 Change Log
+
+Change log since v3.1.4
+
+## Kernel
+
+* Fix the issue when block = NULL in rt_mp_free;
+* Fix the software issue when the system timer thread is pending
+* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
+* Fix an issue with rt_timer_start being broken and destroying the timer list
+* Fix bug of rt_memheap_detach
+* Fix the bug that the linked list is still mounted when the single timer is not modified
+* Fix the delay_until issue
+* Add mb mq value overflow-check code
+* Fix the rt_event_recv function, if the event met without blocking, assigning thread->event_set/event_info will goes well
+* Add the definition of the maximum value of ipc type
+* Fix the delay_until issue
+* fixed __rt_ffs bug on account of armclang LTO.
+* fixed rt_timer_list_next_timeout multi-task safe
+* fix the software issue when the system timer thread pending.
+* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
+* The cleanup operation is executed before the current thread exits
+* Modify cleanup to resolve the issue of unable to free memory and communication between threads
+* Fix double release for thread
+* Fix thread control bug about `RT_THREAD_CTRL_CLOSE` command
+* Fix the issue of critical protection when `rt_thread_delete` change the status of thread;
+* Fix bug in rt_realloc of mem.c, which may cause memory leak
+* Use object_find to implement thread_find/device_find
+* fix the timer code depends on c99
+
+## Components
+
+* Change rt_data_queue_peak to rt_data_queue_peek.
+* Add rt_data_queue_deinit and fix bug of dataqueue
+* Solve the issue that the do_pollfd function processing the underlying network device returns error -1
+* Fix the issue that when the network card device calls to close dhcp, the bottom layer no need to call the dhcp_stop function to close dhcp
+* Modify the spelling error of the macro definition, modify the printing error when printing the IMEI number
+* Fix the issue that the server closed the connection when web socket requests the data that comes back from the server, and the socket status is incorrectly judged at that point
+* Fix the issue of incorrect sal_getaddrinfo release when sal socket supports multiple network cards
+* Adjust where the AT socket callback function
+* Fix at_client, avoid creating the same client repeatedly and prevent working exceptions and memory leaks.
+* Fix the bug that rx_notice out of sync when the data is received after last rt_device_read() is zero
+* Change the header file included in some libc files from <rtthread.h> to <rtconfig.h> to narrow the scope of inclusion to prevent recursive compilation
+* [jffs2] modify the error check of rt_event_recv()
+* [audio] Fix compile warning, undefine var, and fixed re-include of audio
+* [serial] Fix the crash caused when the serial port receiving buffer is full and ULOG_USING_ISR_LOG is not turned on
+* [spi] Fix "response+1" causing hard fault of unaligned access to SPI memory of STM32 HAL library
+* [hwtimer] When getting the timer count, prevent overflow update due to the interruption
+* [dirver/i2c] i2c driver supports bus lock, STOP control
+* [usb] Fix bug in device descriptor that MAC OS enumeration failed
+* Fix the bug that USB cannot recognize composite device normally
+* Fix USB host core bugs
+  * Limit >4 USB ports hubs
+  * Double free intf
+  * dname buffer size is too small
+  * Reset child pointer after detaching instance
+* remove jffs
+* remove uffs
+
+## BSP and CPU porting
+
+* Add license info and code cleanup for vexpress-a9 BSP
+* Fix spelling mistakes of code
+* [allwinner_tina]Fix spi driver bug
+* Optimize BSP dist handle process
+* fixed a bug that caused system crash by changing the run_mode in low power mode
+* drv_flash_f7.c supports single bank mode
+* Optimize the pin-index algorithm for stm32
+* Fix the clock configuration issue of STM32 hardware timer
+* Adjust the interrupt priority configuration of some peripherals of the STM32 series BSP
+* Fix stm32 f1 series rtc bug
+* Fix PWM timer init about pwm
+* remove zynq7000
+* delete stm32f20x/fh8620/gkipc/realview-a8
+* update sam7x/simulator/qemu-vexpress-a9/imx6ul
+* add Copyright_Notice.md
+
+## Tools
+
+* Fixed python 2.x `cmp`
+* Rename GCC_VERSION to GCC_VERSION_STR
+* Optimize project group sort by name
+* Improve the logic of generating `rtconfig.h` files in scons with command `scons --menuconfig`
+* Fixed an issue that *.s src files couldn't be compiled
+* Fixed c99/siginfo_t issue caused by gcc_version
+
 # RT-Thread v3.1.4 Change Log
 
 Change log since v3.1.3

bsp/qemu-vexpress-a9/applications/SConscript

@@ -1,10 +1,8 @@
-Import('RTT_ROOT')
-Import('rtconfig')
 from building import *
 
 cwd     = GetCurrentDir()
 src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
+CPPPATH = [cwd]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 

bsp/qemu-vexpress-a9/applications/lcd_init.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <rtthread.h>
 
 #if defined(RT_USING_RTGUI) || defined(PKG_USING_GUIENGINE)

bsp/qemu-vexpress-a9/applications/main.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>

bsp/qemu-vexpress-a9/applications/mnt.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <rtthread.h>
 
 #ifdef RT_USING_DFS

bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_ac97.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_ac97.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,33 +12,33 @@
 #define __DRV_AC97_H__
 
 /* Register offsets */
-#define AC97_RESET				0x00
-#define AC97_MASTER				0x02
-#define AC97_HEADPHONE			0x04
-#define AC97_MASTER_MONO		0x06
-#define AC97_MASTER_TONE		0x08
-#define AC97_PC_BEEP			0x0A    //mixer volume
-#define AC97_PHONE				0x0C
-#define AC97_MIC				0x0E    //qwert db
-#define AC97_LINE				0x10		
-#define AC97_CD					0x12
-#define AC97_VIDEO				0x14
-#define AC97_AUX				0x16
-#define AC97_PCM				0x18
-#define AC97_REC_SEL			0x1A	//0 represent mic
-#define AC97_REC_GAIN			0x1C
-#define AC97_REC_GAIN_MIC		0x1E
-#define AC97_GENERAL_PURPOSE	0x20
-#define AC97_3D_CONTROL			0x22
-#define AC97_INT_PAGING			0x24    //qwert
-#define AC97_POWERDOWN			0x26
-#define AC97_PCM_FRONT_DAC_RATE 0x2c	/* PCM Front DAC Rate */
-#define AC97_PCM_SURR_DAC_RATE	0x2e	/* PCM Surround DAC Rate */
-#define AC97_PCM_LFE_DAC_RATE	0x30	/* PCM LFE DAC Rate */
-#define AC97_PCM_LR_ADC_RATE	0x32	/* PCM LR ADC Rate */
-#define AC97_PCM_MIC_ADC_RATE	0x34	/* PCM MIC ADC Rate */
-#define AC97_DAC_SLOT_MAP		0x6C
-#define AC97_ADC_SLOT_MAP		0x6E
+#define AC97_RESET              0x00
+#define AC97_MASTER             0x02
+#define AC97_HEADPHONE          0x04
+#define AC97_MASTER_MONO        0x06
+#define AC97_MASTER_TONE        0x08
+#define AC97_PC_BEEP            0x0A    //mixer volume
+#define AC97_PHONE              0x0C
+#define AC97_MIC                0x0E    //qwert db
+#define AC97_LINE               0x10
+#define AC97_CD                 0x12
+#define AC97_VIDEO              0x14
+#define AC97_AUX                0x16
+#define AC97_PCM                0x18
+#define AC97_REC_SEL            0x1A    //0 represent mic
+#define AC97_REC_GAIN           0x1C
+#define AC97_REC_GAIN_MIC       0x1E
+#define AC97_GENERAL_PURPOSE    0x20
+#define AC97_3D_CONTROL         0x22
+#define AC97_INT_PAGING         0x24    //qwert
+#define AC97_POWERDOWN          0x26
+#define AC97_PCM_FRONT_DAC_RATE 0x2c    /* PCM Front DAC Rate */
+#define AC97_PCM_SURR_DAC_RATE  0x2e    /* PCM Surround DAC Rate */
+#define AC97_PCM_LFE_DAC_RATE   0x30    /* PCM LFE DAC Rate */
+#define AC97_PCM_LR_ADC_RATE    0x32    /* PCM LR ADC Rate */
+#define AC97_PCM_MIC_ADC_RATE   0x34    /* PCM MIC ADC Rate */
+#define AC97_DAC_SLOT_MAP       0x6C
+#define AC97_ADC_SLOT_MAP       0x6E
 
 void ac97_reset(void);
 rt_err_t ac97_set_vol(int vol);

bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_pl041.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,7 +22,7 @@
 #include <rtdbg.h>
 
 #define FRAME_PERIOD_US    (50)
-#define PL041_CHANNLE_NUM  (4)
+#define PL041_CHANNEL_NUM  (4)
 
 #define PL041_READ(_a)        (*(volatile rt_uint32_t *)(_a))
 #define PL041_WRITE(_a, _v)   (*(volatile rt_uint32_t *)(_a) = (_v))
@@ -47,7 +33,7 @@ struct pl041_irq_def
     void *user_data;
 };
 
-static struct pl041_irq_def irq_tbl[PL041_CHANNLE_NUM];
+static struct pl041_irq_def irq_tbl[PL041_CHANNEL_NUM];
 
 static void aaci_pl041_delay(rt_uint32_t us)
 {
@@ -169,13 +155,13 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg)
     return v;
 }
 
-int aaci_pl041_channle_disable(int channle)
+int aaci_pl041_channel_disable(int channel)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = PL041_READ(p_rx);
     v &= ~AACI_CR_EN;
     PL041_WRITE(p_rx, v);
@@ -185,13 +171,13 @@ int aaci_pl041_channle_disable(int channle)
     return 0;
 }
 
-int aaci_pl041_channle_enable(int channle)
+int aaci_pl041_channel_enable(int channel)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = PL041_READ(p_rx);
     v |= AACI_CR_EN;
     PL041_WRITE(p_rx, v);
@@ -201,13 +187,13 @@ int aaci_pl041_channle_enable(int channle)
     return 0;
 }
 
-int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
+int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count)
 {
     void *p_data, *p_status;
     int i = 0;
 
-    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
+    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
     for (i = 0; (!(PL041_READ(p_status) & AACI_SR_RXFE)) && (i < count); i++)
     {
         buff[i] = (rt_uint16_t)PL041_READ(p_data);
@@ -215,13 +201,13 @@ int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
     return i;
 }
 
-int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
+int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count)
 {
     void *p_data, *p_status;
     int i = 0;
 
-    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
+    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
     for (i = 0; (!(PL041_READ(p_status) & AACI_SR_TXFF)) && (i < count); i++)
     {
         PL041_WRITE(p_data, buff[i]);
@@ -229,13 +215,13 @@ int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
     return i;
 }
 
-int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
+int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cgf)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->itype;
     PL041_WRITE(p_rx, v);
     v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->otype;
@@ -247,86 +233,86 @@ int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
     return 0;
 }
 
-void aaci_pl041_irq_enable(int channle, rt_uint32_t vector)
+void aaci_pl041_irq_enable(int channel, rt_uint32_t vector)
 {
     rt_uint32_t v;
     void *p_irq;
 
     vector &= vector & 0x7f;
-    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
+    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
     v = PL041_READ(p_irq);
     v |= vector;
     PL041_WRITE(p_irq, v);
 }
 
-void aaci_pl041_irq_disable(int channle, rt_uint32_t vector)
+void aaci_pl041_irq_disable(int channel, rt_uint32_t vector)
 {
     rt_uint32_t v;
     void *p_irq;
 
     vector &= vector & 0x7f;
-    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
+    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
     v = PL041_READ(p_irq);
     v &= ~vector;
     PL041_WRITE(p_irq, v);
 }
 
-rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data)
+rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data)
 {
-    if (channle < 0 || channle >= PL041_CHANNLE_NUM)
+    if (channel < 0 || channel >= PL041_CHANNEL_NUM)
     {
-        LOG_E("%s channle:%d err.", __FUNCTION__, channle);
+        LOG_E("%s channel:%d err.", __FUNCTION__, channel);
         return -RT_ERROR;
     }
-    irq_tbl[channle].fun = fun;
-    irq_tbl[channle].user_data = user_data;
+    irq_tbl[channel].fun = fun;
+    irq_tbl[channel].user_data = user_data;
     return RT_EOK;
 }
 
-rt_err_t aaci_pl041_irq_unregister(int channle)
+rt_err_t aaci_pl041_irq_unregister(int channel)
 {
-    if (channle < 0 || channle >= PL041_CHANNLE_NUM)
+    if (channel < 0 || channel >= PL041_CHANNEL_NUM)
     {
-        LOG_E("%s channle:%d err.", __FUNCTION__, channle);
+        LOG_E("%s channel:%d err.", __FUNCTION__, channel);
         return -RT_ERROR;
     }
-    irq_tbl[channle].fun = RT_NULL;
-    irq_tbl[channle].user_data = RT_NULL;
+    irq_tbl[channel].fun = RT_NULL;
+    irq_tbl[channel].user_data = RT_NULL;
     return RT_EOK;
 }
 
 static void aaci_pl041_irq_handle(int irqno, void *param)
 {
-    rt_uint32_t mask, channle, m;
+    rt_uint32_t mask, channel, m;
     struct pl041_irq_def *_irq = param;
     void *p_status;
 
     mask = PL041_READ(&PL041->allints);
     PL041_WRITE(&PL041->intclr, mask);
 
-    for (channle = 0; (channle < PL041_CHANNLE_NUM) && (mask); channle++)
+    for (channel = 0; (channel < PL041_CHANNEL_NUM) && (mask); channel++)
     {
         mask = mask >> 7;
         m = mask & 0x7f;
         if (m & AACI_ISR_ORINTR)
         {
-            LOG_W("RX overrun on chan %d", channle);
+            LOG_W("RX overrun on chan %d", channel);
         }
 
         if (m & AACI_ISR_RXTOINTR)
         {
-            LOG_W("RX timeout on chan %d", channle);
+            LOG_W("RX timeout on chan %d", channel);
         }
 
         if (mask & AACI_ISR_URINTR)
         {
-            LOG_W("TX underrun on chan %d", channle);
+            LOG_W("TX underrun on chan %d", channel);
         }
 
-        p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-        if (_irq[channle].fun != RT_NULL)
+        p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+        if (_irq[channel].fun != RT_NULL)
         {
-            _irq[channle].fun(PL041_READ(p_status), _irq[channle].user_data);
+            _irq[channel].fun(PL041_READ(p_status), _irq[channel].user_data);
         }
     }
 }

bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_pl041.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,11 +14,11 @@
 #define PL041_BASE_ADDR    (0x10004000)
 
 /* offsets in CTRL_CH */
-#define AACI_RXCR        0x00	/* 29 bits Control Rx FIFO */
-#define AACI_TXCR        0x04	/* 17 bits Control Tx FIFO */
-#define AACI_SR          0x08	/* 12 bits Status */
-#define AACI_ISR         0x0C	/* 7 bits  Int Status */
-#define AACI_IE          0x10	/* 7 bits  Int Enable */
+#define AACI_RXCR        0x00   /* 29 bits Control Rx FIFO */
+#define AACI_TXCR        0x04   /* 17 bits Control Tx FIFO */
+#define AACI_SR          0x08   /* 12 bits Status */
+#define AACI_ISR         0x0C   /* 7 bits  Int Status */
+#define AACI_IE          0x10   /* 7 bits  Int Enable */
 
 /* both for AACI_RXCR and AACI_TXCR */
 #define AACI_CR_FEN           (1 << 16)  /* fifo enable */
@@ -53,7 +39,7 @@
 #define AACI_CR_SL3           (1 << 3)
 #define AACI_CR_SL2           (1 << 2)
 #define AACI_CR_SL1           (1 << 1)
-#define AACI_CR_EN            (1 << 0)	/* receive enable */
+#define AACI_CR_EN            (1 << 0)  /* receive enable */
 
 /* status register bits */
 #define AACI_SR_RXTOFE        (1 << 11)  /* rx timeout fifo empty */
@@ -80,29 +66,29 @@
 /* interrupt enable */
 #define AACI_IE_RXTOIE        (1 << 6)   /*rx timeout interrupt enable*/
 #define AACI_IE_URIE          (1 << 5)   /*Transmit underrun interrupt enable*/
-#define AACI_IE_ORIE          (1 << 4)	 /*Overrun receive interrupt enable*/
+#define AACI_IE_ORIE          (1 << 4)   /*Overrun receive interrupt enable*/
 #define AACI_IE_RXIE          (1 << 3)   /*Receive interrupt enable*/
 #define AACI_IE_TXIE          (1 << 2)   /*Transmit interrupt enable*/
 #define AACI_IE_RXTIE         (1 << 1)   /*Receive timeout interrupt enable*/
-#define AACI_IE_TXCIE         (1 << 0)	 /*Transmit complete interrupt enable*/
+#define AACI_IE_TXCIE         (1 << 0)   /*Transmit complete interrupt enable*/
 
 /* interrupt status */
-#define AACI_ISR_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
-#define AACI_ISR_UR		(1 << 5)	/* tx fifo underrun */
-#define AACI_ISR_OR		(1 << 4)	/* rx fifo overrun */
-#define AACI_ISR_RX		(1 << 3)	/* rx interrupt status */
-#define AACI_ISR_TX		(1 << 2)	/* tx interrupt status */
-#define AACI_ISR_RXTO	(1 << 1)	/* rx timeout */
-#define AACI_ISR_TXC	(1 << 0)	/* tx complete */
+#define AACI_ISR_RXTOFE (1 << 6)    /* rx timeout fifo empty */
+#define AACI_ISR_UR     (1 << 5)    /* tx fifo underrun */
+#define AACI_ISR_OR     (1 << 4)    /* rx fifo overrun */
+#define AACI_ISR_RX     (1 << 3)    /* rx interrupt status */
+#define AACI_ISR_TX     (1 << 2)    /* tx interrupt status */
+#define AACI_ISR_RXTO   (1 << 1)    /* rx timeout */
+#define AACI_ISR_TXC    (1 << 0)    /* tx complete */
 
 /* interrupt enable */
-#define AACI_IE_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
-#define AACI_IE_UR		(1 << 5)	/* tx fifo underrun */
-#define AACI_IE_OR		(1 << 4)	/* rx fifo overrun */
-#define AACI_IE_RX		(1 << 3)	/* rx interrupt status */
-#define AACI_IE_TX		(1 << 2)	/* tx interrupt status */
-#define AACI_IE_RXTO	(1 << 1)	/* rx timeout */
-#define AACI_IE_TXC		(1 << 0)	/* tx complete */
+#define AACI_IE_RXTOFE  (1 << 6)    /* rx timeout fifo empty */
+#define AACI_IE_UR      (1 << 5)    /* tx fifo underrun */
+#define AACI_IE_OR      (1 << 4)    /* rx fifo overrun */
+#define AACI_IE_RX      (1 << 3)    /* rx interrupt status */
+#define AACI_IE_TX      (1 << 2)    /* tx interrupt status */
+#define AACI_IE_RXTO    (1 << 1)    /* rx timeout */
+#define AACI_IE_TXC     (1 << 0)    /* tx complete */
 
 /* slot flag register bits */
 #define AACI_SLFR_RWIS        (1 << 13)    /* raw wake-up interrupt status */
@@ -134,7 +120,7 @@
 #define AACI_ICLR_RXOEC2      (1 << 2)       /* Receive overrun error clear */
 #define AACI_ICLR_RXOEC1      (1 << 1)       /* Receive overrun error clear */
 #define AACI_ICLR_WISC        (1 << 0)       /* Wake-up interrupt status clear */
-                                
+
 /* Main control register bits AACI_MAINCR */
 #define AACI_MAINCR_SCRA(x)   ((x) << 10)     /* secondary codec reg access */
 #define AACI_MAINCR_DMAEN     (1 << 9)        /* dma enable */
@@ -155,13 +141,13 @@
 #define SYNC_FORCE   (1 << 0)
 
 /* Main flag register bits. P66 */
-#define MAINFR_TXB   (1 << 1)	/* transmit busy */
-#define MAINFR_RXB   (1 << 0)	/* receive busy */
+#define MAINFR_TXB   (1 << 1)   /* transmit busy */
+#define MAINFR_RXB   (1 << 0)   /* receive busy */
 
-#define PL041_CHANNLE_LEFT_DAC    (0x1 << 3)
-#define PL041_CHANNLE_RIGHT_DAC   (0x1 << 3)
-#define PL041_CHANNLE_LEFT_ADC    (0x1 << 3)
-#define PL041_CHANNLE_RIGHT_ADC   (0x1 << 3)
+#define PL041_CHANNEL_LEFT_DAC    (0x1 << 3)
+#define PL041_CHANNEL_RIGHT_DAC   (0x1 << 3)
+#define PL041_CHANNEL_LEFT_ADC    (0x1 << 3)
+#define PL041_CHANNEL_RIGHT_ADC   (0x1 << 3)
 
 struct reg_pl041
 {
@@ -225,13 +211,13 @@ typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data);
 rt_err_t aaci_pl041_init(void);
 void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val);
 rt_uint16_t aaci_ac97_read(rt_uint16_t reg);
-int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cfg);
-int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count);
-int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count);
-int aaci_pl041_channle_enable(int channle);
-int aaci_pl041_channle_disable(int channle);
-rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data);
-rt_err_t aaci_pl041_irq_unregister(int channle);
-void aaci_pl041_irq_disable(int channle, rt_uint32_t vector);
-void aaci_pl041_irq_enable(int channle, rt_uint32_t vector);
+int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg);
+int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count);
+int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count);
+int aaci_pl041_channel_enable(int channel);
+int aaci_pl041_channel_disable(int channel);
+rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data);
+rt_err_t aaci_pl041_irq_unregister(int channel);
+void aaci_pl041_irq_disable(int channel, rt_uint32_t vector);
+void aaci_pl041_irq_enable(int channel, rt_uint32_t vector);
 #endif

bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
@@ -227,13 +227,13 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
 
     aaci_pl041_init();
 
-    _cfg.itype = PL041_CHANNLE_LEFT_ADC | PL041_CHANNLE_RIGHT_ADC;
-    _cfg.otype = PL041_CHANNLE_LEFT_DAC | PL041_CHANNLE_RIGHT_DAC;
+    _cfg.itype = PL041_CHANNEL_LEFT_ADC | PL041_CHANNEL_RIGHT_ADC;
+    _cfg.otype = PL041_CHANNEL_LEFT_DAC | PL041_CHANNEL_RIGHT_DAC;
     _cfg.vol   = snd_dev->volume;
     _cfg.rate  = snd_dev->replay_config.samplerate;
 
     ac97_reset();
-    aaci_pl041_channle_cfg(0, &_cfg);
+    aaci_pl041_channel_cfg(0, &_cfg);
     aaci_pl041_irq_register(0, rt_hw_aaci_isr, RT_NULL);
 
     return result;
@@ -246,7 +246,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
     if (stream == AUDIO_STREAM_REPLAY)
     {
         LOG_D("open sound device");
-        aaci_pl041_channle_enable(0);
+        aaci_pl041_channel_enable(0);
         aaci_pl041_irq_enable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
     }
 
@@ -263,7 +263,7 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
         rt_thread_mdelay(100);
         /* disable irq and channels 0 */
         aaci_pl041_irq_disable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
-        aaci_pl041_channle_disable(0);
+        aaci_pl041_channel_disable(0);
         LOG_D("close sound device");
     }
 
@@ -295,7 +295,7 @@ static rt_size_t sound_transmit(struct rt_audio_device *audio, const void *write
     RT_ASSERT(audio != RT_NULL);
 
     /* write data to channel_0 fifo */
-    aaci_pl041_channle_write(0, (rt_uint16_t *)writeBuf, size >> 1);
+    aaci_pl041_channel_write(0, (rt_uint16_t *)writeBuf, size >> 1);
 
     return size;
 }

bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/qemu-vexpress-a9/drivers/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/drv_smc911x.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <board.h>
 #include <rtthread.h>
 #include <netif/ethernetif.h>
@@ -36,12 +46,12 @@ int mdelay(int value)
 #if defined (CONFIG_SMC911X_32_BIT)
 rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
 {
-    return *(volatile uint32_t*)(dev->iobase + offset);
+    return *(volatile uint32_t *)(dev->iobase + offset);
 }
 
 rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
 {
-    *(volatile uint32_t*)(dev->iobase + offset) = val;
+    *(volatile uint32_t *)(dev->iobase + offset) = val;
 }
 
 #elif defined (CONFIG_SMC911X_16_BIT)
@@ -68,47 +78,47 @@ struct chip_id
 
 static const struct chip_id chip_ids[] =
 {
-    { CHIP_89218,"LAN89218" },
-    { CHIP_9115, "LAN9115" },
-    { CHIP_9116, "LAN9116" },
-    { CHIP_9117, "LAN9117" },
-    { CHIP_9118, "LAN9118" },
-    { CHIP_9211, "LAN9211" },
-    { CHIP_9215, "LAN9215" },
-    { CHIP_9216, "LAN9216" },
-    { CHIP_9217, "LAN9217" },
-    { CHIP_9218, "LAN9218" },
-    { CHIP_9220, "LAN9220" },
-    { CHIP_9221, "LAN9221" },
+    { LAN9118_ID_89218, "LAN89218" },
+    { LAN9118_ID_9115, "LAN9115" },
+    { LAN9118_ID_9116, "LAN9116" },
+    { LAN9118_ID_9117, "LAN9117" },
+    { LAN9118_ID_9118, "LAN9118" },
+    { LAN9210_ID_9211, "LAN9211" },
+    { LAN9218_ID_9215, "LAN9215" },
+    { LAN9218_ID_9216, "LAN9216" },
+    { LAN9218_ID_9217, "LAN9217" },
+    { LAN9218_ID_9218, "LAN9218" },
+    { LAN9220_ID_9220, "LAN9220" },
+    { LAN9220_ID_9221, "LAN9221" },
     { 0, RT_NULL },
 };
 
 static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
 {
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
 
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    return smc911x_reg_read(dev, MAC_CSR_DATA);
+    return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
 }
 
 static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
 {
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    smc911x_reg_write(dev, MAC_CSR_DATA, data);
-    smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
 
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 }
 
 static int smc911x_detect_chip(struct eth_device_smc911x *dev)
 {
     unsigned long val, i;
 
-    val = smc911x_reg_read(dev, BYTE_TEST);
+    val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
     if (val == 0xffffffff)
     {
         /* Special case -- no chip present */
@@ -120,7 +130,7 @@ static int smc911x_detect_chip(struct eth_device_smc911x *dev)
         return -1;
     }
 
-    val = smc911x_reg_read(dev, ID_REV) >> 16;
+    val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
     for (i = 0; chip_ids[i].id != 0; i++)
     {
         if (chip_ids[i].id == val) break;
@@ -141,16 +151,16 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
 
     /*
     *  Take out of PM setting first
-    *  Device is already wake up if PMT_CTRL_READY bit is set
+    *  Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
     */
-    if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
+    if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
     {
         /* Write to the bytetest will take out of powerdown */
-        smc911x_reg_write(dev, BYTE_TEST, 0x0);
+        smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
 
         timeout = 10;
 
-        while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
+        while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
             udelay(10);
 
         if (timeout < 0)
@@ -162,11 +172,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
     }
 
     /* Disable interrupts */
-    smc911x_reg_write(dev, INT_EN, 0);
-    smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
+    smc911x_reg_write(dev, LAN9118_INT_EN, 0);
+    smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
 
     timeout = 1000;
-    while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
+    while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
         udelay(10);
 
     if (timeout < 0)
@@ -176,11 +186,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
     }
 
     /* Reset the FIFO level and flow control settings */
-    smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
-    smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
+    smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
+    smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
 
     /* Set to LED outputs */
-    smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
+    smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
 }
 
 static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
@@ -191,20 +201,20 @@ static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
     addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
     addrh = m[4] | (m[5] << 8);
 
-    smc911x_set_mac_csr(dev, ADDRL, addrl);
-    smc911x_set_mac_csr(dev, ADDRH, addrh);
+    smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
+    smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
 }
 
 static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
                                 uint8_t phy, uint8_t reg, uint16_t *val)
 {
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
 
-    smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
+    smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
 
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
 
-    *val = smc911x_get_mac_csr(dev, MII_DATA);
+    *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
 
     return 0;
 }
@@ -212,14 +222,14 @@ static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
 static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
                                  uint8_t phy, uint8_t reg, uint16_t  val)
 {
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
         ;
 
-    smc911x_set_mac_csr(dev, MII_DATA, val);
-    smc911x_set_mac_csr(dev, MII_ACC,
-                        phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
+    smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
+    smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
+                        phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
 
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
         ;
     return 0;
 }
@@ -228,10 +238,10 @@ static int smc911x_phy_reset(struct eth_device_smc911x *dev)
 {
     uint32_t reg;
 
-    reg = smc911x_reg_read(dev, PMT_CTRL);
+    reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
     reg &= ~0xfffff030;
-    reg |= PMT_CTRL_PHY_RST;
-    smc911x_reg_write(dev, PMT_CTRL, reg);
+    reg |= LAN9118_PMT_CTRL_PHY_RST;
+    smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
 
     mdelay(100);
 
@@ -245,10 +255,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
 
     smc911x_phy_reset(dev);
 
-    smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
     mdelay(1);
-    smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
-    smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
 
     timeout = 5000;
     do
@@ -257,10 +267,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
         if ((timeout--) == 0)
             goto err_out;
 
-        if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
+        if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
             goto err_out;
     }
-    while (!(status & BMSR_LSTATUS));
+    while (!(status & LAN9118_BMSR_LSTATUS));
 
     return;
 
@@ -271,17 +281,17 @@ err_out:
 static void smc911x_enable(struct eth_device_smc911x *dev)
 {
     /* Enable TX */
-    smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
+    smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
 
-    smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
+    smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
 
-    smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
+    smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
 
     /* no padding to start of packets */
-    smc911x_reg_write(dev, RX_CFG, 0);
+    smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
 
-    smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
-                        MAC_CR_HBDIS);
+    smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
+                        LAN9118_MAC_CR_HBDIS);
 }
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -319,13 +329,13 @@ static void smc911x_isr(int vector, void *param)
 
     emac = SMC911X_EMAC_DEVICE(param);
 
-    status = smc911x_reg_read(emac, INT_STS);
-    
-    if (status & INT_STS_RSFL)
+    status = smc911x_reg_read(emac, LAN9118_INT_STS);
+
+    if (status & LAN9118_INT_STS_RSFL)
     {
         eth_device_ready(&emac->parent);
     }
-    smc911x_reg_write(emac, INT_STS, status);
+    smc911x_reg_write(emac, LAN9118_INT_STS, status);
 
     return ;
 }
@@ -349,18 +359,18 @@ static rt_err_t smc911x_emac_init(rt_device_t dev)
 
 #if 1
     /* Interrupt on every received packet */
-    smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
-    smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
+    smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
+    smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
 
     /* enable interrupt */
-    smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
+    smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
 #else
 
     /* disable interrupt */
-    smc911x_reg_write(emac, INT_EN, 0);
-    value = smc911x_reg_read(emac, INT_CFG);
-    value &= ~INT_CFG_IRQ_EN;
-    smc911x_reg_write(emac, INT_CFG, value);
+    smc911x_reg_write(emac, LAN9118_INT_EN, 0);
+    value = smc911x_reg_read(emac, LAN9118_IRQ_CFG);
+    value &= ~LAN9118_IRQ_CFG_IRQ_EN;
+    smc911x_reg_write(emac, LAN9118_IRQ_CFG, value);
 #endif
 
     rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
@@ -376,11 +386,11 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
     emac = SMC911X_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
-    switch(cmd)
+    switch (cmd)
     {
     case NIOCTL_GADDR:
         /* get MAC address */
-        if(args) rt_memcpy(args, emac->enetaddr, 6);
+        if (args) rt_memcpy(args, emac->enetaddr, 6);
         else return -RT_ERROR;
         break;
     default :
@@ -392,7 +402,7 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
 /* Ethernet device interface */
 /* transmit packet. */
 static uint8_t tx_buf[2048];
-rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
+rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
 {
     struct eth_device_smc911x *emac;
 
@@ -408,36 +418,36 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
     pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
 
     /* send it out */
-    data = (uint32_t*)tx_buf;
+    data = (uint32_t *)tx_buf;
     length = p->tot_len;
 
-    smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
-    smc911x_reg_write(emac, TX_DATA_FIFO, length);
+    smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
+    smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
 
     tmplen = (length + 3) / 4;
     while (tmplen--)
     {
-        smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
+        smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
     }
 
     /* wait for transmission */
-    while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
+    while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
 
     /* get status. Ignore 'no carrier' error, it has no meaning for
      * full duplex operation
      */
-    status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
-             (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
-              TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
+    status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
+             (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
+              LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
 
     if (!status) return 0;
 
     rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
-               status & TX_STS_LOC ? "TX_STS_LOC " : "",
-               status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
-               status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
-               status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
-               status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
+               status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
+               status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
+               status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
+               status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
+               status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
 
     return -RT_EIO;
 }
@@ -445,24 +455,24 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
 /* reception packet. */
 struct pbuf *smc911x_emac_rx(rt_device_t dev)
 {
-    struct pbuf* p = RT_NULL;
+    struct pbuf *p = RT_NULL;
     struct eth_device_smc911x *emac;
 
     emac = SMC911X_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
     /* take the emac buffer to the pbuf */
-    if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
+    if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
     {
         uint32_t status;
         uint32_t pktlen, tmplen;
 
-        status = smc911x_reg_read(emac, RX_STATUS_FIFO);
+        status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
 
         /* get frame length */
-        pktlen = (status & RX_STS_PKT_LEN) >> 16;
+        pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
 
-        smc911x_reg_write(emac, RX_CFG, 0);
+        smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
 
         tmplen = (pktlen + 3) / 4;
 
@@ -473,11 +483,11 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
             uint32_t *data = (uint32_t *)p->payload;
             while (tmplen--)
             {
-                *data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
+                *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
             }
         }
 
-        if (status & RX_STS_ES)
+        if (status & LAN9118_RXS_ES)
         {
             rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
         }
@@ -487,7 +497,7 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
 }
 
 #ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops smc911x_emac_ops = 
+const static struct rt_device_ops smc911x_emac_ops =
 {
     smc911x_emac_init,
     RT_NULL,
@@ -510,7 +520,7 @@ int smc911x_emac_hw_init(void)
     }
 
     /* set INT CFG */
-    smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
+    smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
 
     /* test MAC address */
     _emac.enetaddr[0] = AUTOMAC0;

bsp/qemu-vexpress-a9/drivers/drv_smc911x.h

@@ -1,402 +1,342 @@
 /*
- * SMSC LAN9[12]1[567] Network driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * SPDX-License-Identifier: Apache-2.0
  *
- * SPDX-License-Identifier: GPL-2.0+
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-21
  */
 
-#ifndef _SMC911X_H_
-#define _SMC911X_H_
 
-#include <stdint.h>
-
-#define CONFIG_SMC911X_32_BIT
-
-/* Below are the register offsets and bit definitions
- * of the Lan911x memory space
+/*  $NetBSD: lan9118reg.h,v 1.3 2010/09/27 12:29:03 kiyohara Exp $  */
+/*
+ * Copyright (c) 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
-#define RX_DATA_FIFO                    0x00
-
-#define TX_DATA_FIFO                    0x20
-#define TX_CMD_A_INT_ON_COMP            0x80000000
-#define TX_CMD_A_INT_BUF_END_ALGN       0x03000000
-#define TX_CMD_A_INT_4_BYTE_ALGN        0x00000000
-#define TX_CMD_A_INT_16_BYTE_ALGN       0x01000000
-#define TX_CMD_A_INT_32_BYTE_ALGN       0x02000000
-#define TX_CMD_A_INT_DATA_OFFSET        0x001F0000
-#define TX_CMD_A_INT_FIRST_SEG          0x00002000
-#define TX_CMD_A_INT_LAST_SEG           0x00001000
-#define TX_CMD_A_BUF_SIZE               0x000007FF
-#define TX_CMD_B_PKT_TAG                0xFFFF0000
-#define TX_CMD_B_ADD_CRC_DISABLE        0x00002000
-#define TX_CMD_B_DISABLE_PADDING        0x00001000
-#define TX_CMD_B_PKT_BYTE_LENGTH        0x000007FF
-
-#define RX_STATUS_FIFO              0x40
-#define RX_STS_PKT_LEN              0x3FFF0000
-#define RX_STS_ES                   0x00008000
-#define RX_STS_BCST                 0x00002000
-#define RX_STS_LEN_ERR              0x00001000
-#define RX_STS_RUNT_ERR             0x00000800
-#define RX_STS_MCAST                0x00000400
-#define RX_STS_TOO_LONG             0x00000080
-#define RX_STS_COLL                 0x00000040
-#define RX_STS_ETH_TYPE             0x00000020
-#define RX_STS_WDOG_TMT             0x00000010
-#define RX_STS_MII_ERR              0x00000008
-#define RX_STS_DRIBBLING            0x00000004
-#define RX_STS_CRC_ERR              0x00000002
-#define RX_STATUS_FIFO_PEEK         0x44
-#define TX_STATUS_FIFO              0x48
-#define TX_STS_TAG                  0xFFFF0000
-#define TX_STS_ES                   0x00008000
-#define TX_STS_LOC                  0x00000800
-#define TX_STS_NO_CARR              0x00000400
-#define TX_STS_LATE_COLL            0x00000200
-#define TX_STS_MANY_COLL            0x00000100
-#define TX_STS_COLL_CNT             0x00000078
-#define TX_STS_MANY_DEFER           0x00000004
-#define TX_STS_UNDERRUN             0x00000002
-#define TX_STS_DEFERRED             0x00000001
-#define TX_STATUS_FIFO_PEEK         0x4C
-#define ID_REV                      0x50
-#define ID_REV_CHIP_ID              0xFFFF0000  /* RO */
-#define ID_REV_REV_ID               0x0000FFFF  /* RO */
-
-#define INT_CFG                     0x54
-#define INT_CFG_INT_DEAS            0xFF000000  /* R/W */
-#define INT_CFG_INT_DEAS_CLR        0x00004000
-#define INT_CFG_INT_DEAS_STS        0x00002000
-#define INT_CFG_IRQ_INT             0x00001000  /* RO */
-#define INT_CFG_IRQ_EN              0x00000100  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define INT_CFG_IRQ_POL             0x00000010
-/* R/W Not Affected by SW Reset */
-#define INT_CFG_IRQ_TYPE            0x00000001
-
-#define INT_STS                     0x58
-#define INT_STS_SW_INT              0x80000000  /* R/WC */
-#define INT_STS_TXSTOP_INT          0x02000000  /* R/WC */
-#define INT_STS_RXSTOP_INT          0x01000000  /* R/WC */
-#define INT_STS_RXDFH_INT           0x00800000  /* R/WC */
-#define INT_STS_RXDF_INT            0x00400000  /* R/WC */
-#define INT_STS_TX_IOC              0x00200000  /* R/WC */
-#define INT_STS_RXD_INT             0x00100000  /* R/WC */
-#define INT_STS_GPT_INT             0x00080000  /* R/WC */
-#define INT_STS_PHY_INT             0x00040000  /* RO */
-#define INT_STS_PME_INT             0x00020000  /* R/WC */
-#define INT_STS_TXSO                0x00010000  /* R/WC */
-#define INT_STS_RWT                 0x00008000  /* R/WC */
-#define INT_STS_RXE                 0x00004000  /* R/WC */
-#define INT_STS_TXE                 0x00002000  /* R/WC */
-/*#define   INT_STS_ERX     0x00001000*/  /* R/WC */
-#define INT_STS_TDFU                0x00000800  /* R/WC */
-#define INT_STS_TDFO                0x00000400  /* R/WC */
-#define INT_STS_TDFA                0x00000200  /* R/WC */
-#define INT_STS_TSFF                0x00000100  /* R/WC */
-#define INT_STS_TSFL                0x00000080  /* R/WC */
-/*#define   INT_STS_RXDF        0x00000040*/  /* R/WC */
-#define INT_STS_RDFO                0x00000040  /* R/WC */
-#define INT_STS_RDFL                0x00000020  /* R/WC */
-#define INT_STS_RSFF                0x00000010  /* R/WC */
-#define INT_STS_RSFL                0x00000008  /* R/WC */
-#define INT_STS_GPIO2_INT           0x00000004  /* R/WC */
-#define INT_STS_GPIO1_INT           0x00000002  /* R/WC */
-#define INT_STS_GPIO0_INT           0x00000001  /* R/WC */
-#define INT_EN                      0x5C
-#define INT_EN_SW_INT_EN            0x80000000  /* R/W */
-#define INT_EN_TXSTOP_INT_EN        0x02000000  /* R/W */
-#define INT_EN_RXSTOP_INT_EN        0x01000000  /* R/W */
-#define INT_EN_RXDFH_INT_EN         0x00800000  /* R/W */
-/*#define   INT_EN_RXDF_INT_EN      0x00400000*/  /* R/W */
-#define INT_EN_TIOC_INT_EN          0x00200000  /* R/W */
-#define INT_EN_RXD_INT_EN           0x00100000  /* R/W */
-#define INT_EN_GPT_INT_EN           0x00080000  /* R/W */
-#define INT_EN_PHY_INT_EN           0x00040000  /* R/W */
-#define INT_EN_PME_INT_EN           0x00020000  /* R/W */
-#define INT_EN_TXSO_EN              0x00010000  /* R/W */
-#define INT_EN_RWT_EN               0x00008000  /* R/W */
-#define INT_EN_RXE_EN               0x00004000  /* R/W */
-#define INT_EN_TXE_EN               0x00002000  /* R/W */
-/*#define   INT_EN_ERX_EN           0x00001000*/  /* R/W */
-#define INT_EN_TDFU_EN              0x00000800  /* R/W */
-#define INT_EN_TDFO_EN              0x00000400  /* R/W */
-#define INT_EN_TDFA_EN              0x00000200  /* R/W */
-#define INT_EN_TSFF_EN              0x00000100  /* R/W */
-#define INT_EN_TSFL_EN              0x00000080  /* R/W */
-/*#define   INT_EN_RXDF_EN          0x00000040*/  /* R/W */
-#define INT_EN_RDFO_EN              0x00000040  /* R/W */
-#define INT_EN_RDFL_EN              0x00000020  /* R/W */
-#define INT_EN_RSFF_EN              0x00000010  /* R/W */
-#define INT_EN_RSFL_EN              0x00000008  /* R/W */
-#define INT_EN_GPIO2_INT            0x00000004  /* R/W */
-#define INT_EN_GPIO1_INT            0x00000002  /* R/W */
-#define INT_EN_GPIO0_INT            0x00000001  /* R/W */
-
-#define BYTE_TEST                   0x64
-#define FIFO_INT                    0x68
-#define FIFO_INT_TX_AVAIL_LEVEL     0xFF000000  /* R/W */
-#define FIFO_INT_TX_STS_LEVEL       0x00FF0000  /* R/W */
-#define FIFO_INT_RX_AVAIL_LEVEL     0x0000FF00  /* R/W */
-#define FIFO_INT_RX_STS_LEVEL       0x000000FF  /* R/W */
-
-#define RX_CFG                      0x6C
-#define RX_CFG_RX_END_ALGN          0xC0000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN4     0x00000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN16    0x40000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN32    0x80000000  /* R/W */
-#define RX_CFG_RX_DMA_CNT           0x0FFF0000  /* R/W */
-#define RX_CFG_RX_DUMP              0x00008000  /* R/W */
-#define RX_CFG_RXDOFF               0x00001F00  /* R/W */
-/*#define   RX_CFG_RXBAD            0x00000001*/  /* R/W */
-
-#define TX_CFG                      0x70
-/*#define   TX_CFG_TX_DMA_LVL       0xE0000000*/     /* R/W */
-/* R/W Self Clearing */
-/*#define   TX_CFG_TX_DMA_CNT       0x0FFF0000*/
-#define TX_CFG_TXS_DUMP             0x00008000  /* Self Clearing */
-#define TX_CFG_TXD_DUMP             0x00004000  /* Self Clearing */
-#define TX_CFG_TXSAO                0x00000004  /* R/W */
-#define TX_CFG_TX_ON                0x00000002  /* R/W */
-#define TX_CFG_STOP_TX              0x00000001  /* Self Clearing */
-
-#define HW_CFG                      0x74
-#define HW_CFG_TTM                  0x00200000  /* R/W */
-#define HW_CFG_SF                   0x00100000  /* R/W */
-#define HW_CFG_TX_FIF_SZ            0x000F0000  /* R/W */
-#define HW_CFG_TR                   0x00003000  /* R/W */
-#define HW_CFG_PHY_CLK_SEL          0x00000060  /* R/W */
-#define HW_CFG_PHY_CLK_SEL_INT_PHY  0x00000000 /* R/W */
-#define HW_CFG_PHY_CLK_SEL_EXT_PHY  0x00000020 /* R/W */
-#define HW_CFG_PHY_CLK_SEL_CLK_DIS  0x00000040 /* R/W */
-#define HW_CFG_SMI_SEL              0x00000010  /* R/W */
-#define HW_CFG_EXT_PHY_DET          0x00000008  /* RO */
-#define HW_CFG_EXT_PHY_EN           0x00000004  /* R/W */
-#define HW_CFG_32_16_BIT_MODE       0x00000004  /* RO */
-#define HW_CFG_SRST_TO              0x00000002  /* RO */
-#define HW_CFG_SRST                 0x00000001  /* Self Clearing */
-
-#define RX_DP_CTRL                  0x78
-#define RX_DP_CTRL_RX_FFWD          0x80000000  /* R/W */
-#define RX_DP_CTRL_FFWD_BUSY        0x80000000  /* RO */
-
-#define RX_FIFO_INF                 0x7C
-#define  RX_FIFO_INF_RXSUSED        0x00FF0000  /* RO */
-#define  RX_FIFO_INF_RXDUSED        0x0000FFFF  /* RO */
-
-#define TX_FIFO_INF                 0x80
-#define TX_FIFO_INF_TSUSED          0x00FF0000  /* RO */
-#define TX_FIFO_INF_TDFREE          0x0000FFFF  /* RO */
-
-#define PMT_CTRL                    0x84
-#define PMT_CTRL_PM_MODE            0x00003000  /* Self Clearing */
-#define PMT_CTRL_PHY_RST            0x00000400  /* Self Clearing */
-#define PMT_CTRL_WOL_EN             0x00000200  /* R/W */
-#define PMT_CTRL_ED_EN              0x00000100  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define PMT_CTRL_PME_TYPE           0x00000040
-#define PMT_CTRL_WUPS               0x00000030  /* R/WC */
-#define PMT_CTRL_WUPS_NOWAKE        0x00000000  /* R/WC */
-#define PMT_CTRL_WUPS_ED            0x00000010  /* R/WC */
-#define PMT_CTRL_WUPS_WOL           0x00000020  /* R/WC */
-#define PMT_CTRL_WUPS_MULTI         0x00000030  /* R/WC */
-#define PMT_CTRL_PME_IND            0x00000008  /* R/W */
-#define PMT_CTRL_PME_POL            0x00000004  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define PMT_CTRL_PME_EN             0x00000002
-#define PMT_CTRL_READY              0x00000001  /* RO */
 
-#define GPIO_CFG                    0x88
-#define GPIO_CFG_LED3_EN            0x40000000  /* R/W */
-#define GPIO_CFG_LED2_EN            0x20000000  /* R/W */
-#define GPIO_CFG_LED1_EN            0x10000000  /* R/W */
-#define GPIO_CFG_GPIO2_INT_POL      0x04000000  /* R/W */
-#define GPIO_CFG_GPIO1_INT_POL      0x02000000  /* R/W */
-#define GPIO_CFG_GPIO0_INT_POL      0x01000000  /* R/W */
-#define GPIO_CFG_EEPR_EN            0x00700000  /* R/W */
-#define GPIO_CFG_GPIOBUF2           0x00040000  /* R/W */
-#define GPIO_CFG_GPIOBUF1           0x00020000  /* R/W */
-#define GPIO_CFG_GPIOBUF0           0x00010000  /* R/W */
-#define GPIO_CFG_GPIODIR2           0x00000400  /* R/W */
-#define GPIO_CFG_GPIODIR1           0x00000200  /* R/W */
-#define GPIO_CFG_GPIODIR0           0x00000100  /* R/W */
-#define GPIO_CFG_GPIOD4             0x00000010  /* R/W */
-#define GPIO_CFG_GPIOD3             0x00000008  /* R/W */
-#define GPIO_CFG_GPIOD2             0x00000004  /* R/W */
-#define GPIO_CFG_GPIOD1             0x00000002  /* R/W */
-#define GPIO_CFG_GPIOD0             0x00000001  /* R/W */
+#ifndef _LAN9118REG_H_
+#define _LAN9118REG_H_
 
-#define GPT_CFG                     0x8C
-#define GPT_CFG_TIMER_EN            0x20000000  /* R/W */
-#define GPT_CFG_GPT_LOAD            0x0000FFFF  /* R/W */
 
-#define GPT_CNT                     0x90
-#define GPT_CNT_GPT_CNT             0x0000FFFF  /* RO */
-
-#define ENDIAN                      0x98
-#define FREE_RUN                    0x9C
-#define RX_DROP                     0xA0
-#define MAC_CSR_CMD                 0xA4
-#define  MAC_CSR_CMD_CSR_BUSY       0x80000000  /* Self Clearing */
-#define  MAC_CSR_CMD_R_NOT_W        0x40000000  /* R/W */
-#define  MAC_CSR_CMD_CSR_ADDR       0x000000FF  /* R/W */
-
-#define MAC_CSR_DATA                0xA8
-#define AFC_CFG                     0xAC
-#define     AFC_CFG_AFC_HI          0x00FF0000  /* R/W */
-#define     AFC_CFG_AFC_LO          0x0000FF00  /* R/W */
-#define     AFC_CFG_BACK_DUR        0x000000F0  /* R/W */
-#define     AFC_CFG_FCMULT          0x00000008  /* R/W */
-#define     AFC_CFG_FCBRD           0x00000004  /* R/W */
-#define     AFC_CFG_FCADD           0x00000002  /* R/W */
-#define     AFC_CFG_FCANY           0x00000001  /* R/W */
-
-#define E2P_CMD                     0xB0
-#define     E2P_CMD_EPC_BUSY        0x80000000  /* Self Clearing */
-#define     E2P_CMD_EPC_CMD         0x70000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_READ    0x00000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_EWDS    0x10000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_EWEN    0x20000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_WRITE   0x30000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_WRAL    0x40000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_ERASE   0x50000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_ERAL    0x60000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_RELOAD  0x70000000  /* R/W */
-#define     E2P_CMD_EPC_TIMEOUT     0x00000200  /* RO */
-#define     E2P_CMD_MAC_ADDR_LOADED 0x00000100  /* RO */
-#define     E2P_CMD_EPC_ADDR        0x000000FF  /* R/W */
-
-#define E2P_DATA                0xB4
-#define E2P_DATA_EEPROM_DATA    0x000000FF  /* R/W */
-/* end of LAN register offsets and bit definitions */
-
-/* MAC Control and Status registers */
-#define MAC_CR                  0x01  /* R/W */
-
-/* MAC_CR - MAC Control Register */
-#define MAC_CR_RXALL            0x80000000
-/* TODO: delete this bit? It is not described in the data sheet. */
-#define MAC_CR_HBDIS            0x10000000
-#define MAC_CR_RCVOWN           0x00800000
-#define MAC_CR_LOOPBK           0x00200000
-#define MAC_CR_FDPX             0x00100000
-#define MAC_CR_MCPAS            0x00080000
-#define MAC_CR_PRMS             0x00040000
-#define MAC_CR_INVFILT          0x00020000
-#define MAC_CR_PASSBAD          0x00010000
-#define MAC_CR_HFILT            0x00008000
-#define MAC_CR_HPFILT           0x00002000
-#define MAC_CR_LCOLL            0x00001000
-#define MAC_CR_BCAST            0x00000800
-#define MAC_CR_DISRTY           0x00000400
-#define MAC_CR_PADSTR           0x00000100
-#define MAC_CR_BOLMT_MASK       0x000000C0
-#define MAC_CR_DFCHK            0x00000020
-#define MAC_CR_TXEN             0x00000008
-#define MAC_CR_RXEN             0x00000004
-
-#define ADDRH                   0x02      /* R/W mask 0x0000FFFFUL */
-#define ADDRL                   0x03      /* R/W mask 0xFFFFFFFFUL */
-#define HASHH                   0x04      /* R/W */
-#define HASHL                   0x05      /* R/W */
-
-#define MII_ACC                 0x06      /* R/W */
-#define MII_ACC_PHY_ADDR        0x0000F800
-#define MII_ACC_MIIRINDA        0x000007C0
-#define MII_ACC_MII_WRITE       0x00000002
-#define MII_ACC_MII_BUSY        0x00000001
-
-#define MII_DATA            0x07      /* R/W mask 0x0000FFFFUL */
-
-#define FLOW                0x08      /* R/W */
-#define FLOW_FCPT           0xFFFF0000
-#define FLOW_FCPASS         0x00000004
-#define FLOW_FCEN           0x00000002
-#define FLOW_FCBSY          0x00000001
-
-#define VLAN1               0x09      /* R/W mask 0x0000FFFFUL */
-#define VLAN1_VTI1          0x0000ffff
-
-#define VLAN2               0x0A      /* R/W mask 0x0000FFFFUL */
-#define VLAN2_VTI2          0x0000ffff
-
-#define WUFF                0x0B      /* WO */
-
-#define WUCSR               0x0C      /* R/W */
-#define WUCSR_GUE           0x00000200
-#define WUCSR_WUFR          0x00000040
-#define WUCSR_MPR           0x00000020
-#define WUCSR_WAKE_EN       0x00000004
-#define WUCSR_MPEN          0x00000002
+#define CONFIG_SMC911X_32_BIT
 
-/* Chip ID values */
-#define CHIP_89218  0x218a
-#define CHIP_9115   0x115
-#define CHIP_9116   0x116
-#define CHIP_9117   0x117
-#define CHIP_9118   0x118
-#define CHIP_9211   0x9211
-#define CHIP_9215   0x115a
-#define CHIP_9216   0x116a
-#define CHIP_9217   0x117a
-#define CHIP_9218   0x118a
-#define CHIP_9220   0x9220
-#define CHIP_9221   0x9221
+#define LAN9118_IOSIZE   0x100
+
+#define LAN9118_ID_89218 0x218a
+#define LAN9118_ID_9115  0x0115
+#define LAN9118_ID_9116  0x0116
+#define LAN9118_ID_9117  0x0117
+#define LAN9118_ID_9118  0x0118
+#define LAN9218_ID_9215  0x115a
+#define LAN9218_ID_9216  0x116a
+#define LAN9218_ID_9217  0x117a
+#define LAN9218_ID_9218  0x118a
+
+#define LAN9210_ID_9210  0x9210
+#define LAN9210_ID_9211  0x9211
+#define LAN9220_ID_9220  0x9220
+#define LAN9220_ID_9221  0x9221
+
+#define IS_LAN9118(id)  ((id) >= LAN9118_ID_9115 && (id) <= LAN9118_ID_9118)
+#define IS_LAN9218(id)  ((id) >= LAN9218_ID_9215 && (id) <= LAN9218_ID_9218)
+
+#define LAN9118_IPHY_ADDR   0x01    /* Internal PHY Address */
+
+
+#define LAN9118_RXDFIFOP    0x00    /* RX Data FIFO Port */
+#define LAN9118_RXDFIFOAP   0x04    /* RX Data FIFO Alias Ports */
+#define LAN9118_TXDFIFOP    0x20    /* TX Data FIFO Port */
+#define LAN9118_TXDFIFOAP   0x24    /* TX Data FIFO Alias Ports */
+#define LAN9118_RXSFIFOP    0x40    /* RX Status FIFO Port */
+#define LAN9118_RXSFIFOPEEK 0x44    /* RX Status FIFO PEEK */
+#define LAN9118_TXSFIFOP    0x48    /* TX Status FIFO Port */
+#define LAN9118_TXSFIFOPEEK 0x4c    /* TX Status FIFO PEEK */
+
+/* System Control and Status Registers */
+#define LAN9118_ID_REV                      0x50    /* Chip ID and Revision */
+#define LAN9118_ID_REV_ID(x)                (((x) >> 16) & 0xffff)
+#define LAN9118_ID_REV_REV(x)               ((x) & 0xffff)
+#define LAN9118_IRQ_CFG                     0x54    /* Main Interrupt Configuration */
+#define LAN9118_IRQ_CFG_INT_DEAS(t)         ((t) << 24) /* Intr Deassert Interval */
+#define LAN9118_IRQ_CFG_INT_DEAS_CLR        (1 << 14)   /* Intr Deass Intrval clr */
+#define LAN9118_IRQ_CFG_INT_DEAS_STS        (1 << 13)   /* Intr Deassert Status */
+#define LAN9118_IRQ_CFG_IRQ_INT             (1 << 12)   /* Master Interrupt */
+#define LAN9118_IRQ_CFG_IRQ_EN              (1 << 8)    /* IRQ Enable */
+#define LAN9118_IRQ_CFG_IRQ_POL             (1 << 4)    /* IRQ Polarity */
+#define LAN9118_IRQ_CFG_IRQ_TYPE            (1 << 0)    /* IRQ Buffer Type */
+#define LAN9118_INT_STS                     0x58    /* Interrupt Status */
+#define LAN9118_INT_EN                      0x5c    /* Interrupt Enable Register */
+#define LAN9118_INT_SW_INT                  (1 << 31) /* Software Interrupt */
+#define LAN9118_INT_TXSTOP_INT              (1 << 25) /* TX Stopped */
+#define LAN9118_INT_RXSTOP_INT              (1 << 24) /* RX Stopped */
+#define LAN9118_INT_RXDFH_INT               (1 << 23) /* RX Drppd Frm Cnt Halfway */
+#define LAN9118_INT_TX_IOC                  (1 << 21) /* TX IOC Interrupt */
+#define LAN9118_INT_RXD_INT                 (1 << 20) /* RX DMA Interrupt */
+#define LAN9118_INT_GPT_INT                 (1 << 19) /* GP Timer */
+#define LAN9118_INT_PHY_INT                 (1 << 18) /* PHY */
+#define LAN9118_INT_PME_INT                 (1 << 17) /* Power Management Event */
+#define LAN9118_INT_TXSO                    (1 << 16) /* TX Status FIFO Overflow */
+#define LAN9118_INT_RWT                     (1 << 15) /* Rcv Watchdog Time-out */
+#define LAN9118_INT_RXE                     (1 << 14) /* Receive Error */
+#define LAN9118_INT_TXE                     (1 << 13) /* Transmitter Error */
+#define LAN9118_INT_TDFO                    (1 << 10) /* TX Data FIFO Overrun */
+#define LAN9118_INT_TDFA                    (1 << 9)  /* TX Data FIFO Available */
+#define LAN9118_INT_TSFF                    (1 << 8)  /* TX Status FIFO Full */
+#define LAN9118_INT_TSFL                    (1 << 7)  /* TX Status FIFO Level */
+#define LAN9118_INT_RXDF_INT                (1 << 6)  /* RX Dropped Frame Intr */
+#define LAN9118_INT_RSFF                    (1 << 4)  /* RX Status FIFO Full */
+#define LAN9118_INT_RSFL                    (1 << 3)  /* RX Status FIFO Level */
+#define LAN9118_INT_GPIOX_INT(x)            (1 << (x)) /* GPIO[2:0] */
+/*              0x60       Reserved for future use */
+#define LAN9118_BYTE_TEST                   0x64    /* Read-only byte order testing reg */
+#define LAN9118_BYTE_TEST_VALUE             0x87654321
+#define LAN9118_FIFO_INT                    0x68    /* FIFO Level Interrupt */
+#define LAN9118_FIFO_INT_TXDAL(x)           ((x) << 24) /* TX Data Available Lvl */
+#define LAN9118_FIFO_INT_TXSL(x)            ((x) << 16) /* TX Status Level */
+#define LAN9118_FIFO_INT_RXSL(x)            ((x) << 0)  /* RX Status Level */
+#define LAN9118_RX_CFG                      0x6c    /* Receive Configuration */
+#define LAN9118_RX_CFG_RXEA_4B              (0 << 30) /* RX End Alignment: 4 Byte */
+#define LAN9118_RX_CFG_RXEA_16B             (1 << 30) /*                  16 Byte */
+#define LAN9118_RX_CFG_RXEA_32B             (2 << 30) /*                  32 Byte */
+#define LAN9118_RX_CFG_RX_DMA_CNT(x)        ((x) << 16) /* RX DMA Count */
+#define LAN9118_RX_CFG_RX_DUMP              (1 << 15)   /* Force RX Discard */
+#define LAN9118_RX_CFG_RXDOFF(x)            ((x) << 8)  /* RX Data Offset */
+#define LAN9118_TX_CFG                      0x70    /* Transmit Configuration */
+#define LAN9118_TX_CFG_TXS_DUMP             (1 << 15) /* Force TX Status Discard */
+#define LAN9118_TX_CFG_TXD_DUMP             (1 << 14) /* Force TX Data Discard */
+#define LAN9118_TX_CFG_TXSAO                (1 << 2)  /* TX Status Allow Overrun */
+#define LAN9118_TX_CFG_TX_ON                (1 << 1)  /* Transmitter Enable */
+#define LAN9118_TX_CFG_STOP_TX              (1 << 0)  /* Stop Transmitter */
+#define LAN9118_HW_CFG                      0x74    /* Hardware Configuration */
+#define LAN9118_HW_CFG_MBO                  (1 << 20)/* Must Be One */
+#define LAN9118_HW_CFG_TX_FIF_MASK          (0xf << 16) /* TX FIFO Size */
+#define LAN9118_HW_CFG_TX_FIF_SZ(sz)        ((sz) << 16)
+#define LAN9118_HW_CFG_PHY_CLK_SEL_MASK     (3 << 5) /* PHY Clock Select */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_IPHY     (0 << 5) /*   Internal PHY */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_EMII     (1 << 5) /*   External MII Port */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_CD       (2 << 5) /*   Clock Disabled */
+#define LAN9118_HW_CFG_SMI_SEL              (1 << 4) /* Serial Mgmt Interface Sel */
+#define LAN9118_HW_CFG_EXT_PHY_DET          (1 << 3) /* External PHY Detect */
+#define LAN9118_HW_CFG_EXT_PHY_EN           (1 << 2) /* External PHY Enable */
+#define LAN9118_HW_CFG_SRST_TO              (1 << 1) /* Soft Reset Timeout */
+#define LAN9118_HW_CFG_SRST                 (1 << 0) /* Soft Reset */
+#define LAN9118_RX_DP_CTL                   0x78    /* RX Datapath Control */
+#define LAN9118_RX_DP_CTL_RX_FFWD           (1 << 31)/* RX Data FIFO Fast Forward */
+#define LAN9118_RX_FIFO_INF                 0x7c    /* Receive FIFO Information */
+#define LAN9118_RX_FIFO_INF_RXSUSED(x)      (((x) >> 16) & 0xff) /*Sts Used Space*/
+#define LAN9118_RX_FIFO_INF_RXDUSED(x)      ((x) & 0xffff)  /*Data FIFO Used Space*/
+#define LAN9118_TX_FIFO_INF                 0x80    /* Transmit FIFO Information */
+#define LAN9118_TX_FIFO_INF_TXSUSED(x)      (((x) >> 16) & 0xff) /*Sts Used Space*/
+#define LAN9118_TX_FIFO_INF_TDFREE(x)       ((x) & 0xffff) /*Data FIFO Free Space*/
+#define LAN9118_PMT_CTRL                    0x84    /* Power Management Control */
+#define LAN9118_PMT_CTRL_PM_MODE_MASK       (3 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D0         (0 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D1         (1 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D2         (2 << 12)
+#define LAN9118_PMT_CTRL_PHY_RST            (1 << 10) /* PHY Reset */
+#define LAN9118_PMT_CTRL_WOL_EN             (1 << 9)  /* Wake-On-LAN Enable */
+#define LAN9118_PMT_CTRL_ED_EN              (1 << 8)  /* Energy-Detect Enable */
+#define LAN9118_PMT_CTRL_PME_TYPE           (1 << 6)  /* PME Buffer Type */
+#define LAN9118_PMT_CTRL_WUPS_NWUED         (0 << 4) /* WAKE-UP Status: No Event */
+#define LAN9118_PMT_CTRL_WUPS_ED            (1 << 4) /* WAKE-UP Status: Energy */
+#define LAN9118_PMT_CTRL_WUPS_WUD           (2 << 4) /* WAKE-UP Status: Wake-up */
+#define LAN9118_PMT_CTRL_PME_IND            (1 << 3)  /* PME indication */
+#define LAN9118_PMT_CTRL_PME_POL            (1 << 2)  /* PME Polarity */
+#define LAN9118_PMT_CTRL_PME_EN             (1 << 1)  /* PME Enable */
+#define LAN9118_PMT_CTRL_READY              (1 << 0)  /* Device Ready */
+#define LAN9118_GPIO_CFG                    0x88    /* General Purpose IO Configuration */
+#define LAN9118_GPIO_CFG_LEDX_EN(x)         (1 << ((x) + 28))  /* LED[3:1] enable */
+#define LAN9118_GPIO_CFG_GPIO_INT_POL(p)    (1 << ((p) + 24)) /* Intr Polarity */
+#define LAN9118_GPIO_CFG_EEPR_EN            (7 << 20)          /* EEPROM Enable */
+#define LAN9118_GPIO_CFG_GPIOBUFN(n)        (1 << ((n) + 16))  /* Buffer Type */
+#define LAN9118_GPIO_CFG_GPDIRN(n)          (1 << ((n) + 8))   /* Direction */
+#define LAN9118_GPIO_CFG_GPODN(n)           (1 << (n)) /* GPIO Data (3,4 is WO) */
+#define LAN9118_GPT_CFG                     0x8c    /* General Purpose Timer Config */
+#define LAN9118_GPT_CNT                     0x90    /* General Purpose Timer Count */
+/*              0x94       Reserved for future use */
+#define LAN9118_WORD_SWAP                   0x98    /* WORD SWAP Register */
+#define LAN9118_FREE_RUN                    0x9c    /* Free Run Counter */
+#define LAN9118_RX_DROP                     0xa0    /* RX Drop Frame Counter */
+#define LAN9118_MAC_CSR_CMD                 0xa4    /* MAC CSR Synchronizer Command */
+#define LAN9118_MAC_CSR_CMD_BUSY            (1 << 31)
+#define LAN9118_MAC_CSR_CMD_W               (0 << 30)
+#define LAN9118_MAC_CSR_CMD_R               (1 << 30)
+#define LAN9118_MAC_CSR_CMD_ADDRESS(a)      ((a) & 0xff)
+#define LAN9118_MAC_CSR_DATA                0xa8    /* MAC CSR Synchronizer Data */
+#define LAN9118_AFC_CFG                     0xac    /* Automatic Flow Control Config */
+#define LAN9118_AFC_CFG_AFC_HI(x)           ((x) << 16)
+#define LAN9118_AFC_CFG_AFC_LO(x)           ((x) << 8)
+#define LAN9118_AFC_CFG_BACK_DUR(x)         ((x) << 4)
+#define LAN9118_AFC_CFG_FCMULT              (1 << 3) /* Flow Control on Multicast */
+#define LAN9118_AFC_CFG_FCBRD               (1 << 2) /* Flow Control on Broadcast */
+#define LAN9118_AFC_CFG_FCADD               (1 << 1) /* Flow Control on Addr Dec */
+#define LAN9118_AFC_CFG_FCANY               (1 << 0) /* Flow Control on Any Frame */
+#define LAN9118_E2P_CMD                     0xb0    /* EEPROM command */
+#define LAN9118_E2P_CMD_EPCB                (1 << 31) /* EPC Busy */
+#define LAN9118_E2P_CMD_EPCC_READ           (0 << 28) /* EPC Command: READ */
+#define LAN9118_E2P_CMD_EPCC_EWDS           (1 << 28) /*              EWDS */
+#define LAN9118_E2P_CMD_EPCC_EWEN           (2 << 28) /*              EWEN */
+#define LAN9118_E2P_CMD_EPCC_WRITE          (3 << 28) /*              WRITE */
+#define LAN9118_E2P_CMD_EPCC_WRAL           (4 << 28) /*              WRAL */
+#define LAN9118_E2P_CMD_EPCC_ERASE          (5 << 28) /*              ERASE */
+#define LAN9118_E2P_CMD_EPCC_ERAL           (6 << 28) /*              ERAL */
+#define LAN9118_E2P_CMD_EPCC_RELOAD         (7 << 28) /*              Reload */
+#define LAN9118_E2P_CMD_EPCTO               (1 << 9)  /* EPC Time-out */
+#define LAN9118_E2P_CMD_MACAL               (1 << 8)  /* MAC Address Loaded */
+#define LAN9118_E2P_CMD_EPCA(a)             ((a) & 0xff) /* EPC Address */
+#define LAN9118_E2P_DATA                    0xb4    /* EEPROM Data */
+/*              0xb8 - 0xfc Reserved for future use */
+
+/* MAC Control and Status Registers */
+#define LAN9118_MAC_CR              0x1 /* MAC Control Register */
+#define LAN9118_MAC_CR_RXALL        (1 << 31) /* Receive All Mode */
+#define LAN9118_MAC_CR_RCVOWN       (1 << 23) /* Disable Receive Own */
+#define LAN9118_MAC_CR_LOOPBK       (1 << 21) /* Loopback operation Mode */
+#define LAN9118_MAC_CR_FDPX         (1 << 20) /* Full Duplex Mode */
+#define LAN9118_MAC_CR_MCPAS        (1 << 19) /* Pass All Multicast */
+#define LAN9118_MAC_CR_PRMS         (1 << 18) /* Promiscuous Mode */
+#define LAN9118_MAC_CR_INVFILT      (1 << 17) /* Inverse filtering */
+#define LAN9118_MAC_CR_PASSBAD      (1 << 16) /* Pass Bad Frames */
+#define LAN9118_MAC_CR_HO           (1 << 15) /* Hash Only Filtering mode */
+#define LAN9118_MAC_CR_HPFILT       (1 << 13) /* Hash/Perfect Flt Mode */
+#define LAN9118_MAC_CR_LCOLL        (1 << 12) /* Late Collision Control */
+#define LAN9118_MAC_CR_BCAST        (1 << 11) /* Disable Broardcast Frms */
+#define LAN9118_MAC_CR_DISRTY       (1 << 10) /* Disable Retry */
+#define LAN9118_MAC_CR_PADSTR       (1 << 8)  /* Automatic Pad String */
+#define LAN9118_MAC_CR_BOLMT        (1 << 7)  /* BackOff Limit */
+#define LAN9118_MAC_CR_DFCHK        (1 << 5)  /* Deferral Check */
+#define LAN9118_MAC_CR_TXEN         (1 << 3)  /* Transmitter enable */
+#define LAN9118_MAC_CR_RXEN         (1 << 2)  /* Receiver enable */
+#define LAN9118_ADDRH               0x2 /* MAC Address High */
+#define LAN9118_ADDRL               0x3 /* MAC Address Low */
+#define LAN9118_HASHH               0x4 /* Multicast Hash Table High */
+#define LAN9118_HASHL               0x5 /* Multicast Hash Table Low */
+#define LAN9118_MII_ACC             0x6 /* MII Access */
+#define LAN9118_MII_ACC_PHYA(a)     ((a) << 11) /* PHY Address */
+#define LAN9118_MII_ACC_MIIRINDA(i) ((i) << 6)  /* MII Register Index */
+#define LAN9118_MII_ACC_MIIWNR      (1 << 1)    /* MII Write */
+#define LAN9118_MII_ACC_MIIBZY      (1 << 0)    /* MII Busy */
+#define LAN9118_MII_DATA            0x7 /* MII Data */
+#define LAN9118_FLOW                0x8 /* Flow Control */
+#define LAN9118_FLOW_FCPT(t)        ((t) << 16) /* Pause Time */
+#define LAN9118_FLOW_FCPASS         (1 << 2)    /* Pass Control Frame */
+#define LAN9118_FLOW_FCEN           (1 << 1)    /* Flow Control Enable */
+#define LAN9118_FLOW_FCBUSY         (1 << 0)    /* Flow Control Busy */
+#define LAN9118_VLAN1               0x9 /* VLAN1 Tag */
+#define LAN9118_VLAN2               0xa /* VLAN2 Tag */
+#define LAN9118_WUFF                0xb /* Wake-up Frame Filter */
+#define LAN9118_WUCSR               0xc /* Wake-up Control and Status */
+
+/* PHY Registers */
+#define LAN9118_MCSR                0x11    /* Mode Control/Status Register */
+#define LAN9118_MCSR_EDPWRDOWN      (1 << 13) /* Energy Detect Power Down */
+#define LAN9118_MCSR_ENERGYON       (1 << 1)
+#define LAN9118_SMR                 0x12    /* Special Modes Register */
+#define LAN9118_SMR_PHYAD           (0x01)
+#define LAN9118_SCSI                0x1b    /* Special Control/Status Indications */
+#define LAN9118_SCSI_VCOOFF_LP      (1 << 10)
+#define LAN9118_SCSI_XPOL           (1 << 4)  /* Polarity state */
+#define LAN9118_ISR                 0x1d    /* Interrupt Source Register */
+#define LAN9118_IMR                 0x1e    /* Interrupt Mask Register */
+#define LAN9118_I_ENERGYON          (1 << 7)
+#define LAN9118_I_AUTONEGOCOMPL     (1 << 6)
+#define LAN9118_I_REMOTEFAULT       (1 << 5)
+#define LAN9118_I_LINKDOWN          (1 << 4)
+#define LAN9118_I_AUTONEGOLPACK     (1 << 3) /* AutoNego LP Acknowledge */
+#define LAN9118_I_PDF               (1 << 2) /* Parallel Detection Fault */
+#define LAN9118_I_AUTONEGOPR        (1 << 1) /* AutoNego Page Received */
+#define LAN9118_PHYSCSR             0x1f    /* PHY Special Control/Status Reg */
+#define LAN9118_PHYSCSR_AUTODONE    (1 << 12) /* AutoNego done indication */
+#define LAN9118_PHYSCSR_SI_10       (1 << 2)  /* Speed Indication */
+#define LAN9118_PHYSCSR_SI_100      (2 << 2)
+#define LAN9118_PHYSCSR_SI_FDX      (4 << 2)
+
+
+/* TX Command 'A' Format */
+#define LAN9118_TXC_A_IC        (1 << 31) /* Interrupt on Completion */
+#define LAN9118_TXC_A_BEA_4B    (0 << 24) /* Buffer End Alignment: 4B */
+#define LAN9118_TXC_A_BEA_16B   (1 << 24) /*                      16B */
+#define LAN9118_TXC_A_BEA_32B   (2 << 24) /*                      32B */
+#define LAN9118_TXC_A_DSO(x)    ((x) << 16) /*Data Start Offset: bytes*/
+#define LAN9118_TXC_A_FS        (1 << 13) /* First Segment */
+#define LAN9118_TXC_A_LS        (1 << 12) /* Last Segment */
+#define LAN9118_TXC_A_BS(x)     ((x) << 0) /* Buffer Size */
+
+/* TX Command 'B' Format */
+#define LAN9118_TXC_B_PT(x)     ((x) << 16) /* Packet Tag */
+#define LAN9118_TXC_B_ACRCD     (1 << 13)  /* Add CRC Disable */
+#define LAN9118_TXC_B_DEFP      (1 << 12)  /* Dis Ether Frame Padding */
+#define LAN9118_TXC_B_PL(x)     ((x) << 0) /* Packet Length */
+
+/* TX Status Format */
+#define LAN9118_TXS_PKTTAG(x)   (((x) >> 16) & 0xff) /* Packet Tag */
+#define LAN9118_TXS_ES          (1 << 15)   /* Error Status */
+#define LAN9118_TXS_LOC         (1 << 11)   /* Loss Of Carrier */
+#define LAN9118_TXS_NC          (1 << 10)   /* No Carrier */
+#define LAN9118_TXS_LCOL        (1 << 9)    /* Late Collision */
+#define LAN9118_TXS_ECOL        (1 << 8)    /* Excessive Collision*/
+#define LAN9118_TXS_COLCNT(x)   (((x) >> 3) & 0xf) /* Collision Count */
+#define LAN9118_TXS_ED          (1 << 2)    /* Excessive Deferral */
+#define LAN9118_TXS_DEFERRED    (1 << 0)    /* Deferred */
+
+/* RX Status Format */
+#define LAN9118_RXS_FILTFAIL    (1 << 30) /* Filtering Fail */
+#define LAN9118_RXS_PKTLEN(x)   (((x) >> 16) & 0x3fff) /* Packet Len */
+#define LAN9118_RXS_ES          (1 << 15) /* Error Status */
+#define LAN9118_RXS_BCF         (1 << 13) /* Broadcast Frame */
+#define LAN9118_RXS_LENERR      (1 << 12) /* Length Error */
+#define LAN9118_RXS_RUNTF       (1 << 11) /* Runt Frame */
+#define LAN9118_RXS_MCF         (1 << 10) /* Multicast Frame */
+#define LAN9118_RXS_FTL         (1 << 7)  /* Frame Too Long */
+#define LAN9118_RXS_COLS        (1 << 6)  /* Collision Seen */
+#define LAN9118_RXS_FT          (1 << 5)  /* Frame Type */
+#define LAN9118_RXS_RWTO        (1 << 4)  /* Rcv Watchdog time-out */
+#define LAN9118_RXS_MIIERR      (1 << 3)  /* MII Error */
+#define LAN9118_RXS_DBIT        (1 << 2)  /* Drabbling Bit */
+#define LAN9118_RXS_CRCERR      (1 << 1)  /* CRC Error */
 
+/* Basic mode control register. */
+#define LAN9118_BMCR_ANRESTART      0x0200  /* Auto negotiation restart  */
+#define LAN9118_BMCR_ANENABLE       0x1000  /* Enable auto negotiation   */
+#define LAN9118_BMCR_RESET          0x8000  /* Reset the DP83840     */
+#define LAN9118_BMSR_LSTATUS        0x0004  /* Link status    */
 
 /* Generic MII registers. */
+#define LAN9118_MII_BMCR            0x00  /* Basic mode control register */
+#define LAN9118_MII_BMSR            0x01  /* Basic mode status register  */
+#define LAN9118_MII_ADVERTISE       0x04  /* Advertisement control register */
 
-#define MII_BMCR        0x00    /* Basic mode control register */
-#define MII_BMSR        0x01    /* Basic mode status register  */
-#define MII_PHYSID1     0x02    /* PHYS ID 1               */
-#define MII_PHYSID2     0x03    /* PHYS ID 2               */
-#define MII_ADVERTISE   0x04    /* Advertisement control reg   */
-#define MII_LPA         0x05    /* Link partner ability reg    */
-#define MII_EXPANSION   0x06    /* Expansion register          */
-#define MII_CTRL1000    0x09    /* 1000BASE-T control          */
-#define MII_STAT1000    0x0a    /* 1000BASE-T status           */
-#define MII_ESTATUS     0x0f    /* Extended Status */
-#define MII_DCOUNTER    0x12    /* Disconnect counter          */
-#define MII_FCSCOUNTER  0x13    /* False carrier counter       */
-#define MII_NWAYTEST    0x14    /* N-way auto-neg test reg     */
-#define MII_RERRCOUNTER 0x15    /* Receive error counter       */
-#define MII_SREVISION   0x16    /* Silicon revision        */
-#define MII_RESV1       0x17    /* Reserved...             */
-#define MII_LBRERROR    0x18    /* Lpback, rx, bypass error    */
-#define MII_PHYADDR     0x19    /* PHY address             */
-#define MII_RESV2       0x1a    /* Reserved...             */
-#define MII_TPISTATUS   0x1b    /* TPI status for 10mbps       */
-#define MII_NCONFIG     0x1c    /* Network interface config    */
+#define LAN9118_GPT_CFG_TIMER_EN    0x20000000  /* R/W */
 
-/* Basic mode control register. */
-#define BMCR_RESV       0x003f  /* Unused...               */
-#define BMCR_SPEED1000  0x0040  /* MSB of Speed (1000)         */
-#define BMCR_CTST       0x0080  /* Collision test          */
-#define BMCR_FULLDPLX   0x0100  /* Full duplex             */
-#define BMCR_ANRESTART  0x0200  /* Auto negotiation restart    */
-#define BMCR_ISOLATE    0x0400  /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN      0x0800  /* Powerdown the DP83840       */
-#define BMCR_ANENABLE   0x1000  /* Enable auto negotiation     */
-#define BMCR_SPEED100   0x2000  /* Select 100Mbps          */
-#define BMCR_LOOPBACK   0x4000  /* TXD loopback bits           */
-#define BMCR_RESET      0x8000  /* Reset the DP83840           */
+#define LAN9118_RX_STS_PKT_LEN      0x3FFF0000
+#define LAN9118_TX_STS_UNDERRUN     0x00000002
+
+#define LAN9118_HW_CFG_SF           0x00100000  /* R/W */
 
-/* Basic mode status register. */
-#define BMSR_ERCAP      0x0001  /* Ext-reg capability          */
-#define BMSR_JCD        0x0002  /* Jabber detected         */
-#define BMSR_LSTATUS    0x0004  /* Link status             */
-#define BMSR_ANEGCAPABLE    0x0008  /* Able to do auto-negotiation */
-#define BMSR_RFAULT     0x0010  /* Remote fault detected       */
-#define BMSR_ANEGCOMPLETE   0x0020  /* Auto-negotiation complete   */
-#define BMSR_RESV       0x00c0  /* Unused...               */
-#define BMSR_ESTATEN    0x0100  /* Extended Status in R15 */
-#define BMSR_100HALF2   0x0200  /* Can do 100BASE-T2 HDX */
-#define BMSR_100FULL2   0x0400  /* Can do 100BASE-T2 FDX */
-#define BMSR_10HALF     0x0800  /* Can do 10mbps, half-duplex  */
-#define BMSR_10FULL     0x1000  /* Can do 10mbps, full-duplex  */
-#define BMSR_100HALF    0x2000  /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL    0x4000  /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4   0x8000  /* Can do 100mbps, 4k packets  */
+#define LAN9118_INT_STS_RSFL        0x00000008  /* R/WC */
+#define LAN9118_INT_EN_RDFL_EN      0x00000020  /* R/W */
+#define LAN9118_MAC_CR_HBDIS        0x10000000
 
-#endif
+#endif  /* _LAN9118REG_H_ */

bsp/qemu-vexpress-a9/drivers/drv_timer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -89,7 +89,7 @@ void timer_init(int timer, unsigned int preload)
 {
     uint32_t val;
 
-    if (timer == 0) 
+    if (timer == 0)
     {
         /* Setup Timer0 for generating irq */
         val = TIMER_CTRL(TIMER01_HW_BASE);
@@ -101,8 +101,8 @@ void timer_init(int timer, unsigned int preload)
 
         /* enable timer */
         TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE;
-    } 
-    else 
+    }
+    else
     {
         /* Setup Timer1 for generating irq */
         val = TIMER_CTRL(TIMER23_HW_BASE);
@@ -122,7 +122,7 @@ void timer_clear_pending(int timer)
     if (timer == 0)
     {
         TIMER_INTCLR(TIMER01_HW_BASE) = 0x01;
-    } 
+    }
     else
     {
         TIMER_INTCLR(TIMER23_HW_BASE) = 0x01;

bsp/qemu-vexpress-a9/drivers/drv_timer.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/qemu-vexpress-a9/drivers/secondary_cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/qemu-vexpress-a9/drivers/serial.c

@@ -1,26 +1,7 @@
 /*
- *  serial.c UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/serial.h

@@ -1,26 +1,7 @@
 /*
- *  UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/vexpress_a9.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/qemu-vexpress-a9/rtconfig.h

@@ -47,7 +47,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x30104
+#define RT_VER_NUM 0x30105
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_A
 #define ARCH_ARM_CORTEX_A9

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -55,6 +55,9 @@ if GetDepend('BSP_USING_LCD_MIPI'):
 if GetDepend('BSP_USING_ONCHIP_RTC'):
     src += ['drv_rtc.c']
 
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32G0']):
+    src += ['drv_flash/drv_flash_g0.c']
+
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
     src += ['drv_flash/drv_flash_f0.c']
 
@@ -73,6 +76,8 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
     src += ['drv_flash/drv_flash_l4.c']
 	
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
+    src += ['drv_flash/drv_flash_h7.c']
 if GetDepend('RT_USING_HWCRYPTO'):
     src += ['drv_crypto.c']
 	
@@ -88,6 +93,9 @@ if GetDepend(['BSP_USING_USBD']):
 if GetDepend(['BSP_USING_PULSE_ENCODER']):
     src += ['drv_pulse_encoder.c']
 
+if GetDepend(['BSP_USING_USBH']):
+    src += ['drv_usbh.c']
+
 src += ['drv_common.c']
 
 path =  [cwd]

bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
 #define UART1_RX_DMA_INSTANCE            DMA1_Channel3
 #define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
 #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
-#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
 #define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn

bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -59,7 +59,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -49,7 +49,7 @@ extern "C" {
     }
 #endif /* UART2_CONFIG */
 #endif /* BSP_USING_UART2 */
-    
+
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
 #define UART2_DMA_RX_CONFIG                                            \

bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC1_CONFIG */
 #endif /* BSP_USING_ADC1 */
 
@@ -45,7 +45,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC2_CONFIG */
 #endif /* BSP_USING_ADC2 */
 
@@ -61,7 +61,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC3_CONFIG */
 #endif /* BSP_USING_ADC3 */
 

bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,6 +17,17 @@
 extern "C" {
 #endif
 
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
 #ifdef BSP_USING_PWM2
 #ifndef PWM2_CONFIG
 #define PWM2_CONFIG                             \

bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -59,7 +59,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -91,7 +91,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -134,7 +134,7 @@ extern "C" {
 #endif
 /* DMA2 stream3 */
 
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)	
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
 #define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
 #define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream3

bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -27,7 +27,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -74,7 +74,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -109,7 +109,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -179,7 +179,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
@@ -214,7 +214,7 @@ extern "C" {
     }
 #endif /* UART6_DMA_RX_CONFIG */
 #endif /* BSP_UART6_RX_USING_DMA */
-		
+
 #if defined(BSP_UART6_TX_USING_DMA)
 #ifndef UART6_DMA_TX_CONFIG
 #define UART6_DMA_TX_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -157,12 +157,12 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
 
 /* DMA2 stream1 */
@@ -208,12 +208,12 @@ extern "C" {
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
 #define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
 
 /* DMA2 stream4 */

bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -61,6 +61,17 @@ extern "C" {
 #endif /* PWM5_CONFIG */
 #endif /* BSP_USING_PWM5 */
 
+#ifdef BSP_USING_PWM9
+#ifndef PWM9_CONFIG
+#define PWM9_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM9,         \
+       .name                    = "pwm9",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM9_CONFIG */
+#endif /* BSP_USING_PWM9 */
+
 #ifdef BSP_USING_PWM12
 #ifndef PWM12_CONFIG
 #define PWM12_CONFIG                            \

bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__

bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -129,7 +129,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -163,7 +163,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,6 +27,17 @@ extern "C" {
     }
 #endif /* TIM_DEV_INFO_CONFIG */
 
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                                         \
+    {                                                       \
+       .tim_handle.Instance     = TIM3,                     \
+       .tim_irqn                = TIM3_IRQn,                \
+       .name                    = "timer3",                 \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
 #ifdef BSP_USING_TIM11
 #ifndef TIM11_CONFIG
 #define TIM11_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -27,7 +27,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -74,7 +74,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -109,7 +109,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -179,7 +179,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
@@ -214,7 +214,7 @@ extern "C" {
     }
 #endif /* UART6_DMA_RX_CONFIG */
 #endif /* BSP_UART6_RX_USING_DMA */
-		
+
 #if defined(BSP_UART6_TX_USING_DMA)
 #ifndef UART6_DMA_TX_CONFIG
 #define UART6_DMA_TX_CONFIG                                        \
@@ -249,7 +249,7 @@ extern "C" {
     }
 #endif /* UART7_DMA_RX_CONFIG */
 #endif /* BSP_UART7_RX_USING_DMA */
-		
+
 #if defined(BSP_UART7_TX_USING_DMA)
 #ifndef UART7_DMA_TX_CONFIG
 #define UART7_DMA_TX_CONFIG                                        \
@@ -284,7 +284,7 @@ extern "C" {
     }
 #endif /* UART8_DMA_RX_CONFIG */
 #endif /* BSP_UART8_RX_USING_DMA */
-		
+
 #if defined(BSP_UART8_TX_USING_DMA)
 #ifndef UART8_DMA_TX_CONFIG
 #define UART8_DMA_TX_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__

bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -60,7 +60,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -94,7 +94,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -128,7 +128,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -162,7 +162,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-05     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_UART1)
-#ifndef UART1_CONFIG    
+#ifndef UART1_CONFIG
 #define UART1_CONFIG                                                \
     {                                                               \
         .name = "uart1",                                            \

bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__

bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -129,7 +129,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -163,7 +163,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,7 @@
  * 2019-01-03     zylx         modify dma support
  * 2019-10-03     xuzhuoyi     modify for STM32G4
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -50,7 +50,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -97,7 +97,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -132,7 +132,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -202,7 +202,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,63 +19,69 @@ extern "C" {
 
 #ifdef BSP_USING_ADC1
 #ifndef ADC1_CONFIG
-#define ADC1_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC1,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC1_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC1,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC1_CONFIG */
 #endif /* BSP_USING_ADC1 */
 
 #ifdef BSP_USING_ADC2
 #ifndef ADC2_CONFIG
-#define ADC2_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC2,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC2_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC2,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC2_CONFIG */
 #endif /* BSP_USING_ADC2 */
 
 #ifdef BSP_USING_ADC3
 #ifndef ADC3_CONFIG
-#define ADC3_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC3,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC3_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC3,                          \
+       .Init.ClockPrescaler            = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC3_CONFIG */
 #endif /* BSP_USING_ADC3 */

bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,27 +19,21 @@ extern "C" {
 #endif
 
 /* DMA1 stream0 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
-#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
-#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
-#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
-#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
-#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
-#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
-#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART2_RX_DMA_REQUEST             DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                 DMA1_Stream0_IRQn
 #endif
 
 /* DMA1 stream1 */
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
-#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
-#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
-#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream1
+#define UART2_TX_DMA_REQUEST             DMA_REQUEST_USART2_TX
+#define UART2_TX_DMA_IRQ                 DMA1_Stream1_IRQn
 #endif
 
 /* DMA1 stream2 */
@@ -49,12 +43,6 @@ extern "C" {
 #define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
 #define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
 #define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
-#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
-#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
-#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
-#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
 #endif
 
 /* DMA1 stream3 */
@@ -83,12 +71,6 @@ extern "C" {
 #define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
 #define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
 #define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
-#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
-#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
-#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
-#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
 #endif
 
 /* DMA1 stream6 */
@@ -109,12 +91,6 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
-#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
-#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
-#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
 
 /* DMA2 stream1 */
@@ -133,18 +109,6 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
-#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
-#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
-#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
-#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
-#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
-#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
-#define QSPI_DMA_INSTANCE                DMA2_Stream2
-#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
-#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
 #endif
 
 /* DMA2 stream3 */
@@ -154,18 +118,6 @@ extern "C" {
 #define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
 #define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
 #define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
-#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
-#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
-#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
 
 /* DMA2 stream4 */
@@ -175,12 +127,6 @@ extern "C" {
 #define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
 #define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
 #define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
 #endif
 
 /* DMA2 stream5 */
@@ -190,18 +136,6 @@ extern "C" {
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
 #define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
-#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
-#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
-#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
-#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
-#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
-#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
-#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
-#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
 #endif
 
 /* DMA2 stream6 */

bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__

bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -60,7 +60,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -94,7 +94,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -128,7 +128,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -162,7 +162,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \

bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-05     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_UART1)
-#ifndef UART1_CONFIG    
+#ifndef UART1_CONFIG
 #define UART1_CONFIG                                                \
     {                                                               \
         .name = "uart1",                                            \
@@ -31,12 +31,12 @@ extern "C" {
 
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
-#define UART1_DMA_RX_CONFIG                                            \
+#define UART1_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART1_RX_DMA_INSTANCE,                         \
-        .channel = UART1_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART1_RX_DMA_RCC,                               \
-        .dma_irq = UART1_RX_DMA_IRQ,                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request = UART1_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART1_RX_DMA_RCC,                                \
+        .dma_irq = UART1_RX_DMA_IRQ,                                \
     }
 #endif /* UART1_DMA_RX_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */
@@ -54,15 +54,26 @@ extern "C" {
 
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
-#define UART2_DMA_RX_CONFIG                                            \
+#define UART2_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART2_RX_DMA_INSTANCE,                         \
-        .channel = UART2_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART2_RX_DMA_RCC,                               \
-        .dma_irq = UART2_RX_DMA_IRQ,                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request = UART2_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_RX_DMA_RCC,                                \
+        .dma_irq = UART2_RX_DMA_IRQ,                                \
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request = UART2_TX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_TX_DMA_RCC,                                \
+        .dma_irq = UART2_TX_DMA_IRQ,                                \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
 
 #if defined(BSP_USING_UART3)
 #ifndef UART3_CONFIG
@@ -77,12 +88,12 @@ extern "C" {
 
 #if defined(BSP_UART3_RX_USING_DMA)
 #ifndef UART3_DMA_RX_CONFIG
-#define UART3_DMA_RX_CONFIG                                            \
+#define UART3_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART3_RX_DMA_INSTANCE,                         \
-        .channel = UART3_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART3_RX_DMA_RCC,                               \
-        .dma_irq = UART3_RX_DMA_IRQ,                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request = UART3_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART3_RX_DMA_RCC,                                \
+        .dma_irq = UART3_RX_DMA_IRQ,                                \
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
@@ -100,12 +111,12 @@ extern "C" {
 
 #if defined(BSP_UART4_RX_USING_DMA)
 #ifndef UART4_DMA_RX_CONFIG
-#define UART4_DMA_RX_CONFIG                                            \
+#define UART4_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART4_RX_DMA_INSTANCE,                         \
-        .channel = UART4_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART4_RX_DMA_RCC,                               \
-        .dma_irq = UART4_RX_DMA_IRQ,                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request = UART4_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART4_RX_DMA_RCC,                                \
+        .dma_irq = UART4_RX_DMA_IRQ,                                \
     }
 #endif /* UART4_DMA_RX_CONFIG */
 #endif /* BSP_UART4_RX_USING_DMA */
@@ -123,12 +134,12 @@ extern "C" {
 
 #if defined(BSP_UART5_RX_USING_DMA)
 #ifndef UART5_DMA_RX_CONFIG
-#define UART5_DMA_RX_CONFIG                                            \
+#define UART5_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART5_RX_DMA_INSTANCE,                         \
-        .channel = UART5_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART5_RX_DMA_RCC,                               \
-        .dma_irq = UART5_RX_DMA_IRQ,                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                          \
+        .request = UART5_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART5_RX_DMA_RCC,                                \
+        .dma_irq = UART5_RX_DMA_IRQ,                                \
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */

bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -49,7 +49,7 @@ extern "C" {
     }
 #endif /* UART2_CONFIG */
 #endif /* BSP_USING_UART2 */
-    
+
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
 #define UART2_DMA_RX_CONFIG                                            \

bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
@@ -28,7 +28,7 @@ extern "C" {
     }
 #endif /* QSPI_BUS_CONFIG */
 #endif /* BSP_USING_QSPI */
-    
+
 #ifdef BSP_QSPI_USING_DMA
 #ifndef QSPI_DMA_CONFIG
 #define QSPI_DMA_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -60,8 +60,20 @@ extern "C" {
         .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_RX_CONFIG */
-#endif /* BSP_UART1_RX_USING_DMA */  
-   
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .request  = UART1_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+
 #if defined(BSP_USING_UART2)
 #ifndef UART2_CONFIG
 #define UART2_CONFIG                                                \
@@ -85,6 +97,18 @@ extern "C" {
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
 
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+
 #if defined(BSP_USING_UART3)
 #ifndef UART3_CONFIG
 #define UART3_CONFIG                                                \
@@ -108,8 +132,20 @@ extern "C" {
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
 
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+
 #ifdef __cplusplus
 }
-#endif 
+#endif
 
 #endif