Merge pull request #3 from ErikChanGit/master

release rt-thread v4.0.4

.gitattributes

@@ -1,3 +1,8 @@
+*.c linguist-language=C
+*.C linguist-language=C
+*.h linguist-language=C
+*.H linguist-language=C
+
 * text=auto
 
 *.S text

.gitignore

@@ -10,6 +10,7 @@
 *.idb
 *.ilk
 *.old
+*.crf
 build
 Debug
 documentation/html
@@ -24,6 +25,8 @@ documentation/html
 *.d
 tools/kconfig-frontends/kconfig-mconf
 packages
+dist
+dist_ide_project
 cconfig.h
 GPUCache
 
@@ -34,3 +37,6 @@ ncscope.*
 #ctag files
 tags
 
+.idea
+CMakeLists.txt
+cmake-build-debug

ChangeLog.md

@@ -1,3 +1,309 @@
+# RT-Thread v4.0.4 released
+
+Change log since v4.0.3
+
+## Kernel
+
+- Update memheap auto binding policy
+- Remove rt_thread_exit function
+- Improve API annotations and code comments
+- Standardize internal function naming
+- Add recessive RT_USING_ASM_MEMCPY definition to Kconfig
+- Add  RT_PRINTF_LONGLONG option to Kconfig, not selected by default
+- Clear support for RT_PRINTF_LONGLONG in kservice.c
+- Fix RT_PRINTF_LONGLONG is supported by default in 64-bit mode
+- Solve the problem that FINSH cannot respond to serial port input in multi-core mode
+- Optimize the comment for ipc
+- Adjust the code to support cpu usage
+- Adjust the exception handling code structure to support backtrace functionality
+- Remove the mutex RT_IPC_FLAG_FIFO  function
+- Remove switch_to_sethook function
+- Add idle reclaimed resources
+- Change defined(__CC_ARM) || defined(__CLANG_ARM) to  ifdef __ARMCC_VERSION
+- Fix comment error for rt_mutex_detach().
+- Remove the rt_sscanf statement
+- Add RT_WEAK for rt_malloc_align,rt_free_align
+- Changed the memory heap protection mechanism from FIFO to PRIO
+- Remove fix priority inversion bug of mutex
+- Add volatile to the rt_tick variable to prevent compiler optimization problems
+- Keep the atomicity of idle task hook function calls
+- Fix the crash problem after opening Oz optimization on ac6.
+- Add protect to the rt_tick_increase critical section
+- Add rt_mutex_trytake function
+- Improve kernel stability
+- Remove C99 dependencies
+- Add conditional compilation for  _has_defunct_thread function
+- Clarify the context
+- Add get/set microsecond time control command
+- Fix code comment error for function rt_memset().
+- Remove rt_device_init_all() function
+- Adjust graphics device driver definitions
+- Unsigned comparisons should still be used when the signed comparison is undone
+- Fix compile error when using LOG_HEX(...) function but RT_USING_ULOG not defined
+
+## Components
+
+- Support armclang
+- Optimized system for suppoort gcc
+- Update Libc
+  - Create a gcc folder and merge the newlib and partical folders
+  - Optimized system to support GCC
+  - Fix support system function
+  - Fix asctime_r return value
+  - Lowers the action of calling printf before libc initialization to the warning level
+  - Replace dfs_select.h with standard sys/select.h
+  - The RT_LIBC_USING_TIME macro definition remains after RT_USING_LIBC is enabled
+  - Optimized fcntil.h definition
+  - Fix syscall was optimized to incorporate minilibc into syscalls.c file
+  - Rebuild _libc_init_array to prevent chip startup failure under GCC
+  - RT_USING_NEWLIB and math libraries are defined without libc enabled
+  - Fix the conflict warning of read and write functions
+  - Remove libc_signal.h and libc_fdset.h
+  - Fix an issue where keil did not compile properly
+  - Remove rtlibc, libc_stdio.h, libc_dirent.h, libc_ioctl.h，libc_signal.h，libc_fdset.h，libc_errno.h， libc_limits.h
+  - Add delay when the scheduler is not running
+  - Fix armClang support issues
+  - usleep supports calling in interrupts.
+  - Fix sys header file import when liBC is not enabled
+  - The gettimeofday () function supports time zones and  specification set_timeval/get_timeval returns a value
+  - Fix warning of posix_signal
+  - Fix bug where nonegcc folder path was not added to project in Simulator Win32
+  - Fix error caused by libc removing sys/errno.h file
+  - Remove _TIMESPEC_DEFINED
+  - Add the RT_LIBC_FIXED_TIMEZONE default value to time.c to prevent projects that do not have RT_LIBC_FIXED_TIMEZONE configured
+  - Add the ability to manually set the time zone
+  - Add riscv.c dlmodule can support riscv architecture
+  - Implement pid_t gettid(void)
+  - Implement  isatty()
+  - Implement set_timeval
+  - Change the libc directory to common and none-gcc
+  - Remove dlib and armlibc `sys` folder
+  - Fix MDK build error when using gmtime_r
+  - Optimize get_timeval and  set_timeval  conditional compiled code structure
+  - Update mktime support fixed timezone
+  - Add microseconds time get feature in gettimeofday
+  - LOG_W will cause a recursive printing if ulog timestamp function is turned on
+  - Remove inherent mutex protect
+- Update drivers
+  - Fix stdint in cputime
+  - Delete NTP configurations
+  - Make rt_soft_rtc_init private
+  - Bypass controlling commands in touch class to driver
+  - Update the RTC device driver framework to unify and simplify RTC device registration and access
+  - Add i2c bus control api
+  - Update uac class, remove GPL code
+  - Fix measurement unit of "percentage" to "permillage" for accuracy
+  - Add spo2 sensor support in drivers/include/drivers/sensor.h and drivers/sensors/sensor.c
+  - Optimize pin.h, sensor.h, rtdevice.h to avoid reverse inclusion
+  - Update usb enlarge uconfig_descriptor's data array space
+  - Add security devices
+- [netif] Fix the eth_tx_msg protection
+- Update utest
+  - Add kernel testcases
+  - Fix TC_FAIL_LIST_MARK_FAILED Subscript calculation error
+- Fix comments error in ringbuffer and workqueue
+- Update ringbuffer
+  - Add an interface comment
+  - Local variables are used to prevent resource competition
+  - Write_index bug in rt_ringbuffer_put_force
+- Update workqueue
+  - Add an interface comment
+  - Remove rt_delayed_work_init()
+  - Privatize the rt_work_sys_workqueue_init function
+  - Fix an unexpected suspension of critical condition threads
+- Fixed timer ASSERT exception due to multithreaded scheduling
+- Optimize the inclusion relationship between dfs.h and dirent.h
+- Update finsh
+  - Restore the FINSH_USING_MSH  definition for compatibility
+  - Expose the finsh_getchar function
+  - Fixed _cmd_xxx command unavailable due to finsh removal
+  - Update Kconfig is more hierarchical
+  - The finsh component can optionally include built-in commands
+  - Repaie that the table key on msh do not work
+  - The list-thread command adds the bind core display for multiple cores
+  - Add support for tasking toolchain
+  - Add mount/umount cmd
+- Fix ringblk_buf  error when no longer using dynamic memory
+- [timezone] implement timezone
+- [DeviceDriver] Change the special device commands form 0x1X to 0x2X. It will avoid same of general device commands
+- Update AT
+  - Update old_urc_table to new_urc_table
+  - Optimized at socket memory leak modification
+  - Add at_utils_send virtual function
+  - Fix at_vprintf and at_vprintfln and end_sign response
+  - Fix at_server_getchar spelling error
+- Add device type USBOTG to redef.h
+- [newlib] fix compile error when closing RT_USING_CONSOLE
+- Update rtc
+  - Add RT_DEVICE_CTRL_RTC_GET_TIMEVAL and RT_DEVICE_CTRL_RTC_SET_TIMEVAL ops
+  - Remove RT_DEVICE_CTRL_RTC_GET_TIME_US and RT_DEVICE_CTRL_RTC_SET_TIME_US. Add RT_DEVICE_CTRL_RTC_GET_TIMEVAL and RT_DEVICE_CTRL_RTC_SET_TIMEVAL. The RT_DEVICE_CTRL_RTC_GET_TIMEVAL cmd can get second time and microsecond time.
+  - Change core.c/.h name to rtc.c /.h
+  - Update rt_rtc_dev_register function name to  rt_hw_rtc_register
+  - Change localtime name to localtime_r
+- [ethernetif] replace rt_memcpy with SMEMCPY
+- [sdio] remove rt_mmcsd_blk_init
+- Update time
+  - Fix an issue where POSIX related functions were not protected for critical sections
+  - Adjust the judgment logic of posiX related functions to obtain time results
+  - Rename nonstandard liBC functions and reposition the time.h definition
+  - Revert the old code
+- Fix the sem init check bug in pthread.
+- Fix MMC initialization error, write card->csd as card->cid
+- Update serial
+  - Add CTS/RTS flowcontrol
+  - Implement function of getting window's size(TIOCGWINSZ)
+  - Optimized RT_USING_POSIX_TERMIOS precompilation
+  - Serial_v2 support device ops feature
+  - Fix the problem that serial Close did not clear the callback interface
+  - Optimize send non-blocking problem when serial_close does not execute rt_completion_done
+  - Optimize DMA receive processing flow and decouple the driver to call the API interface of the serial port framework
+  - Added the Serial V2 framework and the Serial port driver based on STM32
+  - Serial_v2 support device ops feature
+  - Fix do RT_DEVICE_CTRL_CLOSE cmd when close serial device regardless of DMA config
+- Update lwip
+  - Fix lwIP critical section protection bug
+  - Set default lwip stack for old bsp folder.
+  - Change default lwip stack to lwip2.0.3
+  - Fix delete useless code.
+  - The "event_callback" will be change by RT-Thread dfs.
+  - Adjust the string.h position
+  - LWIP_TIMEVAL_PRIVATE: provided by <sys/time.h>
+  - LWIP2.0.2 and 2.1.2 remove ERRNO
+  - Remove ESHUTDOWN from LWIP
+  - Remove the possible critical zone risk
+  - Iperf speed test have been stable.
+  - The overflow problem of lwip rx thread mailbox.
+- [pm] Index should be less than PM_MODLUE_MAX_ID
+- [cputime] Add sys/errno.h
+- Update msh
+  - Implement tail command
+  - Fix shell msh_exec memory over-bound.
+- Update dfs
+  - Fix F_GETFL/F_SETFL should be handled by the drivers.
+  - Change the default maximum number and type of the file system to 4
+  - Add format_ignore file, exclude fatfs format check
+  - Add comments for _device_fs
+- Update ymodem
+  - Modified the enabling conditions of YMODEM USING FILE TRANSFER
+  - Check the file path's legitimacy of'sy' command
+- Add new component: rt-link
+- [net] Add the function of set [internet up] status, activate the callback.
+- [components]  Remove uip
+- Update ulog
+  - Using gettimeofday for timestamp get
+  - Fix thread info show when kernel not startup
+  - Increase the usec check time
+  - Add output locker enabled API
+- Update FatFs
+  - Update the mutex protection timeout can be set using Kconfig
+  - Fix the time dependent function opening condition
+
+## BSP and CPU porting
+
+- Support armclang
+- [stm32h750-artpi-h750] Complete  bsp
+- [ls2k] Fix missing header file applications
+- [AT32] Complete  BSP
+- Add _CRT_DECLARE_NONSTDC_NAMES=0 macro definition in simulator bsp
+- Refresh the project and remove rtlibc and duplicate definitions in simulator bsp
+- Update libcpu
+  - Modified the irq handle interface rt_hw_trap_IRq to support intercore IPI interrupt processing
+  - Add interface dcache invalidate/dcache clean&invalidate
+  - Adjust the stack_top to bss
+  - Remove gtimer/pmu from cortex-a
+  - Repair hard fault return bug
+  - Add in Cortex-A to turn on the _rt_FFS implementation when RT_USING_CPU_FFS macro definition
+  - Add interface to get Cortex-A Generic Timer frequency
+  - Add GICV3 interrupt controller code, updated MenuConfig configuration options with utest config.h
+  - Tidy up the cortex-a aarch32 boot code
+  - Fix RTC driver compile error
+  - add gic&gtimer interface
+  - Optimized the condition for automatically enabling FPU when cortex-A does not define an exception
+  - Fix inconsistent function behavior with different optimization levels
+  - Correct cortex-m23 rvds.S including for armclang platform.
+- Fix simulator:
+  -  Fix sd_sim.c compilation error using rt_dgb instead of old debug output
+  -  Refresh the project and remove rtlibc and duplicate definitions
+  -  Add _CRT_DECLARE_NONSTDC_NAMES=0 macro definition
+- Fix stm32f407-explorer
+  - Optimize fal Settings
+  - Update readme
+  - Implement ESP8266 configuration in extended module driver menu
+  - Optimized Kconfig file system naming, SFUD registration w25Q128 name adaptive, avoid users to set more than one step name
+- Add more BSP on BSP framework:
+  - VangoV85xx
+  - hc32l136
+  - ap32f103xe-miniboard
+  - gd32407v-start
+  - mm32f103x
+  - ch32f103c8-core
+  - n32g452xx
+  - hc32l196
+  - hc32f460petb
+  - gd32f105c-eval
+  - nrf52833
+  - hc32f030c8t6-mini
+  - fm33lc0xx
+  - stm32l4r9-st-sensortile-box
+  - stm32f302-st-nucleo
+  - mm32f3270
+  - stm32f407-robomaster-c
+  - qemu-riscv-virt64
+  - gd32350r-eval
+  - stm32f407-armfly-v5
+  - juicevm
+  - stm32f207-st-nucleo
+  - m2354
+- [ch32f103c8-core] rename function name: ch32f1_hwtimer_clock_init, ch32f1_hwtimer_clock_get
+- Fix thread-smart
+  - Support T-HEAD Xuantie-E9xx Series CPU on Smart-EVB, eg. E906/F/D/P, E907/F/D/P
+  - Formatting  code
+  - Add QEMU support, and code optimization for thead extension
+- [mm32f327x] Fix .ignore_format file path error
+- [hc32f4a0] Fix syntax errors in scons scripts
+- [x86] Enable romfs
+- Replace gmtime with gmtime_r
+- [swm320-lp100] Update  libraries
+- [ft2004] Add gtimer support and fixed can driver initialization issues
+- Fix bluetrum
+  - Optimizing the uart driver
+  - Fix RTC driver building errors
+  - Add RT_USING_CONSOLE judgment
+- [nrf52x] Optimize drv_wdt.c
+- [mm32f327x] Add on-chip flash driver
+- [imxrt1064-nxp-evk] Improved I2C, UART,LCD kconfig, fixed i2C imXrT_i2C_mST_xfer function that would write an address before reading data
+- [w60x] Fix UART1 function unavailable
+- [gd32450z-eval] Update firmware library and delete usb relate library codes
+- [raspi4-32] Update raspi4-32 eth drv
+- [bluetrum] Fix uart1 and uart2 cannot recv data
+- Fix STM32
+  - Implement rtc driver to RTC framework V2.0
+  - Add spi config increases irq_type
+  - Fix driver library USBH initialization errors
+  - Add timeval ops for STM32 platform Sub-second timestamp.
+- Remove BSP on BSP framework:
+  - realview-a8
+  - fh8620
+  - gkipc
+  - stm32f20x
+  - efm32
+  - zynq7000
+  - stm32f1.0-mini-sysytem
+- Fix unused device frame error
+- Update GPL license to Apache-2.0, and format files
+- Fix incorrect setting of word length when parity check is enabled on the STM32 serial port
+
+## Tools
+
+- Support windows cmake tool
+- Optimization the EXTERN_LIB variable use
+- Update eclipse project after dist
+- Add default project name and project path while --dist-ide
+- Fix the problem of an error when opening menuconfig after the project is dist
+- Update cmake.py, add c++ support and libpath.
+- Python 3 compatibility support
+- Update eclipse.py to compatible tasking
+
 # RT-Thread v4.0.3 Change Log
 
 Change log since v4.0.2

Jenkinsfile

@@ -29,7 +29,6 @@ pipeline {
                         // ['gd32e230k-start', 'sourcery-arm'], /* CI compile not support */
                         ['gd32303e-eval', 'sourcery-arm'],
                         // ['gd32450z-eval', 'sourcery-arm'], /* CI link not support */
-                        ['gkipc', 'sourcery-arm'],
                         ['imx6sx/cortex-a9', 'sourcery-arm'],
                         // ['imxrt/imxrt1052-atk-commander', 'sourcery-arm'], /* CI compile not support */
                         // ['imxrt/imxrt1052-fire-pro', 'sourcery-arm'], /* CI compile not support */
@@ -107,9 +106,7 @@ pipeline {
                         ['stm32f20x', 'sourcery-arm'],
                         ['swm320-lq100', 'sourcery-arm'],
                         ['beaglebone', 'sourcery-arm'],
-                        ['zynq7000', 'sourcery-arm'],
                         ['frdm-k64f', 'sourcery-arm'],
-                        ['fh8620', 'sourcery-arm'],
                         ['xplorer4330/M4', 'sourcery-arm'],
                         // ['at32/at32f403a-start', 'sourcery-arm'],/* CI link not support */
                         // ['at32/at32f407-start', 'sourcery-arm']/* CI compile C99 not support */

Kconfig

@@ -1,3 +1,4 @@
 source "$RTT_DIR/src/Kconfig"
 source "$RTT_DIR/libcpu/Kconfig"
 source "$RTT_DIR/components/Kconfig"
+source "$RTT_DIR/examples/utest/testcases/Kconfig"

bsp/qemu-vexpress-a9/.config

@@ -1,7 +1,4 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Project Configuration
-#
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
 
 #
 # RT-Thread Kernel
@@ -21,9 +18,18 @@ CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_SYSTEM_THREAD_STACK_SIZE=1024
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# end of kservice optimization
+
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -46,6 +52,7 @@ CONFIG_RT_USING_EVENT=y
 CONFIG_RT_USING_MAILBOX=y
 CONFIG_RT_USING_MESSAGEQUEUE=y
 CONFIG_RT_USING_SIGNALS=y
+# end of Inter-Thread communication
 
 #
 # Memory Management
@@ -56,8 +63,10 @@ CONFIG_RT_USING_MEMHEAP=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
 CONFIG_RT_USING_MEMTRACE=y
 CONFIG_RT_USING_HEAP=y
+# end of Memory Management
 
 #
 # Kernel Device Object
@@ -68,12 +77,17 @@ CONFIG_RT_USING_INTERRUPT_INFO=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_PRINTF_LONGLONG is not set
+# end of Kernel Device Object
+
+CONFIG_RT_VER_NUM=0x40004
+# end of RT-Thread Kernel
+
 CONFIG_ARCH_ARM=y
-# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_RT_USING_CPU_FFS=y
 CONFIG_ARCH_ARM_CORTEX_A=y
+CONFIG_RT_USING_GIC_V2=y
 CONFIG_ARCH_ARM_CORTEX_A9=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -87,34 +101,37 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # C++ features
 #
 CONFIG_RT_USING_CPLUSPLUS=y
+# CONFIG_RT_USING_CPLUSPLUS11 is not set
+# end of C++ features
 
 #
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
 CONFIG_FINSH_ARG_MAX=10
+# end of Command shell
 
 #
 # Device virtual file system
 #
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEMS_MAX=4
 CONFIG_DFS_FILESYSTEM_TYPES_MAX=8
-CONFIG_DFS_FD_MAX=16
+CONFIG_DFS_FD_MAX=32
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_RT_USING_DFS_ELMFAT=y
 
@@ -128,17 +145,24 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y
 # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
 CONFIG_RT_DFS_ELM_USE_LFN_3=y
 CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
 CONFIG_RT_DFS_ELM_MAX_LFN=255
 CONFIG_RT_DFS_ELM_DRIVES=2
 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
 # CONFIG_RT_DFS_ELM_USE_ERASE is not set
 CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# end of elm-chan's FatFs, Generic FAT Filesystem Module
+
 CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DFS_ROMFS=y
 CONFIG_RT_USING_DFS_RAMFS=y
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
 # CONFIG_RT_USING_DFS_NFS is not set
+# end of Device virtual file system
 
 #
 # Device Drivers
@@ -149,20 +173,25 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
 CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
 CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 CONFIG_RT_USING_MTD_NOR=y
 CONFIG_RT_USING_MTD_NAND=y
 CONFIG_RT_MTD_NAND_DEBUG=y
-# CONFIG_RT_USING_MTD is not set
 # CONFIG_RT_USING_PM is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_ALARM is not set
@@ -181,6 +210,7 @@ CONFIG_RT_USING_SFUD=y
 CONFIG_RT_SFUD_USING_SFDP=y
 CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
 # CONFIG_RT_SFUD_USING_QSPI is not set
+CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
 # CONFIG_RT_DEBUG_SFUD is not set
 # CONFIG_RT_USING_ENC28J60 is not set
 # CONFIG_RT_USING_SPI_WIFI is not set
@@ -188,15 +218,9 @@ CONFIG_RT_USING_WDT=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
-
-#
-# Using Hardware Crypto drivers
-#
 # CONFIG_RT_USING_HWCRYPTO is not set
-
-#
-# Using WiFi
-#
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -204,6 +228,8 @@ CONFIG_RT_USING_WDT=y
 #
 # CONFIG_RT_USING_USB_HOST is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
 
 #
 # POSIX layer and C standard library
@@ -214,8 +240,12 @@ CONFIG_PTHREAD_NUM_MAX=8
 CONFIG_RT_USING_POSIX=y
 CONFIG_RT_USING_POSIX_MMAP=y
 CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_GETLINE=y
 CONFIG_RT_USING_POSIX_AIO=y
+CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# end of POSIX layer and C standard library
 
 #
 # Network
@@ -225,12 +255,16 @@ CONFIG_RT_USING_POSIX_AIO=y
 # Socket abstraction layer
 #
 CONFIG_RT_USING_SAL=y
+CONFIG_SAL_INTERNET_CHECK=y
 
 #
 # protocol stack implement
 #
 CONFIG_SAL_USING_LWIP=y
+# end of protocol stack implement
+
 CONFIG_SAL_USING_POSIX=y
+# end of Socket abstraction layer
 
 #
 # Network interface device
@@ -243,16 +277,18 @@ CONFIG_NETDEV_USING_AUTO_DEFAULT=y
 # CONFIG_NETDEV_USING_IPV6 is not set
 CONFIG_NETDEV_IPV4=1
 CONFIG_NETDEV_IPV6=0
-# CONFIG_NETDEV_IPV6_SCOPES is not set
+# end of Network interface device
 
 #
 # light weight TCP/IP stack
 #
 CONFIG_RT_USING_LWIP=y
 # CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP210 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP212=y
 # CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
 # CONFIG_RT_LWIP_IGMP is not set
 CONFIG_RT_LWIP_ICMP=y
 # CONFIG_RT_LWIP_SNMP is not set
@@ -267,6 +303,8 @@ CONFIG_IP_SOF_BROADCAST_RECV=1
 CONFIG_RT_LWIP_IPADDR="192.168.1.30"
 CONFIG_RT_LWIP_GWADDR="192.168.1.1"
 CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+# end of Static IPv4 Address
+
 CONFIG_RT_LWIP_UDP=y
 CONFIG_RT_LWIP_TCP=y
 CONFIG_RT_LWIP_RAW=y
@@ -294,28 +332,29 @@ CONFIG_SO_REUSE=1
 CONFIG_LWIP_SO_RCVTIMEO=1
 CONFIG_LWIP_SO_SNDTIMEO=1
 CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
 CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_RT_LWIP_STATS is not set
 # CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
 CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_RT_LWIP_DEBUG is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
+# end of light weight TCP/IP stack
 
 #
 # AT commands
 #
 # CONFIG_RT_USING_AT is not set
+# end of AT commands
+
 # CONFIG_LWIP_USING_DHCPD is not set
+# end of Network
 
 #
 # VBUS(Virtual Software BUS)
 #
 # CONFIG_RT_USING_VBUS is not set
+# end of VBUS(Virtual Software BUS)
 
 #
 # Utilities
@@ -323,7 +362,18 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
 CONFIG_RT_USING_LWP=y
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
 
 #
 # RT-Thread online packages
@@ -332,14 +382,20 @@ CONFIG_RT_USING_LWP=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
@@ -352,18 +408,26 @@ CONFIG_RT_USING_LWP=y
 # Marvell WiFi
 #
 # CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
 
 #
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
 # CONFIG_PKG_USING_RW007 is not set
+# end of Wi-Fi
+
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -372,13 +436,46 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# end of IoT Cloud
+
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
 # CONFIG_PKG_USING_LSSDP is not set
 # CONFIG_PKG_USING_AIRKISS_OPEN is not set
 # CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# end of IoT - internet of things
 
 #
 # security packages
@@ -386,6 +483,9 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
 
 #
 # language packages
@@ -393,6 +493,8 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# end of language packages
 
 #
 # multimedia packages
@@ -401,6 +503,32 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_MUPDF is not set
 # CONFIG_PKG_USING_STEMWIN is not set
 
+#
+# lvgl: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LVGL is not set
+# end of lvgl: powerful and easy-to-use embedded GUI library
+
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+# end of multimedia packages
+
 #
 # tools packages
 #
@@ -408,28 +536,101 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# end of tools packages
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_PERSIMMON is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# end of system packages
 
 #
 # peripheral libraries and drivers
@@ -437,18 +638,24 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_U8G2 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
 # CONFIG_PKG_USING_AD7746 is not set
@@ -456,33 +663,124 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
 # CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# end of AI packages
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# end of entertainment: terminal games and other interesting software packages
+
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# end of miscellaneous packages
+# end of RT-Thread online packages
+
 CONFIG_SOC_VEXPRESS_A9=y
 CONFIG_RT_USING_UART0=y
 CONFIG_RT_USING_UART1=y

bsp/qemu-vexpress-a9/Kconfig

@@ -23,6 +23,7 @@ config SOC_VEXPRESS_A9
     select ARCH_ARM_CORTEX_A9
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
+    select RT_USING_GIC_V2
     default y
 
 source "$BSP_DIR/drivers/Kconfig"

bsp/qemu-vexpress-a9/README.md

@@ -34,7 +34,7 @@ QEMU/VExpress A9是QEMU模拟器针对ARM VExpress-A9 FPGA开发板进行软件
 
 ## 3. 执行
 
-当要执行编译好的RT-Thread时，在这个bsp目录下已经提供了运行脚本文件：qemu.bat/qemu.sh
+当要执行编译好的RT-Thread时，在这个bsp目录下已经提供了运行脚本文件：qemu.bat和qemu.sh。可以在bsp目录下运行env，在env中敲入qemu.bat即可直接运行。
 
 这个执行脚本默认把串口输出到stdio（即控制台）上，所以直接执行脚本后就可以输出结果了。
 
@@ -99,7 +99,7 @@ start qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.b
 
 维护人：[bernard][4]
 
-  [1]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.boards.express/index.html
-  [2]: https://www.rt-thread.org/page/download.html
-  [3]: https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q3-update/+download/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2
-  [4]: https://github.com/BernardXiong
+[1]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.boards.express/index.html
+[2]: https://www.rt-thread.org/page/download.html
+[3]: https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q3-update/+download/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2
+[4]: https://github.com/BernardXiong

bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c

@@ -102,6 +102,6 @@ int _ac97_reg_dump(int argc, char **argv)
     AC97_DUMP(AC97_ADC_SLOT_MAP);
     return 0;
 }
-FINSH_FUNCTION_EXPORT_ALIAS(_ac97_reg_dump, __cmd_ac97_dump, ac97 dump reg.);
+MSH_CMD_EXPORT_ALIAS(_ac97_reg_dump, ac97_dump, ac97 dump reg);
 
 #endif

bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c

@@ -391,5 +391,6 @@ int _aaci_pl041_reg_dump(int argc, char **argv)
     PL041_DUMP(PL041->dr4[0]);
     return 0;
 }
-FINSH_FUNCTION_EXPORT_ALIAS(_aaci_pl041_reg_dump, __cmd_pl041_dump, aaci pl041 dump reg.);
+MSH_CMD_EXPORT_ALIAS(_aaci_pl041_reg_dump, pl041_dump, aaci pl041 dump reg);
+
 #endif

bsp/qemu-vexpress-a9/drivers/board.c

@@ -55,3 +55,8 @@ void rt_hw_board_init(void)
     rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
 #endif
 }
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+
+}

bsp/qemu-vexpress-a9/drivers/drv_smc911x.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,25 +33,15 @@ struct eth_device_smc911x
 };
 static struct eth_device_smc911x _emac;
 
-int udelay(int value)
-{
-    return 0;
-}
-
-int mdelay(int value)
-{
-    return 0;
-}
-
 #if defined (CONFIG_SMC911X_32_BIT)
 rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
 {
-    return *(volatile uint32_t*)(dev->iobase + offset);
+    return *(volatile uint32_t *)(dev->iobase + offset);
 }
 
 rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
 {
-    *(volatile uint32_t*)(dev->iobase + offset) = val;
+    *(volatile uint32_t *)(dev->iobase + offset) = val;
 }
 
 #elif defined (CONFIG_SMC911X_16_BIT)
@@ -78,47 +68,47 @@ struct chip_id
 
 static const struct chip_id chip_ids[] =
 {
-    { CHIP_89218,"LAN89218" },
-    { CHIP_9115, "LAN9115" },
-    { CHIP_9116, "LAN9116" },
-    { CHIP_9117, "LAN9117" },
-    { CHIP_9118, "LAN9118" },
-    { CHIP_9211, "LAN9211" },
-    { CHIP_9215, "LAN9215" },
-    { CHIP_9216, "LAN9216" },
-    { CHIP_9217, "LAN9217" },
-    { CHIP_9218, "LAN9218" },
-    { CHIP_9220, "LAN9220" },
-    { CHIP_9221, "LAN9221" },
+    { LAN9118_ID_89218, "LAN89218" },
+    { LAN9118_ID_9115, "LAN9115" },
+    { LAN9118_ID_9116, "LAN9116" },
+    { LAN9118_ID_9117, "LAN9117" },
+    { LAN9118_ID_9118, "LAN9118" },
+    { LAN9210_ID_9211, "LAN9211" },
+    { LAN9218_ID_9215, "LAN9215" },
+    { LAN9218_ID_9216, "LAN9216" },
+    { LAN9218_ID_9217, "LAN9217" },
+    { LAN9218_ID_9218, "LAN9218" },
+    { LAN9220_ID_9220, "LAN9220" },
+    { LAN9220_ID_9221, "LAN9221" },
     { 0, RT_NULL },
 };
 
 static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
 {
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
 
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    return smc911x_reg_read(dev, MAC_CSR_DATA);
+    return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
 }
 
 static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
 {
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 
-    smc911x_reg_write(dev, MAC_CSR_DATA, data);
-    smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
+    smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
 
-    while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
+    while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
 }
 
 static int smc911x_detect_chip(struct eth_device_smc911x *dev)
 {
     unsigned long val, i;
 
-    val = smc911x_reg_read(dev, BYTE_TEST);
+    val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
     if (val == 0xffffffff)
     {
         /* Special case -- no chip present */
@@ -130,7 +120,7 @@ static int smc911x_detect_chip(struct eth_device_smc911x *dev)
         return -1;
     }
 
-    val = smc911x_reg_read(dev, ID_REV) >> 16;
+    val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
     for (i = 0; chip_ids[i].id != 0; i++)
     {
         if (chip_ids[i].id == val) break;
@@ -151,16 +141,16 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
 
     /*
     *  Take out of PM setting first
-    *  Device is already wake up if PMT_CTRL_READY bit is set
+    *  Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
     */
-    if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
+    if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
     {
         /* Write to the bytetest will take out of powerdown */
-        smc911x_reg_write(dev, BYTE_TEST, 0x0);
+        smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
 
         timeout = 10;
 
-        while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
+        while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
             udelay(10);
 
         if (timeout < 0)
@@ -172,11 +162,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
     }
 
     /* Disable interrupts */
-    smc911x_reg_write(dev, INT_EN, 0);
-    smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
+    smc911x_reg_write(dev, LAN9118_INT_EN, 0);
+    smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
 
     timeout = 1000;
-    while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
+    while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
         udelay(10);
 
     if (timeout < 0)
@@ -186,11 +176,11 @@ static void smc911x_reset(struct eth_device_smc911x *dev)
     }
 
     /* Reset the FIFO level and flow control settings */
-    smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
-    smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
+    smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
+    smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
 
     /* Set to LED outputs */
-    smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
+    smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
 }
 
 static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
@@ -201,20 +191,20 @@ static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
     addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
     addrh = m[4] | (m[5] << 8);
 
-    smc911x_set_mac_csr(dev, ADDRL, addrl);
-    smc911x_set_mac_csr(dev, ADDRH, addrh);
+    smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
+    smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
 }
 
 static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
                                 uint8_t phy, uint8_t reg, uint16_t *val)
 {
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
 
-    smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
+    smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
 
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
 
-    *val = smc911x_get_mac_csr(dev, MII_DATA);
+    *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
 
     return 0;
 }
@@ -222,14 +212,14 @@ static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
 static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
                                  uint8_t phy, uint8_t reg, uint16_t  val)
 {
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
         ;
 
-    smc911x_set_mac_csr(dev, MII_DATA, val);
-    smc911x_set_mac_csr(dev, MII_ACC,
-                        phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
+    smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
+    smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
+                        phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
 
-    while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+    while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
         ;
     return 0;
 }
@@ -238,10 +228,10 @@ static int smc911x_phy_reset(struct eth_device_smc911x *dev)
 {
     uint32_t reg;
 
-    reg = smc911x_reg_read(dev, PMT_CTRL);
+    reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
     reg &= ~0xfffff030;
-    reg |= PMT_CTRL_PHY_RST;
-    smc911x_reg_write(dev, PMT_CTRL, reg);
+    reg |= LAN9118_PMT_CTRL_PHY_RST;
+    smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
 
     mdelay(100);
 
@@ -255,10 +245,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
 
     smc911x_phy_reset(dev);
 
-    smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
     mdelay(1);
-    smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
-    smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
+    smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
 
     timeout = 5000;
     do
@@ -267,10 +257,10 @@ static void smc911x_phy_configure(struct eth_device_smc911x *dev)
         if ((timeout--) == 0)
             goto err_out;
 
-        if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
+        if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
             goto err_out;
     }
-    while (!(status & BMSR_LSTATUS));
+    while (!(status & LAN9118_BMSR_LSTATUS));
 
     return;
 
@@ -281,17 +271,17 @@ err_out:
 static void smc911x_enable(struct eth_device_smc911x *dev)
 {
     /* Enable TX */
-    smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
+    smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
 
-    smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
+    smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
 
-    smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
+    smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
 
     /* no padding to start of packets */
-    smc911x_reg_write(dev, RX_CFG, 0);
+    smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
 
-    smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
-                        MAC_CR_HBDIS);
+    smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
+                        LAN9118_MAC_CR_HBDIS);
 }
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -329,13 +319,13 @@ static void smc911x_isr(int vector, void *param)
 
     emac = SMC911X_EMAC_DEVICE(param);
 
-    status = smc911x_reg_read(emac, INT_STS);
-    
-    if (status & INT_STS_RSFL)
+    status = smc911x_reg_read(emac, LAN9118_INT_STS);
+
+    if (status & LAN9118_INT_STS_RSFL)
     {
         eth_device_ready(&emac->parent);
     }
-    smc911x_reg_write(emac, INT_STS, status);
+    smc911x_reg_write(emac, LAN9118_INT_STS, status);
 
     return ;
 }
@@ -359,18 +349,18 @@ static rt_err_t smc911x_emac_init(rt_device_t dev)
 
 #if 1
     /* Interrupt on every received packet */
-    smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
-    smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
+    smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
+    smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
 
     /* enable interrupt */
-    smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
+    smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
 #else
 
     /* disable interrupt */
-    smc911x_reg_write(emac, INT_EN, 0);
-    value = smc911x_reg_read(emac, INT_CFG);
-    value &= ~INT_CFG_IRQ_EN;
-    smc911x_reg_write(emac, INT_CFG, value);
+    smc911x_reg_write(emac, LAN9118_INT_EN, 0);
+    value = smc911x_reg_read(emac, LAN9118_IRQ_CFG);
+    value &= ~LAN9118_IRQ_CFG_IRQ_EN;
+    smc911x_reg_write(emac, LAN9118_IRQ_CFG, value);
 #endif
 
     rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
@@ -386,11 +376,11 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
     emac = SMC911X_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
-    switch(cmd)
+    switch (cmd)
     {
     case NIOCTL_GADDR:
         /* get MAC address */
-        if(args) rt_memcpy(args, emac->enetaddr, 6);
+        if (args) rt_memcpy(args, emac->enetaddr, 6);
         else return -RT_ERROR;
         break;
     default :
@@ -402,7 +392,7 @@ static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
 /* Ethernet device interface */
 /* transmit packet. */
 static uint8_t tx_buf[2048];
-rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
+rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
 {
     struct eth_device_smc911x *emac;
 
@@ -418,36 +408,36 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
     pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
 
     /* send it out */
-    data = (uint32_t*)tx_buf;
+    data = (uint32_t *)tx_buf;
     length = p->tot_len;
 
-    smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
-    smc911x_reg_write(emac, TX_DATA_FIFO, length);
+    smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
+    smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
 
     tmplen = (length + 3) / 4;
     while (tmplen--)
     {
-        smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
+        smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
     }
 
     /* wait for transmission */
-    while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
+    while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
 
     /* get status. Ignore 'no carrier' error, it has no meaning for
      * full duplex operation
      */
-    status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
-             (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
-              TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
+    status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
+             (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
+              LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
 
     if (!status) return 0;
 
     rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
-               status & TX_STS_LOC ? "TX_STS_LOC " : "",
-               status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
-               status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
-               status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
-               status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
+               status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
+               status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
+               status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
+               status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
+               status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
 
     return -RT_EIO;
 }
@@ -455,24 +445,24 @@ rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
 /* reception packet. */
 struct pbuf *smc911x_emac_rx(rt_device_t dev)
 {
-    struct pbuf* p = RT_NULL;
+    struct pbuf *p = RT_NULL;
     struct eth_device_smc911x *emac;
 
     emac = SMC911X_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
     /* take the emac buffer to the pbuf */
-    if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
+    if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
     {
         uint32_t status;
         uint32_t pktlen, tmplen;
 
-        status = smc911x_reg_read(emac, RX_STATUS_FIFO);
+        status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
 
         /* get frame length */
-        pktlen = (status & RX_STS_PKT_LEN) >> 16;
+        pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
 
-        smc911x_reg_write(emac, RX_CFG, 0);
+        smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
 
         tmplen = (pktlen + 3) / 4;
 
@@ -483,11 +473,11 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
             uint32_t *data = (uint32_t *)p->payload;
             while (tmplen--)
             {
-                *data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
+                *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
             }
         }
 
-        if (status & RX_STS_ES)
+        if (status & LAN9118_RXS_ES)
         {
             rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
         }
@@ -497,7 +487,7 @@ struct pbuf *smc911x_emac_rx(rt_device_t dev)
 }
 
 #ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops smc911x_emac_ops = 
+const static struct rt_device_ops smc911x_emac_ops =
 {
     smc911x_emac_init,
     RT_NULL,
@@ -520,7 +510,7 @@ int smc911x_emac_hw_init(void)
     }
 
     /* set INT CFG */
-    smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
+    smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
 
     /* test MAC address */
     _emac.enetaddr[0] = AUTOMAC0;

bsp/qemu-vexpress-a9/drivers/drv_smc911x.h

@@ -1,402 +1,342 @@
 /*
- * SMSC LAN9[12]1[567] Network driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * SPDX-License-Identifier: Apache-2.0
  *
- * SPDX-License-Identifier: GPL-2.0+
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-04-21
  */
 
-#ifndef _SMC911X_H_
-#define _SMC911X_H_
 
-#include <stdint.h>
-
-#define CONFIG_SMC911X_32_BIT
-
-/* Below are the register offsets and bit definitions
- * of the Lan911x memory space
+/*  $NetBSD: lan9118reg.h,v 1.3 2010/09/27 12:29:03 kiyohara Exp $  */
+/*
+ * Copyright (c) 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
-#define RX_DATA_FIFO                    0x00
-
-#define TX_DATA_FIFO                    0x20
-#define TX_CMD_A_INT_ON_COMP            0x80000000
-#define TX_CMD_A_INT_BUF_END_ALGN       0x03000000
-#define TX_CMD_A_INT_4_BYTE_ALGN        0x00000000
-#define TX_CMD_A_INT_16_BYTE_ALGN       0x01000000
-#define TX_CMD_A_INT_32_BYTE_ALGN       0x02000000
-#define TX_CMD_A_INT_DATA_OFFSET        0x001F0000
-#define TX_CMD_A_INT_FIRST_SEG          0x00002000
-#define TX_CMD_A_INT_LAST_SEG           0x00001000
-#define TX_CMD_A_BUF_SIZE               0x000007FF
-#define TX_CMD_B_PKT_TAG                0xFFFF0000
-#define TX_CMD_B_ADD_CRC_DISABLE        0x00002000
-#define TX_CMD_B_DISABLE_PADDING        0x00001000
-#define TX_CMD_B_PKT_BYTE_LENGTH        0x000007FF
-
-#define RX_STATUS_FIFO              0x40
-#define RX_STS_PKT_LEN              0x3FFF0000
-#define RX_STS_ES                   0x00008000
-#define RX_STS_BCST                 0x00002000
-#define RX_STS_LEN_ERR              0x00001000
-#define RX_STS_RUNT_ERR             0x00000800
-#define RX_STS_MCAST                0x00000400
-#define RX_STS_TOO_LONG             0x00000080
-#define RX_STS_COLL                 0x00000040
-#define RX_STS_ETH_TYPE             0x00000020
-#define RX_STS_WDOG_TMT             0x00000010
-#define RX_STS_MII_ERR              0x00000008
-#define RX_STS_DRIBBLING            0x00000004
-#define RX_STS_CRC_ERR              0x00000002
-#define RX_STATUS_FIFO_PEEK         0x44
-#define TX_STATUS_FIFO              0x48
-#define TX_STS_TAG                  0xFFFF0000
-#define TX_STS_ES                   0x00008000
-#define TX_STS_LOC                  0x00000800
-#define TX_STS_NO_CARR              0x00000400
-#define TX_STS_LATE_COLL            0x00000200
-#define TX_STS_MANY_COLL            0x00000100
-#define TX_STS_COLL_CNT             0x00000078
-#define TX_STS_MANY_DEFER           0x00000004
-#define TX_STS_UNDERRUN             0x00000002
-#define TX_STS_DEFERRED             0x00000001
-#define TX_STATUS_FIFO_PEEK         0x4C
-#define ID_REV                      0x50
-#define ID_REV_CHIP_ID              0xFFFF0000  /* RO */
-#define ID_REV_REV_ID               0x0000FFFF  /* RO */
-
-#define INT_CFG                     0x54
-#define INT_CFG_INT_DEAS            0xFF000000  /* R/W */
-#define INT_CFG_INT_DEAS_CLR        0x00004000
-#define INT_CFG_INT_DEAS_STS        0x00002000
-#define INT_CFG_IRQ_INT             0x00001000  /* RO */
-#define INT_CFG_IRQ_EN              0x00000100  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define INT_CFG_IRQ_POL             0x00000010
-/* R/W Not Affected by SW Reset */
-#define INT_CFG_IRQ_TYPE            0x00000001
-
-#define INT_STS                     0x58
-#define INT_STS_SW_INT              0x80000000  /* R/WC */
-#define INT_STS_TXSTOP_INT          0x02000000  /* R/WC */
-#define INT_STS_RXSTOP_INT          0x01000000  /* R/WC */
-#define INT_STS_RXDFH_INT           0x00800000  /* R/WC */
-#define INT_STS_RXDF_INT            0x00400000  /* R/WC */
-#define INT_STS_TX_IOC              0x00200000  /* R/WC */
-#define INT_STS_RXD_INT             0x00100000  /* R/WC */
-#define INT_STS_GPT_INT             0x00080000  /* R/WC */
-#define INT_STS_PHY_INT             0x00040000  /* RO */
-#define INT_STS_PME_INT             0x00020000  /* R/WC */
-#define INT_STS_TXSO                0x00010000  /* R/WC */
-#define INT_STS_RWT                 0x00008000  /* R/WC */
-#define INT_STS_RXE                 0x00004000  /* R/WC */
-#define INT_STS_TXE                 0x00002000  /* R/WC */
-/*#define   INT_STS_ERX     0x00001000*/  /* R/WC */
-#define INT_STS_TDFU                0x00000800  /* R/WC */
-#define INT_STS_TDFO                0x00000400  /* R/WC */
-#define INT_STS_TDFA                0x00000200  /* R/WC */
-#define INT_STS_TSFF                0x00000100  /* R/WC */
-#define INT_STS_TSFL                0x00000080  /* R/WC */
-/*#define   INT_STS_RXDF        0x00000040*/  /* R/WC */
-#define INT_STS_RDFO                0x00000040  /* R/WC */
-#define INT_STS_RDFL                0x00000020  /* R/WC */
-#define INT_STS_RSFF                0x00000010  /* R/WC */
-#define INT_STS_RSFL                0x00000008  /* R/WC */
-#define INT_STS_GPIO2_INT           0x00000004  /* R/WC */
-#define INT_STS_GPIO1_INT           0x00000002  /* R/WC */
-#define INT_STS_GPIO0_INT           0x00000001  /* R/WC */
-#define INT_EN                      0x5C
-#define INT_EN_SW_INT_EN            0x80000000  /* R/W */
-#define INT_EN_TXSTOP_INT_EN        0x02000000  /* R/W */
-#define INT_EN_RXSTOP_INT_EN        0x01000000  /* R/W */
-#define INT_EN_RXDFH_INT_EN         0x00800000  /* R/W */
-/*#define   INT_EN_RXDF_INT_EN      0x00400000*/  /* R/W */
-#define INT_EN_TIOC_INT_EN          0x00200000  /* R/W */
-#define INT_EN_RXD_INT_EN           0x00100000  /* R/W */
-#define INT_EN_GPT_INT_EN           0x00080000  /* R/W */
-#define INT_EN_PHY_INT_EN           0x00040000  /* R/W */
-#define INT_EN_PME_INT_EN           0x00020000  /* R/W */
-#define INT_EN_TXSO_EN              0x00010000  /* R/W */
-#define INT_EN_RWT_EN               0x00008000  /* R/W */
-#define INT_EN_RXE_EN               0x00004000  /* R/W */
-#define INT_EN_TXE_EN               0x00002000  /* R/W */
-/*#define   INT_EN_ERX_EN           0x00001000*/  /* R/W */
-#define INT_EN_TDFU_EN              0x00000800  /* R/W */
-#define INT_EN_TDFO_EN              0x00000400  /* R/W */
-#define INT_EN_TDFA_EN              0x00000200  /* R/W */
-#define INT_EN_TSFF_EN              0x00000100  /* R/W */
-#define INT_EN_TSFL_EN              0x00000080  /* R/W */
-/*#define   INT_EN_RXDF_EN          0x00000040*/  /* R/W */
-#define INT_EN_RDFO_EN              0x00000040  /* R/W */
-#define INT_EN_RDFL_EN              0x00000020  /* R/W */
-#define INT_EN_RSFF_EN              0x00000010  /* R/W */
-#define INT_EN_RSFL_EN              0x00000008  /* R/W */
-#define INT_EN_GPIO2_INT            0x00000004  /* R/W */
-#define INT_EN_GPIO1_INT            0x00000002  /* R/W */
-#define INT_EN_GPIO0_INT            0x00000001  /* R/W */
-
-#define BYTE_TEST                   0x64
-#define FIFO_INT                    0x68
-#define FIFO_INT_TX_AVAIL_LEVEL     0xFF000000  /* R/W */
-#define FIFO_INT_TX_STS_LEVEL       0x00FF0000  /* R/W */
-#define FIFO_INT_RX_AVAIL_LEVEL     0x0000FF00  /* R/W */
-#define FIFO_INT_RX_STS_LEVEL       0x000000FF  /* R/W */
-
-#define RX_CFG                      0x6C
-#define RX_CFG_RX_END_ALGN          0xC0000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN4     0x00000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN16    0x40000000  /* R/W */
-#define     RX_CFG_RX_END_ALGN32    0x80000000  /* R/W */
-#define RX_CFG_RX_DMA_CNT           0x0FFF0000  /* R/W */
-#define RX_CFG_RX_DUMP              0x00008000  /* R/W */
-#define RX_CFG_RXDOFF               0x00001F00  /* R/W */
-/*#define   RX_CFG_RXBAD            0x00000001*/  /* R/W */
-
-#define TX_CFG                      0x70
-/*#define   TX_CFG_TX_DMA_LVL       0xE0000000*/     /* R/W */
-/* R/W Self Clearing */
-/*#define   TX_CFG_TX_DMA_CNT       0x0FFF0000*/
-#define TX_CFG_TXS_DUMP             0x00008000  /* Self Clearing */
-#define TX_CFG_TXD_DUMP             0x00004000  /* Self Clearing */
-#define TX_CFG_TXSAO                0x00000004  /* R/W */
-#define TX_CFG_TX_ON                0x00000002  /* R/W */
-#define TX_CFG_STOP_TX              0x00000001  /* Self Clearing */
-
-#define HW_CFG                      0x74
-#define HW_CFG_TTM                  0x00200000  /* R/W */
-#define HW_CFG_SF                   0x00100000  /* R/W */
-#define HW_CFG_TX_FIF_SZ            0x000F0000  /* R/W */
-#define HW_CFG_TR                   0x00003000  /* R/W */
-#define HW_CFG_PHY_CLK_SEL          0x00000060  /* R/W */
-#define HW_CFG_PHY_CLK_SEL_INT_PHY  0x00000000 /* R/W */
-#define HW_CFG_PHY_CLK_SEL_EXT_PHY  0x00000020 /* R/W */
-#define HW_CFG_PHY_CLK_SEL_CLK_DIS  0x00000040 /* R/W */
-#define HW_CFG_SMI_SEL              0x00000010  /* R/W */
-#define HW_CFG_EXT_PHY_DET          0x00000008  /* RO */
-#define HW_CFG_EXT_PHY_EN           0x00000004  /* R/W */
-#define HW_CFG_32_16_BIT_MODE       0x00000004  /* RO */
-#define HW_CFG_SRST_TO              0x00000002  /* RO */
-#define HW_CFG_SRST                 0x00000001  /* Self Clearing */
-
-#define RX_DP_CTRL                  0x78
-#define RX_DP_CTRL_RX_FFWD          0x80000000  /* R/W */
-#define RX_DP_CTRL_FFWD_BUSY        0x80000000  /* RO */
-
-#define RX_FIFO_INF                 0x7C
-#define  RX_FIFO_INF_RXSUSED        0x00FF0000  /* RO */
-#define  RX_FIFO_INF_RXDUSED        0x0000FFFF  /* RO */
-
-#define TX_FIFO_INF                 0x80
-#define TX_FIFO_INF_TSUSED          0x00FF0000  /* RO */
-#define TX_FIFO_INF_TDFREE          0x0000FFFF  /* RO */
-
-#define PMT_CTRL                    0x84
-#define PMT_CTRL_PM_MODE            0x00003000  /* Self Clearing */
-#define PMT_CTRL_PHY_RST            0x00000400  /* Self Clearing */
-#define PMT_CTRL_WOL_EN             0x00000200  /* R/W */
-#define PMT_CTRL_ED_EN              0x00000100  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define PMT_CTRL_PME_TYPE           0x00000040
-#define PMT_CTRL_WUPS               0x00000030  /* R/WC */
-#define PMT_CTRL_WUPS_NOWAKE        0x00000000  /* R/WC */
-#define PMT_CTRL_WUPS_ED            0x00000010  /* R/WC */
-#define PMT_CTRL_WUPS_WOL           0x00000020  /* R/WC */
-#define PMT_CTRL_WUPS_MULTI         0x00000030  /* R/WC */
-#define PMT_CTRL_PME_IND            0x00000008  /* R/W */
-#define PMT_CTRL_PME_POL            0x00000004  /* R/W */
-/* R/W Not Affected by SW Reset */
-#define PMT_CTRL_PME_EN             0x00000002
-#define PMT_CTRL_READY              0x00000001  /* RO */
 
-#define GPIO_CFG                    0x88
-#define GPIO_CFG_LED3_EN            0x40000000  /* R/W */
-#define GPIO_CFG_LED2_EN            0x20000000  /* R/W */
-#define GPIO_CFG_LED1_EN            0x10000000  /* R/W */
-#define GPIO_CFG_GPIO2_INT_POL      0x04000000  /* R/W */
-#define GPIO_CFG_GPIO1_INT_POL      0x02000000  /* R/W */
-#define GPIO_CFG_GPIO0_INT_POL      0x01000000  /* R/W */
-#define GPIO_CFG_EEPR_EN            0x00700000  /* R/W */
-#define GPIO_CFG_GPIOBUF2           0x00040000  /* R/W */
-#define GPIO_CFG_GPIOBUF1           0x00020000  /* R/W */
-#define GPIO_CFG_GPIOBUF0           0x00010000  /* R/W */
-#define GPIO_CFG_GPIODIR2           0x00000400  /* R/W */
-#define GPIO_CFG_GPIODIR1           0x00000200  /* R/W */
-#define GPIO_CFG_GPIODIR0           0x00000100  /* R/W */
-#define GPIO_CFG_GPIOD4             0x00000010  /* R/W */
-#define GPIO_CFG_GPIOD3             0x00000008  /* R/W */
-#define GPIO_CFG_GPIOD2             0x00000004  /* R/W */
-#define GPIO_CFG_GPIOD1             0x00000002  /* R/W */
-#define GPIO_CFG_GPIOD0             0x00000001  /* R/W */
+#ifndef _LAN9118REG_H_
+#define _LAN9118REG_H_
 
-#define GPT_CFG                     0x8C
-#define GPT_CFG_TIMER_EN            0x20000000  /* R/W */
-#define GPT_CFG_GPT_LOAD            0x0000FFFF  /* R/W */
 
-#define GPT_CNT                     0x90
-#define GPT_CNT_GPT_CNT             0x0000FFFF  /* RO */
-
-#define ENDIAN                      0x98
-#define FREE_RUN                    0x9C
-#define RX_DROP                     0xA0
-#define MAC_CSR_CMD                 0xA4
-#define  MAC_CSR_CMD_CSR_BUSY       0x80000000  /* Self Clearing */
-#define  MAC_CSR_CMD_R_NOT_W        0x40000000  /* R/W */
-#define  MAC_CSR_CMD_CSR_ADDR       0x000000FF  /* R/W */
-
-#define MAC_CSR_DATA                0xA8
-#define AFC_CFG                     0xAC
-#define     AFC_CFG_AFC_HI          0x00FF0000  /* R/W */
-#define     AFC_CFG_AFC_LO          0x0000FF00  /* R/W */
-#define     AFC_CFG_BACK_DUR        0x000000F0  /* R/W */
-#define     AFC_CFG_FCMULT          0x00000008  /* R/W */
-#define     AFC_CFG_FCBRD           0x00000004  /* R/W */
-#define     AFC_CFG_FCADD           0x00000002  /* R/W */
-#define     AFC_CFG_FCANY           0x00000001  /* R/W */
-
-#define E2P_CMD                     0xB0
-#define     E2P_CMD_EPC_BUSY        0x80000000  /* Self Clearing */
-#define     E2P_CMD_EPC_CMD         0x70000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_READ    0x00000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_EWDS    0x10000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_EWEN    0x20000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_WRITE   0x30000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_WRAL    0x40000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_ERASE   0x50000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_ERAL    0x60000000  /* R/W */
-#define     E2P_CMD_EPC_CMD_RELOAD  0x70000000  /* R/W */
-#define     E2P_CMD_EPC_TIMEOUT     0x00000200  /* RO */
-#define     E2P_CMD_MAC_ADDR_LOADED 0x00000100  /* RO */
-#define     E2P_CMD_EPC_ADDR        0x000000FF  /* R/W */
-
-#define E2P_DATA                0xB4
-#define E2P_DATA_EEPROM_DATA    0x000000FF  /* R/W */
-/* end of LAN register offsets and bit definitions */
-
-/* MAC Control and Status registers */
-#define MAC_CR                  0x01  /* R/W */
-
-/* MAC_CR - MAC Control Register */
-#define MAC_CR_RXALL            0x80000000
-/* TODO: delete this bit? It is not described in the data sheet. */
-#define MAC_CR_HBDIS            0x10000000
-#define MAC_CR_RCVOWN           0x00800000
-#define MAC_CR_LOOPBK           0x00200000
-#define MAC_CR_FDPX             0x00100000
-#define MAC_CR_MCPAS            0x00080000
-#define MAC_CR_PRMS             0x00040000
-#define MAC_CR_INVFILT          0x00020000
-#define MAC_CR_PASSBAD          0x00010000
-#define MAC_CR_HFILT            0x00008000
-#define MAC_CR_HPFILT           0x00002000
-#define MAC_CR_LCOLL            0x00001000
-#define MAC_CR_BCAST            0x00000800
-#define MAC_CR_DISRTY           0x00000400
-#define MAC_CR_PADSTR           0x00000100
-#define MAC_CR_BOLMT_MASK       0x000000C0
-#define MAC_CR_DFCHK            0x00000020
-#define MAC_CR_TXEN             0x00000008
-#define MAC_CR_RXEN             0x00000004
-
-#define ADDRH                   0x02      /* R/W mask 0x0000FFFFUL */
-#define ADDRL                   0x03      /* R/W mask 0xFFFFFFFFUL */
-#define HASHH                   0x04      /* R/W */
-#define HASHL                   0x05      /* R/W */
-
-#define MII_ACC                 0x06      /* R/W */
-#define MII_ACC_PHY_ADDR        0x0000F800
-#define MII_ACC_MIIRINDA        0x000007C0
-#define MII_ACC_MII_WRITE       0x00000002
-#define MII_ACC_MII_BUSY        0x00000001
-
-#define MII_DATA            0x07      /* R/W mask 0x0000FFFFUL */
-
-#define FLOW                0x08      /* R/W */
-#define FLOW_FCPT           0xFFFF0000
-#define FLOW_FCPASS         0x00000004
-#define FLOW_FCEN           0x00000002
-#define FLOW_FCBSY          0x00000001
-
-#define VLAN1               0x09      /* R/W mask 0x0000FFFFUL */
-#define VLAN1_VTI1          0x0000ffff
-
-#define VLAN2               0x0A      /* R/W mask 0x0000FFFFUL */
-#define VLAN2_VTI2          0x0000ffff
-
-#define WUFF                0x0B      /* WO */
-
-#define WUCSR               0x0C      /* R/W */
-#define WUCSR_GUE           0x00000200
-#define WUCSR_WUFR          0x00000040
-#define WUCSR_MPR           0x00000020
-#define WUCSR_WAKE_EN       0x00000004
-#define WUCSR_MPEN          0x00000002
+#define CONFIG_SMC911X_32_BIT
 
-/* Chip ID values */
-#define CHIP_89218  0x218a
-#define CHIP_9115   0x115
-#define CHIP_9116   0x116
-#define CHIP_9117   0x117
-#define CHIP_9118   0x118
-#define CHIP_9211   0x9211
-#define CHIP_9215   0x115a
-#define CHIP_9216   0x116a
-#define CHIP_9217   0x117a
-#define CHIP_9218   0x118a
-#define CHIP_9220   0x9220
-#define CHIP_9221   0x9221
+#define LAN9118_IOSIZE   0x100
+
+#define LAN9118_ID_89218 0x218a
+#define LAN9118_ID_9115  0x0115
+#define LAN9118_ID_9116  0x0116
+#define LAN9118_ID_9117  0x0117
+#define LAN9118_ID_9118  0x0118
+#define LAN9218_ID_9215  0x115a
+#define LAN9218_ID_9216  0x116a
+#define LAN9218_ID_9217  0x117a
+#define LAN9218_ID_9218  0x118a
+
+#define LAN9210_ID_9210  0x9210
+#define LAN9210_ID_9211  0x9211
+#define LAN9220_ID_9220  0x9220
+#define LAN9220_ID_9221  0x9221
+
+#define IS_LAN9118(id)  ((id) >= LAN9118_ID_9115 && (id) <= LAN9118_ID_9118)
+#define IS_LAN9218(id)  ((id) >= LAN9218_ID_9215 && (id) <= LAN9218_ID_9218)
+
+#define LAN9118_IPHY_ADDR   0x01    /* Internal PHY Address */
+
+
+#define LAN9118_RXDFIFOP    0x00    /* RX Data FIFO Port */
+#define LAN9118_RXDFIFOAP   0x04    /* RX Data FIFO Alias Ports */
+#define LAN9118_TXDFIFOP    0x20    /* TX Data FIFO Port */
+#define LAN9118_TXDFIFOAP   0x24    /* TX Data FIFO Alias Ports */
+#define LAN9118_RXSFIFOP    0x40    /* RX Status FIFO Port */
+#define LAN9118_RXSFIFOPEEK 0x44    /* RX Status FIFO PEEK */
+#define LAN9118_TXSFIFOP    0x48    /* TX Status FIFO Port */
+#define LAN9118_TXSFIFOPEEK 0x4c    /* TX Status FIFO PEEK */
+
+/* System Control and Status Registers */
+#define LAN9118_ID_REV                      0x50    /* Chip ID and Revision */
+#define LAN9118_ID_REV_ID(x)                (((x) >> 16) & 0xffff)
+#define LAN9118_ID_REV_REV(x)               ((x) & 0xffff)
+#define LAN9118_IRQ_CFG                     0x54    /* Main Interrupt Configuration */
+#define LAN9118_IRQ_CFG_INT_DEAS(t)         ((t) << 24) /* Intr Deassert Interval */
+#define LAN9118_IRQ_CFG_INT_DEAS_CLR        (1 << 14)   /* Intr Deass Intrval clr */
+#define LAN9118_IRQ_CFG_INT_DEAS_STS        (1 << 13)   /* Intr Deassert Status */
+#define LAN9118_IRQ_CFG_IRQ_INT             (1 << 12)   /* Master Interrupt */
+#define LAN9118_IRQ_CFG_IRQ_EN              (1 << 8)    /* IRQ Enable */
+#define LAN9118_IRQ_CFG_IRQ_POL             (1 << 4)    /* IRQ Polarity */
+#define LAN9118_IRQ_CFG_IRQ_TYPE            (1 << 0)    /* IRQ Buffer Type */
+#define LAN9118_INT_STS                     0x58    /* Interrupt Status */
+#define LAN9118_INT_EN                      0x5c    /* Interrupt Enable Register */
+#define LAN9118_INT_SW_INT                  (1 << 31) /* Software Interrupt */
+#define LAN9118_INT_TXSTOP_INT              (1 << 25) /* TX Stopped */
+#define LAN9118_INT_RXSTOP_INT              (1 << 24) /* RX Stopped */
+#define LAN9118_INT_RXDFH_INT               (1 << 23) /* RX Drppd Frm Cnt Halfway */
+#define LAN9118_INT_TX_IOC                  (1 << 21) /* TX IOC Interrupt */
+#define LAN9118_INT_RXD_INT                 (1 << 20) /* RX DMA Interrupt */
+#define LAN9118_INT_GPT_INT                 (1 << 19) /* GP Timer */
+#define LAN9118_INT_PHY_INT                 (1 << 18) /* PHY */
+#define LAN9118_INT_PME_INT                 (1 << 17) /* Power Management Event */
+#define LAN9118_INT_TXSO                    (1 << 16) /* TX Status FIFO Overflow */
+#define LAN9118_INT_RWT                     (1 << 15) /* Rcv Watchdog Time-out */
+#define LAN9118_INT_RXE                     (1 << 14) /* Receive Error */
+#define LAN9118_INT_TXE                     (1 << 13) /* Transmitter Error */
+#define LAN9118_INT_TDFO                    (1 << 10) /* TX Data FIFO Overrun */
+#define LAN9118_INT_TDFA                    (1 << 9)  /* TX Data FIFO Available */
+#define LAN9118_INT_TSFF                    (1 << 8)  /* TX Status FIFO Full */
+#define LAN9118_INT_TSFL                    (1 << 7)  /* TX Status FIFO Level */
+#define LAN9118_INT_RXDF_INT                (1 << 6)  /* RX Dropped Frame Intr */
+#define LAN9118_INT_RSFF                    (1 << 4)  /* RX Status FIFO Full */
+#define LAN9118_INT_RSFL                    (1 << 3)  /* RX Status FIFO Level */
+#define LAN9118_INT_GPIOX_INT(x)            (1 << (x)) /* GPIO[2:0] */
+/*              0x60       Reserved for future use */
+#define LAN9118_BYTE_TEST                   0x64    /* Read-only byte order testing reg */
+#define LAN9118_BYTE_TEST_VALUE             0x87654321
+#define LAN9118_FIFO_INT                    0x68    /* FIFO Level Interrupt */
+#define LAN9118_FIFO_INT_TXDAL(x)           ((x) << 24) /* TX Data Available Lvl */
+#define LAN9118_FIFO_INT_TXSL(x)            ((x) << 16) /* TX Status Level */
+#define LAN9118_FIFO_INT_RXSL(x)            ((x) << 0)  /* RX Status Level */
+#define LAN9118_RX_CFG                      0x6c    /* Receive Configuration */
+#define LAN9118_RX_CFG_RXEA_4B              (0 << 30) /* RX End Alignment: 4 Byte */
+#define LAN9118_RX_CFG_RXEA_16B             (1 << 30) /*                  16 Byte */
+#define LAN9118_RX_CFG_RXEA_32B             (2 << 30) /*                  32 Byte */
+#define LAN9118_RX_CFG_RX_DMA_CNT(x)        ((x) << 16) /* RX DMA Count */
+#define LAN9118_RX_CFG_RX_DUMP              (1 << 15)   /* Force RX Discard */
+#define LAN9118_RX_CFG_RXDOFF(x)            ((x) << 8)  /* RX Data Offset */
+#define LAN9118_TX_CFG                      0x70    /* Transmit Configuration */
+#define LAN9118_TX_CFG_TXS_DUMP             (1 << 15) /* Force TX Status Discard */
+#define LAN9118_TX_CFG_TXD_DUMP             (1 << 14) /* Force TX Data Discard */
+#define LAN9118_TX_CFG_TXSAO                (1 << 2)  /* TX Status Allow Overrun */
+#define LAN9118_TX_CFG_TX_ON                (1 << 1)  /* Transmitter Enable */
+#define LAN9118_TX_CFG_STOP_TX              (1 << 0)  /* Stop Transmitter */
+#define LAN9118_HW_CFG                      0x74    /* Hardware Configuration */
+#define LAN9118_HW_CFG_MBO                  (1 << 20)/* Must Be One */
+#define LAN9118_HW_CFG_TX_FIF_MASK          (0xf << 16) /* TX FIFO Size */
+#define LAN9118_HW_CFG_TX_FIF_SZ(sz)        ((sz) << 16)
+#define LAN9118_HW_CFG_PHY_CLK_SEL_MASK     (3 << 5) /* PHY Clock Select */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_IPHY     (0 << 5) /*   Internal PHY */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_EMII     (1 << 5) /*   External MII Port */
+#define LAN9118_HW_CFG_PHY_CLK_SEL_CD       (2 << 5) /*   Clock Disabled */
+#define LAN9118_HW_CFG_SMI_SEL              (1 << 4) /* Serial Mgmt Interface Sel */
+#define LAN9118_HW_CFG_EXT_PHY_DET          (1 << 3) /* External PHY Detect */
+#define LAN9118_HW_CFG_EXT_PHY_EN           (1 << 2) /* External PHY Enable */
+#define LAN9118_HW_CFG_SRST_TO              (1 << 1) /* Soft Reset Timeout */
+#define LAN9118_HW_CFG_SRST                 (1 << 0) /* Soft Reset */
+#define LAN9118_RX_DP_CTL                   0x78    /* RX Datapath Control */
+#define LAN9118_RX_DP_CTL_RX_FFWD           (1 << 31)/* RX Data FIFO Fast Forward */
+#define LAN9118_RX_FIFO_INF                 0x7c    /* Receive FIFO Information */
+#define LAN9118_RX_FIFO_INF_RXSUSED(x)      (((x) >> 16) & 0xff) /*Sts Used Space*/
+#define LAN9118_RX_FIFO_INF_RXDUSED(x)      ((x) & 0xffff)  /*Data FIFO Used Space*/
+#define LAN9118_TX_FIFO_INF                 0x80    /* Transmit FIFO Information */
+#define LAN9118_TX_FIFO_INF_TXSUSED(x)      (((x) >> 16) & 0xff) /*Sts Used Space*/
+#define LAN9118_TX_FIFO_INF_TDFREE(x)       ((x) & 0xffff) /*Data FIFO Free Space*/
+#define LAN9118_PMT_CTRL                    0x84    /* Power Management Control */
+#define LAN9118_PMT_CTRL_PM_MODE_MASK       (3 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D0         (0 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D1         (1 << 12)
+#define LAN9118_PMT_CTRL_PM_MODE_D2         (2 << 12)
+#define LAN9118_PMT_CTRL_PHY_RST            (1 << 10) /* PHY Reset */
+#define LAN9118_PMT_CTRL_WOL_EN             (1 << 9)  /* Wake-On-LAN Enable */
+#define LAN9118_PMT_CTRL_ED_EN              (1 << 8)  /* Energy-Detect Enable */
+#define LAN9118_PMT_CTRL_PME_TYPE           (1 << 6)  /* PME Buffer Type */
+#define LAN9118_PMT_CTRL_WUPS_NWUED         (0 << 4) /* WAKE-UP Status: No Event */
+#define LAN9118_PMT_CTRL_WUPS_ED            (1 << 4) /* WAKE-UP Status: Energy */
+#define LAN9118_PMT_CTRL_WUPS_WUD           (2 << 4) /* WAKE-UP Status: Wake-up */
+#define LAN9118_PMT_CTRL_PME_IND            (1 << 3)  /* PME indication */
+#define LAN9118_PMT_CTRL_PME_POL            (1 << 2)  /* PME Polarity */
+#define LAN9118_PMT_CTRL_PME_EN             (1 << 1)  /* PME Enable */
+#define LAN9118_PMT_CTRL_READY              (1 << 0)  /* Device Ready */
+#define LAN9118_GPIO_CFG                    0x88    /* General Purpose IO Configuration */
+#define LAN9118_GPIO_CFG_LEDX_EN(x)         (1 << ((x) + 28))  /* LED[3:1] enable */
+#define LAN9118_GPIO_CFG_GPIO_INT_POL(p)    (1 << ((p) + 24)) /* Intr Polarity */
+#define LAN9118_GPIO_CFG_EEPR_EN            (7 << 20)          /* EEPROM Enable */
+#define LAN9118_GPIO_CFG_GPIOBUFN(n)        (1 << ((n) + 16))  /* Buffer Type */
+#define LAN9118_GPIO_CFG_GPDIRN(n)          (1 << ((n) + 8))   /* Direction */
+#define LAN9118_GPIO_CFG_GPODN(n)           (1 << (n)) /* GPIO Data (3,4 is WO) */
+#define LAN9118_GPT_CFG                     0x8c    /* General Purpose Timer Config */
+#define LAN9118_GPT_CNT                     0x90    /* General Purpose Timer Count */
+/*              0x94       Reserved for future use */
+#define LAN9118_WORD_SWAP                   0x98    /* WORD SWAP Register */
+#define LAN9118_FREE_RUN                    0x9c    /* Free Run Counter */
+#define LAN9118_RX_DROP                     0xa0    /* RX Drop Frame Counter */
+#define LAN9118_MAC_CSR_CMD                 0xa4    /* MAC CSR Synchronizer Command */
+#define LAN9118_MAC_CSR_CMD_BUSY            (1 << 31)
+#define LAN9118_MAC_CSR_CMD_W               (0 << 30)
+#define LAN9118_MAC_CSR_CMD_R               (1 << 30)
+#define LAN9118_MAC_CSR_CMD_ADDRESS(a)      ((a) & 0xff)
+#define LAN9118_MAC_CSR_DATA                0xa8    /* MAC CSR Synchronizer Data */
+#define LAN9118_AFC_CFG                     0xac    /* Automatic Flow Control Config */
+#define LAN9118_AFC_CFG_AFC_HI(x)           ((x) << 16)
+#define LAN9118_AFC_CFG_AFC_LO(x)           ((x) << 8)
+#define LAN9118_AFC_CFG_BACK_DUR(x)         ((x) << 4)
+#define LAN9118_AFC_CFG_FCMULT              (1 << 3) /* Flow Control on Multicast */
+#define LAN9118_AFC_CFG_FCBRD               (1 << 2) /* Flow Control on Broadcast */
+#define LAN9118_AFC_CFG_FCADD               (1 << 1) /* Flow Control on Addr Dec */
+#define LAN9118_AFC_CFG_FCANY               (1 << 0) /* Flow Control on Any Frame */
+#define LAN9118_E2P_CMD                     0xb0    /* EEPROM command */
+#define LAN9118_E2P_CMD_EPCB                (1 << 31) /* EPC Busy */
+#define LAN9118_E2P_CMD_EPCC_READ           (0 << 28) /* EPC Command: READ */
+#define LAN9118_E2P_CMD_EPCC_EWDS           (1 << 28) /*              EWDS */
+#define LAN9118_E2P_CMD_EPCC_EWEN           (2 << 28) /*              EWEN */
+#define LAN9118_E2P_CMD_EPCC_WRITE          (3 << 28) /*              WRITE */
+#define LAN9118_E2P_CMD_EPCC_WRAL           (4 << 28) /*              WRAL */
+#define LAN9118_E2P_CMD_EPCC_ERASE          (5 << 28) /*              ERASE */
+#define LAN9118_E2P_CMD_EPCC_ERAL           (6 << 28) /*              ERAL */
+#define LAN9118_E2P_CMD_EPCC_RELOAD         (7 << 28) /*              Reload */
+#define LAN9118_E2P_CMD_EPCTO               (1 << 9)  /* EPC Time-out */
+#define LAN9118_E2P_CMD_MACAL               (1 << 8)  /* MAC Address Loaded */
+#define LAN9118_E2P_CMD_EPCA(a)             ((a) & 0xff) /* EPC Address */
+#define LAN9118_E2P_DATA                    0xb4    /* EEPROM Data */
+/*              0xb8 - 0xfc Reserved for future use */
+
+/* MAC Control and Status Registers */
+#define LAN9118_MAC_CR              0x1 /* MAC Control Register */
+#define LAN9118_MAC_CR_RXALL        (1 << 31) /* Receive All Mode */
+#define LAN9118_MAC_CR_RCVOWN       (1 << 23) /* Disable Receive Own */
+#define LAN9118_MAC_CR_LOOPBK       (1 << 21) /* Loopback operation Mode */
+#define LAN9118_MAC_CR_FDPX         (1 << 20) /* Full Duplex Mode */
+#define LAN9118_MAC_CR_MCPAS        (1 << 19) /* Pass All Multicast */
+#define LAN9118_MAC_CR_PRMS         (1 << 18) /* Promiscuous Mode */
+#define LAN9118_MAC_CR_INVFILT      (1 << 17) /* Inverse filtering */
+#define LAN9118_MAC_CR_PASSBAD      (1 << 16) /* Pass Bad Frames */
+#define LAN9118_MAC_CR_HO           (1 << 15) /* Hash Only Filtering mode */
+#define LAN9118_MAC_CR_HPFILT       (1 << 13) /* Hash/Perfect Flt Mode */
+#define LAN9118_MAC_CR_LCOLL        (1 << 12) /* Late Collision Control */
+#define LAN9118_MAC_CR_BCAST        (1 << 11) /* Disable Broardcast Frms */
+#define LAN9118_MAC_CR_DISRTY       (1 << 10) /* Disable Retry */
+#define LAN9118_MAC_CR_PADSTR       (1 << 8)  /* Automatic Pad String */
+#define LAN9118_MAC_CR_BOLMT        (1 << 7)  /* BackOff Limit */
+#define LAN9118_MAC_CR_DFCHK        (1 << 5)  /* Deferral Check */
+#define LAN9118_MAC_CR_TXEN         (1 << 3)  /* Transmitter enable */
+#define LAN9118_MAC_CR_RXEN         (1 << 2)  /* Receiver enable */
+#define LAN9118_ADDRH               0x2 /* MAC Address High */
+#define LAN9118_ADDRL               0x3 /* MAC Address Low */
+#define LAN9118_HASHH               0x4 /* Multicast Hash Table High */
+#define LAN9118_HASHL               0x5 /* Multicast Hash Table Low */
+#define LAN9118_MII_ACC             0x6 /* MII Access */
+#define LAN9118_MII_ACC_PHYA(a)     ((a) << 11) /* PHY Address */
+#define LAN9118_MII_ACC_MIIRINDA(i) ((i) << 6)  /* MII Register Index */
+#define LAN9118_MII_ACC_MIIWNR      (1 << 1)    /* MII Write */
+#define LAN9118_MII_ACC_MIIBZY      (1 << 0)    /* MII Busy */
+#define LAN9118_MII_DATA            0x7 /* MII Data */
+#define LAN9118_FLOW                0x8 /* Flow Control */
+#define LAN9118_FLOW_FCPT(t)        ((t) << 16) /* Pause Time */
+#define LAN9118_FLOW_FCPASS         (1 << 2)    /* Pass Control Frame */
+#define LAN9118_FLOW_FCEN           (1 << 1)    /* Flow Control Enable */
+#define LAN9118_FLOW_FCBUSY         (1 << 0)    /* Flow Control Busy */
+#define LAN9118_VLAN1               0x9 /* VLAN1 Tag */
+#define LAN9118_VLAN2               0xa /* VLAN2 Tag */
+#define LAN9118_WUFF                0xb /* Wake-up Frame Filter */
+#define LAN9118_WUCSR               0xc /* Wake-up Control and Status */
+
+/* PHY Registers */
+#define LAN9118_MCSR                0x11    /* Mode Control/Status Register */
+#define LAN9118_MCSR_EDPWRDOWN      (1 << 13) /* Energy Detect Power Down */
+#define LAN9118_MCSR_ENERGYON       (1 << 1)
+#define LAN9118_SMR                 0x12    /* Special Modes Register */
+#define LAN9118_SMR_PHYAD           (0x01)
+#define LAN9118_SCSI                0x1b    /* Special Control/Status Indications */
+#define LAN9118_SCSI_VCOOFF_LP      (1 << 10)
+#define LAN9118_SCSI_XPOL           (1 << 4)  /* Polarity state */
+#define LAN9118_ISR                 0x1d    /* Interrupt Source Register */
+#define LAN9118_IMR                 0x1e    /* Interrupt Mask Register */
+#define LAN9118_I_ENERGYON          (1 << 7)
+#define LAN9118_I_AUTONEGOCOMPL     (1 << 6)
+#define LAN9118_I_REMOTEFAULT       (1 << 5)
+#define LAN9118_I_LINKDOWN          (1 << 4)
+#define LAN9118_I_AUTONEGOLPACK     (1 << 3) /* AutoNego LP Acknowledge */
+#define LAN9118_I_PDF               (1 << 2) /* Parallel Detection Fault */
+#define LAN9118_I_AUTONEGOPR        (1 << 1) /* AutoNego Page Received */
+#define LAN9118_PHYSCSR             0x1f    /* PHY Special Control/Status Reg */
+#define LAN9118_PHYSCSR_AUTODONE    (1 << 12) /* AutoNego done indication */
+#define LAN9118_PHYSCSR_SI_10       (1 << 2)  /* Speed Indication */
+#define LAN9118_PHYSCSR_SI_100      (2 << 2)
+#define LAN9118_PHYSCSR_SI_FDX      (4 << 2)
+
+
+/* TX Command 'A' Format */
+#define LAN9118_TXC_A_IC        (1 << 31) /* Interrupt on Completion */
+#define LAN9118_TXC_A_BEA_4B    (0 << 24) /* Buffer End Alignment: 4B */
+#define LAN9118_TXC_A_BEA_16B   (1 << 24) /*                      16B */
+#define LAN9118_TXC_A_BEA_32B   (2 << 24) /*                      32B */
+#define LAN9118_TXC_A_DSO(x)    ((x) << 16) /*Data Start Offset: bytes*/
+#define LAN9118_TXC_A_FS        (1 << 13) /* First Segment */
+#define LAN9118_TXC_A_LS        (1 << 12) /* Last Segment */
+#define LAN9118_TXC_A_BS(x)     ((x) << 0) /* Buffer Size */
+
+/* TX Command 'B' Format */
+#define LAN9118_TXC_B_PT(x)     ((x) << 16) /* Packet Tag */
+#define LAN9118_TXC_B_ACRCD     (1 << 13)  /* Add CRC Disable */
+#define LAN9118_TXC_B_DEFP      (1 << 12)  /* Dis Ether Frame Padding */
+#define LAN9118_TXC_B_PL(x)     ((x) << 0) /* Packet Length */
+
+/* TX Status Format */
+#define LAN9118_TXS_PKTTAG(x)   (((x) >> 16) & 0xff) /* Packet Tag */
+#define LAN9118_TXS_ES          (1 << 15)   /* Error Status */
+#define LAN9118_TXS_LOC         (1 << 11)   /* Loss Of Carrier */
+#define LAN9118_TXS_NC          (1 << 10)   /* No Carrier */
+#define LAN9118_TXS_LCOL        (1 << 9)    /* Late Collision */
+#define LAN9118_TXS_ECOL        (1 << 8)    /* Excessive Collision*/
+#define LAN9118_TXS_COLCNT(x)   (((x) >> 3) & 0xf) /* Collision Count */
+#define LAN9118_TXS_ED          (1 << 2)    /* Excessive Deferral */
+#define LAN9118_TXS_DEFERRED    (1 << 0)    /* Deferred */
+
+/* RX Status Format */
+#define LAN9118_RXS_FILTFAIL    (1 << 30) /* Filtering Fail */
+#define LAN9118_RXS_PKTLEN(x)   (((x) >> 16) & 0x3fff) /* Packet Len */
+#define LAN9118_RXS_ES          (1 << 15) /* Error Status */
+#define LAN9118_RXS_BCF         (1 << 13) /* Broadcast Frame */
+#define LAN9118_RXS_LENERR      (1 << 12) /* Length Error */
+#define LAN9118_RXS_RUNTF       (1 << 11) /* Runt Frame */
+#define LAN9118_RXS_MCF         (1 << 10) /* Multicast Frame */
+#define LAN9118_RXS_FTL         (1 << 7)  /* Frame Too Long */
+#define LAN9118_RXS_COLS        (1 << 6)  /* Collision Seen */
+#define LAN9118_RXS_FT          (1 << 5)  /* Frame Type */
+#define LAN9118_RXS_RWTO        (1 << 4)  /* Rcv Watchdog time-out */
+#define LAN9118_RXS_MIIERR      (1 << 3)  /* MII Error */
+#define LAN9118_RXS_DBIT        (1 << 2)  /* Drabbling Bit */
+#define LAN9118_RXS_CRCERR      (1 << 1)  /* CRC Error */
 
+/* Basic mode control register. */
+#define LAN9118_BMCR_ANRESTART      0x0200  /* Auto negotiation restart  */
+#define LAN9118_BMCR_ANENABLE       0x1000  /* Enable auto negotiation   */
+#define LAN9118_BMCR_RESET          0x8000  /* Reset the DP83840     */
+#define LAN9118_BMSR_LSTATUS        0x0004  /* Link status    */
 
 /* Generic MII registers. */
+#define LAN9118_MII_BMCR            0x00  /* Basic mode control register */
+#define LAN9118_MII_BMSR            0x01  /* Basic mode status register  */
+#define LAN9118_MII_ADVERTISE       0x04  /* Advertisement control register */
 
-#define MII_BMCR        0x00    /* Basic mode control register */
-#define MII_BMSR        0x01    /* Basic mode status register  */
-#define MII_PHYSID1     0x02    /* PHYS ID 1               */
-#define MII_PHYSID2     0x03    /* PHYS ID 2               */
-#define MII_ADVERTISE   0x04    /* Advertisement control reg   */
-#define MII_LPA         0x05    /* Link partner ability reg    */
-#define MII_EXPANSION   0x06    /* Expansion register          */
-#define MII_CTRL1000    0x09    /* 1000BASE-T control          */
-#define MII_STAT1000    0x0a    /* 1000BASE-T status           */
-#define MII_ESTATUS     0x0f    /* Extended Status */
-#define MII_DCOUNTER    0x12    /* Disconnect counter          */
-#define MII_FCSCOUNTER  0x13    /* False carrier counter       */
-#define MII_NWAYTEST    0x14    /* N-way auto-neg test reg     */
-#define MII_RERRCOUNTER 0x15    /* Receive error counter       */
-#define MII_SREVISION   0x16    /* Silicon revision        */
-#define MII_RESV1       0x17    /* Reserved...             */
-#define MII_LBRERROR    0x18    /* Lpback, rx, bypass error    */
-#define MII_PHYADDR     0x19    /* PHY address             */
-#define MII_RESV2       0x1a    /* Reserved...             */
-#define MII_TPISTATUS   0x1b    /* TPI status for 10mbps       */
-#define MII_NCONFIG     0x1c    /* Network interface config    */
+#define LAN9118_GPT_CFG_TIMER_EN    0x20000000  /* R/W */
 
-/* Basic mode control register. */
-#define BMCR_RESV       0x003f  /* Unused...               */
-#define BMCR_SPEED1000  0x0040  /* MSB of Speed (1000)         */
-#define BMCR_CTST       0x0080  /* Collision test          */
-#define BMCR_FULLDPLX   0x0100  /* Full duplex             */
-#define BMCR_ANRESTART  0x0200  /* Auto negotiation restart    */
-#define BMCR_ISOLATE    0x0400  /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN      0x0800  /* Powerdown the DP83840       */
-#define BMCR_ANENABLE   0x1000  /* Enable auto negotiation     */
-#define BMCR_SPEED100   0x2000  /* Select 100Mbps          */
-#define BMCR_LOOPBACK   0x4000  /* TXD loopback bits           */
-#define BMCR_RESET      0x8000  /* Reset the DP83840           */
+#define LAN9118_RX_STS_PKT_LEN      0x3FFF0000
+#define LAN9118_TX_STS_UNDERRUN     0x00000002
+
+#define LAN9118_HW_CFG_SF           0x00100000  /* R/W */
 
-/* Basic mode status register. */
-#define BMSR_ERCAP      0x0001  /* Ext-reg capability          */
-#define BMSR_JCD        0x0002  /* Jabber detected         */
-#define BMSR_LSTATUS    0x0004  /* Link status             */
-#define BMSR_ANEGCAPABLE    0x0008  /* Able to do auto-negotiation */
-#define BMSR_RFAULT     0x0010  /* Remote fault detected       */
-#define BMSR_ANEGCOMPLETE   0x0020  /* Auto-negotiation complete   */
-#define BMSR_RESV       0x00c0  /* Unused...               */
-#define BMSR_ESTATEN    0x0100  /* Extended Status in R15 */
-#define BMSR_100HALF2   0x0200  /* Can do 100BASE-T2 HDX */
-#define BMSR_100FULL2   0x0400  /* Can do 100BASE-T2 FDX */
-#define BMSR_10HALF     0x0800  /* Can do 10mbps, half-duplex  */
-#define BMSR_10FULL     0x1000  /* Can do 10mbps, full-duplex  */
-#define BMSR_100HALF    0x2000  /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL    0x4000  /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4   0x8000  /* Can do 100mbps, 4k packets  */
+#define LAN9118_INT_STS_RSFL        0x00000008  /* R/WC */
+#define LAN9118_INT_EN_RDFL_EN      0x00000020  /* R/W */
+#define LAN9118_MAC_CR_HBDIS        0x10000000
 
-#endif
+#endif  /* _LAN9118REG_H_ */

bsp/qemu-vexpress-a9/drivers/secondary_cpu.c

@@ -26,10 +26,16 @@ static void rt_hw_timer2_isr(int vector, void *param)
     timer_clear_pending(0);
 }
 
-void rt_hw_secondary_cpu_up(void)
+void set_secondary_cpu_boot_address(void)
 {
-    extern void set_secondary_cpu_boot_address(void);
+    extern void secondary_cpu_start(void);
+    uint32_t *boot_address = (uint32_t *)0x10000030;
+    *(boot_address + 1) = ~0ul;
+    *boot_address = (uint32_t )&secondary_cpu_start;
+}
 
+void rt_hw_secondary_cpu_up(void)
+{
     set_secondary_cpu_boot_address();
     __asm__ volatile ("dsb":::"memory");
     rt_hw_ipi_send(0, 1 << 1);

bsp/qemu-vexpress-a9/link.lds

@@ -26,7 +26,12 @@ SECTIONS
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+
+        /* section information for var export */
         . = ALIGN(4);
+        __ve_table_start = .;
+        KEEP(*(SORT(*.VarExpTab.*)))
+        __ve_table_end = .;
 
         /* section information for modules */
         . = ALIGN(4);

bsp/qemu-vexpress-a9/rtconfig.h

@@ -1,8 +1,7 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Project Configuration */
+/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */
 
 /* RT-Thread Kernel */
 
@@ -18,9 +17,14 @@
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 1024
+#define SYSTEM_THREAD_STACK_SIZE 1024
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 1024
+
+/* kservice optimization */
+
+/* end of kservice optimization */
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
 
@@ -32,6 +36,7 @@
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
 #define RT_USING_SIGNALS
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -40,6 +45,7 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_MEMTRACE
 #define RT_USING_HEAP
+/* end of Memory Management */
 
 /* Kernel Device Object */
 
@@ -49,9 +55,13 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40002
+/* end of Kernel Device Object */
+#define RT_VER_NUM 0x40004
+/* end of RT-Thread Kernel */
 #define ARCH_ARM
+#define RT_USING_CPU_FFS
 #define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V2
 #define ARCH_ARM_CORTEX_A9
 
 /* RT-Thread Components */
@@ -64,29 +74,32 @@
 /* C++ features */
 
 #define RT_USING_CPLUSPLUS
+/* end of C++ features */
 
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
+/* end of Command shell */
 
 /* Device virtual file system */
 
 #define RT_USING_DFS
 #define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEMS_MAX 4
 #define DFS_FILESYSTEM_TYPES_MAX 8
-#define DFS_FD_MAX 16
+#define DFS_FD_MAX 32
 #define RT_USING_DFS_ELMFAT
 
 /* elm-chan's FatFs, Generic FAT Filesystem Module */
@@ -95,13 +108,18 @@
 #define RT_DFS_ELM_WORD_ACCESS
 #define RT_DFS_ELM_USE_LFN_3
 #define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
 #define RT_DFS_ELM_MAX_LFN 255
 #define RT_DFS_ELM_DRIVES 2
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
 #define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
+/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
 #define RT_USING_DFS_DEVFS
 #define RT_USING_DFS_ROMFS
 #define RT_USING_DFS_RAMFS
+/* end of Device virtual file system */
 
 /* Device Drivers */
 
@@ -111,6 +129,7 @@
 #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_I2C
@@ -132,16 +151,13 @@
 #define RT_USING_SFUD
 #define RT_SFUD_USING_SFDP
 #define RT_SFUD_USING_FLASH_INFO_TABLE
+#define RT_SFUD_SPI_MAX_HZ 50000000
 #define RT_USING_WDT
 
-/* Using Hardware Crypto drivers */
-
-
-/* Using WiFi */
-
-
 /* Using USB */
 
+/* end of Using USB */
+/* end of Device Drivers */
 
 /* POSIX layer and C standard library */
 
@@ -151,18 +167,25 @@
 #define RT_USING_POSIX
 #define RT_USING_POSIX_MMAP
 #define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_GETLINE
 #define RT_USING_POSIX_AIO
+#define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+/* end of POSIX layer and C standard library */
 
 /* Network */
 
 /* Socket abstraction layer */
 
 #define RT_USING_SAL
+#define SAL_INTERNET_CHECK
 
 /* protocol stack implement */
 
 #define SAL_USING_LWIP
+/* end of protocol stack implement */
 #define SAL_USING_POSIX
+/* end of Socket abstraction layer */
 
 /* Network interface device */
 
@@ -173,11 +196,13 @@
 #define NETDEV_USING_AUTO_DEFAULT
 #define NETDEV_IPV4 1
 #define NETDEV_IPV6 0
+/* end of Network interface device */
 
 /* light weight TCP/IP stack */
 
 #define RT_USING_LWIP
-#define RT_USING_LWIP202
+#define RT_USING_LWIP212
+#define RT_LWIP_MEM_ALIGNMENT 4
 #define RT_LWIP_ICMP
 #define RT_LWIP_DNS
 #define RT_LWIP_DHCP
@@ -189,6 +214,7 @@
 #define RT_LWIP_IPADDR "192.168.1.30"
 #define RT_LWIP_GWADDR "192.168.1.1"
 #define RT_LWIP_MSKADDR "255.255.255.0"
+/* end of Static IPv4 Address */
 #define RT_LWIP_UDP
 #define RT_LWIP_TCP
 #define RT_LWIP_RAW
@@ -213,20 +239,29 @@
 #define LWIP_SO_RCVTIMEO 1
 #define LWIP_SO_SNDTIMEO 1
 #define LWIP_SO_RCVBUF 1
+#define LWIP_SO_LINGER 0
 #define LWIP_NETIF_LOOPBACK 0
 #define RT_LWIP_USING_PING
-
-/* Modbus master and slave stack */
-
+/* end of light weight TCP/IP stack */
 
 /* AT commands */
 
+/* end of AT commands */
+/* end of Network */
 
 /* VBUS(Virtual Software BUS) */
 
+/* end of VBUS(Virtual Software BUS) */
 
 /* Utilities */
+
+/* end of Utilities */
 #define RT_USING_LWP
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -237,36 +272,72 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
+/* end of language packages */
 
 /* multimedia packages */
 
 
+/* lvgl: powerful and easy-to-use embedded GUI library */
+
+/* end of lvgl: powerful and easy-to-use embedded GUI library */
+
+/* u8g2: a monochrome graphic library */
+
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
+
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
+/* end of peripheral libraries and drivers */
 
-/* miscellaneous packages */
+/* AI packages */
 
+/* end of AI packages */
+
+/* miscellaneous packages */
 
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
+
+/* entertainment: terminal games and other interesting software packages */
+
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
+/* end of RT-Thread online packages */
 #define SOC_VEXPRESS_A9
 #define RT_USING_UART0
 #define RT_USING_UART1

bsp/stm32/README.md

@@ -6,6 +6,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | **BSP 文件夹名称**       | **开发板名称**                 |
 |:------------------------- |:-------------------------- |
 | **F0 系列** |  |
+| [stm32f072-st-nucleo](stm32f072-st-nucleo) | ST 官方 STM32F072-nucleo 开发板 |
 | [stm32f091-st-nucleo](stm32f091-st-nucleo) | ST 官方 STM32F091-nucleo 开发板 |
 | **F1 系列** |  |
 | [stm32f103-atk-nano](stm32f103-atk-nano)        | 正点原子 F103 NANO 开发板  |
@@ -14,30 +15,40 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f103-dofly-lyc8](stm32f103-dofly-lyc8) | 德飞莱 STM32F103 开发板 |
 | [stm32f103-dofly-M3S](stm32f103-dofly-M3S) | 德飞莱 STM32F103 开发板 |
 | [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/)  | 野火 F103 霸道开发板     |
+| [stm32f103-gizwits-gokitv21](stm32f103-gizwits-gokitv21) | GoKit V2.1开发板 |
 | [stm32f103-hw100k-ibox](stm32f103-hw100k-ibox) |  硬件十万个为什么 STM32F103 iBox 开发板 |
-| [stm32f103-mini-system](stm32f103-mini-system)        | STM32F103C8T6最小系统板  |
-| [stm32f107-uc-eval](stm32f107-uc-eval) | 麦克泰 STM32F107 评估板（中国版） |
+| [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 |
+| [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 |
+| [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板（中国版） |
+| **F2 系列** |  |
+| [stm32f207-st-nucleo](stm32f207-st-nucleo) | ST 官方 STM32F207-nucleo 开发板 |
 | **F4 系列** |  |
 | [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 |
 | [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 |
-| [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 |
 | [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 |
+| [stm32f407-robomaster-c](stm32f407-robomaster-c) | 大疆公司 RoboMaster C型开发板 |
+| [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 |
+| [stm32f410-st-nucleo](stm32f410-st-nucleo) | ST 官方 STM32F410-Nucleo-64 开发板 |
 | [stm32f411-atk-nano](stm32f411-atk-nano/) | 正点原子 F411 NANO 开发板 |
 | [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 |
+| [stm32f411-weact-MiniF4](stm32f411-weact-MiniF4/) | F401/F411最小系统开发板（Black Pill） |
+| [stm32f412-st-nucleo](stm32f412-st-nucleo/) | ST 官方 STM32F412-Nucleo-144 开发板 |
+| [stm32f413-st-nucleo](stm32f413-st-nucleo/) | ST 官方 STM32F413-Nucleo-144 开发板 |
 | [stm32f427-robomaster-a](stm32f427-robomaster-a/) |大疆公司 RoboMaster A型开发板|
+| [stm32f429-armfly-v6](stm32f429-armfly-v6) |安富莱 F429-v6 开发板|
+| [stm32f429-atk-apollo](stm32f429-atk-apollo) |正点原子 F429 阿波罗开发板|
+| [stm32f429-fire-challenger](stm32f429-fire-challenger/) |野火 F429 挑战者开发板|
 | [stm32f429-st-disco](stm32f429-st-disco) | ST 官方 STM32F429-discovery 开发板 |
-| [stm32f429-atk-apollo](stm32f429-atk-apollo)      | 正点原子 F429 阿波罗开发板 |
-| [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 |
-| [stm32f429-armfly-v6](stm32f429-armfly-v6) | 安富莱 F429-v6 开发板 |
 | [stm32f446-st-nucleo](stm32f446-st-nucleo) | ST 官方 STM32F446-nucleo 开发板 |
 | [stm32f469-st-disco](stm32f469-st-disco) | ST 官方 STM32F469-discovery 开发板 |
 | **F7 系列** |  |
 | [stm32f746-st-disco](stm32f746-st-disco) | ST 官方 STM32F746-discovery 开发板 |
 | [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 |
-| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 |
+| [stm32f767-fire-challenger-v1](stm32f767-fire-challenger-v1/) | 野火 F767-V1 挑战者开发板 |
 | [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 |
 | [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 |
 | **G0 系列** |  |
+| [stm32g070-st-nucleo](stm32g070-st-nucleo) | ST 官方 STM32G070-nucleo 开发板 |
 | [stm32g071-st-nucleo](stm32g071-st-nucleo) | ST 官方 STM32G071-nucleo 开发板 |
 | **G4 系列** |  |
 | [stm32g431-st-nucleo](stm32g431-st-nucleo) | ST 官方 STM32G431-nucleo 开发板 |
@@ -45,21 +56,29 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32h743-atk-apollo](stm32h743-atk-apollo) | 正点原子 h743 阿波罗开发板 |
 | [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 |
 | [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 |
+| [stm32h750-armfly-h7-tool](stm32h750-armfly-h7-tool) | 安富莱 STM32H750 Tool 开发板 |
 | **L0 系列** |  |
 | [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 |
 | [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 |
 | **L4 系列** |  |
+| [stm32l4r5-st-nucleo](stm32l4r5-st-nucleo) | ST 官方 STM32L4R5-Nucleo 开发板 |
 | [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 |
-| [stm32l432-st-nucleo](stm32l432-st-nucleo) | ST 官方 STM32L432-nucleo 开发板 |
+| [stm32l412-st-nucleo](stm32l412-st-nucleo) | ST 官方 STM32L412-Nucleo 开发板 |
+| [stm32l431-BearPi](stm32l431-BearPi) | STM32L431 小熊派 开发板 |
+| [stm32l432-st-nucleo](stm32l432-st-nucleo) | ST 官方 STM32L432-Nucleo 开发板 |
+| [stm32l433-st-nucleo](stm32l433-st-nucleo) | ST 官方 STM32L433-Nucleo 开发板 |
+| [stm32l452-st-nucleo](stm32l452-st-nucleo) | ST 官方 STM32L452-Nucleo 开发板 |
 | [stm32l475-atk-pandora](stm32l475-atk-pandora) | 正点原子 L475 潘多拉 IoT 开发板 |
 | [stm32l475-st-discovery](stm32l475-st-discovery) | ST 官方 stm32l475-discovery 开发板 |
-| [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-nucleo 开发板 |
+| [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-Nucleo 开发板 |
 | [stm32l496-ali-developer](stm32l496-ali-developer) | 诺行 STM32L496 Ali Developer Kit 开发板 |
+| [stm32l496-st-nucleo](stm32l496-st-nucleo) | ST 官方 STM32L496-Nucleo 开发板 |
 | **MP1 系列** |  |
 | [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
 | [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
 | **WB 系列** |  |
-| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-nucleo 开发板 |
+| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 |
+| [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 |
 
 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
 

bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md

@@ -0,0 +1,246 @@
+# How to make a STM32 BSP for RT-Thread
+
+In order to allow developers to use BSP for development better and more conveniently, the RT-Thread team rearranged the existing STM32 series of BSPs and launched a new BSP framework. The new BSP framework has been greatly improved in terms of ease of use, portability, driver integrity, and code standardization. Development under the new BSP framework can greatly improve the efficiency of application development. 
+
+The new BSP framework also introduces the CubeMX tool, which can be used to configure the peripheral pins which are used in the BSP. The CubeMX tool provides a graphical configuration interface. This graphical configuration method is more intuitive for developers. It not only allows developers to flexibly configure the resources used in the BSP, but also allows developers to understand the use of resources at a glance .
+
+The main features of the new STM32 BSP framework are as follows: 
+
+- Provide multiple series of BSP templates, greatly reducing the difficulty of adding new BSPs; 
+- Each BSP is equipped with a complete set of driver files, so that developers can easily use all drivers; 
+- Developers can use the CubeMX tool to configure the BSP graphically.
+
+## 1. Introduction to BSP Framework 
+
+The BSP frame structure is shown in the figure below: 
+
+![BSP frame structure](./figures_en/frame.png)
+
+Each BSP of the STM32 series consists of three parts, namely the general library, the BSP template and the specific development board BSP. The following table uses the F1 series BSP as an example to introduce these three parts: 
+
+| Item                                | Folder                              | Detail                                                       |
+| ----------------------------------- | ----------------------------------- | :----------------------------------------------------------- |
+| General library                     | stm32/libraries                     | Used to place HAL library and multi-series general peripheral driver files developed based on HAL library |
+| STM32F1 series BSP project template | stm32/libraries/templates/stm32f10x | You can make more F1 series BSP by modifying this template   |
+| Specific development board BSP      | stm32/stm32f103-blue-pill           | Modified on the basis of the BSP template                    |
+
+## 2. Knowledge of background
+
+## 3. Make a STM32 BSP for steps
+
+Making a STM32 BSP is divided into the following five steps: 
+
+1. Copy the generic template 
+2. Use CubeMX tool to configure the project
+3. Modify the Kconfig file in the BSP 
+4. Modify the relevant files of the build project
+5. Regenerate the project
+
+In the following chapters, these five steps will be introduced in detail to help developers quickly create the required BSP. 
+
+### 3.1 Copy the generic template 
+
+The first step in making a new BSP is to copy a BSP template of the same series as the basis, and obtain a new BSP by modifying the BSP template. 
+
+The folder structure of the F1 series BSP template used in this example is as follows: 
+
+![F1 series BSP template folder contents](figures_en/bsp_template_dir.png)
+
+Copy the `stm32f10x` folder under the template folder and change the name of the folder to `stm32f103-blue-pill`, as shown in the following figure: 
+
+![Copying common templates](./figures_en/copy.png)
+
+Modify the configuration file in the board folder. The modified content is shown in the following table: 
+
+| Item                      | Instruction                                                  |
+| ------------------------- | ------------------------------------------------------------ |
+| CubeMX_Config （folder）  | CubeMX project                                               |
+| linker_scripts （folder） | BSP link script                                              |
+| board.c/h                 | System clock, GPIO initialization function, chip memory size |
+| Kconfig                   | Chip series, peripheral resources                            |
+| SConscript                | Chip startup file, target chip model                         |
+
+### 3.2 Use CubeMX to configure the project 
+
+Create a CubeMX project based on the target chip. The default CubeMX project is in the **CubeMX_Config** folder, double-click to open the `CubeMX_Config.ioc` project, as shown in the figure below: 
+
+![open_cubemx](figures_en/open_cubemx.png)
+
+Change the chip model to STM32F103C8Tx in the CubeMX project. 
+
+#### 3.2.1 Generate CubeMX project 
+
+Configure the system clock, peripheral pins, etc. The steps are shown in the figure below: 
+
+1. Turn on the external clock, set the download mode, and turn on the serial peripherals (note that only the pins of the serial peripherals need to be selected, no other parameters need to be configured): 
+
+   ![Configure chip pins](./figures_en/CubeMX_1.png)
+
+2. Configure the system clock: 
+
+   ![Configuring the System Clock](./figures_en/CubeMX_2.png)
+
+3. Set the project name and regenerate the CubeMX project at a specified address: 
+
+   ![Generate the corresponding configuration code](./figures_en/CubeMX_4.png)
+
+   Note: When generating the code, do not check the following options (ie: Do not let it generate a peripheral initialization as a pair of .c/.h files per perioheral.) 
+
+   ![generate-code](figures/generate-code.png)
+
+4. The final project directory structure generated by CubeMX is shown in the figure below: 
+
+   ![CubeMX 7](./figures_en/CubeMX_5.png)
+
+#### 3.2.2 Copy initialization function 
+
+The function `SystemClock_Config()` is placed in the **board.c** file, which is responsible for initializing the system clock. When using the CubeMX tool to reconfigure the system clock, this function needs to be updated. This function is generated by the CubeMX tool and is placed in the file `board/CubeMX_Config/Src/main.c` by default. However, this file does not include in our project, so we need to copy this function from main.c to the board.c file. In the entire BSP making process, this function is the only function to be copied. The content of this function is as follows: 
+
+![board_1](./figures_en/board_1.png)
+
+The relevant parameters of FLASH and RAM are configured in the **board.h** file. What needs to be modified in this file is the parameters controlled by the two macros `STM32_FLASH_SIZE` and `STM32_SRAM_SIZE`. The flash size of the STM32F103C8Tx chip used in the BSP produced this time is 64k, and the size of the ram is 20k, so the file is modified as follows: 
+
+![Modified board.h](./figures_en/board_h.png)
+
+#### 3.2.3 Heap memory configuration 
+
+Normally, a part of the memory space in the system RAM will be used as heap memory. The function of the following code is to specify the start address **HEAP_BEGIN** and end address **HEAP_END** of the heap memory under different compilers. The values of **HEAP_BEGIN** and **HEAP_END** here need to be consistent with the configuration modified in the following section [3.4.1 Modify Link Script](# 3.4.1 Modify Link Script).
+
+In some series of chips, the chip RAM may be distributed in multiple discrete memory areas. At this time, the location of the heap memory can be in the same continuous memory area as the system memory, or it can be stored in a separate memory area. For example, on the L4 series of chips, the heap memory can be configured in a 96k memory space with a starting address of `0x20000000`, and the 32k memory space starting from `0x10000000` can be used as the system running memory. 
+
+![heap_config](figures_en/heap_config.png)
+
+### 3.3 Modify Kconfig configuration
+
+Modify the contents of the `board/Kconfig` file in this section as follows: 
+
+- Chip model and series 
+- Peripheral support options on BSP 
+
+The modification of chip model and series is shown in the following table: 
+
+| Macro Definition   | Meaning     | Format             |
+| ------------------ | ----------- | ------------------ |
+| SOC_STM32F103RB    | Chip model  | SOC_STM32xxx       |
+| SOC_SERIES_STM32F1 | Chip series | SOC_SERIES_STM32xx |
+
+Regarding the peripheral support options on the BSP, a BSP submitted for the first time only needs to support the GPIO driver and the serial port driver, which means only these two driver configuration items need to be retained in the configuration options, as shown in the following figure: 
+
+![Modified Kconfig](./figures_en/Kconfig.png)
+
+### 3.4 Modify project building related files 
+
+#### 3.4.1 Modify the link script 
+
+**linker_scripts** The link file is as shown in the figure below: 
+
+![Link scripts that need to be modified](./figures_en/linker_scripts.png)
+
+The following uses the link script link.sct used by MDK as an example to demonstrate how to modify the link script: 
+
+![linkscripts_change](figures_en/linkscripts_change.png)
+
+The chip used to make the BSP this time is STM32F103RB, and the FLASH is 128k, so modify the parameters of LR_IROM1 and ER_IROM1 to 0x00020000. The size of RAM is 20k, so modify the parameter of RW_IRAM1 to 0x00005000. Such a modification method is sufficient for general applications. If there are special requirements in the future, you need to modify it as required according to the syntax of the link script. When modifying the link script, you can refer to the [**3.2.3 Heap memory configuration**](# 3.2.3 Heap memory configuration) chapter to determine the BSP memory allocation. 
+
+The other two link script files are link.icf used by IAR and link.lds used by the GCC compiler. The modification method is similar, as shown in the following figure: 
+
+![link_icf](figures_en/link_icf.png)
+
+![link_lds](figures_en/link_lds.png)
+
+#### 3.4.2 Modify the build script 
+
+The **SConscript** script determines the files to be added during the generation and compilation of the MDK/IAR project. 
+
+In this step, you need to modify the chip model and the address of the chip startup file. The modification content is shown in the figure below: 
+
+![Modify the startup file and chip model](./figures_en/SConscript.png)
+
+Note: If you cannot find the .s file of the corresponding series in the folder, it may be that multiple series of chips reuse the same startup file. At this time, you can generate the target chip project in CubeMX to see which startup file is used. Then modify the startup file name. 
+
+#### 3.4.3 Modify the project template 
+
+The **template** file is a template file for generating the MDK/IAR project. By modifying the file, you can set the chip model used in the project and the download method. The project template file of MDK4/MDK5/IAR, as shown in the figure below: 
+
+![MDK/IAR engineering template](./figures_en/template_1.png)
+
+The following takes the modification of the MDK5 template as an example to introduce how to modify the template configuration: 
+
+![Select the chip model](./figures_en/template_2.png)
+
+Modify the program download method: 
+
+![Configuring the Download Mode](./figures_en/template_3.png)
+
+### 3.5 Regenerate the project 
+
+Env tool is required to regenerate the project. 
+
+#### 3.5.1 Regenerate the rtconfig.h file 
+
+Enter the command menuconfig in the Env interface to configure the project and generate a new rtconfig.h file. As shown below: 
+
+![Enter menuconfig to go to the configuration screen](./figures_en/menuconfig_1.png)
+
+#### 3.5.2 Rebuild the MDK/IAR project 
+
+The following takes regenerating the MDK project as an example to introduce how to regenerate the BSP project. Use the Env tool to enter the command `scons --target=mdk5` to regenerate the project, as shown in the following figure: 
+
+![Regenerate the BSP project](./figures_en/menuconfig_3.png)
+
+Rebuild the project successfully: 
+
+![Regenerate the BSP project](./figures_en/menuconfig_4.png)
+
+At this point, the new BSP can be used. Next, we can use the commands `scons --target=mdk4` and `scons --target=iar` respectively to update the MDK4 and IAR projects so that the BSP becomes a complete BSP that can be submitted to GitHub (Making MDK4 project is optional). 
+
+## 4. Specifications 
+
+This chapter introduces the specifications that should be followed when making and submitting the RT-Thread STM32 series BSP. After the BSP is produced, the developer can check the produced BSP according to the checkpoints set out in this specification to ensure that the BSP has a higher quality before submission. 
+
+### 4.1 Specification of making BSP
+
+The specifications of making STM32 BSP are mainly divided into three aspects: engineering configuration, ENV configuration and IDE configuration. In the existing STM32 series BSP templates, the templates have been configured according to the following specifications. In the process of making a new BSP, when copying the template for modification, you need to be careful not to modify these default configurations. After the BSP is completed, the newly-made BSP needs to be tested for its function, and the code is submitted after the function is normal. The production specifications of the BSP will be described in detail below:
+
+#### 4.1.1 Project configuration 
+
+- Comply with RT-Thread coding standard, unified code comment style 
+
+- The main function remains the same   
+  - If there is an LED, **only put ONE** LED 1HZ flashing program in the main function 
+- Heap initialization needs to be completed in `rt_hw_board_init`: call `rt_system_heap_init` 
+- By default, only the GPIO driver and the serial port driver corresponding to FinSH are initialized, and DMA is not used 
+- When the onboard peripheral driver is enabled, it should be able to compile, download and use without modifying the code
+- Before submitting, check whether the three compilers of GCC/MDK/IAR are directly compiled or compiled successfully after regenerating 
+- Use the `dist` command to publish the BSP and check whether the project generated by the dist command can be used normally 
+
+#### 4.1.2 ENV configuration 
+
+- The system heartbeat is uniformly set to 1000 (Macro: RT_TICK_PER_SECOND) 
+- The assertion in the debugging option needs to be turned on in the BSP (macro: RT_DEBUG) 
+- The system idle thread stack size is uniformly set to 256 (Macro: IDLE_THREAD_STACK_SIZE) 
+- Turn on automatic component initialization (Macro: RT_USING_COMPONENTS_INIT) 
+- Need to enable the user main option (Macro: RT_USING_USER_MAIN) 
+- Disable libc by default (Macro: RT_USING_LIBC) 
+- FinSH only uses MSH mode by default (Macro: FINSH_USING_MSH_ONLY) 
+
+#### 4.1.3 IDE configuration
+
+- Enable automatic operation after downloading the code 
+- Enable C99 support 
+- Enable One ELF Section per Function (MDK)
+- Temporary files generated by MDK/IAR are placed in the keil/iar folder under build
+- The names of bin files generated by MDK/GCC/IAR are unified into rtthread.bin 
+
+### 4.2 Specification of BSP submission
+
+- Please carefully modify the README.md file of the BSP before submission. The peripheral support form of the README.md file only fills in the peripherals supported by the BSP. You can refer to other BSPs to fill in. 
+- Submission of BSP is divided into two stages: 
+  - The first stage: Basic BSP includes serial port driver and GPIO driver, and can run FinSH console. Completion of MDK4, MDK5, IAR and GCC compiler support, if the chip does not support a certain type of compiler (such as MDK4), you don’t need to do it.
+  - The second stage: complete the onboard peripheral driver support, all onboard peripherals can be used directly after they are configured using `menuconfig`. If the development board does not have on-board peripherals, this stage don't need to be completed. Different drivers should be submitted separately to facilitate review and merging. 
+
+- Only submit documents necessary for the BSP and delete irrelevant intermediate documents. Please check other BSPs for documents that can be submitted. 
+- When submitting libraries of different series of STM32, please refer to the HAL libraries of f1/f4 series and delete redundant library files.
+- Compile and test the BSP before submission to ensure that it compiles properly under different compilers.
+- Perform functional tests on the BSP before submission to ensure that the BSP meets the requirements in the engineering configuration chapter before submission.
+

bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md

@@ -14,7 +14,7 @@ By reading the ***Quickly Get Started*** section developers can quickly get thei
 
 ## Resources Introduction
 
-[<img src="figures/stm32-nucleo-144.png" alt="board" style="zoom:50%;" />](figures/stm32-nucleo-144.jpg) 
+[<img src="figures_en/stm32-nucleo-144.png" alt="board" style="zoom:50%;" />](figures/stm32-nucleo-144.jpg) 
 
 ### Description 
 
@@ -52,7 +52,7 @@ The STM32 Nucleo-144 board provides an affordable and flexible way for users to
 
 This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system.
 
-![nucleo144_layout](figures/nucleo144_layout.jpg)
+![nucleo144_layout](figures_en/nucleo144_layout.jpg)
 
 ### Hardware connection
 

bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md

@@ -14,7 +14,7 @@ By reading the ***Quickly Get Started*** section developers can quickly get thei
 
 ## Resources Introduction
 
-[![board](figures/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) 
+[![board](figures_en/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) 
 
 ### Description 
 
@@ -50,7 +50,7 @@ The STM32 Nucleo-64 board provides an affordable and flexible way for users to t
 
 This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system.
 
-![nucleo64_layout](figures/nucleo64_layout.jpg)
+![nucleo64_layout](figures_en/nucleo64_layout.jpg)
 
 ### Hardware connection
 

bsp/stm32/docs/STM32系列BSP制作教程.md

@@ -30,25 +30,25 @@ BSP 框架结构如下图所示：
 
 制作一个 BSP 的过程就是构建一个新系统的过程，因此想要制作出好用的 BSP，要对 RT-Thread 系统的构建过程有一定了解，需要的知识准备如下所示：
 
-- 掌握  stm32 系列 BSP 的使用方法
+- 掌握  STM32 系列 BSP 的使用方法
 
   了解 BSP 的使用方法，可以阅读 [BSP 说明文档](../README.md) 中使用教程表格内的文档。了解外设驱动的添加方法可以参考《外设驱动添加指南》。
 
-- 了解 scons 工程构建方法
+- 了解 Scons 工程构建方法
 
-  RT-Thread 使用 scons 作为系统的构建工具，因此了解 scons 的常用命令对制作新 BSP 是基本要求。
+  RT-Thread 使用 Scons 作为系统的构建工具，因此了解 Scons 的常用命令对制作新 BSP 是基本要求。
 
 - 了解设备驱动框架
 
   在 RT-Thread 系统中，应用程序通过设备驱动框架来操作硬件，因此了解设备驱动框架，对添加 BSP 驱动是很重要的。
 
-- 了解 kconfig 语法
+- 了解 Kconfig 语法
 
-  RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
+  RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 Kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
 
 - 熟悉 CubeMX 工具的使用
 
-  在新的 stm32 系列 BSP 中利用了 CubeMX 工具对底层硬件进行配置，因此需要了解 CubeMX 工具的使用方法。
+  在新的 STM32 系列 BSP 中利用了 CubeMX 工具对底层硬件进行配置，因此需要了解 CubeMX 工具的使用方法。
 
 ## 3. BSP 制作方法
 
@@ -117,6 +117,10 @@ BSP 的制作过程分为如下五个步骤：
 
 ![生成对应的配置代码](./figures/CubeMX_4.png)
 
+注意：在生成代码时，不要勾选以下选项（即：不让其生成单独的 .c/.h 驱动文件，直接全部更新到 rt-thread 要使用的 stm32xxx_hal_msp.c 文件中）
+
+![generate-code](figures/generate-code.png)
+
 最终 CubeMX 生成的工程目录结构如下图所示：
 
 ![CubeMX 图7](./figures/CubeMX_5.png)
@@ -210,17 +214,17 @@ BSP 的制作过程分为如下五个步骤：
 
 ### 3.5 重新生成工程
 
-重新生成工程需要使用 env 工具。
+重新生成工程需要使用 Env 工具。
 
 #### 3.5.1 重新生成 rtconfig.h 文件
 
-在 env 界面输入命令 menuconfig 对工程进行配置，并生成新的 rtconfig.h 文件。如下图所示：
+在 Env 界面输入命令 menuconfig 对工程进行配置，并生成新的 rtconfig.h 文件。如下图所示：
 
 ![输入menuconfig进入配置界面](./figures/menuconfig_1.png)
 
 ![选择要打开的外设](./figures/menuconfig_2.png)
 
-#### 3.5.2 重新 MDK/IAR 工程
+#### 3.5.2 重新生成 MDK/IAR 工程
 下面以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。
 
 使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示：
@@ -233,7 +237,7 @@ BSP 的制作过程分为如下五个步骤：
 
 到这一步为止，新的 BSP 就可以使用了。
 
-接下来我们可以分别使用命令 `scons --target=mdk4` 和 `scons --target=iar`，来更新 mdk4 和 iar 的工程，使得该 BSP 变成一个完整的，可以提交到 GitHub 的 BSP。
+接下来我们可以分别使用命令 `scons --target=mdk4` 和 `scons --target=iar`，来更新 MDK4 和 IAR 的工程，使得该 BSP 变成一个完整的，可以提交到 GitHub 的 BSP （MDK4工程的制作为可选）。
 
 感谢每一位贡献代码的开发者，RT-Thread 将与你一同成长。
 
@@ -241,13 +245,13 @@ BSP 的制作过程分为如下五个步骤：
 
 本章节介绍 RT-Thread STM32 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。
 
-### 1. BSP 制作规范
+### 4.1 BSP 制作规范
 
 STM32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 IDE 配置。在已有的 STM32 系列 BSP 的模板中，已经根据下列规范对模板进行配置。在制作新 BSP 的过程中，拷贝模板进行修改时，需要注意的是不要修改这些默认的配置。BSP 制作完成后，需要对新制作的 BSP 进行功能测试，功能正常后再进行代码提交。
 
 下面将详细介绍 BSP 的制作规范。
 
-#### 工程配置
+#### 4.1.1 工程配置
 
 - 遵从RT-Thread 编码规范，代码注释风格统一
 - main 函数功能保持一致
@@ -255,10 +259,10 @@ STM32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和
 - 在 `rt_hw_board_init` 中需要完成堆的初始化：调用 `rt_system_heap_init`
 - 默认只初始化 GPIO 驱动和 FinSH 对应的串口驱动，不使用 DMA
 - 当使能板载外设驱动时，应做到不需要修改代码就能编译下载使用
-- 提交前应检查 gcc/mdk/iar 三种编译器直接编译或者重新生成后编译是否成功
-- 使用 dist 功能对 BSP 进行发布，检查使用 dist 命令生成的工程是否可以正常使用
+- 提交前应检查 GCC/MDK/IAR 三种编译器直接编译或者重新生成后编译是否成功
+- 使用 `dist` 命令对 BSP 进行发布，检查使用 `dist` 命令生成的工程是否可以正常使用
 
-#### ENV 配置
+#### 4.1.2 ENV 配置
 
 - 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
 - BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
@@ -268,21 +272,21 @@ STM32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和
 - 默认关闭 libc（宏：RT_USING_LIBC）
 - FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
 
-#### IDE 配置
+#### 4.1.3 IDE 配置
 
 - 使能下载代码后自动运行
 - 使能 C99 支持
-- 使能 One ELF Setion per Function（MDK）
-- keil/iar 生成的临时文件分别放到build下的 keil/iar 文件夹下
-- mdk/gcc/iar 生成 bin 文件名字统一成 rtthread.bin
+- 使能 One ELF Section per Function（MDK）
+- MDK/IAR 生成的临时文件分别放到build下的 MDK/IAR 文件夹下
+- MDK/GCC/IAR 生成 bin 文件名字统一成 rtthread.bin
 
-### 2. BSP 提交规范
+### 4.2 BSP 提交规范
 
 - 提交前请认真修改 BSP 的 README.md 文件，README.md 文件的外设支持表单只填写 BSP 支持的外设，可参考其他 BSP 填写。查看文档[《STM32系列驱动介绍》](./STM32系列驱动介绍.md)了解驱动分类。
 - 提交 BSP 分为 2 个阶段提交：
   - 第一阶段：基础 BSP 包括串口驱动和 GPIO 驱动，能运行 FinSH 控制台。完成 MDK4、MDK5 、IAR 和 GCC 编译器支持，如果芯片不支持某款编译器（比如MDK4）可以不用做。 BSP 的 README.md 文件需要填写第二阶段要完成的驱动。
-  - 第二阶段：完成板载外设驱动支持，所有板载外设使用 menuconfig 配置后就能直接使用。若开发板没有板载外设，则此阶段可以不用完成。不同的驱动也要分开提交，方便 review 和合并。
+  - 第二阶段：完成板载外设驱动支持，所有板载外设使用 menuconfig 配置后就能直接使用。若开发板没有板载外设，则此阶段可以不用完成。不同的驱动要分开提交，方便 review 和合并。
 - 只提交 BSP 必要的文件，删除无关的中间文件，能够提交的文件请对照其他 BSP。
-- 提交 stm32 不同系列的 Library 库时，请参考 f1/f4 系列的 HAL 库，删除多余库文件
+- 提交 STM32 不同系列的 Library 库时，请参考 f1/f4 系列的 HAL 库，删除多余库文件
 - 提交前要对 BSP 进行编译测试，确保在不同编译器下编译正常
-- 提交前要对 BSP 进行功能测试，确保 BSP 的在提交前符合工程配置章节中的要求
+- 提交前要对 BSP 进行功能测试，确保 BSP 的在提交前符合工程配置章节中的要求

bsp/stm32/docs/STM32系列外设驱动添加指南.md

@@ -69,6 +69,9 @@
 - 部分驱动如果没有适配 BSP 所属的 STM32 系列，请等待 RT-Thread 团队更新。
   - 驱动文件对 STM32 系列的支持情况可以查看 [STM32系列驱动介绍文档](STM32系列驱动介绍文档.md)。
 - 对于驱动文件或文档说明，有任何建议或者意见，欢迎反馈到 [RT_Thread GitHub](https://github.com/RT-Thread/rt-thread) 网站或 [RT-Thread 官方论坛](https://www.rt-thread.org/qa/forum.php)。
+- 在生成代码时，不要勾选以下选项（即：不让其生成单独的 .c/.h 驱动文件，直接全部更新到 rt-thread 要使用的 stm32xxx_hal_msp.c 文件中）
+
+![generate-code](figures/generate-code.png)
 
 ## 5. 附录
 

bsp/stm32/libraries/.ignore_format.yml

@@ -0,0 +1,20 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- STM32F0xx_HAL
+- STM32F1xx_HAL
+- STM32F2xx_HAL
+- STM32F3xx_HAL
+- STM32F4xx_HAL
+- STM32F7xx_HAL
+- STM32G0xx_HAL
+- STM32G4xx_HAL
+- STM32H7xx_HAL
+- STM32L0xx_HAL
+- STM32L1xx_HAL
+- STM32L4xx_HAL
+- STM32MPxx_HAL
+- STM32WBxx_HAL
+- STM32WLxx_HAL

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -12,7 +12,10 @@ if GetDepend(['RT_USING_PIN']):
     src += ['drv_gpio.c']
 
 if GetDepend(['RT_USING_SERIAL']):
-    src += ['drv_usart.c']
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        src += ['drv_usart.c']
 
 if GetDepend(['RT_USING_HWTIMER']):
     src += ['drv_hwtimer.c']

bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
 #define UART1_RX_DMA_INSTANCE            DMA1_Channel3
 #define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
 #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
-#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
 #define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn

bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *