release rt-thread v4.0.3

.gitee/ISSUE_TEMPLATE.en.md

@@ -0,0 +1,9 @@
+### How is this problem caused?
+
+
+
+### Steps to reproduce
+
+
+
+### Error message

.gitee/ISSUE_TEMPLATE.zh-CN.md

@@ -0,0 +1,9 @@
+### 该问题是怎么引起的？
+
+
+
+### 重现步骤
+
+
+
+### 报错信息

.gitee/ISSUE_TEMPLATE.zh-TW.md

@@ -0,0 +1,9 @@
+### 該問題是怎麽引起的？
+
+
+
+### 重現步驟
+
+
+
+### 報錯信息

.gitee/PULL_REQUEST_TEMPLATE.en.md

@@ -0,0 +1,29 @@
+## PR description
+
+[
+The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
+
+Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
+
+And confirm in which case or board has been tested.
+]
+
+The following content must not be changed in the submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use a web browser to visit PR, and check items one by one, and ticked them if no problem.
+
+### The intent for your PR
+
+Choose one (Mandatory):
+
+- [ ] This PR is for a code-review and is intended to get feedback.
+- [ ] This PR is mature, and ready to be integrated into the repo.
+
+### Code Quality：
+
+As part of this pull request, I've considered the following:
+
+- [ ] Already check the difference between PR and old code.
+- [ ] The style guide is adhered to, including spacing, naming and other styles.
+- [ ] All redundant code is removed and cleaned up.
+- [ ] All modifications to BSP are justified and do not affect other components or BSPs.
+- [ ] I've commented appropriately where code is tricky.
+- [ ] Code in this PR is of high quality.

.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md

@@ -0,0 +1,29 @@
+## 拉取/合并请求描述：
+
+[
+这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
+
+请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
+
+并确认并列出已经在什么情况或板卡上进行了测试。
+]
+
+以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
+
+### 当前拉取/合并请求的状态：
+
+必须选择一项:
+
+- [ ] 本拉取/合并请求是一个草稿版本
+- [ ] 本拉取/合并请求是一个成熟版本
+
+### 代码质量：
+
+我在这个拉取/合并请求中已经考虑了:
+
+- [ ] 已经仔细查看过代码改动的对比
+- [ ] 代码风格正确，包括缩进空格，命名及其他风格
+- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码
+- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或
+- [ ] 对难懂代码均提供对应的注释
+- [ ] 本拉取/合并请求代码是高质量的

.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md

@@ -0,0 +1,29 @@
+## 拉取/合並請求描述：
+
+[
+這段方括號裏的內容是您**必須填寫並替換掉**的，否則PR不可能被合並。**方括號外面的內容不需要修改，但請仔細閱讀。**
+
+請在這裏填寫您的PR描述，可以包括以下之壹的內容：為什麽提交這份PR；解決的問題是什麽，妳的解決方案是什麽；
+
+並確認並列出已經在什麽情況或板卡上進行了測試。
+]
+
+以下的內容不應該在提交PR時的message修改，修改下述message，PR會被直接關閉。請在提交PR後，瀏覽器查看PR並對以下檢查項逐項check，沒問題後逐條在頁面上打鉤。
+
+### 當前拉取/合並請求的狀態：
+
+必須選擇壹項:
+
+- [ ] 本拉取/合並請求是壹個草稿版本
+- [ ] 本拉取/合並請求是壹個成熟版本
+
+### 代碼質量：
+
+我在這個拉取/合並請求中已經考慮了:
+
+- [ ] 已經仔細查看過代碼改動的對比
+- [ ] 代碼風格正確，包括縮進空格，命名及其他風格
+- [ ] 沒有垃圾代碼，代碼盡量精簡，不包含`#if 0`代碼，不包含已經被註釋了的代碼
+- [ ] 所有變更均有原因及合理的，並且不會影響到其他軟件組件代碼或
+- [ ] 對難懂代碼均提供對應的註釋
+- [ ] 本拉取/合並請求代碼是高質量的

.github/PULL_REQUEST_TEMPLATE.md

@@ -2,17 +2,17 @@
 
 [
 这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
-The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
+The content in this square bracket must be filled in and replaced, otherwise, PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
 
 请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
 Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
 
 并确认并列出已经在什么情况或板卡上进行了测试。
-And confirm in which case or board have been tested.
+And confirm in which case or board has been tested.
 ]
 
 以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
-The following content must not be changed in submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use web browser to visit PR, and check items one by one, and ticked them if no problem.
+The following content must not be changed in the submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use a web browser to visit PR, and check items one by one, and ticked them if no problem.
 
 ### 当前拉取/合并请求的状态 Intent for your PR
 
@@ -26,7 +26,7 @@ The following content must not be changed in submitted PR message. Otherwise, th
 我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
 
 - [ ] 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
-- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other style
+- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
 - [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
 - [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
 - [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky

.github/workflows/action.yml

@@ -0,0 +1,173 @@
+name: RT-Thread
+
+# Controls when the action will run. Triggers the workflow on push or pull request
+# events but only for the master branch
+on:
+  # Runs at 16:00 UTC (BeiJing 00:00) on the 1st of every month
+  schedule:
+    - cron:  '0 16 1 * *'
+  push:
+    branches:
+      - master
+    paths-ignore:
+      - documentation/**
+      - '**/README.md'
+      - '**/README_zh.md'
+  pull_request:
+    branches:
+      - master
+    paths-ignore:
+      - documentation/**
+      - '**/README.md'
+      - '**/README_zh.md'
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    name: ${{ matrix.legs.RTT_BSP }}
+    strategy:
+      fail-fast: false
+      matrix:
+       legs:
+         - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}         
+         - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "gkipc", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm3s9b9x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lm4f232", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tm4c123bsp", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "tm4c129x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc43xx/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc176x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc178x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc408x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc1114", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-lyc8", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f411-weact-MiniF4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f413-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f427-robomaster-a", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}  
+         - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} 
+         - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} 
+    steps:
+      - uses: actions/checkout@v2
+      - name: Set up Python
+        uses: actions/setup-python@master
+        with:
+          python-version: 3.8
+
+      - name: Install Tools
+        shell: bash
+        run: |
+          sudo apt-get update
+          sudo apt-get -qq install gcc-multilib libsdl-dev scons
+          echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
+          echo "RTT_CC=gcc" >> $GITHUB_ENV
+    
+      - name: Install Arm ToolChains
+        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
+        shell: bash
+        run: |
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 
+          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt  
+          /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
+          echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
+
+      - name: Install Mips ToolChains
+        if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
+        shell: bash
+        run: |
+          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 
+          sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt  
+          /opt/mips-2016.05/bin/mips-sde-elf-gcc --version
+          echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
+
+      - name: Bsp Scons Compile
+        if: ${{ success() }}
+        shell: bash
+        env:
+          RTT_BSP: ${{ matrix.legs.RTT_BSP }}
+          RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }}
+        run: |
+          scons -C bsp/$RTT_BSP

.travis.yml

@@ -1,127 +0,0 @@
-language: c
-
-notifications:
-  email: false
-
-before_script:
-# travis has changed to 64-bit and we require 32-bit compatibility libraries
-  - sudo apt-get update
-  # clang
-  - "sudo apt-get -qq install gcc-multilib libc6:i386 libgcc1:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev scons || true"
-  # - sudo apt-get -qq install gcc-arm-none-eabi
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 && sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
-  - export RTT_ROOT=`pwd`
-  - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
-
-env:
-#  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
-  - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
-#  - RTT_BSP='bf533' # no scons
-  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='es32f0334' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-#  - RTT_BSP='es32f0654' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='gd32e230k-start' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-atk-commander' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-fire-pro' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1052-nxp-evk' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc1114' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc824' RTT_TOOL_CHAIN='sourcery-arm' # not support gcc
-  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc54114-lite' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-#  - RTT_BSP='m16c62p' # m32c
-  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='microblaze' # no scons
-  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='mini4020' # no scons
-#  - RTT_BSP='mm32l07x' # not support gcc
-#  - RTT_BSP='nios_ii' # no scons
-  - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='pic32ethernet' # no scons
-  - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='simulator' # x86
-  - RTT_BSP='stm32/stm32f072-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-dofly-M3S' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f103-yf-ufun' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f427-robomaster-a' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f429-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f469-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32g431-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l475-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
-#  - RTT_BSP='upd70f3454' # iar
-#  - RTT_BSP='x86' # x86
-  - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
-
-stage: compile
-script:
-  - scons -C bsp/$RTT_BSP

ChangeLog.md

@@ -1,3 +1,357 @@
+# RT-Thread v4.0.3 Change Log
+
+Change log since v4.0.2
+
+## Kernel
+
+* Add `__RTTHREAD__` global macro definition
+* Add user heap options
+* Fix bug of rt_memheap_detach
+* Add rt_memory_info() for memheap.c
+* Add rt_object_get_length/rt_object_get_pointers APIs
+* Fix double release for thread
+* Fix thread control bug about `RT_THREAD_CTRL_CLOSE` command
+* Avoid deadlock (rt_hw_interrupt_disable and rt_enter_critical when enable smp)
+* Fix the issue of judging the ready_table of pcpu when multi-core rt_schedule_remove_thread
+* Fix the issue that the yield operation cannot release the cpu in time
+* Fix the iterator failure for softtimer list timeout check
+* Fix rt_timer_list_next_timeout multi-task safe
+* Add timer working status query function to software timer
+* Fix the software issue when the system timer thread is pending
+* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
+* Fix an issue with rt_timer_start being broken and destroying the timer list
+* Fix the bug that the linked list is still mounted when the single timer is not modified
+* Add function rt_tick_get_millisecond()
+* Fix the delay_until issue
+* Add mb mq value overflow-check code
+* Fix the rt_event_recv function, if the event met without blocking, assigning thread->event_set/event_info will goes well
+* Add the definition of the maximum value of ipc type
+* Remove the call of rt_system_object_init/rt_system_tick_init from the code.
+* Removes component configuration macro `RT_USING_FINSH` from the kernel
+* Use object_find to implement thread_find/device_find
+* The cleanup operation is executed before the current thread exits
+
+## Components
+
+* Fix assert in the sys_arch_mbox_fetch function when close socket
+* Add dhcp start or stop function to start or stop dhcp.
+* Change rt_data_queue_peak to rt_data_queue_peek.
+* Update elmfat to R0.14 patch 1.
+* Add SAL_INTERNET_CHECK configuration item to support turning on or off the network status check
+* Solve the issue that the do_pollfd function processing the underlying network device returns error -1
+* Fix the issue that when the network card device calls to close dhcp, the bottom layer no need to call the dhcp_stop function to close dhcp
+* Add the function of judging the network card up and down in the sal_accept function
+* Modify the spelling error of the macro definition, modify the printing error when printing the IMEI number
+* Fix the issue that the server closed the connection when web socket requests the data that comes back from the server, and the socket status is incorrectly judged at that point
+* Fix the issue of incorrect sal_getaddrinfo release when sal socket supports multiple network cards
+* Update AT socket
+  * Support alloc socket dynamically with at device
+  * Update AT_SW_VERSION and adjust at_socket_ops
+  * Adjust where the AT socket callback function
+  * Fix at_client, avoid creating the same client repeatedly and prevent working exceptions and memory leaks.
+  * Fix the bug that rx_notice out of sync when the data is received after last rt_device_read() is zero
+* [FinSH] rm command supports recursive deletion of folders
+* Add clear command for FINSH
+* [posix] Implement usleep function
+* Fix the issue of pthreads compilation error when using the new version of newlib; at the same time solve the problem of pthreads under 64-bit;
+* [dlmodule] Fix crash when dlmodule exits
+* Add priority & stack_size param parsing for dlmodule
+* libc adds getline/getdelim functions
+* Change the header file included in some libc files from <rtthread.h> to <rtconfig.h> to narrow the scope of inclusion to prevent recursive compilation
+* [jffs2] error check of rt_event_recv()
+* Add rt_data_queue_deinit and fix bug of dataqueue
+* Change log in device driver framework
+  * [pin] Add rt_pin_get to pin frame
+  * [PM] Update RT-Thread PM2.0 framework
+  * [audio] Fix compile warning, undefine var
+  * [serial] Fix the crash caused when the serial port receiving buffer is full and ULOG_USING_ISR_LOG is not turned on
+  * [wlan] Add raw frame send interface and Management frame filter interface
+  * [Sensor] Add vendor info and sensor types for cmd
+  * [Sensor] Support custom commands for rt_sensor_control
+  * [sensor] Support TOF sensor class 
+  * [SFUD] Update the 'sf bench' command.
+  * [spi] Fix "response+1" causing hard fault of unaligned access to SPI memory of STM32 HAL library
+  * [RTC] Optimize RTC alarm function, add alarm function for SOFT_RTC
+  * [hwtimer] When getting the timer count, prevent overflow update due to the interruption
+  * [dirver/i2c] i2c driver supports bus lock, STOP control
+  * [usb] Fix bug in device descriptor that MAC OS enumeration failed
+  * Fix the bug that USB cannot recognize composite device normally
+  * Fix USB host core bugs
+    * Limit >4 USB ports hubs
+    * Double free intf
+    * dname buffer size is too small
+    * Reset child pointer after detaching instance
+
+## BSP and CPU porting
+
+* Add license info and code cleanup for vexpress-a9 BSP
+* Add HDSC hc32f4a0 BSP support
+* Add support for Cypress PSoC6 series products
+* Fix the lpc55 issue under Linux/GCC
+* [qemu] Fix spelling mistakes of code in drv_pl041.c
+* [loongson] Update the SPI driver and UART driver on the Loongson 2K1000 platform
+* [allwinner_tina]Fix spi driver bug
+* [smartfusion2]Support Microsemi SmartFusion2 family FPGA
+* [imxrt] Add ethernet configuration for imxrt1064-nxp-evk
+* Add support for architecture sparc-v8 and soc bm3803.
+* [libc] libc adds getline/getdelim functions (posix.1-2008)
+* Add support for c28x mcu hardware fpu
+* [at32] Add link detecting thread for ethernet driver
+* Fix gcc assembly option in rtconfig.py for imxrt1064-nxp-evk
+* [IMXRT]Fix scons --dist in IMXRT BSP
+* [ls2kdev] Initial gpio driver without irq support on ls2kdev
+* Optimize BSP dist handle process
+* [nrfx] Add the qspi_flash of nordic pdk
+* [nrf5x] Add the BSP of nrf5x, which support UART, SPI, PWM, ADC, i2c drivers and rtc device driver
+* [nrfx] Add the on-chip flash for nrf5x
+* [RISC-V:K210]Add UART1~3 support for K210
+* [Nuclei] Add Nuclei RISC-V Processor support
+* Update BSP for mini2440
+* Add soc timer cntpct
+* LPC55S69: Add NS project and TFM support on LPC55S69
+* Make MicroPython runs on Raspi3-64 BSP
+* Add rt_hw_us_delay for W60x
+* [imxrt] [driver] Add usb device driver
+* Fix raspi4-32
+  * Add: dma driver,  bsc driver, dsi lcd/touch driver, waveshare spi lcd/touch driver, watchdog driver, hdmi driver, sdio driver, gpio interrupt
+  * Fix: eth driver, spi driver, uart driver
+* Add more BSP on BSP framework:
+  * At32/at32f403a-start
+  * At32/at32f407-start
+  * bluetrum/ab32vg1-ab-prougen
+  * bm3803
+  * cypress/psoc6-pioneerkit_modus
+  * essemi/es32f0271
+  * essemi/es32f369x
+  * essemi/es32f0654
+  * lpc55sxx/lpc55s69_nxp_evk_ns
+  * ls2kdev
+  * nrf5x
+  * nuclei/gd32vf103_rvstar
+  * nuclei/hbird_eval
+  * nuvoton/nk-980iot
+  * nuvoton/numaker-iot-m487
+  * nuvoton/numaker-pfm-m487
+  * raspi2
+  * raspi3-32
+  * raspi3-64
+  * raspi4-32
+  * raspi4-64
+  * smartfusion2
+  * thead-smart
+  * tm4c123 BSP
+  * zynqmp-r5-axu4ev
+
+* Add more STM32 BSP based on new STM32 BSP framework:
+  * STM32L431-BearPi
+  * stm32f103-blue-pill
+  * stm32f103-onenet-nbiot
+  * stm32f410-st-nucleo
+  * stm32f411-atk-nano
+  * stm32f413-st-nucleo
+  * stm32g070-st-nucleo
+  * stm32h747-st-discovery
+  * stm32l010-st-nucleo
+  * stm32l412-st-nucleo
+  * stm32l433-st-nucleo
+  * stm32l496-st-nucleo
+  * stm32mp157a-st-discovery
+  * stm32mp157a-st-ev1
+  * stm32wb55-st-nucleo
+* New STM32 BSP framework:
+  * Add dcmi, ov2640 and SD Card driver for stm32h743
+  * Fix bug that caused system crash by changing the run_mode in low power mode
+  * Fix issue when using gcc to compile the chips of stm G4 series, but chip doesn't work
+  * drv_flash_f7.c supports single bank mode
+  * Add stm32f103-atk-warshipv3 sram driver
+  * Update void HAL_Delay(__IO uint32_t Delay)
+  * Add PWM9_CONFIG default configuration and TIM3_CONFIG default configuration
+  * [stm32f103-atk-warshipv3] Add sdcard driver
+  * Add English readme for stm32
+  * Add dac and can driver for stm32l4 and stm32f4
+  * openamp driver and add rs485 driver for stm32mp157a
+  * Optimize the pin-index algorithm
+  * [stm32f769-disco] Support ethernet device
+  * Add C++ Support
+  * Fix the clock configuration issue of STM32 hardware timer
+  * Adjust the interrupt priority configuration of some peripherals of the STM32 series BSP
+  * Fix stm32 f1 series rtc bug
+  * Support SPI/ADC/TIME on-chip peripheral driver
+  * [stm32h743-atk-apollo]Support stm32h7 uart dma
+  * Add stm32h743-atk-apollo support for pcf8574 and uart2
+  * Support stm32h743-atk-apollo pcf8574 and uart2(485)
+  * Update bsp/stm32/stm32h743-st-nucleo
+  * Fix ADC channel Configuration bug for SMT32F0/L0/H7
+  * Add support for onboard AP6181
+  * Fix UART DMA TX
+  * Add pm support by cubemx tool for stm32l4
+  * Add stm32f407-atk-explorer sram driver
+  * Fix PWM timer init about pwm
+  * [stm32f103-atk-warshipv3]Add sdcard driver
+  * Add stm32f103-atk-warshipv3 sram driver
+
+## Tools
+
+* Add C++ support for eclipse target
+* Keep user's lib configuration while running --target=eclipse
+* Add Libraries when perform `scons --dist`
+* Update tools/building.py and add `tackanalysis` option 
+* Improve the logic of generating `rtconfig.h` files in scons with command `scons --menuconfig`
+* Fix makeimg.py wrong on linux
+* Add Studio IDE dist feature for stm32 BSP
+
+# RT-Thread v4.0.2 Change Log
+
+Change log since v4.0.1
+
+## Kernel
+
+* Split the component automatic initialization to component automatic initialization and main funciton;
+* Add spin lock API in SMP mode;
+* Fix RT_IDLE_HOOK spelling issue;
+* Add thread waiting for message queue when queue is full;
+* Fix the issue of delete mq in `rt_mq_create` in some abnormal case;
+* Remove the C++ keywords in the`rt_console_set_device`function;
+* Remove the `suspend_thread_count` member from memory_pool structure;
+* Fix the issue when block = NULL in rt_mp_free;
+* Fix the issue of incorrect scheduling task sequence caused by rt_thread_yeild in system scheduling;
+* Fix the issue that the interrupt is opened too late and cause the signal handling delayed;
+* When disable SMP, `cpu.c` will not be added into project by default;
+* Fix the issue that `rt_thread_exit` turned on the interrupt prematurely in the SMP mode, so other cores might delete this task, causing the issue in subsequent function stacks;
+* Fix the issue of critical protection when `rt_thread_delete` change the status of thread;
+
+## Components
+
+* Fix the issue of mPool size in C++ / Queue;
+* Add the error status return in C++ / Thread task join/wait function;
+* Fix compilation warning in DFS/ELM FatFS;
+* Add support for Linux NFS Server in DFS/NFS;
+* Fix mkfs issue in DFS/UFFS;
+* Add ftruncate, flock, getuid, umask APIs;
+* Fix the display issue of fd with offset in list_fd command;
+* Add `dfs_mount_device` API to mount a file system on a device which is already in mount_table;
+* Rename the C++ keywords in DFS/rename function;
+* Connnect dfs/poll, select with RT_USING_POSIX in Kconfig;
+* Optimize the part of the code of finsh to make it more simple;
+* When RT_USING_DEVICE is not used, finsh can use the `rt_hw_console_getchar()` function which is simple to implement and not using the device framework;
+* Increase the line length of the finsh shell to more than 256 characters;
+* utest can support clang compiler and C++ compiler;
+* Fix possible cross-boundary issues in ulog;
+* Fix compilation warning in `ulog/ulog_console_backend_output`;
+* Add support for file sending and receiving feature in YModem;
+* CRC16 can be calculated without the lookup talbe to reduce code size in YModem component;
+* Fix the issue that stack may be wrongly released during pthread/destory;
+* Fix the possible memory leaks issue which caused by pthread_create abnormal case;
+* The timer-related APIs under different compiler of libc are moved to the `libc\compilers\common` folder;
+* Remove redundant definitions in `dlib/sys/unistd.h` (which will cause compilation warnings);
+* Add `sys/errno.h` and`sys/signal.h` header files under dlib;
+* Freemodbus is no longer in the kernel, and split it as a standalone softwre package;
+* AT socket updated to v1.3.0:
+  - Add multi-client and multi-device function support in AT Socket, and improve the dirty data handling when AT device hardware module reboot;
+  - Support netdev network card feature, which can manage and control AT device network connection through the network card interface;
+* Improve AT Server function support in AT components, add AT Server data sending and receiving interfaces `at_server_send ()` and `at_server_recv ()`;
+* Fix the issue of `closesocket()` in SAL component when socket closing failure after `shutdown()`;
+* Improve `sal_bind ()` network card binding related function in SAL component;
+* Add IPV6 related options configuration and function support to SAL and netdev;
+* Improve ping command error handling and log display in the netdev;
+* Add hostname configuration options and functions in lwIP component;
+* Fix the assertion issue of `sys_arch_mbox_fetch()` in lwIP which may occur when a socket is closed;
+* Add network card uninstallation function and support for dhcpd service stop function to the lwip component;
+* Fix lwIP component compilation failure caused by closing FinSH component;
+* Fix the issue that the socket may not be closed during the DHCPD task in the lwIP DHCP server;
+* Add `dhcpd_stop()` interface;
+* Change log in device driver framework:
+  * Refactor audio driver framework;
+  * Fix the issue that the receiving length is 0 in CAN and the issue of returning wrong values;
+  * Add hardware encryption and decryption driver framework;
+  * Fix the flag handling issue of `rt_i2c_master_send/rt_i2c_master_recv`;
+  * Add input capture and pulse encoding driver framework;
+  * Fix the issue that partition lock is deleted when `rt_mmcsd_blk_remove`;
+  * Fix the issue that the enumerated capacity of the large-capacity card in MMC/SD exceeded the data range;
+  * When the SDIO device is initialized, the function's manufacturer and product can also use the information in CIS;
+  * Improve the interrupt mode handling in the sensor framework, and fix the issue that the memory is not released when registering the sensor;
+  * More information are provided in command line of sensor framework;
+  * Add the checking for Rx buffer size in the serial port framework, and provide a notification when RX buffer full;
+  * Remove the old Nor SPI Flash driver in SPI framework, and replace with SFUD component;
+  * Fix some judgements issue in the return value of SFUD;
+  * Fix the definition warning of `SFUD_FLASH_DEVICE_TABLE` in SFUD;
+  * Add support for W25Q64DW devices in SFUD;
+  * Fix FiFo creation failure handling when creating a pipe;
+  * Fix the issue of releasing RBB in advance in `rt_rbb_destroy()` function;
+  * Rename the new keyword using of C++ in `rt_rbb_blk_alloc` function;
+  * Unify the `struct rt_delayed_work` in workqueue to `struct rt_work`;
+  * Add touch driver framework;
+  * Add USB Audio class;
+  * Fix RNDIS plug-in/out issue in USB device stack;
+  * Add the interface callback function in USB device stack;
+  * Improve wlan framework, including command line functions, handling of AP name, password length, support for netdev, better configurability, etc.
+
+## BSP and CPU porting
+
+* Add Clang compiler support in ARM-related CPU porting;
+* Fix SCB_AIRCR definition issue in ARM Cortex-M0;
+* Add ARM Cortex-M33 porting;
+* Add DMB/DSB related operations for cache operations in ARM Cortex-A porting;
+* Add FPU support in ARM Cortex-A porting;
+* Re-organize MIPS port. And XBurst related porting are moved to X1000 BSP;
+* The porting of loongson 1B and 1C CPU are combined into one GS232 porting;
+* Add support for RISC-V Hummingbird processor porting;
+* The context switch exit operation of risc-v is forced back to machine mode;
+* Fix the issue of switch interruption during TI C28x DSP porting; 
+* Add _ffs like implementation in the TI C28x DSP porting;
+* Unify the .data .bss section to 8bytes alignment in GCC tool chain;
+* The es32f0334 BSP is moved to `bsp/essemi/es32f0334`;
+* Add `bsp/essemi/es8p508x` BSP, including UART and GPIO drivers;
+* Add GD32VF103V-EVAL (RISC-V MCU) BSP, including UART driver;
+* Rerange NXP i.MXRT BSP and add related BSP documents;
+* Add i.MXRT1052 ATK Commander, Fire Pro BSP and i.MXRT1064 EVK BSP to the new i.MXRT BSP;
+* Add BSP for NXP LPC55S6X series, and increase support for NXP official development board LPC55S69-EVK;
+* Fix I2C operation (master_xfer) in LPC54114-lite BSP;
+* Add Audio driver in LPC54114-lite BSP;
+* Update Loongson 1B BSP and use automatic component initialization in default;
+* Add Kconfig configuration for Loongson 1B BSP;
+* Add QEMU/mipssim BSP for simulate RT-Thread/MIPS without MIPS hardware;
+* Refactor qemu-vexpress-a9's Audio driver and fix the issue of OS Tick accuracy;
+* Add LPUART driver to RV32M1 VEGA BSP;
+* Remove old STM32 BSP: stm32f4xx-HAL, stm32f10x, stm32f10x-HAL, stm32f429-apollo, stm32f429-disco, stm32h743-nucleo;
+* Fix the issue of `rt_hw_sci_init()` for opening the global interrupt in tms320f28379d BSP;
+* Add support of soft I2C and hardware encryption module to WinnerMicro W60x BSP（AES/DES/3DES/RC/SHA1/MD3/CRC);
+* Add oneshot WiFi configuration support in WinnerMicro W60x BSP;
+* Add more STM32 BSP based on new STM32 BSP framework:
+  * stm32f072-st-nucleo
+  * stm32f103-gizwits-gokitv21
+  * stm32f103-yf-ufun
+  * stm32f412-st-nucleo
+  * stm32f427-robomaster-a
+  * stm32f429-st-disco
+  * stm32f769-st-disco
+  * stm32g431-st-nucleo
+  * stm32h743-st-nucleo
+  * stm32h750-armfly-h7-tool
+  * stm32l4r5-st-nucleo
+  * stm32l452-st-nucleo
+* For the new STM32 BSP framework:
+  * Add DMAMUX support to stm32l4+;
+  * Update F7 HAL library SConscript;
+  * Open the SWD port configuration on cubemx in stm32f103-atk-warshipv3 BSP;
+  * Add support for SD card in stm32f427-robomaster-a BSP;
+  * Add USBFS driver to stm32f412-nucleo BSP;
+  * Remove use of device user data on uart driver;
+  * Add QSPI FLASH support in stm32h743-atk-apollo BSP;
+  * Optimized Ethernet driver;
+  * Add hardware encryption and decryption driver;
+  * Add MIPI LCD driver;
+  * Add pulse encoding driver;
+  * Optimize hardware timer driver;
+  * Add support for UART 7/8 in serial driver;
+  * Optimize WDT driver; 
+
+## Tools
+
+* Optimize scons script for eclipse in order to generate eclipse project better;
+* Improve rtconfig.h generator, PATH type configuration can be generated correctly;
+* Fix gcc path detection issue when using the default cross toolchain of the Linux distribution;
+
 # RT-Thread v4.0.1 Change Log
 
 ## Kernel
@@ -674,7 +1028,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 *  修正USB host代码的编译错误；
 *  修正sensor框架回调函数的问题；
 *  修正pin设备注册时的设备名称问题；
- 
+
 而v2.1.0 alpha这个技术预览版则沿着最初设定的roadmap技术路线进行，这其中主要包括：
 
 *  lwip更深度的集成：把它集成到RT-Thread的文件系统接口中，这样Linux/Unix下的一些socket网络应用能够更顺利的移植到RT-Thread上，也为以后可以应用到更多地方的select接口铺路。
@@ -687,7 +1041,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 以下是自v2.0.0 RC版本以来的详细更改记录。后续我还会给出v2.0.0版本自v1.2.x版本的主要不同、看点，以及给出下一个版本的roadmap规划。
 
 ## 内核
- 
+
 *  console以RT_DEVICE_FLAG_STREAM参数打开字符设备；
 *  在rt_memheap_free中加入更多的断言检查；
 
@@ -707,7 +1061,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 *  添加VBUS组件用于Linux与RT-Thread系统之间，RT-Thread与RT-Thread系统之间通信（睿赛德服务公司捐赠）；
 *  增加lwIP/NAT组件，可以做多个网口间的地址转换（Hicard）；
 *  增加lwIP/DHCP服务端，用于向客户端分配IP地址（睿赛德服务公司提供）；
- 
+
 ## BSP
 
 *  修正LPC4357串口驱动初始化时过早打开中断的问题（nongxiaoming）；
@@ -738,487 +1092,4 @@ RT-Thread做为一个开源组织参与的CSDN开源夏令营结出了丰硕的
 由wzyy2参与的GDB stub实现，也完美的支持BeagleBoneBlack开发板和STM32F4平台；
 CSDN开源夏令营其他的成果，例如bluedroid移植也有了初步的成果，希望能够在后续的版本（可能会是2.1.0系列版本？）包含进来。CSDN开源夏令营是一次非常棒的活动，能够让学生提前进入实战，了解软件开发的初步知识。对开源社区来说，也是一次非常有益的社区互动活动。希望明年这个活动可以继续，关注RT-Thread、嵌入式开发的同学可以关注明年的动向。
 
-当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相应的做出了积极的响应，所以这个版本开始加入sensor的应用框架（APP/算法 <--> sensor framework <--> RT-Thread device driver <--> 硬件外设）。希望在小型化的RT-Thread操作系统基础上融合智能化相关的技术，让RT-Thread成为这方面可选的OS系统之一。RT-Thread操作系统的sensor框架也尝试新的实现方式，即采用C++的方式来实现（当然也会考虑C方面的兼容，无疑C++的面向对象特性会更好，所以最终选择了C++），在这个基础上也可能融合其他的一些生态技术，例如ARM mbed平台上的一些社区组件技术。所以这个发布版本中既包括sensor框架，也包括了C++底层的一些基础支撑。
-
-这个版本是RT-Thread 2.0.0系列正式版本的候选版本，正式版本预计会在年底正式发布，距离正式版本还会加入更完善的一些支撑（例如各种传感器驱动）。也计划2014年11月22日，在上海浦东举行RT-Thread嵌入式系统沙龙活动，欢迎大家关注并参与进行RT-Thread方方面面的技术交流。
-
-以下是这个版本的更改记录:
-
-## 内核
-
-* 修正当采用高级别优化编译时，idle任务中查询是否有僵尸线程的潜在bug；
-
-* 修正memory pool中的竞争问题；
-
-* 在console中打开设备时，加入流标志进行打开；
-
-## 组件
-
-* 加入C++基础支撑组件。C++组件依赖于RT_USING_LIBC库，当使用GCC编译器时请注意查看其中的说明文档并更改ld script；
-* 修正DFS中NFS打开目录的bug；
-* 更改DFS ROMFS默认romfs_root为弱化符号；
-* 添加DFS中dfs_file_lseek接口中关于fs的检查；
-* 移除I2C core中无用的core lock锁；
-* 添加sensor framework（采用C++的方式支持各种sensor）；
-* 修正serial框架中DMA发送的bug（heyuanjie87）；
-* 移除SPI框架中不必要的device初始化代码；
-* 完善SPI Wi-Fi网卡RW009驱动并提供RSSI相关的命令；
-* 修正MSH中未定义DFS_USING_WORKDIR时更改当前目录的bug；
-* 修正MSH中未定义RT_LWIP_TCP时依然定义了netstat命令的bug；
-* 修正MSH中未定义RT_USING_HEAP时依然定义了free命令的bug；
-* 修正finsh中FINSH_USING_HISTORY相关的裁剪；
-* 加入gdb stub组件，当前支持ARM Cortex-A8和Cortex-M3/4（wzyy2）；
-* 统一不同编译器下使用LIBC的宏为RT_USING_LIBC，原有的宏定义RT_USING_NEWLIB/RT_USING_ARM_LIBC需要从rtconfig.h中移除，并替换成RT_USING_LIBC；
-* 加入最新的lwIP分支：lwip-head，以提供IPv4/v6双栈的功能（hduffddybz）；
-* YMode中打开串口设备时，添加open flag（armink）；
-
-## bsp
-
-* 加入北京京微雅格的M7（华山）低功耗FPGA的ARM Cortex-M3移植（aozima）；
-* 加入北京京微雅格的M7 EMAC以太网驱动（aozima）；
-* AT91SAM9260分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
-* BeagleBoneBlack分支中加入gdb stub支持（wzyy2）；
-* LPC176x分支中加入C++支持；
-* LPC176x分支中修正SD卡驱动返回卡信息的bug；
-* 修正LPC408x分支中GCC编译时的问题；
-* LPC408x分支中加入C++支持；
-* 龙芯1B分支中加入UART3驱动；
-* 加入飞索半导体的MB9BF568 FM4分支移植（yangfasheng）；
-* mini2440分支中更改RT_USING_NEWLIB为 RT_USING_LIBC；
-* stm32f0x分支中移除不同编译器下的LIBC定义，统一更改为RT_USING_LIBC；
-* stm32f0x分支中加入串口接收溢出中断处理（armink）；
-* stm32f40x分支中加入gdb stub支持并添加UART6驱动（wzzy2）；
-* zynq7000分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
-* 加入ARM Cortex-M4芯片指令级的ffs实现；
-* 修正MB0BF618S分支中缺少timer初始化的bug（mike mao）；
-
-## 工具
-
-* 移除Python 2.6中未支持的语法（xfguo）；
-* 移除Windows平台中的startupinfo信息（对Python版本兼容性更好）；
-* 修正CPPPATH被打乱的bug；
-
-# RT-Thread 2.0.0 Beta更改说明
-
-发布时间:2014/8/1
-
-v2.0.0这个版本系列是RT-Thread当前的开发分支，如果要上新项目，建议使用这个版本来进行，预计这个版本的正式版会在年底发布。欢迎对这个版本进行测试、并反馈问题，能够早日进入到稳定版。
-
-v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持：如Arda贡献的TM4C129x移植，Romeo贡献的frdm-k64f移植，xiaonong的LPC4300移植等，以及睿赛德服务公司捐赠的Zynq7000移植，MB9BF618S移植，以及SPI WiFi网卡的驱动代码等。
-
-更改记录
-
-## 内核
-
-* 移除rt_device_init_all()函数：在系统启动时不需要再调用这个函数来初始化驱动，而是由上层应用执行rt_device_open时自动进行设备初始化；
-* 修正设备对象引用计数在打开设备失败依然递增的问题；
-* 增加WEAK宏用于定义/声明弱符号；
-* 在执行静态内存块分配前，重置线程的errno；
-* 修正timer未打开调试选项时，无用的静态函数定义（导致编译警告）；
-* 启动timer前，对timer进行强制移除；
-* 在执行soft timer超时函数时，打开调度器锁；
-* 新增块设备的自动刷新参数，RT_DEVICE_CTRL_BLK_AUTOREFRESH；
- 
-## 工具
-
-* 修正scons命令编译时，选择keil mdk (armcc)编译器时，命令行太长编译失败的问题；
-
-## 移植
-
-* 移除rt_device_init_all()相关的调用；
-* 根据串口框架调整相关的驱动代码；
-* 新增frdm-k64f移植（FreeScale K64芯片）；
-* 移除K60Fxxxx移植；
-* 新增LPC43xx移植（NXP LPC4357芯片）；
-* 移除LPC176x中的组件初始化配置；
-* 修正龙芯1B移植（ls1bdev）中链接脚本关于组件初始化部分的配置；
-* 修正STM32F40x中UART3的配置；
-* 修正STM32F40x中GNU GCC连接脚本中ROM/RAM大小的配置；
-* 移除STM32F107中的组件初始化配置；
-* 增强STM32F107 EMAC驱动性能，同时加入自动查找PHY芯片地址功能；
-* 重写xplorer4330（NXP LPC4330芯片）移植（xiaonong完成）；
-* 新增Zynq7000 ARM Dual Cortex-A9移植；
-* 新增MB9BF618S移植；
-* 新增tm4c129x移植，并加入相应的EMAC以太网驱动；
-
-## 组件
-
-* DFS: 新增根据设备对象获得其上装载文件系统路径的函数：dfs_filesystem_get_mounted_path(struct rt_device* device);
-* DFS: 修正readdir在GNU GCC下的编译警告；
-* DeviceDrivers：新增workqueue实现；
-* DeviceDrivers: 修正USB Device栈中的一些拼写错误；
-* DeviceDrivers: 重写serial框架，能够让串口设备驱动同时支持三种模式：poll、interrupt、DMA。模式选择需要在执行rt_device_open时，由open flags指定；
-* DeviceDrivers: 加入更多的SPI设备驱动，例如RW009的SPI WiFi网口驱动（2.4G 802.11 b/g/n，WEP/WPA/WPA2，SoftAP/Station），SPI NorFlash块设备驱动，ENC28J60以太网网卡驱动；
-* Finsh: list_device()命令中增加refcount的信息；
-* Finsh: 修正'0'零常量无法识别的错误；
-* Finsh: mv命令，实现把一个文件移动到一个目录中；
-* Finsh: ifconfig命令支持对一个网络接口的基本配置；
-* Finsh: 新增netstat命令，用于显示当前系统中TCP连接的状态；
-* Finsh: 修正当命令行太长导致的缓冲区移除的问题；
-* libc: 修正arm libc中未使用DFS时的编译警告；
-* libc: 修正newlib中使用DFS时的系统调用编译警告（GNU GCC下）；
-* lwIP 1.4.1: 默认打开LWIP_SO_SNDTIMEO以支持连接发送超时；
-* lwIP 1.4.1: 修正MEMP_NUM_TCP_SEG定义错误的问题；
-* lwIP 1.4.1: 加入RT_LWIP_REASSEMBLY_FRAG选项定义以支持IP分组及合并；
-* lwIP 1.4.1: ethnet网络接口支持定义LWIP_NO_TX_THREAD/LWIP_NO_RX_THREAD，以关闭etx/erx线程；
-* lwIP 1.4.1: 用户可以重新定义RT_LWIP_ETH_MTU，以修改网络中的MTU值；
-* lwIP 1.4.1: 修正LWIP_NETIF_LINK_CALLBACK条件编译的问题；
-* lwIP 1.4.1: 完善移植相关的注释；
-* log trace: 增加log_session_lvl接口；
-* log trace: log trace中的session引用更改成常量形式；
-* ymodem: 增强数据接收的稳定性；
-
-# RT-Thread 2.0.0 Alpha更改说明
-
-发布时间:2014/4/8
-	
-RT-Thread 2.0.0分支的第一个技术预览版本，仅用于展示2.0.0发展分支的演化动向(按照roadmap，2.0.0这个分支会有一部分RT-Thread和Linux互补性的技术，为Linux增加更好的实时性，为RT-Thread增加更多的功能性，这份技术预览版正是朝着这个目标而努力)，欢迎反馈建议和问题。
-
-## 组件
-
-* msh： bugfix 和功能性增强。新的 msh 在调用外部模块方面更加方便。
-* DFS： nfs 的 bugfix 和内置命令的增强。ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题。
-* JS：新添了轻量级Javascript引擎，可以在RT-Thread中直接运行javascript脚本。
-* VMM：可以在qemu中运行的 Virtual Machine Module 组件。暂时只支持 realview-pb-a8 的 bsp。
-* CMSIS：版本更新至 3.20
-* drivers：USB 协议栈的重构。新的框架中编写驱动变得更加容易了。
-
-## BSP
-
-* beaglebone：串口驱动更新
-* realview-a8：添加了 VMM 组件
-
-## 工具
-
-* 固件加入scons --target=ua -s，用于准备用户应用环境；
-
-[发布后记]
-
-RT-Thread 2.0.0. Alpha版本相比于RT-Thread 1.2.1，新的特性主要有两部分：
-- RT-Thread + Linux双系统，这部分以RealView-A8处理器(ARM Cortex-A8单核)为蓝本，给出一个简单的双系统并行运行的demo；在没有硬件的环境下，可以使用QEMU软件虚拟方式的执行。这个链接中包含一个编译好的Linux及RT-Thread二进制包，可以直接下载进行体验。
-
-目录中有 Linux 的内核镜像 zImage，ramdisk rootfs.cpio.gz。可以用
-qemu-system-arm -M realview-pb-a8 -kernel zImage -initrd rootfs.cpio.gz -serial vc -serial vc
-来启动。启动之后 Linux 的控制台在第一个串口上(Atl + Ctrl + 3)，可以直接无密码以 root 用户登录。登录之后加载内核模块：
-insmod rtvmm.ko
-来启动 RT-Thread。RT-Thread 启动之后控制台在第二个串口上(Atl + Ctrl + 4)。第一个串口Linux shell依然可以使用，第二个串口则是RT-Thread的shell。
-- JavaScript解析器，这个是由牛头哥移植的，可以在一个非常小资料的MCU上以JavaScript脚本方式进行编程、开发。根据这种方式，也提供了RN001JS的以太网硬件模块：以JavaScript脚本语言作为二次开发，提供在线web(即WebIDE)进行编程并运行JavaScript程序。JavaScript作为一门轻量级、解释型的语言，更容易上手，配合WebIDE、及提供的一些example可以使得开发变得非常的轻松，也包括一些传感器的JavaScript例子，让做网页的人也可以玩硬件了！
-
-# RT-Thread 1.2.1更改说明
-
-发布时间: 2014/4/8
-	
-在原有的1.2.0版本的bug修正版本，也是1.2.0系列的第一个修正版本，原则上不添加任何的新功能，我们尽量会按照每个季度一个修订版本的方式推进。大家在使用的过程中有什么问题还请反馈给我们，这些问题很可能会在下个版本中修正！
-
-以下是更改记录：
-
-## 内核
-
-* 用户应用，增加用户应用命令行参数支持；
-* 在挂起一个任务时，把相应的定时器也关闭；
-
-## BSP
-
-* BeagleBone，加入更多串口驱动支持；
-* 移除BSP中rt_device_init_all函数调用，改成打开设备时自动进行初始化；
-* LPC176x，移除components初始化管理器；
-* LPC4088，修正LED驱动的问题；
-* STM32F107，移除components初始化管理器；
-
-## 组件
-
-* 文件系统，ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题；
-* 文件系统，NFS网络文件系统修正相关的一些编译警告信息；
-* 文件系统，copy命令加入文件夹方式复制功能；
-* 文件系统，RAMFS，加入到components初始化管理器中；
-* 文件系统，ROMFS，用于转换文件的工具mkromfs.py，增加Linux主机的支持；
-* CMSIS更新到3.2.0版本；
-* 串口驱动框架加入serial->ops->control的调用；
-* 命令行系统，优化msh，支持用户应用的命令行参数；
-* 命令行系统，当使用msh时，默认使用msh >的命令行提示符；
-* TCP/IP协议栈，导出更多的lwIP接口给用户应用；
-* POSIX thread，修正了同时使用lwIP组件时的编译警告；
-* 第三方组件，加入TJPGD的移植，加入libpng的移植；
-
-## 工具
-
-* 固件加入scons --target=ua -s，用于准备用户应用环境；
-
-[发布后记]
-* RT-Thread携带了众多的BSP，不一定能够一一保证每个分支上把RT-Thread上相应的功能使用起来。所以针对这种情况，我们有一款评估用的硬件开发板：RealBoard 4088，在上面力求把一些相关例程都添加上，这样在一个基本的BSP基础上，可以对照着把其他的组件、功能添加进去；
-* RealBoard 4088使用的RT-Thread版本主要以RT-Thread 1.2.1版本为主。
-
-# RT-Thread 1.2.0正式版本更改说明
-
-发布时间: 2014/1/6 
-
-实现roadmap中提到的大部分内容
-	
-1，文档方面已完成《RT-Thread编程手册》，同时还有论坛上jiezhi童鞋的《一起来学RT-Thread系列连载教程》
-2，BSP分支方面新增cortext-A8(beaglebone)，cortext-R4(rm48x50)，UNITY-2(SEP6200),lpc408x的移植
-3，组件方面：
-- 加入msh(类似linux shell的风格)，能够直接执行应用程序
-- 新增freemodbus 1.6.0的移植
-- 新增开源的嵌入式关系数据库SQLite 3.8.1的移植
-- 新增Ymodem协议
-- 默认使用lwIP 1.4.1
-
-下面是自RT-Thread 1.2.0 RC版本发布以来具体的变更履历：
-
-## 内核
-
-* timer.c - 使用跳跃表(skip list)实现系统定时器链表，并在bsp中的startup.c中重新加入定时器初始化函数rt_system_timer_init()
-* rtdebug.h - 新增宏定义RT_DEBUG_IN_THREAD_CONTEXT
-* idle.c - 在函数rt_thread_idle_excute()中一次清除所有的死线程
-* scheduler.c - 新增API rt_critical_level()返回调度器上锁次数
-
-## 移植
-
-* cortex-m0 - 修正 cortex-m0 GCC移植中hardfault的问题点
-* cortex-r4 - 在startup后释放IRQ堆栈空间
-* cortex-r4 - 按字节长度分配堆栈空间
-
-## BSP分支
-
-* 新增lpc408x移植
-* bsp/stm32f0x - 增加USART1，USART2驱动，支持finsh，支持组件初始化
-* bsp/simulator - 当RTGUI配置无效时打印错误信息
-* bsp/simulator - 默认情况下关闭RTGUI选项
-* bsp/simulator - 增加createdef.py文件来生成VS的def文件
-* bsp/simulator - 当使用VC++编译时去除_TIME_T_DEFINED的定义
-* bsp/xplorer4330 - 重命名文件Retarget.c为retarget.c,否则linux系统中编译会报错
-* bsp/xplorer4330 - 修正GCC编译链接时关于ENTRY的警告
-* bsp/rm48x50 - 新增GCC的移植
-* bsp/K60Fxxxx - 修正一个编译错误
-
-## 组件
-
-* dfs - 正确处理mkfs未实现的情况
-* dfs - 使用指针代替index变量
-* dfs - 在函数dfs_filesystem_lookup()将含义模糊的指针变量名称empty重命名为fs
-* dfs - 修正dfs_unmount问题点
-* dfs - 在设备打开错误时令挂载失败
-* dfs/elmfat - 令elmfatfs每次都检查扇区大小
-* net - 新增freemodbus 1.6.0的移植
-* finsh - 新增FINSH_USING_MSH_ONLY选项
-* finsh - 只有当shell设备为空时调用rt_console_get_device()
-* finsh - 修正FINSH_USING_SYMTAB未定义的错误
-* finsh - 重构control按键的处理
-* msh - 增加文件和路径名称自动补全的功能
-* msh - msh内增加执行module的功能
-* msh - msh内增加更多的命令
-* libc - 修正 _sys_read()/_sys_write()问题点
-* external - 增加开源的嵌入式关系数据库SQLite 3.8.1的移植
-* pthreads - 避免ESHUTDOWN重复定义
-* mtd_nand - 在MTD nand中增加更多的调试措施
-* mtd_nand - 修正操作MTD nand时起始块错误的问题
-* lwip-1.4.1 - 在lwIP内加入更多的RT-Thread选项设置
-* log_trace - 修正函数memmove()参数使用错误的问题
-* drivers/pipe - 增加一个control命令来获得pipe剩余的空间
-* drivers/serial - 如果读写长度为0，则立即返回
-
-## 例程
-
-* examples - 用rt_sem_control()中的RT_IPC_CMD_RESET命令rt_sem_trytake()来清除信号量
-* examples - 始终打印输出测试结果
-* examples - 在所有的测试结束后打印输出简报
-* examples - 在TC线程中清除变量_tc_stat的TC_STAT_RUNNING状态
-* examples - 重新实现loop功能，并新增finsh命令tc_loop
-* examples - 在tc_stop中增加延时，由原来的延时RT_TICK_PER_SECOND/2调整为10 * RT_TICK_PER_SECOND
-* examples - 在SConscript中判断TC如果被使能，在CPPPATH中增加TC路径
-* examples - 新增一个in-mem-log的例子
-* semaphore_priority.c - 在cleanup时释放信号量
-* heap_realloc.c - 检查调用realloc(ptr, 0)是否成功
-* thread_delete.c - tc线程的延时应该比tid2的延时长，保证其测试过程中正常运行
-* thread_delay.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-* semaphore_static.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-* semaphore_dynamic.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-
-其他：
-* 更新README.md
-	
-# RT-Thread 1.2.0RC更改说明
-
-发布时间: 2013/10/10/ 10:19
-	 
-主要说明: 该版本新增ARM Cortex-A8的支持(BeagleBone)，新增UNITY-2内核的支持(SEP6200)，新增Ymodem协议。
-
-变更履历
-========
-
-[内核]
-
-* 修正rtdef.h中的拼写错误(_MSC_VER_ -> _MSC_VER)
-* 修正scheduler.c中的调试打印输出错误
-* ipc - 在函数rt_event_recv()中增加对参数option有效性的检查
-* device - 增加统计设备引用次数的变量ref_count
-* memheap - 修正内存块分割问题点
-* memheap - 优化函数rt_memheap_realloc()
-* kservice - 函数声明使用rt_vsnprintf代替vsnprintf
-
-
-[组件]
-
-* dfs - 修正dfs_file.c中一处变量参数类型错误的问题
-* dfs - 增加mount table
-* dfs - 在building脚本中加入ramfs的支持
-* dfs - 修正ramfs中O_APPEND write的问题
-* dfs/elm - 在mkfs中加入device_open/close
-* dfs/jffs2 - 修正jffs2_opn/opendir中的f_flag初始化问题
-* dfs/jffs2 - 修正jffs2卸载问题
-* pthread - 修正一处编译警告
-* drivers/pipe - 增加rt_pipe_init/rt_pipe_detach
-* drivers/pipe - 增加非阻塞读写和强制写模式
-* drivers/pipe - 当恢复读的时候调用函数rx_indicate()
-* drivers/pipe - 增加一个设备类型(pipe类型)
-* drivers/portal - 实现portal设备类型
-* drivers/ringbuffer - 修改一些模糊不清的函数名称
-* drivers/ringbuffer - 新增put_force和putchar_force接口函数
-* finsh - 当set_device时增加设备检查
-* finsh - 在rx_ind中增加对shell设备的自动设置
-* finsh - 增加pipe和portal设备的描述
-* finsh - 在变量定义时使用别名
-* finsh - 当关闭设备时注销rx_indicate
-* finsh - 修正命令行太长的问题
-* finsh/msh - 只有当DFS_USING_WORKDIR使能时才声明cd/pwd
-* init - 为新的组件初始化机制更新连接脚本
-* init - 增加组件初始化调试代码
-* logtrace - 整理代码，去除编译警告
-* logtrace - 增加LOG_TRACE_VERBOSE
-* logtrace - 调整log values
-* logtrace - 只有当finsh使能的时候才声明cmd
-* libc/minilibc - 在sys/time.h中增加gettimeofday的声明
-* utilities - 新增ymodem
-
-工具:
-
-* building.py - 增加clang静态缝隙器的支持
-* building.py - 为Keil MDK增加buildlib功能
-* building.py - 在clang-analyze中执行'clang -Wall -fsyntas-only'
-* clang-analyze.py - 增加一个定制工具实现clang静态分析
-
-分支:
-
-* 新增BeagleBone的移植
-* 新增SEP6200的移植
-* 新增K60Fxxxx的移植
-* 修正Linux中的编译错误(lm4f232, stm32f40x, xplorer4330)
-* cortex-m3 - 加强hard fault的异常处理函数
-* at91sam9260 - 更新串口驱动，使用组件中的通用串口驱动
-* at91sam9260 - 更新工程目录结构
-* at91sam9260 - 修正编译错误
-* at91sam9260 - 内嵌GPLv2许可
-* stm32f10x - 删除无用的文件
-* stm32f10x - 更新工程目录结构
-* stm32f10x - 更新工程文件
-* stm32f10x - 为使用新的组件初始化更新连接脚本
-* stm32f10x - 为使用新的组件初始化更新SD card驱动
-* stm32f10x - 为使用新的组件初始化更新DM9000驱动
-* stm32f10x - 更新串口驱动，使用组件中的通用串口驱动
-* stm32f10x - 修正rtgui初始化问题
-* simulator - 为使用新的组件初始化更新代码，以便支持mingw
-* simulator - 支持Linux系统
-* simulator - 修正Linux系统中的SDL初始化问题
-* simulator - 在rt_components_init之后初始化SDL
-* simulator - 将对SDL设置的内容移入drivers/SConstruct
-* simulator - 在env中获得CORSS_TOOL和EXEC_PATH的值
-* simulator - 支持clang-analyze
-* simulator - 增加tap netif driver
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-
-版本: RT-Thread 1.2.0 Beta 版本
-
-发布时间: 2013/6/30
-		
-进过开发人员三个月的努力，RT-Thread 1.2.0 Beta 版本如期发布。
-该版本默认采用lwIP 1.4.1协议栈，USB device stack也进一步完善。加入 log_trace 子系统，加入组件初始化升级版本，加入 ARM Cortex-R 的移植。
-
-主要变化：
-
-* 1，新增组件初始化功能
-- 详情请看论坛帖子[新功能] 组件初始化
-* 2，支持ARM Cortex-R系列处理器
-- Grissiom 完成 ARM Cortex-R 的移植，目前BSP中已有TI RM48x50分支（仅支持TI CCS开发环境）
-* 3，文件系统中新增 RAMFS
-* 4，加入 log_trace 子系统
-* 5，优化Cortex-M4线程上下文切换，使用了浮点运算的线程才保存及恢复FPU寄存器
-- 详情请看论坛帖子[优化]cortex-m4f线程切换，优化FPU寄存器
-* 6，新增API rt_memheap_realloc()
-* 7，重新实现ringbuffer，采用镜像的方法区分“满”和“空”，同时支持任意大小的buffer
-* 8，内核中加入RT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOC宏。
-如果用户未定义这些宏，将默认指向rt_malloc/rt_free/rt_realloc。
-同时内核仅局限于使用这些宏来使用动态内存
-* 9，在 building.py 中新增生成 cscope database 的选项
-* 10，USB组件新增reset函数，支持热插拔
-* 11，scons编译系统支持CCS开发环境
-* 12，USB组件新增状态信息（USB_STATE_NOTATTACHED，USB_STATE_ATTACHED，USB_STATE_POWERED...）
-
-修复问题点：
-
-* 1，USB组件HOST可以挂起endpoints
-* 2，simulator分支，修复 serial_write 问题
-* 3，udisk可以被弹出
-* 4，iar.py中修复绝对路径的问题
-* 5，dfs_fs.h内增加dfs_mkfs()函数的申明
-* 6，生成MDK工程文件的时候加入library文件
-* 7，当PC不再接受数据的时候，重置VCOM相应的状态
-* 8，USB组件：返回正确的LangID字符串长度给HOST
-* 9，Cortex-M0，Cortex-M3，Cortex-M4上下文切换时，回收系统初始化时用到的栈空间
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-
-
-版本: RT-Thread 1.2.0 Alpha版本
-
-发布时间: 2013/4/10
-	
-遵循2013年RT-Thread roadmap，RT-Thread 1.2.0 Alpha版本发布，Alpha意味着此版本为技术预览版，仅用于展示RT-Thread 1.2.0未来的发展方向，并不适合于开发正式产品。RT-Thread 1.2.0版本是1.1.x系列的下一个分支，这个分支主要体现的是RT-Thread 1.x系列的文档情况。当然也有一些功能、代码方面的增强。
-
-伴随着新版本的到来，RT-Thread有几个重大的转变：
-1，代码托管从google code(SVN)迁移到github(GIT)
-2，RT-Thread与RTGUI区分开来，并成为两个独立的开发分支
-3，重视文档，将文档建设作为1.2.0版本的首要任务来抓
-
-内核主要变化：
-1，加入__rt_ffs函数用于实现32位整数中获取第一个置1的位；同时调度器中位图相关算法直接使用__rt_ffs函数；CPU移植时，可定义RT_USING_CPU_FFS，使用芯片指令完成。
-
-2，新的中断注册机制
-weety加入interrupt description功能，用于为interrupt增加更多的信息，同时中断服务例程也可以携带用户自定义的参数类型。
-* 这部分对ARM7、ARM9、MIPS等影响很大，需要对CPU移植做相应的一些修改。
-* 这部分对ARM Cortex-M系列芯片没有影响。
-
-3，调整定时器插入位置，为相同超时定时的后面。
-
-组件主要变化：
-1，添加lwIP 1.4.1。
-2，在finsh shell中加入module shell功能。finsh shell本身是一个C语言表达式的shell命令行，而module shell更类似于一个传统的命令行，由命令，参数等方式构成。
-
-分支主要变化：
-1，完善simulator分支，支持RTGUI，支持应用模块。
-2，完善at91sam9260分支的移植及驱动更新。
-
-编译系统主要变化：
-1，开启省略编译时长命令特性，如果需要查看编译时命令行，可以使用scons --verbose查看。
-2，加入生成CodeBlocks工程特性。
-3，修正当系统安装使用Keil MDK 4.6+版本的问题。
-
-github主要提交履历:
-5646189b29: elm fatfs支持mkfs，并且无需提前执行dfs_mount; mount/umount/mkfs操作也不会引起reset
-22786f8817: 允许用户自定义PID和VID
-0001344105: 更明确的定时器运行机制，如果两个定时器在同一个时刻发生超时，那么先开始的定时器先处理
-5d68ef8ec1: 修正使用64位GCC时编译finsh过程中发生错误的问题
-a4d661dcf1: 修正dfs_elm.c中一处内存泄露，并且在mount fatfs失败时执行 umount fatfs操作
-43228aeb9c: 修正list_tcps问题：ipaddr_ntoa不是可重入的函数。
-3de4b92a68: 修正AT91SAM9260分支中PHY link状态错误的问题。
-1abaa0492d
+当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相

Jenkinsfile

@@ -0,0 +1,158 @@
+pipeline {
+    agent {
+        docker { 
+            image 'ubuntu_ci:latest' 
+        }
+    }
+    stages {
+        stage('build') {
+            steps {
+                sh '''
+
+                    uname -a
+                    cat /etc/issue
+                    apt-get update
+                    apt-get install -y -qq lib32ncurses5 lib32z1 > /dev/null
+
+                    curl -s http://download.isrc.rt-thread.com/download/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2 | sudo tar xjf - -C /opt
+                    /opt/gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi-gcc --version
+                '''
+
+                script {
+                    def bsp_array = [
+                        ['CME_M7', 'sourcery-arm'],
+                        // ['apollo2', 'sourcery-arm'], /* CI compile not support */
+                        ['asm9260t', 'sourcery-arm'],
+                        ['at91sam9260', 'sourcery-arm'],
+                        ['allwinner_tina', 'sourcery-arm'],
+                        ['efm32', 'sourcery-arm'],
+                        // ['gd32e230k-start', 'sourcery-arm'], /* CI compile not support */
+                        ['gd32303e-eval', 'sourcery-arm'],
+                        // ['gd32450z-eval', 'sourcery-arm'], /* CI link not support */
+                        ['gkipc', 'sourcery-arm'],
+                        ['imx6sx/cortex-a9', 'sourcery-arm'],
+                        // ['imxrt/imxrt1052-atk-commander', 'sourcery-arm'], /* CI compile not support */
+                        // ['imxrt/imxrt1052-fire-pro', 'sourcery-arm'], /* CI compile not support */
+                        // ['imxrt/imxrt1052-nxp-evk', 'sourcery-arm'], /* CI compile not support */
+                        ['lm3s8962', 'sourcery-arm'],
+                        ['lm3s9b9x', 'sourcery-arm'],
+                        ['lm4f232', 'sourcery-arm'],
+                        ['tm4c129x', 'sourcery-arm'],
+                        // ['lpc43xx/M4', 'sourcery-arm'], /* CI compile not support */
+                        ['lpc176x', 'sourcery-arm'],
+                        ['lpc178x', 'sourcery-arm'],
+                        ['lpc408x', 'sourcery-arm'],
+                        ['lpc1114', 'sourcery-arm'],
+                        ['lpc2148', 'sourcery-arm'],
+                        ['lpc2478', 'sourcery-arm'],
+                        ['lpc5410x', 'sourcery-arm'],
+                        // ['lpc54114-lite', 'sourcery-arm'], /* CI link not support */
+                        ['mb9bf500r', 'sourcery-arm'],
+                        ['mb9bf506r', 'sourcery-arm'],
+                        ['mb9bf618s', 'sourcery-arm'],
+                        ['mb9bf568r', 'sourcery-arm'],
+                        ['mini2440', 'sourcery-arm'],
+                        ['nuvoton_nuc472', 'sourcery-arm'],
+                        ['nuvoton_m05x', 'sourcery-arm'],
+                        ['qemu-vexpress-a9', 'sourcery-arm'],
+                        ['qemu-vexpress-gemini', 'sourcery-arm'],
+                        ['sam7x', 'sourcery-arm'],
+                        // ['stm32/stm32f072-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f091-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-atk-nano', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-atk-warshipv3', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-dofly-lyc8', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-dofly-M3S', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-fire-arbitrary', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-hw100k-ibox', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-mini-system', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-onenet-nbiot', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f103-yf-ufun', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f107-uc-eval', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f401-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f405-smdz-breadfruit', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f407-atk-explorer', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f407-st-discovery', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f410-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f411-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f411-weact-MiniF4', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f413-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f427-robomaster-a', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f429-armfly-v6', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f429-atk-apollo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f429-fire-challenger', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f429-st-disco', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f446-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f469-st-disco', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32f746-st-disco', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32f767-atk-apollo', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32f767-fire-challenger', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32f767-st-nucleo', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32g071-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32g431-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32h743-atk-apollo', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32h743-st-nucleo', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32h747-st-discovery', 'sourcery-arm'], /* CI compile -mcpu= not support */
+                        // ['stm32/stm32l4r9-st-eval', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l010-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l053-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l412-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l432-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l433-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l475-atk-pandora', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l475-st-discovery', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l476-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l496-ali-developer', 'sourcery-arm'], /* CI compile C99 not support */
+                        // ['stm32/stm32l496-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
+                        ['stm32f20x', 'sourcery-arm'],
+                        ['swm320-lq100', 'sourcery-arm'],
+                        ['beaglebone', 'sourcery-arm'],
+                        ['zynq7000', 'sourcery-arm'],
+                        ['frdm-k64f', 'sourcery-arm'],
+                        ['fh8620', 'sourcery-arm'],
+                        ['xplorer4330/M4', 'sourcery-arm'],
+                        // ['at32/at32f403a-start', 'sourcery-arm'],/* CI link not support */
+                        // ['at32/at32f407-start', 'sourcery-arm']/* CI compile C99 not support */
+                    ]
+
+                    for (int i in bsp_array) {
+
+                        sh """
+
+                        export RTT_BSP=${i.getAt(0)}
+                        export RTT_TOOL_CHAIN=${i.getAt(1)}
+                        export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/
+                        export RTT_CC='gcc'
+                        export RTT_ROOT=`pwd`
+
+                        echo \$RTT_EXEC_PATH
+
+                        export CPUS=\$(cat /proc/cpuinfo | grep "processor" | sort | uniq | wc -l)
+                        scons -j\${CPUS} -C bsp/\$RTT_BSP
+                        """
+                    }
+                }
+            }
+        }
+    }
+    post {
+        failure {
+            addGiteeMRComment(comment: """:x: Jenkins CI 构建失败。\n\n \
+查看更多日志详细信息： \
+<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a> \
+<hr /> \
+:x: The Jenkins CI build failed.\n\n \
+Results available at: \
+<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a>""")
+        }
+        success {
+            addGiteeMRComment(comment: """:white_check_mark: Jenkins CI 构建通过。\n\n \
+查看更多日志详细信息： \
+<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a> \
+<hr /> \
+:white_check_mark: The Jenkins CI build passed.\n\n \
+Results available at: \
+<a href="${env.RUN_DISPLAY_URL}">Jenkins[${env.JOB_NAME} # ${env.BUILD_NUMBER}]</a>""")
+        }
+    }
+}

README.md

@@ -9,76 +9,143 @@
 [![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
 [![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
 
-RT-Thread is an open source IoT operating system from China, which has strong scalability: from a tiny kernel running on a tiny core, for example ARM Cortex-M0, or Cortex-M3/4/7, to a rich feature system running on MIPS32, ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
+# Introduction
 
-## Overview ##
+RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS). 
 
-RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue, signal etc. However, it has three different things:
+RT-Thread is mainly written in C language, easy to understand and easy to port(can be quickly port to a wide range of mainstream MCUs and module chips). It applies object-oriented programming methods to real-time system design, making the code elegant, structured, modular, and very tailorable. 
 
-* Device Driver;
-* Component;
-* Dynamic Module
+RT-Thread has Standard version and Nano version. For resource-constrained microcontroller (MCU) systems, the NANO kernel version that requires only 3KB Flash and 1.2KB RAM memory resources can be tailored  with easy-to-use tools; And for resource-rich IoT devices, RT-Thread can use the on-line software package management tool, together with system configuration tools, to achieve intuitive and rapid modular cutting, seamlessly import rich software packages, thus achieving complex functions like Android's graphical interface and touch sliding effects, smart voice interaction effects, and so on.
 
-The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
+## RT-Thread Architecture
 
-The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
+RT-Thread has not only a real-time kernel, but also rich components. Its architecture is as follows:
 
-The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
 
-## Board Support Package ##
+![architecture](./documentation/figures/architecture.png)
 
-RT-Thread RTOS can support many architectures:
 
-* ARM Cortex-M0
-* ARM Cortex-M3/M4/7
-* ARM Cortex-R4
-* ARM Cortex-A8/A9
-* ARM920T/ARM926 etc
-* MIPS32
-* x86
-* Andes
-* C-Sky
-* RISC-V
-* PowerPC
+It includes:
 
-## License ##
+- Kernel layer: RT-Thread kernel, the core part of RT-Thread, includes the implementation of objects in the kernel system, such as multi-threading and its scheduling, semaphore, mailbox, message queue, memory management, timer, etc.; libcpu/BSP (Chip Migration Related Files/Board Support Package) is closely related to hardware and consists of peripheral drivers and CPU porting.
 
-RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code.
+- Components and Service Layer: Components are based on upper-level software on top of the RT-Thread kernel, such as virtual file systems, FinSH command-line interfaces, network frameworks, device frameworks, and more. Its modular design allows for high internal cohesion inside the components and low coupling between components. 
+  
+- RT-Thread software package: A general-purpose software component running on the RT-Thread IoT operating system platform for different application areas, consisting of description information, source code or library files. RT-Thread provides an open package platform with officially available or developer-supplied packages that provide developers with a choice of reusable packages that are an important part of the RT-Thread ecosystem. The package ecosystem is critical to the choice of an operating system because these packages are highly reusable and modular, making it easy for application developers to build the system they want in the shortest amount of time. RT-Thread supports more than 180 software packages. 
 
-    /*
-     * Copyright (c) 2006-2018, RT-Thread Development Team
-     *
-     * SPDX-License-Identifier: Apache-2.0
-     */
+## RT-Thread Features
 
-Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).
+- Designed for resource-constrained devices, the minimum kernel requires only 1.2KB of RAM and 3 KB of Flash.                                                                                                              
 
-## Usage ##
+- Has rich components and a prosperous and fast growing package ecosystem.                                                              
 
-RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly. 
-So far, the RT-Thread scons building system support the command line compile or generate some IDE's project. There are some option varaibles in the scons building script (rtconfig.py):
+- Elegant code style, easy to use, read and master.                                                                                                                                                                             
 
-* ```CROSS_TOOL``` the compiler which you want to use, gcc/keil/iar. 
-* ```EXEC_PATH``` the path of compiler. 
+- High Scalability. RT-Thread has high-quality scalable software architecture, loose coupling, modularity, is easy to tailor and expand.                                                                                                                                                                           
 
-In SConstruct file:
+- Supports high-performance applications.                                                                                                                    
 
-```RTT_ROOT``` This variable is the root directory of RT-Thread RTOS. If you build the porting in the bsp directory, you can use the default setting. Also, you can set the root directory in ```RTT_ROOT``` environment variable and not modify SConstruct files.
+- Supports cross-platform and a wide range of chips.                                                                                                          
 
-When you set these variables correctly, you can use command:
+## Code Catalogue
 
-    scons
+   RT-Thread source code catalog is shown as follow:
 
-under BSP directory to simplely compile RT-Thread RTOS.
+| Name          | Description                                             |
+| ------------- | ------------------------------------------------------- |
+| BSP          | Board Support Package based on the porting of various development boards |
+| components    | Components, such as finsh shell, file system, protocol stack etc. |
+| documentation | Related documents, like coding style, doxygen etc.        |
+| examples      | Related sample code                                     |
+| include       | Head files of RT-Thread kernel                           |
+| libcpu        | CPU porting code such as ARM/MIPS/RISC-V etc. |
+| src           | The source files for the RT-Thread kernel. |
+| tools         | The script files for the RT-Thread command build tool. |
 
-If you want to generate the IDE's project file, you can use command:
+RT-Thread has now been ported for nearly 90 development boards, most BSPs support MDK, IAR development environment and GCC compiler, and have provided default MDK and IAR project, which allows users to add their own application code directly based on the project. Each BSP has a similar directory structure, and most BSPs provide a README.md file, which is a markdown-format file that contains the basic introduction of BSP, and introduces how to simply start using BSP.
 
-    scons --target=mdk/mdk4/mdk5/iar/cb -s
+Env is a development tool developed by RT-Thread which provides a build environment, text graphical system configuration, and package management capabilities for project based on the RT-Thread operating system. Its built-in `menuconfig` provides an easy-to-use configuration tool. It can tailor the kernels, components and software packages freely, so that the system can be constructed by building blocks.
 
-to generate the project file.
+- [Download Env Tool](https://www.rt-thread.io/download.html?download=Env)
+- [User manual of Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
 
-NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files.
+# Resources
 
-## Contribution ##
+## Supported Architectures
 
-Please refer the contributors in the github. Thank all of RT-Thread Developers.
+RT-Thread supports many architectures, and has covered the major architectures in current applications. Architecture and chip manufacturer involved:
+
+- **ARM Cortex-M0/M0+**：manufacturers like ST
+- **ARM Cortex-M3**：manufacturers like ST、Winner Micro、MindMotion, ect.
+- **ARM Cortex-M4**：manufacturers like ST、Nuvton、NXP、GigaDevice、Realtek、Ambiq Micro, ect.
+- **ARM Cortex-M7**：manufacturers like ST、NXP
+- **ARM Cortex-M23**：manufacturers like GigaDevice
+- **ARM Cortex-R4**
+- **ARM Cortex-A8/A9**：manufacturers like NXP
+- **ARM7**：manufacturers like Samsung
+- **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
+- **ARM11**：manufacturers like Fullhan
+- **MIPS32**：manufacturers like loongson、Ingenic
+- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/)
+- **ARC**：manufacturers like SYNOPSYS
+- **DSP**：manufacturers like TI
+- **C-Sky**
+- **x86**
+
+## Supported IDE and Compiler
+
+The main IDE/compilers supported by RT-Thread are:
+
+- MDK KEIL
+- IAR
+- GCC
+- RT-Thread Studio
+
+Use Python-based [scons](http://www.scons.org/) for command-line builds.
+
+RT-Thread Studio Demonstration:
+
+![studio](./documentation/figures/studio.gif)                                                 
+
+## Getting Started
+
+RT-Thread BSP can be compiled directly and downloaded to the corresponding development board for use. In addition, RT-Thread also provides qemu-vexpress-a9 BSP, which can be used without hardware platform. See the getting started guide below for details.
+
+- [Getting Started of QEMU (Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
+
+- [Getting Started of QEMU (Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
+
+## Documentation
+
+[RT-Thread Programming Guide](https://github.com/RT-Thread/rtthread-manual-doc) | [RT-Thread Supported Chips & Boards](https://www.rt-thread.io/board.html) |
+[RT-Thread Software Package](https://github.com/RT-Thread/packages) | [RT-Thread Studio](https://www.rt-thread.io/studio.html) 
+
+## Sample
+
+[Kernel Sample](https://github.com/RT-Thread-packages/kernel-sample) | [Device Sample Code](https://github.com/RT-Thread-packages/peripheral-sample) | [File System Sample Code](https://github.com/RT-Thread-packages/filesystem-sample ) | [Network Sample Code](https://github.com/RT-Thread-packages/network-sample ) | 
+
+[Based on the STM32L475 IoT Board SDK](https://github.com/RT-Thread/IoT_Board) | [Based on the W601 IoT Board SDK](https://github.com/RT-Thread/W601_IoT_Board)
+
+# License
+
+RT-Thread is an open source software and has been licensed under Apache License Version 2.0 since v3.1.1. License information and copyright information can generally be seen at the beginning of the code:
+
+```c
+/* Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * ...
+ */
+```
+
+To avoid possible future license conflicts, developers need to sign a Contributor License Agreement (CLA) when submitting PR to RT-Thread.
+
+# Community
+
+RT-Thread is very grateful for the support from all community developers, and if you have any ideas, suggestions or questions in the process of using RT-Thread, RT-Thread can be reached by the following means, and we are also updating RT-Thread in real time on these channels. At the same time, Any questions can be asked in the [issue section of rtthread-manual-doc](https://github.com/RT-Thread/rtthread-manual-doc/issues). By creating a new issue to describe your questions, community members will answer them.
+
+[Website](https://www.rt-thread.io) | [Twitter](https://twitter.com/rt_thread) | [Youtube]( https://www.youtube.com/channel/UCdDHtIfSYPq4002r27ffqPw?view_as=subscriber) | [Gitter](  https://gitter.im/RT-Thread) | [Facebook](https://www.facebook.com/RT-Thread-IoT-OS-110395723808463/?modal=admin_todo_tour) | [Medium](https://medium.com/@rt_thread)
+
+# Contribution
+
+If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/contribution_guide/contribution_guide.md).

README_zh.md

@@ -1,97 +1,178 @@
-# RT-Thread #
+## 简介
 
-[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
-[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
-[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
-[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
-[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
+RT-Thread诞生于2006年，是一款以开源、中立、社区化发展起来的物联网操作系统。
+RT-Thread主要采用 C 语言编写，浅显易懂，且具有方便移植的特性（可快速移植到多种主流 MCU 及模组芯片上）。RT-Thread把面向对象的设计方法应用到实时系统设计中，使得代码风格优雅、架构清晰、系统模块化并且可裁剪性非常好。
 
-RT-Thread是一个来自中国的开源物联网操作系统，它提供了非常强的可伸缩能力：从一个可以运行在ARM Cortex-M0芯片上的极小内核，到中等的ARM Cortex-M3/4/7系统，甚至是运行于MIPS32、ARM Cortex-A系列处理器上功能丰富系统。
+RT-Thread有完整版和Nano版，对于资源受限的微控制器（MCU）系统，可通过简单易用的工具，裁剪出仅需要 3KB Flash、1.2KB RAM 内存资源的 NANO 内核版本；而相对资源丰富的物联网设备，可使用RT-Thread完整版，通过在线的软件包管理工具，配合系统配置工具实现直观快速的模块化裁剪，并且可以无缝地导入丰富的软件功能包，实现类似 Android 的图形界面及触摸滑动效果、智能语音交互效果等复杂功能。
 
-## 简介 ##
+## **RT-Thread架构**
 
-RT-Thread包含了一个自有的、传统的硬实时内核：可抢占的多任务实时调度器，信号量，互斥量，邮箱，消息队列，信号等。当然，它和传统的实时操作系统还存在着三种不同：
+RT-Thread是一个集实时操作系统（RTOS）内核、中间件组件的物联网操作系统，架构如下：
 
-* 设备驱动框架；
-* 软件组件；
-* 应用模块
+![architecturezh](./documentation/figures/architecturezh.png)  
 
-设备驱动框架更类似一套驱动框架，涉及到UART，IIC，SPI，SDIO，USB从设备/主设备，EMAC，NAND闪存设备等。它会把这些设备驱动中的共性抽象/抽取出来，而驱动工程师只需要按照固定的模式实现少量的底层硬件操作及板级配置。通过这样的方式，让一个硬件外设更容易地对接到RT-Thread系统中，并获得RT-Thread平台上的完整软件栈功能。
 
-软件组件是位于RT-Thread内核上的软件单元，例如命令行（finsh/msh shell），虚拟文件系统（FAT，YAFFS，UFFS，ROM/RAM文件系统等），TCP/IP网络协议栈（lwIP），Libc/POSIX标准层等。一般的，一个软件组件放置于一个目录下，例如RT-Thread/components目录下的文件夹，并且每个软件组件通过一个 SConscript文件来描述并被添加到RT-Thread的构建系统中。当系统配置中开启了这一软件组件时，这个组件将被编译并链接到最终的RT-Thread固件中。
 
-注：随着RT-Thread 3.0中的包管理器开启，越来越多的软件组件将以package方式出现在RT-Thread平台中。而RT-Thread平台更多的是指：
+- 内核层：RT-Thread内核，是 RT-Thread的核心部分，包括了内核系统中对象的实现，例如多线程及其调度、信号量、邮箱、消息队列、内存管理、定时器等；libcpu/BSP（芯片移植相关文件 / 板级支持包）与硬件密切相关，由外设驱动和 CPU 移植构成。
 
-* RT-Thread内核；
-* shell命令行；
-* 虚拟文件系统；
-* TCP/IP网络协议栈；
-* 设备驱动框架；
-* Libc/POSIX标准层。
+- 组件与服务层：组件是基于 RT-Thread内核之上的上层软件，例如虚拟文件系统、FinSH命令行界面、网络框架、设备框架等。采用模块化设计，做到组件内部高内聚，组件之间低耦合。
 
-更多的IoT软件包则以package方式被添加到RT-Thread系统中。
 
-应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象链表，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。
+- RT-Thread软件包：运行于 RT-Thread物联网操作系统平台上，面向不同应用领域的通用软件组件，由描述信息、源代码或库文件组成。RT-Thread提供了开放的软件包平台，这里存放了官方提供或开发者提供的软件包，该平台为开发者提供了众多可重用软件包的选择，这也是 RT-Thread生态的重要组成部分。软件包生态对于一个操作系统的选择至关重要，因为这些软件包具有很强的可重用性，模块化程度很高，极大的方便应用开发者在最短时间内，打造出自己想要的系统。RT-Thread已经支持的软件包数量已经达到 180+。
+  
 
-## 支持的芯片架构 ##
 
-RT-Thread支持数种芯片体系架构，已经覆盖当前应用中的主流体系架构：
+## RT-Thread的特点
 
-* ARM Cortex-M0
-* ARM Cortex-M3/M4/7
-* ARM Cortex-R4
-* ARM Cortex-A8/A9
-* ARM920T/ARM926 etc
-* MIPS32
-* x86
-* Andes
-* C-Sky
-* RISC-V
-* PowerPC
+- 资源占用极低，超低功耗设计，最小内核（Nano版本）仅需1.2KB RAM，3KB Flash。
 
-## 许可证 ##
+- 组件丰富，繁荣发展的软件包生态 。                                 
 
-RT-Thread从v3.1.1版本开始，是一个以Apache许可证2.0版本授权的开源软件，许可证信息以及版权信息一般的可以在代码首部看到：
+- 简单易用 ，优雅的代码风格，易于阅读、掌握。
 
-    /*
-     * Copyright (c) 2006-2018, RT-Thread Development Team
-     *
-     * SPDX-License-Identifier: Apache-2.0
-     */
+- 高度可伸缩，优质的可伸缩的软件架构，松耦合，模块化，易于裁剪和扩展。
 
-从2018/09/09开始，开发者提交PR需要签署贡献者许可协议（CLA）。
+- 强大，支持高性能应用。
 
-注意：
+- 跨平台、芯片支持广泛。
 
-以Apache许可协议v2.0版本授权仅在RT-Thread v3.1.1正式版发布之后才正式实施，当前依然在准备阶段（准备所有原有开发者签署CLA协议）。
 
-## 编译 ##
+## **代码目录**
 
-RT-Thread使用了[scons](http://www.scons.org)做为自身的编译构建系统，并进行一定的定制以满足自身的需求（可以通过scons --help查看RT-Thread中额外添加的命令）。在编译RT-Thread前，请先安装Python 2.7.x及scons。
+RT-Thread源代码目录结构如下图所示：
 
-截至目前，RT-Thread scons构建系统可以使用命令行方式编译代码，或者使用scons来生成不同IDE的工程文件。在使用scons时，需要对构建配置文件（rtconfig.py）中如下的变量进行配置：
+| 名称          | 描述                                                    |
+| ------------- | ------------------------------------------------------- |
+| BSP           | Board Support Package（板级支持包）基于各种开发板的移植 |
+| components    | RT-Thread 的各个组件代码，例如 finsh，gui 等。          |
+| documentation | 相关文档，如编码规范等                                  |
+| examples      | 相关示例代码                                            |
+| include       | RT-Thread 内核的头文件。                                |
+| libcpu        | 各类芯片的移植代码。                                    |
+| src           | RT-Thread 内核的源文件。                                |
+| tools         | RT-Thread 命令构建工具的脚本文件。                      |
 
-* ```CROSS_TOOL``` 指定希望使用的工具链，例如gcc/keil/iar. 
-* ```EXEC_PATH``` 工具链的路径. 
+目前RT-Thread已经针对将近90种开发板做好了移植，大部分 BSP 都支持 MDK﹑IAR开发环境和GCC编译器，并且已经提供了默认的 MDK 和 IAR 工程，用户可以直接基于这个工程添加自己的应用代码。 每个 BSP 的目录结构高度统一，且都提供一个 README.md 文件，包含了对这个 BSP 的基本介绍，以及相应的说明，方便用户快速上手。
 
-注：在SConstruct文件中：
+Env 是RT-Thread推出的开发辅助工具，针对基于RT-Thread操作系统的项目工程，提供编译构建环境、图形化系统配置及软件包管理功能。其内置的 menuconfig 提供了简单易用的配置剪裁工具，可对内核、组件和软件包进行自由裁剪，使系统以搭积木的方式进行构建。
 
-```RTT_ROOT``` 这个变量指向了RT-Thread的发布源代码根目录。如果你仅计划编译bsp目录下的target，这个`RTT_ROOT`可以使用默认配置。另外，你也可以设置同名的环境变量来指向不同的RT-Thread源代码根目录。
+[下载 Env 工具](https://www.rt-thread.org/page/download.html)
 
-当你把相关的配置都配置正确后，你可以在具有目标目录下（这个目录应包括rtconfig.py、SContruct文件）执行以下命令：
+[Env 用户手册](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
 
-    scons 
 
-从而简单地就编译好RT-Thread。
+# 资源文档
 
-如果你希望使用IDE来编译RT-Thread，你也可以使用命令行：
+## **硬件支持**
 
-    scons --target=mdk/mdk4/mdk5/iar/cb -s 
+RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主要架构。涉及的架构和芯片制造商有：
 
-来生成mdk/iar等的工程文件。而后在IDE中打开project前缀的工程文件来编译RT-Thread。
+- ARM Cortex-M0/M0+：如芯片制造商 ST
 
-注意：RT-Thread的scons构建系统会根据配置头文件rtconfig.h来裁剪系统。例如，如果你关闭了rtconfig.h中的lwIP定义（通过注释掉```#define RT_USING_LWIP```的方式），则scons生成的IDE工程文件中将自动不包括lwIP相关的文件。而在RT-Thread 3.0版本中，可以通过menuconfig的方式来配置整个系统，而不需要再手工更改rtconfig.h配置头文件。
+- ARM Cortex-M3：如芯片制造商 ST、全志、灵动等.
 
-## 贡献者 ##
+- ARM Cortex-M4：如芯片制造商 ST、Nuvton、NXP、GigaDevice、Realtek、Ambiq Micro等
+
+- ARM Cortex-M7：如芯片制造商 ST、NXP
+
+- ARM Cortex-M23：如芯片制造商 GigaDevice
+
+- ARM Cortex-R4
+
+- ARM Cortex-A8/A9：如芯片制造商 NXP
+
+- ARM7：如芯片制造商Samsung
+
+- ARM9：如芯片制造商Allwinner、Xilinx 、GOKE
+
+- ARM11：如芯片制造商Fullhan
+
+- MIPS32：如芯片制造商loongson、Ingenic
+
+- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/)
+
+- ARC：如芯片制造商SYNOPSYS
+
+- DSP：如芯片制造商 TI
+
+- C-Sky
+
+- x86
+
+
+## **支持的 IDE 和编译器**
+
+RT-Thread主要支持的IDE/编译器包括：
+
+- MDK KEIL
+
+- IAR
+
+- Gcc
+
+- RT-Thread Studio
+
+使用基于 Python 的 [scons](http://www.scons.org/) 进行命令行生成。
+
+RT-Thread Studio演示：
+
+
+![studiozh](./documentation/figures/studiozh.gif)                                        
+
+
+## **快速上手**
+
+RT-Thread BSP可以直接编译并下载到相应的开发板使用。此外，RT-Thread还提供 qemu-vexpress-a9 BSP，无需硬件平台即可使用。有关详细信息，请参阅下面的入门指南。
+
+[QEMU 入门指南(Windows)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu.md)
+
+[QEMU 入门指南(Ubuntu)](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/quick_start_qemu/quick_start_qemu_linux.md)
+
+
+## 文档
+
+[文档中心](https://www.rt-thread.org/document/site/ ) | [编程指南](https://www.rt-thread.org/document/site/programming-manual/basic/basic/ ) 
+
+[应用 RT-Thread 实现蜂鸣器播放器教程](https://www.rt-thread.org/document/site/tutorial/beep-player/) | [分布式温度监控系统教程](https://www.rt-thread.org/document/site/tutorial/temperature-system/ ) | [智能车连载教程](https://www.rt-thread.org/document/site/tutorial/smart-car/ ) 
+
+## 例程
+
+[内核示例](https://github.com/RT-Thread-packages/kernel-sample)  | [设备示例代码](https://github.com/RT-Thread-packages/peripheral-sample ) | [文件系统示例代码](https://github.com/RT-Thread-packages/filesystem-sample ) | [网络示例代码](https://github.com/RT-Thread-packages/network-sample ) | [RT-Thread API参考手册](https://www.rt-thread.org/document/api/ ) 
+
+[基于STM32L475 IoT Board 开发板SDK](https://github.com/RT-Thread/IoT_Board) | [基于W601 IoT Board 开发板SDK](https://github.com/RT-Thread/W601_IoT_Board) 
+
+## 视频
+
+RT-Thread视频中心提供了一系列RT-Thread相关教程及分享内容。
+
+如：内核入门系列 | Env系列 | 网络系列 | Nano移植系列 |  RT-Thread Studio系列 | 柿饼UI系列 | 答疑直播系列 | 社区作品系列
+
+更多详情，请前往 [视频中心](https://www.rt-thread.org/page/video.html)
+
+# **许可协议**
+
+RT-Thread系统完全开源，3.1.0 及以前的版本遵循 GPL V2 + 开源许可协议。从 3.1.0 以后的版本遵循Apache License 2.0开源许可协议，可以免费在商业产品中使用，并且不需要公开私有代码。
+
+```
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+```
+
+# 社区支持
+
+RT-Thread非常感谢所有社区小伙伴的支持，在使用RT-Thread的过程中若您有任何的想法，建议或疑问都可通过以下方式联系到 RT-Thread，我们也实时在这些频道更新RT-Thread的最新讯息。同时，任何问题都可以在 [issue section](https://github.com/RT-Thread/rtthread-manual-doc/issues) 中提出。通过创建一个issue来描述您的问题，社区成员将回答这些问题。
+
+[官网]( https://www.rt-thread.org) | [论坛]( https://www.rt-thread.org/qa/forum.php) | [哔哩哔哩官方账号](https://space.bilibili.com/423462075?spm_id_from=333.788.b_765f7570696e666f.2) | [微博官方账号](https://weibo.com/rtthread?is_hot=1) | [知乎官方账号](https://www.zhihu.com/topic/19964581/hot) 
+
+RT-Thread微信公众号：
+
+![qrcode](./documentation/figures/qrcode.png)
+
+
+# 贡献代码
+
+如果您对RT-Thread感兴趣，并希望参与RT-Thread的开发并成为代码贡献者，请参阅[代码贡献指南](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/documentation/contribution_guide/contribution_guide.md)。
 
-请访问github上RT-Thread项目上的contributors了解已经为RT-Thread提交过代码，PR的贡献者。感谢所有为RT-Thread付出的开发者们！

bsp/qemu-vexpress-a9/SConscript

@@ -1,8 +1,9 @@
-# for module compiling
+# RT-Thread building script for bridge
+
 import os
-Import('RTT_ROOT')
+from building import *
 
-cwd = str(Dir('#'))
+cwd = GetCurrentDir()
 objs = []
 list = os.listdir(cwd)
 

bsp/qemu-vexpress-a9/applications/SConscript

@@ -1,10 +1,8 @@
-Import('RTT_ROOT')
-Import('rtconfig')
 from building import *
 
 cwd     = GetCurrentDir()
 src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
+CPPPATH = [cwd]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 

bsp/qemu-vexpress-a9/applications/lcd_init.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <rtthread.h>
 
 #if defined(RT_USING_RTGUI) || defined(PKG_USING_GUIENGINE)

bsp/qemu-vexpress-a9/applications/main.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -8,4 +18,3 @@ int main(void)
 
     return 0;
 }
-

bsp/qemu-vexpress-a9/applications/mnt.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <rtthread.h>
 
 #ifdef RT_USING_DFS
@@ -16,4 +26,3 @@ int mnt_init(void)
 }
 INIT_ENV_EXPORT(mnt_init);
 #endif
-

bsp/qemu-vexpress-a9/drivers/audio/SConscript

@@ -4,6 +4,6 @@ cwd = GetCurrentDir()
 src = Glob('*.c') + Glob('*.S')
 CPPPATH = [cwd]
 
-group = DefineGroup('drv_audio', src, depend = ['BSP_DRV_AUDIO'], CPPPATH = CPPPATH)
+group = DefineGroup('Drivers', src, depend = ['BSP_DRV_AUDIO'], CPPPATH = CPPPATH)
 
 Return('group')

bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_ac97.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_ac97.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c

@@ -1,21 +1,7 @@
 /*
- * File      : drv_pl041.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,7 +22,7 @@
 #include <rtdbg.h>
 
 #define FRAME_PERIOD_US    (50)
-#define PL041_CHANNLE_NUM  (4)
+#define PL041_CHANNEL_NUM  (4)
 
 #define PL041_READ(_a)        (*(volatile rt_uint32_t *)(_a))
 #define PL041_WRITE(_a, _v)   (*(volatile rt_uint32_t *)(_a) = (_v))
@@ -47,7 +33,7 @@ struct pl041_irq_def
     void *user_data;
 };
 
-static struct pl041_irq_def irq_tbl[PL041_CHANNLE_NUM];
+static struct pl041_irq_def irq_tbl[PL041_CHANNEL_NUM];
 
 static void aaci_pl041_delay(rt_uint32_t us)
 {
@@ -169,13 +155,13 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg)
     return v;
 }
 
-int aaci_pl041_channle_disable(int channle)
+int aaci_pl041_channel_disable(int channel)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = PL041_READ(p_rx);
     v &= ~AACI_CR_EN;
     PL041_WRITE(p_rx, v);
@@ -185,13 +171,13 @@ int aaci_pl041_channle_disable(int channle)
     return 0;
 }
 
-int aaci_pl041_channle_enable(int channle)
+int aaci_pl041_channel_enable(int channel)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = PL041_READ(p_rx);
     v |= AACI_CR_EN;
     PL041_WRITE(p_rx, v);
@@ -201,13 +187,13 @@ int aaci_pl041_channle_enable(int channle)
     return 0;
 }
 
-int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
+int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count)
 {
     void *p_data, *p_status;
     int i = 0;
 
-    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
+    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
     for (i = 0; (!(PL041_READ(p_status) & AACI_SR_RXFE)) && (i < count); i++)
     {
         buff[i] = (rt_uint16_t)PL041_READ(p_data);
@@ -215,13 +201,13 @@ int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
     return i;
 }
 
-int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
+int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count)
 {
     void *p_data, *p_status;
     int i = 0;
 
-    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
+    p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+    p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
     for (i = 0; (!(PL041_READ(p_status) & AACI_SR_TXFF)) && (i < count); i++)
     {
         PL041_WRITE(p_data, buff[i]);
@@ -229,13 +215,13 @@ int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
     return i;
 }
 
-int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
+int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cgf)
 {
     rt_uint32_t v;
     void *p_rx, *p_tx;
 
-    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
-    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
+    p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
+    p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
     v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->itype;
     PL041_WRITE(p_rx, v);
     v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->otype;
@@ -247,86 +233,86 @@ int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
     return 0;
 }
 
-void aaci_pl041_irq_enable(int channle, rt_uint32_t vector)
+void aaci_pl041_irq_enable(int channel, rt_uint32_t vector)
 {
     rt_uint32_t v;
     void *p_irq;
 
     vector &= vector & 0x7f;
-    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
+    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
     v = PL041_READ(p_irq);
     v |= vector;
     PL041_WRITE(p_irq, v);
 }
 
-void aaci_pl041_irq_disable(int channle, rt_uint32_t vector)
+void aaci_pl041_irq_disable(int channel, rt_uint32_t vector)
 {
     rt_uint32_t v;
     void *p_irq;
 
     vector &= vector & 0x7f;
-    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
+    p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
     v = PL041_READ(p_irq);
     v &= ~vector;
     PL041_WRITE(p_irq, v);
 }
 
-rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data)
+rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data)
 {
-    if (channle < 0 || channle >= PL041_CHANNLE_NUM)
+    if (channel < 0 || channel >= PL041_CHANNEL_NUM)
     {
-        LOG_E("%s channle:%d err.", __FUNCTION__, channle);
+        LOG_E("%s channel:%d err.", __FUNCTION__, channel);
         return -RT_ERROR;
     }
-    irq_tbl[channle].fun = fun;
-    irq_tbl[channle].user_data = user_data;
+    irq_tbl[channel].fun = fun;
+    irq_tbl[channel].user_data = user_data;
     return RT_EOK;
 }
 
-rt_err_t aaci_pl041_irq_unregister(int channle)
+rt_err_t aaci_pl041_irq_unregister(int channel)
 {
-    if (channle < 0 || channle >= PL041_CHANNLE_NUM)
+    if (channel < 0 || channel >= PL041_CHANNEL_NUM)
     {
-        LOG_E("%s channle:%d err.", __FUNCTION__, channle);
+        LOG_E("%s channel:%d err.", __FUNCTION__, channel);
         return -RT_ERROR;
     }
-    irq_tbl[channle].fun = RT_NULL;
-    irq_tbl[channle].user_data = RT_NULL;
+    irq_tbl[channel].fun = RT_NULL;
+    irq_tbl[channel].user_data = RT_NULL;
     return RT_EOK;
 }
 
 static void aaci_pl041_irq_handle(int irqno, void *param)
 {
-    rt_uint32_t mask, channle, m;
+    rt_uint32_t mask, channel, m;
     struct pl041_irq_def *_irq = param;
     void *p_status;
 
     mask = PL041_READ(&PL041->allints);
     PL041_WRITE(&PL041->intclr, mask);
 
-    for (channle = 0; (channle < PL041_CHANNLE_NUM) && (mask); channle++)
+    for (channel = 0; (channel < PL041_CHANNEL_NUM) && (mask); channel++)
     {
         mask = mask >> 7;
         m = mask & 0x7f;
         if (m & AACI_ISR_ORINTR)
         {
-            LOG_W("RX overrun on chan %d", channle);
+            LOG_W("RX overrun on chan %d", channel);
         }
 
         if (m & AACI_ISR_RXTOINTR)
         {
-            LOG_W("RX timeout on chan %d", channle);
+            LOG_W("RX timeout on chan %d", channel);
         }
 
         if (mask & AACI_ISR_URINTR)
         {
-            LOG_W("TX underrun on chan %d", channle);
+            LOG_W("TX underrun on chan %d", channel);
         }
 
-        p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
-        if (_irq[channle].fun != RT_NULL)
+        p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
+        if (_irq[channel].fun != RT_NULL)
         {
-            _irq[channle].fun(PL041_READ(p_status), _irq[channle].user_data);
+            _irq[channel].fun(PL041_READ(p_status), _irq[channel].user_data);
         }
     }
 }

bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h

@@ -1,21 +1,7 @@
 /*
- * File      : drv_pl041.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -158,10 +144,10 @@
 #define MAINFR_TXB   (1 << 1)	/* transmit busy */
 #define MAINFR_RXB   (1 << 0)	/* receive busy */
 
-#define PL041_CHANNLE_LEFT_DAC    (0x1 << 3)
-#define PL041_CHANNLE_RIGHT_DAC   (0x1 << 3)
-#define PL041_CHANNLE_LEFT_ADC    (0x1 << 3)
-#define PL041_CHANNLE_RIGHT_ADC   (0x1 << 3)
+#define PL041_CHANNEL_LEFT_DAC    (0x1 << 3)
+#define PL041_CHANNEL_RIGHT_DAC   (0x1 << 3)
+#define PL041_CHANNEL_LEFT_ADC    (0x1 << 3)
+#define PL041_CHANNEL_RIGHT_ADC   (0x1 << 3)
 
 struct reg_pl041
 {
@@ -225,13 +211,13 @@ typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data);
 rt_err_t aaci_pl041_init(void);
 void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val);
 rt_uint16_t aaci_ac97_read(rt_uint16_t reg);
-int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cfg);
-int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count);
-int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count);
-int aaci_pl041_channle_enable(int channle);
-int aaci_pl041_channle_disable(int channle);
-rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data);
-rt_err_t aaci_pl041_irq_unregister(int channle);
-void aaci_pl041_irq_disable(int channle, rt_uint32_t vector);
-void aaci_pl041_irq_enable(int channle, rt_uint32_t vector);
+int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg);
+int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count);
+int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count);
+int aaci_pl041_channel_enable(int channel);
+int aaci_pl041_channel_disable(int channel);
+rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data);
+rt_err_t aaci_pl041_irq_unregister(int channel);
+void aaci_pl041_irq_disable(int channel, rt_uint32_t vector);
+void aaci_pl041_irq_enable(int channel, rt_uint32_t vector);
 #endif

bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c

@@ -227,13 +227,13 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
 
     aaci_pl041_init();
 
-    _cfg.itype = PL041_CHANNLE_LEFT_ADC | PL041_CHANNLE_RIGHT_ADC;
-    _cfg.otype = PL041_CHANNLE_LEFT_DAC | PL041_CHANNLE_RIGHT_DAC;
+    _cfg.itype = PL041_CHANNEL_LEFT_ADC | PL041_CHANNEL_RIGHT_ADC;
+    _cfg.otype = PL041_CHANNEL_LEFT_DAC | PL041_CHANNEL_RIGHT_DAC;
     _cfg.vol   = snd_dev->volume;
     _cfg.rate  = snd_dev->replay_config.samplerate;
 
     ac97_reset();
-    aaci_pl041_channle_cfg(0, &_cfg);
+    aaci_pl041_channel_cfg(0, &_cfg);
     aaci_pl041_irq_register(0, rt_hw_aaci_isr, RT_NULL);
 
     return result;
@@ -246,7 +246,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
     if (stream == AUDIO_STREAM_REPLAY)
     {
         LOG_D("open sound device");
-        aaci_pl041_channle_enable(0);
+        aaci_pl041_channel_enable(0);
         aaci_pl041_irq_enable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
     }
 
@@ -263,7 +263,7 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
         rt_thread_mdelay(100);
         /* disable irq and channels 0 */
         aaci_pl041_irq_disable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
-        aaci_pl041_channle_disable(0);
+        aaci_pl041_channel_disable(0);
         LOG_D("close sound device");
     }
 
@@ -295,7 +295,7 @@ static rt_size_t sound_transmit(struct rt_audio_device *audio, const void *write
     RT_ASSERT(audio != RT_NULL);
 
     /* write data to channel_0 fifo */
-    aaci_pl041_channle_write(0, (rt_uint16_t *)writeBuf, size >> 1);
+    aaci_pl041_channel_write(0, (rt_uint16_t *)writeBuf, size >> 1);
 
     return size;
 }

bsp/qemu-vexpress-a9/drivers/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/drv_clcd.c

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #include <stdint.h>
 #include <string.h>
 #include <stdlib.h>

bsp/qemu-vexpress-a9/drivers/drv_clcd.h

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #ifndef DRV_CLCD_H__
 #define DRV_CLCD_H__
 

bsp/qemu-vexpress-a9/drivers/drv_keyboard.c

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>

bsp/qemu-vexpress-a9/drivers/drv_keyboard.h

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #ifndef __DEV_KEYBOARD_H__
 #define __DEV_KEYBOARD_H__
 

bsp/qemu-vexpress-a9/drivers/drv_mouse.c

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>

bsp/qemu-vexpress-a9/drivers/drv_mouse.h

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #ifndef __DRV_MOUSE_H__
 #define __DRV_MOUSE_H__
 

bsp/qemu-vexpress-a9/drivers/drv_sdio.c

@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>

bsp/qemu-vexpress-a9/drivers/drv_sdio.h

@@ -1,7 +1,15 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
 #ifndef __DRV_SDIO_H__
 #define __DRV_SDIO_H__
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif

bsp/qemu-vexpress-a9/drivers/drv_smc911x.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+
 #include <board.h>
 #include <rtthread.h>
 #include <netif/ethernetif.h>

bsp/qemu-vexpress-a9/drivers/realview.h

@@ -1,5 +1,14 @@
-#ifndef __AM33XX_H__
-#define __AM33XX_H__
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/31     Bernard      Add license info
+ */
+#ifndef __REALVIEW_H__
+#define __REALVIEW_H__
 
 #define __REG32(x)  (*((volatile unsigned int *)(x)))
 #define __REG16(x)  (*((volatile unsigned short *)(x)))

bsp/qemu-vexpress-a9/drivers/serial.c

@@ -1,26 +1,7 @@
 /*
- *  serial.c UART driver
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/drivers/serial.h

@@ -1,26 +1,7 @@
 /*
- *  UART driver
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/qemu-vexpress-a9/qemu-nographic.sh

@@ -2,5 +2,5 @@ if [ ! -f "sd.bin" ]; then
 dd if=/dev/zero of=sd.bin bs=1024 count=65536
 fi
 
-qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin -net nic -net tap
+qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -nographic -sd sd.bin
 

bsp/stm32/README.md

@@ -1,3 +1,4 @@
+
 # STM32 BSP 说明
 
 STM32 系列 BSP 目前支持情况如下表所示：
@@ -9,6 +10,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | **F1 系列** |  |
 | [stm32f103-atk-nano](stm32f103-atk-nano)        | 正点原子 F103 NANO 开发板  |
 | [stm32f103-atk-warshipv3](stm32f103-atk-warshipv3)  | 正点原子 F103 战舰V3 开发板  |
+| [stm32f103-blue-pill](stm32f103-blue-pill) | STM32F103C8T6蓝色最小系统板 |
 | [stm32f103-dofly-lyc8](stm32f103-dofly-lyc8) | 德飞莱 STM32F103 开发板 |
 | [stm32f103-dofly-M3S](stm32f103-dofly-M3S) | 德飞莱 STM32F103 开发板 |
 | [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/)  | 野火 F103 霸道开发板     |
@@ -20,6 +22,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 |
 | [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 |
 | [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 |
+| [stm32f411-atk-nano](stm32f411-atk-nano/) | 正点原子 F411 NANO 开发板 |
 | [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 |
 | [stm32f427-robomaster-a](stm32f427-robomaster-a/) |大疆公司 RoboMaster A型开发板|
 | [stm32f429-st-disco](stm32f429-st-disco) | ST 官方 STM32F429-discovery 开发板 |
@@ -41,7 +44,9 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | **H7 系列** |  |
 | [stm32h743-atk-apollo](stm32h743-atk-apollo) | 正点原子 h743 阿波罗开发板 |
 | [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 |
+| [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 |
 | **L0 系列** |  |
+| [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 |
 | [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 |
 | **L4 系列** |  |
 | [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 |
@@ -50,6 +55,11 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32l475-st-discovery](stm32l475-st-discovery) | ST 官方 stm32l475-discovery 开发板 |
 | [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-nucleo 开发板 |
 | [stm32l496-ali-developer](stm32l496-ali-developer) | 诺行 STM32L496 Ali Developer Kit 开发板 |
+| **MP1 系列** |  |
+| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
+| [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
+| **WB 系列** |  |
+| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-nucleo 开发板 |
 
 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
 

bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md

@@ -0,0 +1,128 @@
+# STM32 Nucleo-144 BSP Introduction
+
+This document records the instruction of the BSP (board support package) that provided by the RT-Thread development team for the STM32 Nucleo-144 development boards.
+
+The document is covered in three parts:
+
+- Resources Introduction
+- Quickly Get Started
+- Advanced Features
+
+By reading the ***Quickly Get Started*** section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+
+
+## Resources Introduction
+
+[<img src="figures/stm32-nucleo-144.png" alt="board" style="zoom:50%;" />](figures/stm32-nucleo-144.jpg) 
+
+### Description 
+
+The STM32 Nucleo-144 board provides an affordable and flexible way for users to try out new concepts and build prototypes by choosing from the various combinations of performance and power consumption features, provided by the STM32 microcontroller. For the compatible boards, the internal or external SMPS significantly reduces power consumption in Run mode. The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and the ST morpho headers provide an easy means of expanding the functionality of the Nucleo open development platform with a wide choice of specialized shields. The STM32 Nucleo-144 board does not require any separate probe as it integrates the ST-LINK debugger/programmer. The STM32 Nucleo-144 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package.
+
+### Features
+
+- Common features
+  - STM32 microcontroller in LQFP144 package 
+  - 3 user LEDs
+  - 2 user and reset push-buttons
+  - 32.768 kHz crystal oscillator
+  - Board connectors: 
+    - SWD 
+    - ST Zio expansion connector including ARDUINO® Uno V3
+    - ST morpho expansion connector
+  - Flexible power-supply options: ST-LINK, USB VBUS or external sources
+  - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port
+  - Comprehensive free software libraries and examples available with the STM32Cube MCU Package
+  - Support of a wide choice of Integrated Development Environments (IDEs) including IAR™, Keil®, and STM32CubeIDE
+- Board-specific features
+  - External or internal SMPS to generate Vcore logic supply
+  - Ethernet compliant with IEEE-802.3-2002
+  - USB OTG full speed or device only
+  - Board connectors: 
+    - USB with Micro-AB or USB Type-C™ 
+    - Ethernet RJ45
+  - Arm® Mbed Enabled™ compliant
+
+### **For more details about these boards, please refer to [ST Nucleo Official Website](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847).**
+
+
+
+## Quickly Get Started
+
+This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system.
+
+![nucleo144_layout](figures/nucleo144_layout.jpg)
+
+### Hardware connection
+
+Use a Type-A to Mini-B cable to connect the development board to the PC and turn on the power switch. The LD3 (PWR) and LD1 (COM) will light.
+
+### Compile and Download
+
+- Double-click the `project.uvprojx` file to open the MDK-Keil5 project  (**NOT** `template.uvprojx` file)
+- Click the “option for target” button
+  - Debug: Choose "ST-LINK Debugger" and Click "Setting" button:
+    - Port: choose "SW (Serial Wire)"
+    - Flash Download: check "Reset and Run"
+
+- Compile and download the program to the board
+
+### Running Results
+
+After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the LD3 and LD1 will light all the time, and LD2 will flash periodically.
+
+The USB virtual COM port connects to **USART3 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset:
+
+```shell
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Dec 21 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+
+### Terminal tool - PuTTy 
+
+If you don't have a terminal tool software available, you can download *PuTTy*:
+
+>  https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html
+
+![putty](figures/putty.png)
+
+
+
+Follow these tutorial videos to learn PuTTy:
+
+> https://www.youtube.com/watch?v=ab4ilbsteWU
+>
+> https://www.youtube.com/watch?v=dO-BMOzNKcI
+
+
+
+## Advanced Features
+
+This BSP only enables GPIO and USART3 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows:
+
+1. Open the Env tool under the specific BSP folder;
+2. Enter `menuconfig` command to configure the project, then save and exit;
+3. Enter `pkgs --update` command to update the package;
+4. Enter `scons --target=mdk4/mdk5/iar` command to regenerate the project.
+
+Learn how to use RT-Thread Env, click [Here](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md).
+
+
+
+## Translated & Maintained By
+
+Cathy Lee @ RT-Thread Team
+
+> https://github.com/Cathy-lulu
+>
+> contact@rt-thread.org
+
+Meco Man @ RT-Thread Community
+
+> jiantingman@foxmail.com 
+>
+> https://github.com/mysterywolf

bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md

@@ -0,0 +1,126 @@
+# STM32 Nucleo-64 BSP Introduction
+
+This document records the instruction of the BSP (board support package) that provided by the RT-Thread development team for the STM32 Nucleo-64 development boards.
+
+The document is covered in three parts:
+
+- Resources Introduction
+- Quickly Get Started
+- Advanced Features
+
+By reading the ***Quickly Get Started*** section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+
+
+## Resources Introduction
+
+[![board](figures/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) 
+
+### Description 
+
+The STM32 Nucleo-64 board provides an affordable and flexible way for users to try out new concepts and build prototypes by choosing from the various combinations of performance and power consumption features, provided by the STM32 microcontroller. For the compatible boards, the external SMPS significantly reduces power consumption in Run mode. The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the easy expansion of the functionality of the STM32 Nucleo open development platform with a wide choice of specialized shields. The STM32 Nucleo-64 board does not require any separate probe as it integrates the ST-LINK debugger/programmer. The STM32 Nucleo-64 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package.
+
+### Features
+
+- Common features
+  - STM32 microcontroller in LQFP64 package
+  - 1 user LED shared with ARDUINO®
+  - 1 user and 1 reset push-buttons
+  - 32.768 kHz crystal oscillator
+  - Board connectors: 
+    - ARDUINO® Uno V3 expansion connector
+    - ST morpho extension pin headers for full access to all STM32 I/Os
+  - Flexible power-supply options: ST-LINK, USB VBUS, or external sources
+  - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port
+  - Comprehensive free software libraries and examples available with the STM32Cube MCU Package
+  - Support of a wide choice of Integrated Development Environments (IDEs) including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE
+- Board-specific features
+  - External SMPS to generate Vcore logic supply
+  - 24 MHz HSE – Board connectors: 
+    - External SMPS experimentation dedicated connector
+    - Micro-AB or Mini-AB USB connector for the ST-LINK
+    - MIPI® debug connector 
+  - Arm® Mbed Enabled™ compliant
+
+### **For more details about these boards, please refer to [ST Nucleo Official Website](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847).**
+
+
+
+## Quickly Get Started
+
+This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system.
+
+![nucleo64_layout](figures/nucleo64_layout.jpg)
+
+### Hardware connection
+
+Use a Type-A to Mini-B cable to connect the development board to the PC and turn on the power switch. The LD3 (PWR) and LD1 (COM) will light.
+
+### Compile and Download
+
+- Double-click the `project.uvprojx` file to open the MDK-Keil5 project  (**NOT** `template.uvprojx` file)
+- Click the “option for target” button
+  - Debug: Choose "ST-LINK Debugger" and Click "Setting" button:
+    - Port: choose "SW (Serial Wire)"
+    - Flash Download: check "Reset and Run"
+
+- Compile and download the program to the board
+
+### Running Results
+
+After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the LD3 and LD1 will light all the time, and LD2 will flash periodically.
+
+The USB virtual COM port connects to **USART2 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset:
+
+```shell
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Dec 21 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+
+### Terminal tool - PuTTy 
+
+If you don't have a terminal tool software available, you can download *PuTTy*:
+
+>  https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html
+
+![putty](figures/putty.png)
+
+
+
+Follow these tutorial videos to learn PuTTy:
+
+> https://www.youtube.com/watch?v=ab4ilbsteWU
+>
+> https://www.youtube.com/watch?v=dO-BMOzNKcI
+
+
+
+## Advanced Features
+
+This BSP only enables GPIO and USART2 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows:
+
+1. Open the Env tool under the specific BSP folder;
+2. Enter `menuconfig` command to configure the project, then save and exit;
+3. Enter `pkgs --update` command to update the package;
+4. Enter `scons --target=mdk4/mdk5/iar` command to regenerate the project.
+
+Learn how to use RT-Thread Env, click [Here](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md).
+
+
+
+## Translated & Maintained By
+
+Cathy Lee @ RT-Thread Team
+
+> https://github.com/Cathy-lulu
+>
+> contact@rt-thread.org
+
+Meco Man @ RT-Thread Community
+
+> jiantingman@foxmail.com 
+>
+> https://github.com/mysterywolf

bsp/stm32/docs/STM32绯诲垪BSP澶栬椹卞姩浣跨敤鏁欑▼.md → bsp/stm32/docs/STM32系列BSP外设驱动使用教程.md

@@ -1,4 +1,4 @@
-# BSP 外设驱动使用教程
+# STM32系列BSP外设驱动使用教程
 
 ## 简介
 
@@ -12,7 +12,7 @@
 
 ## 前提要求
 
-- 学会如何使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/rtthread-development-guide/rtthread-tool-manual/env/env-user-manual/)
+- 学会如何使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/programming-manual/env/env/)
 
 ## 如何使用更多的板载资源
 

bsp/stm32/docs/STM32绯诲垪椹卞姩浠嬬粛.md → bsp/stm32/docs/STM32系列驱动介绍.md

@@ -1,4 +1,4 @@
-#  外设驱动介绍与应用
+#  STM32系列驱动介绍
 
 在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套  I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示：
 

bsp/stm32/libraries/HAL_Drivers/Kconfig

@@ -30,7 +30,7 @@ config BSP_USING_CRC
     select RT_HWCRYPTO_USING_CRC
     # "Crypto device frame dose not support above 8-bits granularity"
     # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
-    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7)
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
     default n 
 
 config BSP_USING_RNG
@@ -38,9 +38,23 @@ config BSP_USING_RNG
     select RT_USING_HWCRYPTO
     select RT_HWCRYPTO_USING_RNG
     depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
-                SOC_SERIES_STM32H7)
+                SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
     default n
-    
+
+config BSP_USING_HASH
+    bool "Enable HASH (Hash House Harriers)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_HASH
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
+config BSP_USING_CRYP
+    bool "Enable CRYP (Encrypt And Decrypt Data)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRYP
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
 config BSP_USING_UDID
     bool "Enable UDID (Unique Device Identifier)"
     select RT_USING_HWCRYPTO

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -10,7 +10,7 @@ src = Split("""
 
 if GetDepend(['RT_USING_PIN']):
     src += ['drv_gpio.c']
-    
+
 if GetDepend(['RT_USING_SERIAL']):
     src += ['drv_usart.c']
 
@@ -36,6 +36,9 @@ if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
 if GetDepend(['RT_USING_ADC']):
     src += Glob('drv_adc.c')
 
+if GetDepend(['RT_USING_DAC']):
+    src += Glob('drv_dac.c')
+
 if GetDepend(['RT_USING_CAN']):
     src += ['drv_can.c']
 
@@ -55,6 +58,9 @@ if GetDepend('BSP_USING_LCD_MIPI'):
 if GetDepend('BSP_USING_ONCHIP_RTC'):
     src += ['drv_rtc.c']
 
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32G0']):
+    src += ['drv_flash/drv_flash_g0.c']
+
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
     src += ['drv_flash/drv_flash_f0.c']
 
@@ -72,10 +78,16 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
 
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
     src += ['drv_flash/drv_flash_l4.c']
-	
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
+    src += ['drv_flash/drv_flash_h7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32WB']):
+    src += ['drv_flash/drv_flash_wb.c']
+
 if GetDepend('RT_USING_HWCRYPTO'):
     src += ['drv_crypto.c']
-	
+
 if GetDepend(['BSP_USING_WDT']):
     src += ['drv_wdt.c']
 
@@ -88,6 +100,9 @@ if GetDepend(['BSP_USING_USBD']):
 if GetDepend(['BSP_USING_PULSE_ENCODER']):
     src += ['drv_pulse_encoder.c']
 
+if GetDepend(['BSP_USING_USBH']):
+    src += ['drv_usbh.c']
+
 src += ['drv_common.c']
 
 path =  [cwd]

bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h

@@ -17,6 +17,17 @@
 extern "C" {
 #endif
 
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
 #ifdef BSP_USING_PWM2
 #ifndef PWM2_CONFIG
 #define PWM2_CONFIG                             \

bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -157,12 +157,12 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
 
 /* DMA2 stream1 */
@@ -208,12 +208,12 @@ extern "C" {
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
 #define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
 
 /* DMA2 stream4 */

bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h

@@ -61,6 +61,17 @@ extern "C" {
 #endif /* PWM5_CONFIG */
 #endif /* BSP_USING_PWM5 */
 
+#ifdef BSP_USING_PWM9
+#ifndef PWM9_CONFIG
+#define PWM9_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM9,         \
+       .name                    = "pwm9",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM9_CONFIG */
+#endif /* BSP_USING_PWM9 */
+
 #ifdef BSP_USING_PWM12
 #ifndef PWM12_CONFIG
 #define PWM12_CONFIG                            \

bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h

@@ -27,6 +27,17 @@ extern "C" {
     }
 #endif /* TIM_DEV_INFO_CONFIG */
 
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                                         \
+    {                                                       \
+       .tim_handle.Instance     = TIM3,                     \
+       .tim_irqn                = TIM3_IRQn,                \
+       .name                    = "timer3",                 \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
 #ifdef BSP_USING_TIM11
 #ifndef TIM11_CONFIG
 #define TIM11_CONFIG                                        \

bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h

@@ -19,63 +19,69 @@ extern "C" {
 
 #ifdef BSP_USING_ADC1
 #ifndef ADC1_CONFIG
-#define ADC1_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC1,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC1_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC1,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC1_CONFIG */
 #endif /* BSP_USING_ADC1 */
 
 #ifdef BSP_USING_ADC2
 #ifndef ADC2_CONFIG
-#define ADC2_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC2,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC2_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC2,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC2_CONFIG */
 #endif /* BSP_USING_ADC2 */
 
 #ifdef BSP_USING_ADC3
 #ifndef ADC3_CONFIG
-#define ADC3_CONFIG                                                 \
-    {                                                               \
-       .Instance                   = ADC3,                          \
-       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
-       .Init.Resolution            = ADC_RESOLUTION_12B,            \
-       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
-       .Init.ScanConvMode          = DISABLE,                       \
-       .Init.EOCSelection          = DISABLE,                       \
-       .Init.ContinuousConvMode    = DISABLE,                       \
-       .Init.NbrOfConversion       = 1,                             \
-       .Init.DiscontinuousConvMode = DISABLE,                       \
-       .Init.NbrOfDiscConversion   = 0,                             \
-       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
-       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
-       .Init.DMAContinuousRequests = DISABLE,                       \
+#define ADC3_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC3,                          \
+       .Init.ClockPrescaler            = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
     }
 #endif /* ADC3_CONFIG */
 #endif /* BSP_USING_ADC3 */

bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2019-01-02     zylx         first version
  * 2019-01-08     SummerGift   clean up the code
+ * 2020-05-02     whj4674672   support stm32h7 dma1 and dma2
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -19,27 +20,21 @@ extern "C" {
 #endif
 
 /* DMA1 stream0 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
-#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
-#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
-#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
-#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
-#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
-#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
-#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART2_RX_DMA_REQUEST             DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                 DMA1_Stream0_IRQn
 #endif
 
 /* DMA1 stream1 */
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
-#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
-#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
-#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream1
+#define UART2_TX_DMA_REQUEST             DMA_REQUEST_USART2_TX
+#define UART2_TX_DMA_IRQ                 DMA1_Stream1_IRQn
 #endif
 
 /* DMA1 stream2 */
@@ -49,12 +44,6 @@ extern "C" {
 #define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
 #define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
 #define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
-#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
-#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
-#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
-#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
 #endif
 
 /* DMA1 stream3 */
@@ -83,12 +72,6 @@ extern "C" {
 #define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
 #define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
 #define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
-#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
-#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
-#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
-#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
 #endif
 
 /* DMA1 stream6 */
@@ -109,12 +92,6 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
-#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
-#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
-#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
 
 /* DMA2 stream1 */
@@ -133,18 +110,6 @@ extern "C" {
 #define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
 #define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
-#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
-#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
-#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
-#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
-#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
-#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
-#define QSPI_DMA_INSTANCE                DMA2_Stream2
-#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
-#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
 #endif
 
 /* DMA2 stream3 */
@@ -154,18 +119,6 @@ extern "C" {
 #define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
 #define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
 #define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
-#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
-#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
-#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
-#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
-#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
 
 /* DMA2 stream4 */
@@ -175,12 +128,6 @@ extern "C" {
 #define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
 #define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
 #define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
-#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
-#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
-#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
 #endif
 
 /* DMA2 stream5 */
@@ -190,18 +137,6 @@ extern "C" {
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
 #define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
 #define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
-#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
-#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
-#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
-#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
-#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
-#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
-#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
-#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
-#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
 #endif
 
 /* DMA2 stream6 */

bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-10-30     SummerGift   first version
  * 2019-01-05     zylx         modify dma support
+ * 2020-05-02     whj4674672   support stm32h7 uart dma
  */
  
 #ifndef __UART_CONFIG_H__
@@ -31,12 +32,12 @@ extern "C" {
 
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
-#define UART1_DMA_RX_CONFIG                                            \
+#define UART1_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART1_RX_DMA_INSTANCE,                         \
-        .channel = UART1_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART1_RX_DMA_RCC,                               \
-        .dma_irq = UART1_RX_DMA_IRQ,                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request = UART1_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART1_RX_DMA_RCC,                                \
+        .dma_irq = UART1_RX_DMA_IRQ,                                \
     }
 #endif /* UART1_DMA_RX_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */
@@ -54,16 +55,27 @@ extern "C" {
 
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
-#define UART2_DMA_RX_CONFIG                                            \
+#define UART2_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART2_RX_DMA_INSTANCE,                         \
-        .channel = UART2_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART2_RX_DMA_RCC,                               \
-        .dma_irq = UART2_RX_DMA_IRQ,                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request = UART2_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_RX_DMA_RCC,                                \
+        .dma_irq = UART2_RX_DMA_IRQ,                                \
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request = UART2_TX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_TX_DMA_RCC,                                \
+        .dma_irq = UART2_TX_DMA_IRQ,                                \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+    
 #if defined(BSP_USING_UART3)
 #ifndef UART3_CONFIG
 #define UART3_CONFIG                                                \
@@ -77,12 +89,12 @@ extern "C" {
 
 #if defined(BSP_UART3_RX_USING_DMA)
 #ifndef UART3_DMA_RX_CONFIG
-#define UART3_DMA_RX_CONFIG                                            \
+#define UART3_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART3_RX_DMA_INSTANCE,                         \
-        .channel = UART3_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART3_RX_DMA_RCC,                               \
-        .dma_irq = UART3_RX_DMA_IRQ,                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request = UART3_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART3_RX_DMA_RCC,                                \
+        .dma_irq = UART3_RX_DMA_IRQ,                                \
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
@@ -100,12 +112,12 @@ extern "C" {
 
 #if defined(BSP_UART4_RX_USING_DMA)
 #ifndef UART4_DMA_RX_CONFIG
-#define UART4_DMA_RX_CONFIG                                            \
+#define UART4_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART4_RX_DMA_INSTANCE,                         \
-        .channel = UART4_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART4_RX_DMA_RCC,                               \
-        .dma_irq = UART4_RX_DMA_IRQ,                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request = UART4_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART4_RX_DMA_RCC,                                \
+        .dma_irq = UART4_RX_DMA_IRQ,                                \
     }
 #endif /* UART4_DMA_RX_CONFIG */
 #endif /* BSP_UART4_RX_USING_DMA */
@@ -123,12 +135,12 @@ extern "C" {
 
 #if defined(BSP_UART5_RX_USING_DMA)
 #ifndef UART5_DMA_RX_CONFIG
-#define UART5_DMA_RX_CONFIG                                            \
+#define UART5_DMA_RX_CONFIG                                         \
     {                                                               \
-        .Instance = UART5_RX_DMA_INSTANCE,                         \
-        .channel = UART5_RX_DMA_CHANNEL,                           \
-        .dma_rcc = UART5_RX_DMA_RCC,                               \
-        .dma_irq = UART5_RX_DMA_IRQ,                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                          \
+        .request = UART5_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART5_RX_DMA_RCC,                                \
+        .dma_irq = UART5_RX_DMA_IRQ,                                \
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */

bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC1,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC2,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC3,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-02     SummerGift   first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler         DMA1_Channel2_IRQHandler
+#define UART3_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE           DMA1_Channel2
+#define UART3_TX_DMA_IRQ                DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE           DMA1_Channel7
+#define UART2_TX_DMA_IRQ                DMA1_Channel7_IRQn
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
+#define SPI3_RX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_RX_DMA_INSTANCE            DMA2_Channel1
+#define SPI3_RX_DMA_IRQ                 DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
+#define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART4_RX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_RX_DMA_INSTANCE           DMA2_Channel3
+#define UART4_RX_DMA_IRQ                DMA2_Channel3_IRQn
+#endif
+/* DMA2 channel4 */
+/* DMA2 channel5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler         DMA2_Channel4_5_IRQHandler
+#define UART4_TX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_TX_DMA_INSTANCE           DMA2_Channel5
+#define UART4_TX_DMA_IRQ                DMA2_Channel4_5_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                     \
+    {                                             \
+       .tim_handler.Instance     = TIM1,          \
+       .encoder_irqn             = TIM1_UP_IRQn,  \
+       .name                     = "pulse1"       \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM2,       \
+       .encoder_irqn             = TIM2_IRQn,  \
+       .name                     = "pulse2"    \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM3,       \
+       .encoder_irqn             = TIM3_IRQn,  \
+       .name                     = "pulse3"    \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM4,       \
+       .encoder_irqn             = TIM4_IRQn,  \
+       .name                     = "pulse4"    \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32l1xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel4,                \
+        .dma_tx.dma_irq = DMA2_Channel4_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     BalanceTWK   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-07-29     Chinese66    change from f4 to f1
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#define USBD_IRQ_TYPE        USB_LP_IRQn
+#define USBD_IRQ_HANDLER     USB_LP_IRQHandler
+#define USBD_INSTANCE        USB
+#define USBD_PCD_SPEED       PCD_SPEED_FULL
+#define USBD_PCD_PHY_MODULE  PCD_PHY_EMBEDDED
+
+#ifndef BSP_USB_CONNECT_PIN
+#define BSP_USB_CONNECT_PIN  -1
+#endif
+
+#ifndef BSP_USB_PULL_UP_STATUS
+#define BSP_USB_PULL_UP_STATUS  1
+#endif
+#endif

bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h

@@ -61,7 +61,19 @@ extern "C" {
     }
 #endif /* UART1_DMA_RX_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */  
-   
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .request  = UART1_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+
 #if defined(BSP_USING_UART2)
 #ifndef UART2_CONFIG
 #define UART2_CONFIG                                                \
@@ -85,6 +97,18 @@ extern "C" {
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
 
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+
 #if defined(BSP_USING_UART3)
 #ifndef UART3_CONFIG
 #define UART3_CONFIG                                                \
@@ -108,6 +132,18 @@ extern "C" {
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
 
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+
 #ifdef __cplusplus
 }
 #endif 

bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = ADC1,                          \
+       .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV2,      \
+       .Init.Resolution               = ADC_RESOLUTION_12B,            \
+       .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait         = DISABLE,                       \
+       .Init.ContinuousConvMode       = DISABLE,                       \
+       .Init.NbrOfConversion          = 1,                             \
+       .Init.DiscontinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfDiscConversion      = 1,                             \
+       .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+       .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+       .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = ADC2,                          \
+       .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV2,      \
+       .Init.Resolution               = ADC_RESOLUTION_12B,            \
+       .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait         = DISABLE,                       \
+       .Init.ContinuousConvMode       = DISABLE,                       \
+       .Init.NbrOfConversion          = 1,                             \
+       .Init.DiscontinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfDiscConversion      = 1,                             \
+       .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+       .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+       .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = ADC3,                          \
+       .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV2,      \
+       .Init.Resolution               = ADC_RESOLUTION_12B,            \
+       .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait         = DISABLE,                       \
+       .Init.ContinuousConvMode       = DISABLE,                       \
+       .Init.NbrOfConversion          = 1,                             \
+       .Init.DiscontinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfDiscConversion      = 1,                             \
+       .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+       .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+       .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC1_CONFIG */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-20     thread-liu   first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+
+/* DMA1 stream1 */
+
+/* DMA1 stream2 */
+
+/* DMA1 stream3 */
+
+/* DMA1 stream4 */
+
+/* DMA1 stream5 */
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+
+/* DMA2 stream0 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_RX_DMA_IRQHandler          DMA2_Stream0_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART3_RX_DMA_INSTANCE            DMA2_Stream0
+#define UART3_RX_DMA_CHANNEL             DMA_REQUEST_USART3_RX
+#define UART3_RX_DMA_IRQ                 DMA2_Stream0_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI5_RX_DMA_CHANNEL              DMA_REQUEST_SPI5_RX
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+    
+/* DMA2 stream1 */
+#if defined(BSP_UART3_TX_USING_DMA) && !defined(BSP_UART3_TX_USING_INSTANCE)
+#define UART3_TX_DMA_IRQHandler           DMA2_Stream1_IRQHandler
+#define UART3_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define UART3_TX_DMA_INSTANCE             DMA2_Stream1
+#define UART3_TX_DMA_CHANNEL              DMA_REQUEST_USART3_TX
+#define UART3_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI5_TX_DMA_CHANNEL              DMA_REQUEST_SPI5_TX
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_MC_AHB2ENSETR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA2_Stream3_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_RX_DMA_INSTANCE            DMA2_Stream3
+#define UART4_RX_DMA_CHANNEL             DMA_REQUEST_UART4_RX
+#define UART4_RX_DMA_IRQ                 DMA2_Stream3_IRQn        
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define UART4_TX_DMA_INSTANCE            DMA2_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_REQUEST_UART4_TX
+#define UART4_TX_DMA_IRQ                 DMA2_Stream4_IRQn   
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_USING_CRYP) && !defined(CRYP2_OUT_DMA_INSTANCE)
+#define CRYP2_DMA_OUT_IRQHandler           DMA2_Stream5_IRQHandler
+#define CRYP2_OUT_DMA_RCC                  RCC_MC_AHB2ENSETR_DMA2EN
+#define CRYP2_OUT_DMA_INSTANCE             DMA2_Stream5
+#define CRYP2_OUT_DMA_CHANNEL              DMA_REQUEST_CRYP2_OUT
+#define CRYP2_OUT_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_USING_CRYP) && !defined(CRYP2_IN_DMA_INSTANCE)
+#define CRYP2_DMA_IN_IRQHandler          DMA2_Stream6_IRQHandler
+#define CRYP2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define CRYP2_IN_DMA_INSTANCE            DMA2_Stream6
+#define CRYP2_IN_DMA_CHANNEL             DMA_REQUEST_CRYP2_IN
+#define CRYP2_IN_DMA_IRQ                 DMA2_Stream6_IRQn    
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_USING_HASH) && !defined(HASH2_IN_DMA_INSTANCE)
+#define HASH2_DMA_IN_IRQHandler          DMA2_Stream7_IRQHandler
+#define HASH2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
+#define HASH2_IN_DMA_INSTANCE            DMA2_Stream7
+#define HASH2_IN_DMA_CHANNEL             DMA_REQUEST_HASH2_IN
+#define HASH2_IN_DMA_IRQ                 DMA2_Stream7_IRQn  
+#endif
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .request = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .request = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .request = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .request = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .request = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .request = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .request = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .request = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .request = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .request = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .request = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .request = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .request = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .request = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .request = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .request = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .request = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .request = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .request = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .request = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .request = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .request = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h

@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_SPI1_RX
+#else /* for L4 */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#else /* for L4 */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_USART3_RX
+#else /* for L4 */
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_USART1_TX
+#else /* for L4 */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#else /* for L4 */
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#else /* for L4 */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
+#define QSPI_DMA_INSTANCE               DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_OCTOSPI1
+#else /* for L4 */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
+#endif /* DMAMUX1 */
+#define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#else /* for L4 */
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_1
+#endif /* DMAMUX1 */
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#if defined(DMAMUX1) /* for L4+ */
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#else /* for L4 */
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_TX_DMA_INSTANCE           DMA2_Channel1
+#if defined(DMAMUX1) /* for L4+ */
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_UART5_TX
+#else /* for L4 */
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_RX_DMA_INSTANCE           DMA2_Channel2
+#if defined(DMAMUX1) /* for L4+ */
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_UART5_RX
+#else /* for L4 */
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_SPI1_RX
+#else /* for L4 */
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
+#if defined(DMAMUX1) /* for L4+ */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#else /* for L4 */
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
+#endif
+
+/* DMA2 channel5 */
+
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_USART1_TX
+#else /* for L4 */
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#else /* for L4 */
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#endif /* DMAMUX1 */
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE               DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_OCTOSPI1
+#else /* for L4 */
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
+#endif /* DMAMUX1 */
+#define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
+#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA2_Channel7_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHB1ENR_DMA2EN
+#define LPUART1_RX_DMA_INSTANCE         DMA2_Channel7
+#if defined(DMAMUX1) /* for L4+ */
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#else /* for L4 */
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_4
+#endif /* DMAMUX1 */
+#define LPUART1_RX_DMA_IRQ              DMA2_Channel7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+    
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI2,                                   \
+        .bus_name = "spi2",                                 \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI3,                                   \
+        .bus_name = "spi3",                                 \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_TX_DMA_RCC,                         \
+        .Instance = SPI3_TX_DMA_INSTANCE,                   \
+        .request = SPI3_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_RX_DMA_RCC,                         \
+        .Instance = SPI3_RX_DMA_INSTANCE,                   \
+        .request = SPI3_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */  
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .request  = UART1_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_adc.c

@@ -7,7 +7,9 @@
  * Date           Author       Notes
  * 2018-12-05     zylx         first version
  * 2018-12-12     greedyhao    Porting for stm32f7xx
- * 2019-02-01     yuneizhilin   fix the stm32_adc_init function initialization issue
+ * 2019-02-01     yuneizhilin  fix the stm32_adc_init function initialization issue
+ * 2020-06-17     thread-liu   Porting for stm32mp1xx
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include <board.h>
@@ -50,7 +52,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
 
     if (enabled)
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
         ADC_Enable(stm32_adc_handler);
 #else
         __HAL_ADC_ENABLE(stm32_adc_handler);
@@ -58,7 +60,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
     }
     else
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
         ADC_Disable(stm32_adc_handler);
 #else
         __HAL_ADC_DISABLE(stm32_adc_handler);
@@ -122,16 +124,23 @@ static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
     case 15:
         stm32_channel = ADC_CHANNEL_15;
         break;
+#ifdef ADC_CHANNEL_16
     case 16:
         stm32_channel = ADC_CHANNEL_16;
         break;
+#endif
     case 17:
         stm32_channel = ADC_CHANNEL_17;
         break;
-#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#ifdef ADC_CHANNEL_18
     case 18:
         stm32_channel = ADC_CHANNEL_18;
         break;
+#endif
+#ifdef ADC_CHANNEL_19
+    case 19:
+        stm32_channel = ADC_CHANNEL_19;
+        break;
 #endif
     }
 
@@ -150,10 +159,22 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
 
     rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
 
-#if defined(SOC_SERIES_STM32F1)
+#ifndef ADC_CHANNEL_16
+    if (channel == 16)
+    {
+        LOG_E("ADC channel must not be 16.");
+        return -RT_ERROR;
+    }
+#endif
+
+/* ADC channel number is up to 17 */
+#if !defined(ADC_CHANNEL_18)
     if (channel <= 17)
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2)  || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
-        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+/* ADC channel number is up to 19 */
+#elif defined(ADC_CHANNEL_19)
+    if (channel <= 19)
+/* ADC channel number is up to 18 */
+#else
     if (channel <= 18)
 #endif
     {
@@ -162,15 +183,22 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     }
     else
     {
-#if defined(SOC_SERIES_STM32F1)
+#if !defined(ADC_CHANNEL_18)
         LOG_E("ADC channel must be between 0 and 17.");
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2)  || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
-        || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
+#elif defined(ADC_CHANNEL_19)
+        LOG_E("ADC channel must be between 0 and 19.");
+#else
         LOG_E("ADC channel must be between 0 and 18.");
 #endif
         return -RT_ERROR;
     }
+    
+#if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
+    ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
+#else
     ADC_ChanConf.Rank = 1;
+#endif
+    
 #if defined(SOC_SERIES_STM32F0)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
 #elif defined(SOC_SERIES_STM32F1)
@@ -179,16 +207,44 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
 #elif defined(SOC_SERIES_STM32L4)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
+#elif defined(SOC_SERIES_STM32MP1)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
+#elif defined(SOC_SERIES_STM32H7)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_64CYCLES_5;
+    #elif defined (SOC_SERIES_STM32WB)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
 #endif
-#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.Offset = 0;
 #endif
-#ifdef SOC_SERIES_STM32L4
+
+#if defined(SOC_SERIES_STM32L4)
     ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
     ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
+    ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;  /* ADC channel affected to offset number */
+    ADC_ChanConf.Offset       = 0; 
+    ADC_ChanConf.SingleDiff   = ADC_SINGLE_ENDED; /* ADC channel differential mode */
 #endif
     HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
 
+    /* perform an automatic ADC calibration to improve the conversion accuracy */
+#if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
+    if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_ChanConf.SingleDiff) != HAL_OK)
+    {
+        LOG_E("ADC calibration error!\n");
+        return -RT_ERROR;
+    }
+#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+    /* Run the ADC linear calibration in single-ended mode */
+    if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_ChanConf.SingleDiff) != HAL_OK)
+    {
+        LOG_E("ADC open linear calibration error!\n");
+        /* Calibration Error */
+        return -RT_ERROR;
+    }
+#endif
     /* start ADC */
     HAL_ADC_Start(stm32_adc_handler);
 

bsp/stm32/libraries/HAL_Drivers/drv_can.c

@@ -59,6 +59,19 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
     {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 150)},
     {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ  | CAN_BS2_7TQ | 300)}
 };
+#elif defined (SOC_SERIES_STM32L4)/* APB1 80MHz(max) */
+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ  | CAN_BS2_2TQ | 10)},
+    {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_14TQ  | CAN_BS2_5TQ | 5)},
+    {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_7TQ  | CAN_BS2_2TQ | 16)},
+    {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 20)},
+    {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 40)},
+    {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 50)},
+    {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 100)},
+    {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 250)},
+    {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ  | CAN_BS2_2TQ | 500)}
+};
 #endif
 
 #ifdef BSP_USING_CAN1
@@ -688,9 +701,9 @@ void CAN1_SCE_IRQHandler(void)
         drv_can1.device.status.ackerrcnt++;
         if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
             rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
-        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
             rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
-        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+        else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
             rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
         break;
     case RT_CAN_BUS_IMPLICIT_BIT_ERR:
@@ -806,11 +819,11 @@ void CAN2_SCE_IRQHandler(void)
         break;
     case RT_CAN_BUS_ACK_ERR:
         drv_can2.device.status.ackerrcnt++;
-        if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+        if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
             rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
-        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
             rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
-        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
+        else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
             rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
         break;
     case RT_CAN_BUS_IMPLICIT_BIT_ERR:

bsp/stm32/libraries/HAL_Drivers/drv_common.c

@@ -29,11 +29,15 @@ void rt_hw_systick_init(void)
 {
 #if defined (SOC_SERIES_STM32H7)
     HAL_SYSTICK_Config((HAL_RCCEx_GetD1SysClockFreq()) / RT_TICK_PER_SECOND);
+#elif defined (SOC_SERIES_STM32MP1)
+    HAL_SYSTICK_Config(HAL_RCC_GetSystemCoreClockFreq() / RT_TICK_PER_SECOND);
 #else
     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
 #endif
+#if !defined (SOC_SERIES_STM32MP1)
     HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-    HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+#endif
+    NVIC_SetPriority(SysTick_IRQn, 0xFF);
 }
 
 /**
@@ -54,7 +58,7 @@ void SysTick_Handler(void)
 
 uint32_t HAL_GetTick(void)
 {
-    return rt_tick_get() * 1000 / RT_TICK_PER_SECOND;
+    return rt_tick_get_millisecond();
 }
 
 void HAL_SuspendTick(void)
@@ -67,6 +71,17 @@ void HAL_ResumeTick(void)
 
 void HAL_Delay(__IO uint32_t Delay)
 {
+    if (rt_thread_self())
+    {
+        rt_thread_mdelay(Delay);
+    }
+    else
+    {
+        for (rt_uint32_t count = 0; count < Delay; count++)
+        {
+            rt_hw_us_delay(1000);
+        }
+    }
 }
 
 /* re-implement tick interface for STM32 HAL */
@@ -85,7 +100,7 @@ void _Error_Handler(char *s, int num)
 {
     /* USER CODE BEGIN Error_Handler */
     /* User can add his own implementation to report the HAL error return state */
-    while(1)
+    while (1)
     {
     }
     /* USER CODE END Error_Handler */
@@ -102,10 +117,12 @@ void rt_hw_us_delay(rt_uint32_t us)
     start = SysTick->VAL;
     reload = SysTick->LOAD;
     us_tick = SystemCoreClock / 1000000UL;
-    do {
+    do
+    {
         now = SysTick->VAL;
-        delta = start > now ? start - now : reload + start - now;
-    } while(delta < us_tick * us);
+        delta = start >= now ? start - now : reload + start - now;
+    }
+    while (delta < us_tick * us);
 }
 
 /**

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author            Notes
  * 2018-10-30     SummerGift        first version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
  
 #ifndef __DRV_CONFIG_H__
@@ -50,6 +51,7 @@ extern "C" {
 #include "f4/qspi_config.h"
 #include "f4/usbd_config.h"
 #include "f4/adc_config.h"
+#include "f4/dac_config.h"
 #include "f4/tim_config.h"
 #include "f4/sdio_config.h"
 #include "f4/pwm_config.h"
@@ -72,6 +74,7 @@ extern "C" {
 #include "l4/spi_config.h"
 #include "l4/qspi_config.h"
 #include "l4/adc_config.h"
+#include "l4/dac_config.h"
 #include "l4/tim_config.h"
 #include "l4/sdio_config.h"
 #include "l4/pwm_config.h"
@@ -100,10 +103,29 @@ extern "C" {
 #include "h7/spi_config.h"
 #include "h7/qspi_config.h"
 #include "h7/adc_config.h"
+#include "h7/dac_config.h"
 #include "h7/tim_config.h"
 #include "h7/sdio_config.h"
 #include "h7/pwm_config.h"
 #include "h7/usbd_config.h"
+#elif  defined(SOC_SERIES_STM32MP1)
+#include "mp1/dma_config.h"
+#include "mp1/uart_config.h"
+#include "mp1/qspi_config.h"
+#include "mp1/spi_config.h"
+#include "mp1/adc_config.h"
+#include "mp1/dac_config.h"    
+#include "mp1/tim_config.h"
+#include "mp1/pwm_config.h"    
+#elif  defined(SOC_SERIES_STM32WB)
+#include "wb/adc_config.h"
+#include "wb/dma_config.h"
+#include "wb/pwm_config.h"
+#include "wb/qspi_config.h" 
+#include "wb/spi_config.h"
+#include "wb/tim_config.h"
+#include "wb/uart_config.h"
+#include "wb/usbd_config.h"
 #endif
 
 #ifdef __cplusplus

bsp/stm32/libraries/HAL_Drivers/drv_crypto.c

@@ -6,6 +6,10 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-07-10     Ernest       1st version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
+ * 2020-11-26     thread-liu   add hash
+ * 2020-11-26     thread-liu   add cryp
+ * 2020-12-11     WKJay        fix build problem
  */
 
 #include <rtthread.h>
@@ -14,7 +18,8 @@
 #include <string.h>
 #include "drv_crypto.h"
 #include "board.h"
-
+#include "drv_config.h"
+     
 struct stm32_hwcrypto_device
 {
     struct rt_hwcrypto_device dev;
@@ -23,12 +28,7 @@ struct stm32_hwcrypto_device
 
 #if defined(BSP_USING_CRC)
 
-struct hash_ctx_des
-{
-    CRC_HandleTypeDef contex;
-};
-
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1)
 static struct hwcrypto_crc_cfg  crc_backup_cfg;
 
 static int reverse_bit(rt_uint32_t n)
@@ -48,12 +48,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
     rt_uint32_t result = 0;
     struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
 
-#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1)
     CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex);
 #endif
 
     rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1)
     if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
     {
         if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE)
@@ -112,7 +112,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
 
     result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length);
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1)
     if (HW_TypeDef->Init.OutputDataInversionMode)
     {
         ctx ->crc_cfg.last_val = reverse_bit(result);
@@ -148,7 +148,7 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
     {
         return gen_random ;
     }
-
+    
     return 0;
 }
 
@@ -158,18 +158,229 @@ static const struct hwcrypto_rng_ops rng_ops =
 };
 #endif /* BSP_USING_RNG */
 
+#if defined(BSP_USING_HASH)
+static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_uint32_t tickstart = 0;
+    rt_uint32_t result = RT_EOK;
+    struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
+    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);    
+    
+#if defined(SOC_SERIES_STM32MP1)
+    HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex);
+    /* Start HASH computation using DMA transfer */
+    switch (ctx->parent.type)
+    {
+    case HWCRYPTO_TYPE_SHA224:
+       result = HAL_HASHEx_SHA224_Start_DMA(HW_TypeDef, (uint8_t *)in, length);
+       break;
+    case HWCRYPTO_TYPE_SHA256:
+       result = HAL_HASHEx_SHA256_Start_DMA(HW_TypeDef, (uint8_t *)in, length);
+       break;
+    case HWCRYPTO_TYPE_MD5:
+       result = HAL_HASH_MD5_Start_DMA(HW_TypeDef, (uint8_t *)in, length);
+       break;
+    case HWCRYPTO_TYPE_SHA1:
+       result = HAL_HASH_SHA1_Start_DMA(HW_TypeDef, (uint8_t *)in, length);
+       break;
+    default :
+        rt_kprintf("not support hash type: %x", ctx->parent.type);
+        break;
+    }
+    if (result != HAL_OK)
+    {
+        goto _exit;
+    }
+    /* Wait for DMA transfer to complete */ 
+    tickstart = rt_tick_get();
+    while (HAL_HASH_GetState(HW_TypeDef) == HAL_HASH_STATE_BUSY)
+    {
+        if (rt_tick_get() - tickstart > 0xFFFF)
+        {
+            result = RT_ETIMEOUT;
+            goto _exit;
+        }
+    }
+    
+#endif
+_exit:
+    rt_mutex_release(&stm32_hw_dev->mutex);
+        
+   return  result;
+}
+
+static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size_t length)
+{
+    rt_uint32_t result = RT_EOK;
+    struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
+    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
+#if defined(SOC_SERIES_STM32MP1)
+    HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex);
+    /* Get the computed digest value */
+    switch (ctx->parent.type)
+    {
+    case HWCRYPTO_TYPE_SHA224:
+       result = HAL_HASHEx_SHA224_Finish(HW_TypeDef, (uint8_t *)out, length);
+       break;
+
+    case HWCRYPTO_TYPE_SHA256:
+       result = HAL_HASHEx_SHA256_Finish(HW_TypeDef, (uint8_t *)out, length);
+       break;
+
+    case HWCRYPTO_TYPE_MD5:
+       result = HAL_HASH_MD5_Finish(HW_TypeDef, (uint8_t *)out, length);
+       break;
+
+    case HWCRYPTO_TYPE_SHA1:
+       result = HAL_HASH_SHA1_Finish(HW_TypeDef, (uint8_t *)out, length);
+       break;
+
+    default :
+        rt_kprintf("not support hash type: %x", ctx->parent.type);
+        break;
+    }
+    if (result != HAL_OK)
+    {
+        goto _exit;
+    }
+#endif    
+    
+_exit:
+    rt_mutex_release(&stm32_hw_dev->mutex);
+    
+    return result;     
+}
+
+static const struct hwcrypto_hash_ops hash_ops =
+{
+    .update = _hash_update,
+    .finish  = _hash_finish
+};
+
+#endif /* BSP_USING_HASH */
+
+#if defined(BSP_USING_CRYP) 
+static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
+                            struct hwcrypto_symmetric_info *info)
+{
+    rt_uint32_t result = RT_EOK;
+    rt_uint32_t tickstart = 0;
+
+    struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
+    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
+    
+#if defined(SOC_SERIES_STM32MP1)
+    CRYP_HandleTypeDef *HW_TypeDef = (CRYP_HandleTypeDef *)(ctx->parent.contex);
+    
+    switch (ctx->parent.type)
+    {
+    case HWCRYPTO_TYPE_AES_ECB:
+       HW_TypeDef->Init.Algorithm = CRYP_AES_ECB;
+       break;
+
+    case HWCRYPTO_TYPE_AES_CBC:
+       HW_TypeDef->Init.Algorithm = CRYP_AES_CBC;
+       break;
+
+    case HWCRYPTO_TYPE_AES_CTR:
+       HW_TypeDef->Init.Algorithm = CRYP_AES_CTR;
+       break;
+
+    case HWCRYPTO_TYPE_DES_ECB:
+       HW_TypeDef->Init.Algorithm = CRYP_DES_ECB; 
+       break;
+       
+    case HWCRYPTO_TYPE_DES_CBC:
+       HW_TypeDef->Init.Algorithm = CRYP_DES_CBC; 
+       break;
+       
+    default :
+        rt_kprintf("not support cryp type: %x", ctx->parent.type);
+        break; 
+    }
+    
+    HAL_CRYP_DeInit(HW_TypeDef);
+    
+    HW_TypeDef->Init.DataType       = CRYP_DATATYPE_8B;
+    HW_TypeDef->Init.DataWidthUnit  = CRYP_DATAWIDTHUNIT_BYTE;
+    HW_TypeDef->Init.KeySize        = CRYP_KEYSIZE_128B;
+    HW_TypeDef->Init.pKey           = (uint32_t*)ctx->key;
+    
+    result =  HAL_CRYP_Init(HW_TypeDef);
+    if (result != HAL_OK)
+    {
+        /* Initialization Error */
+        goto _exit;
+    }
+    if (info->mode == HWCRYPTO_MODE_ENCRYPT)
+    {
+         result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); 
+    }
+    else if (info->mode == HWCRYPTO_MODE_DECRYPT)
+    {
+         result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);   
+    }
+    else
+    {
+        rt_kprintf("error cryp mode : %02x!\n", info->mode);
+        result = RT_ERROR;
+        goto _exit;
+    }
+    
+    if (result != HAL_OK)
+    {
+        goto _exit;
+    }
+
+    tickstart = rt_tick_get();
+    while (HAL_CRYP_GetState(HW_TypeDef) != HAL_CRYP_STATE_READY)
+    {   
+        if (rt_tick_get() - tickstart > 0xFFFF)
+        {
+            result = RT_ETIMEOUT;
+            goto _exit;
+        }
+    }
+  
+#endif
+    
+    if (result != HAL_OK)
+    {
+        goto _exit;
+    }
+    
+_exit:
+    rt_mutex_release(&stm32_hw_dev->mutex);
+
+    return result;    
+}
+
+static const struct hwcrypto_symmetric_ops cryp_ops = 
+{
+    .crypt = _cryp_crypt
+};
+#endif
+
 static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
 {
     rt_err_t res = RT_EOK;
-
+    
     switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
     {
 #if defined(BSP_USING_RNG)
     case HWCRYPTO_TYPE_RNG:
     {
         RNG_HandleTypeDef *hrng = rt_calloc(1, sizeof(RNG_HandleTypeDef));
-
+        if (RT_NULL == hrng)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+#if defined(SOC_SERIES_STM32MP1)
+        hrng->Instance = RNG2;
+#else
         hrng->Instance = RNG;
+#endif
         HAL_RNG_Init(hrng);
         ctx->contex = hrng;
         ((struct hwcrypto_rng *)ctx)->ops = &rng_ops;
@@ -187,9 +398,12 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
             res = -RT_ERROR;
             break;
         }
-
+#if defined(SOC_SERIES_STM32MP1)
+        hcrc->Instance = CRC2;
+#else
         hcrc->Instance = CRC;
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#endif
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32MP1)
         hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
         hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;
         hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE;
@@ -203,9 +417,77 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
 #endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
         ctx->contex = hcrc;
         ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
+        
         break;
     }
 #endif /* BSP_USING_CRC */
+    
+#if defined(BSP_USING_HASH)
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+    case HWCRYPTO_TYPE_SHA2:
+    {
+        HASH_HandleTypeDef *hash = rt_calloc(1, sizeof(HASH_HandleTypeDef));
+        if (RT_NULL == hash)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+#if defined(SOC_SERIES_STM32MP1)
+        /* enable dma for hash */
+        __HAL_RCC_DMA2_CLK_ENABLE();
+        HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 0);
+        HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 
+
+        hash->Init.DataType = HASH_DATATYPE_8B;
+        if (HAL_HASH_Init(hash) != HAL_OK)
+        {
+            res = -RT_ERROR;
+        } 
+#endif
+        ctx->contex = hash;
+        ((struct hwcrypto_hash *)ctx)->ops = &hash_ops;
+        
+        break;  
+    }
+#endif /* BSP_USING_HASH */
+
+#if defined(BSP_USING_CRYP)
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_DES:
+    case HWCRYPTO_TYPE_3DES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_GCM:
+    {
+        CRYP_HandleTypeDef *cryp = rt_calloc(1, sizeof(CRYP_HandleTypeDef));
+        if (RT_NULL == cryp)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+#if defined(SOC_SERIES_STM32MP1)
+        cryp->Instance = CRYP2;
+        /* enable dma for cryp */
+        __HAL_RCC_DMA2_CLK_ENABLE();
+
+        HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0);
+        HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
+
+        HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 2, 0);
+        HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
+
+        if (HAL_CRYP_Init(cryp) != HAL_OK)
+        {
+            res = -RT_ERROR;
+        }
+#endif  
+        ctx->contex = cryp;
+        ((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops;
+
+        break;  
+    }
+#endif  /* BSP_USING_CRYP */
+    
     default:
         res = -RT_ERROR;
         break;
@@ -228,6 +510,26 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
         HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex));
         break;
 #endif /* BSP_USING_CRC */
+        
+#if defined(BSP_USING_HASH)
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+    case HWCRYPTO_TYPE_SHA2:
+        __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex));
+        HAL_HASH_DeInit((HASH_HandleTypeDef *)(ctx->contex));
+        break;
+#endif /* BSP_USING_HASH */
+
+#if defined(BSP_USING_CRYP)
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_DES:
+    case HWCRYPTO_TYPE_3DES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_GCM:
+         HAL_CRYP_DeInit((CRYP_HandleTypeDef *)(ctx->contex));
+         break;
+#endif /* BSP_USING_CRYP */
+             
     default:
         break;
     }
@@ -245,7 +547,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
     case HWCRYPTO_TYPE_RNG:
         if (des->contex && src->contex)
         {
-            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+            rt_memcpy(des->contex, src->contex, sizeof(RNG_HandleTypeDef));
         }    
         break;
 #endif /* BSP_USING_RNG */
@@ -254,10 +556,35 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
     case HWCRYPTO_TYPE_CRC:
         if (des->contex && src->contex)
         {
-            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+            rt_memcpy(des->contex, src->contex, sizeof(CRC_HandleTypeDef));
         }
         break;
 #endif /* BSP_USING_CRC */
+        
+#if defined(BSP_USING_HASH)
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+    case HWCRYPTO_TYPE_SHA2:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(HASH_HandleTypeDef));
+        } 
+        break;
+#endif /* BSP_USING_HASH */
+
+#if defined(BSP_USING_CRYP)
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_DES:
+    case HWCRYPTO_TYPE_3DES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_GCM:    
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(CRYP_HandleTypeDef));
+        } 
+        break;
+#endif /* BSP_USING_CRYP */
+        
     default:
         res = -RT_ERROR;
         break;
@@ -279,11 +606,74 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
         __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
         break;
 #endif /* BSP_USING_CRC */
+        
+#if defined(BSP_USING_HASH)
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+    case HWCRYPTO_TYPE_SHA2:
+        __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex));
+        break;
+#endif /* BSP_USING_HASH*/
+        
+#if defined(BSP_USING_CRYP)
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_DES:
+    case HWCRYPTO_TYPE_3DES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_GCM:  
+        break;
+#endif /* BSP_USING_CRYP */
+        
     default:
         break;
     }
 }
 
+#if defined(HASH2_IN_DMA_INSTANCE)
+void HASH2_DMA_IN_IRQHandler(void)
+{
+    extern DMA_HandleTypeDef hdma_hash_in;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    
+    HAL_DMA_IRQHandler(&hdma_hash_in);
+    
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(CRYP2_IN_DMA_INSTANCE)
+void CRYP2_DMA_IN_IRQHandler(void)
+{   
+    extern DMA_HandleTypeDef hdma_cryp_in;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    
+    HAL_DMA_IRQHandler(&hdma_cryp_in);
+    
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined (CRYP2_OUT_DMA_INSTANCE)
+void CRYP2_DMA_OUT_IRQHandler(void)
+{
+    extern DMA_HandleTypeDef hdma_cryp_out;
+    
+    /* enter interrupt */
+    rt_interrupt_enter();
+    
+    HAL_DMA_IRQHandler(&hdma_cryp_out);
+    
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
 static const struct rt_hwcrypto_ops _ops =
 {
     .create = _crypto_create,
@@ -300,10 +690,10 @@ int stm32_hw_crypto_device_init(void)
     _crypto_dev.dev.ops = &_ops;
 #if defined(BSP_USING_UDID)
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 
     cpuid[0] = HAL_GetUIDw0();
     cpuid[1] = HAL_GetUIDw1();
-#elif defined(SOC_SERIES_STM32H7)
+#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
     cpuid[0] = HAL_GetREVID();
     cpuid[1] = HAL_GetDEVID();
 #endif

bsp/stm32/libraries/HAL_Drivers/drv_dac.c

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-06-18     thread-liu        the first version
+ * 2020-10-09     thread-liu   Porting for stm32h7xx
+ */
+
+#include <board.h>
+
+#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2) 
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.dac"
+#include <drv_log.h>
+
+static DAC_HandleTypeDef dac_config[] =
+{
+#ifdef BSP_USING_DAC1
+    DAC1_CONFIG,
+#endif
+    
+#ifdef BSP_USING_DAC2
+    DAC2_CONFIG,
+#endif
+};
+
+struct stm32_dac
+{
+    DAC_HandleTypeDef DAC_Handler;
+    struct rt_dac_device stm32_dac_device;
+};
+
+static struct stm32_dac stm32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
+
+static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    DAC_HandleTypeDef *stm32_dac_handler;
+    RT_ASSERT(device != RT_NULL);
+    stm32_dac_handler = device->parent.user_data;
+
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+        HAL_DAC_Start(stm32_dac_handler, channel);
+#endif
+    
+    return RT_EOK;
+}
+
+static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    DAC_HandleTypeDef *stm32_dac_handler;
+    RT_ASSERT(device != RT_NULL);
+    stm32_dac_handler = device->parent.user_data;
+    
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+    HAL_DAC_Stop(stm32_dac_handler, channel);
+#endif
+    
+    return RT_EOK;
+}
+
+static rt_uint32_t stm32_dac_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t stm32_channel = 0;
+
+    switch (channel)
+    {
+    case  1:
+        stm32_channel = DAC_CHANNEL_1;
+        break;
+    case  2:
+        stm32_channel = DAC_CHANNEL_2;
+        break;
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+
+    return stm32_channel;
+}
+
+static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    uint32_t dac_channel;
+    DAC_ChannelConfTypeDef DAC_ChanConf;	
+    DAC_HandleTypeDef *stm32_dac_handler;
+   
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    stm32_dac_handler = device->parent.user_data;
+
+    rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
+    
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+    if ((channel <= 2) && (channel > 0))
+    {
+        /* set stm32 dac channel */
+        dac_channel =  stm32_dac_get_channel(channel);
+    }
+    else
+    {
+      LOG_E("dac channel must be 1 or 2.");  
+      return -RT_ERROR;
+    }
+#endif  
+    
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+    DAC_ChanConf.DAC_Trigger      = DAC_TRIGGER_NONE;             
+    DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
+#endif    
+    /* config dac out channel*/
+    if (HAL_DAC_ConfigChannel(stm32_dac_handler, &DAC_ChanConf, dac_channel) != HAL_OK)
+    {
+        LOG_D("Config dac out channel Error!\n");
+        return -RT_ERROR;
+    }
+    /* set dac channel out value*/
+    if (HAL_DAC_SetValue(stm32_dac_handler, dac_channel, DAC_ALIGN_12B_R, *value) != HAL_OK)
+    {
+        LOG_D("Setting dac channel out value Error!\n");
+        return -RT_ERROR;
+    }
+    /* start dac */
+    if (HAL_DAC_Start(stm32_dac_handler, dac_channel) != HAL_OK)
+    {
+        LOG_D("Start dac Error!\n");
+        return -RT_ERROR;
+    }
+  
+    return RT_EOK;
+}
+
+static const struct rt_dac_ops stm_dac_ops =
+{
+    .disabled = stm32_dac_disabled,
+    .enabled  = stm32_dac_enabled,
+    .convert  = stm32_set_dac_value,
+};
+
+static int stm32_dac_init(void)
+{
+    int result = RT_EOK;
+    /* save dac name */
+    char name_buf[5] = {'d', 'a', 'c', '0', 0};
+    int i = 0;
+
+    for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
+    {
+        /* dac init */
+        name_buf[3] = '0';
+        stm32_dac_obj[i].DAC_Handler = dac_config[i];
+#if defined(DAC1)
+        if (stm32_dac_obj[i].DAC_Handler.Instance == DAC1)
+        {
+            name_buf[3] = '1';
+        }
+#endif
+#if defined(DAC2)
+        if (stm32_dac_obj[i].dac_Handler.Instance == DAC2)
+        {
+            name_buf[3] = '2';
+        }
+#endif
+        if (HAL_DAC_Init(&stm32_dac_obj[i].DAC_Handler) != HAL_OK)
+        {
+            LOG_E("%s init failed", name_buf);
+            result = -RT_ERROR;
+        }
+        else
+        {
+            /* register dac device */
+            if (rt_hw_dac_register(&stm32_dac_obj[i].stm32_dac_device, name_buf, &stm_dac_ops, &stm32_dac_obj[i].DAC_Handler) == RT_EOK)
+            {
+                LOG_D("%s init success", name_buf);
+            }
+            else
+            {
+                LOG_E("%s register failed", name_buf);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+    return result;
+}
+INIT_DEVICE_EXPORT(stm32_dac_init);
+
+#endif /* BSP_USING_DAC */

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-10     SummerGift   first version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #ifndef __DRV_DMA_H_
@@ -19,10 +20,10 @@ extern "C" {
 #endif
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
-	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
-	|| defined(SOC_SERIES_STM32H7)
+	|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
 
@@ -35,7 +36,8 @@ struct dma_config {
     rt_uint32_t channel;
 #endif
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
     rt_uint32_t request;
 #endif
 };

bsp/stm32/libraries/HAL_Drivers/drv_eth.c

@@ -19,7 +19,7 @@
 
 /*
 * Emac driver uses CubeMX tool to generate emac and phy's configuration,
-* the configuration files can be found in CubeMX_Config floder.
+* the configuration files can be found in CubeMX_Config folder.
 */
 
 /* debug option */
@@ -248,7 +248,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
 
     /* Prepare transmit descriptors to give to DMA */
     /* TODO Optimize data send speed*/
-    LOG_D("transmit frame lenth :%d", framelength);
+    LOG_D("transmit frame length :%d", framelength);
 
     /* wait for unlocked */
     while (EthHandle.Lock == HAL_LOCKED);
@@ -411,11 +411,11 @@ static void phy_linkchange()
 
     if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
     {
-        rt_uint32_t SR;
+        rt_uint32_t SR = 0;
 
         phy_speed_new |= PHY_LINK;
 
-        SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
+        HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
         LOG_D("phy control status reg is 0x%X", SR);
 
         if (PHY_Status_SPEED_100M(SR))

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c

@@ -6,6 +6,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-12-5      SummerGift   first version
+ * 2020-03-05     redoc        support stm32f103vg
+ *
  */
 
 #include "board.h"
@@ -122,16 +124,17 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 }
 
 /**
- * Erase data on flash.
+ * Erase data on flash with bank.
  * @note This operation is irreversible.
  * @note This operation's units is different which on many chips.
  *
+ * @param bank flash bank
  * @param addr flash address
  * @param size erase bytes size
  *
  * @return result
  */
-int stm32_flash_erase(rt_uint32_t addr, size_t size)
+int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
 {
     rt_err_t result = RT_EOK;
     uint32_t PAGEError = 0;
@@ -151,7 +154,8 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
     EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
     EraseInitStruct.PageAddress = GetPage(addr);
     EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
-
+    EraseInitStruct.Banks       = bank;
+    
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
     {
         result = -RT_ERROR;
@@ -170,6 +174,78 @@ __exit:
     return size;
 }
 
+/**
+ * Erase data on flash .
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(rt_uint32_t addr, size_t size)
+{
+#if defined(FLASH_BANK2_END)    
+    rt_err_t result = RT_EOK;   
+    rt_uint32_t addr_bank1 = 0;
+    rt_uint32_t size_bank1 = 0;
+    rt_uint32_t addr_bank2 = 0;
+    rt_uint32_t size_bank2 = 0;
+
+    if((addr + size) <= FLASH_BANK1_END)
+    {
+        addr_bank1 = addr;
+        size_bank1 = size;
+        size_bank2 = 0;
+    }
+    else if(addr > FLASH_BANK1_END)
+    {
+        size_bank1 = 0;
+        addr_bank2 = addr;
+        size_bank2 = size; 
+    }
+    else
+    {
+        addr_bank1 = addr;
+        size_bank1 = FLASH_BANK1_END + 1 - addr_bank1;
+        addr_bank2 = FLASH_BANK1_END + 1;
+        size_bank2 = addr + size - (FLASH_BANK1_END + 1);
+    }
+
+    if(size_bank1)
+    {
+        LOG_D("bank1: addr (0x%p), size %d", (void *)addr_bank1, size_bank1);
+        if(size_bank1 != stm32_flash_erase_bank(FLASH_BANK_1, addr_bank1, size_bank1))
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+    
+    if(size_bank2)
+    {
+        LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
+        if(size_bank2 != stm32_flash_erase_bank(FLASH_BANK_2, addr_bank2, size_bank2))
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+__exit:    
+    if(result != RT_EOK)
+    {
+        return result;
+    }
+    
+    return size_bank1 + size_bank2;
+#else
+    return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
+#endif
+}
+
+
 #if defined(PKG_USING_FAL)
 
 static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c

@@ -211,6 +211,8 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 {
     rt_err_t result      = RT_EOK;
     rt_uint32_t end_addr = addr + size;
+    rt_uint32_t written_size = 0;
+    rt_uint32_t write_size = 0;
 
     if ((end_addr) > STM32_FLASH_END_ADDRESS)
     {
@@ -227,22 +229,61 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
 
-    for (size_t i = 0; i < size; i++, addr++, buf++)
+    while (written_size < size)
     {
-        /* write data to flash */
-        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr, (rt_uint64_t)(*buf)) == HAL_OK)
+        if (((addr + written_size) % 4 == 0) && (size - written_size >= 4))
         {
-            if (*(rt_uint8_t *)addr != *buf)
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr + written_size, *((rt_uint32_t *)(buf + written_size))) == HAL_OK)
+            {
+                if (*(rt_uint32_t *)(addr + written_size) != *(rt_uint32_t *)(buf + written_size))
+                {
+                    result = -RT_ERROR;
+                    break;
+                }
+            }
+            else
             {
                 result = -RT_ERROR;
                 break;
             }
+            write_size = 4;
+        }
+        else if (((addr + written_size) % 2 == 0) && (size - written_size >= 2))
+        {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, addr + written_size, *((rt_uint16_t *)(buf + written_size))) == HAL_OK)
+            {
+                if (*(rt_uint16_t *)(addr + written_size) != *(rt_uint16_t *)(buf + written_size))
+                {
+                    result = -RT_ERROR;
+                    break;
+                }
+            }
+            else
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            write_size = 2;
         }
         else
         {
-            result = -RT_ERROR;
-            break;
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr + written_size, *((rt_uint8_t *)(buf + written_size))) == HAL_OK)
+            {
+                if (*(rt_uint8_t *)(addr + written_size) != *(rt_uint8_t *)(buf + written_size))
+                {
+                    result = -RT_ERROR;
+                    break;
+                }
+            }
+            else
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            write_size = 1;
         }
+
+        written_size += write_size;
     }
 
     HAL_FLASH_Lock();
@@ -277,6 +318,11 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
         return -RT_EINVAL;
     }
 
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
     /*Variable used for Erase procedure*/
     FLASH_EraseInitTypeDef EraseInitStruct;
 

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-12-5      SummerGift   first version
  * 2019-3-2       jinsheng     add Macro judgment
+ * 2020-1-6       duminmin     support single bank mode
  */
 
 #include "board.h"
@@ -22,32 +23,6 @@
 //#define DRV_DEBUG
 #define LOG_TAG                "drv.flash"
 #include <drv_log.h>
-#if defined (FLASH_OPTCR_nDBANK)
-#define ADDR_FLASH_SECTOR_0     ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_1     ((rt_uint32_t)0x08004000) /* Base address of Sector 1, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_2     ((rt_uint32_t)0x08008000) /* Base address of Sector 2, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_3     ((rt_uint32_t)0x0800C000) /* Base address of Sector 3, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_4     ((rt_uint32_t)0x08010000) /* Base address of Sector 4, 64 Kbytes */
-#define ADDR_FLASH_SECTOR_5     ((rt_uint32_t)0x08020000) /* Base address of Sector 5, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_6     ((rt_uint32_t)0x08040000) /* Base address of Sector 6, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_7     ((rt_uint32_t)0x08060000) /* Base address of Sector 7, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_8     ((rt_uint32_t)0x08080000) /* Base address of Sector 8, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_9     ((rt_uint32_t)0x080A0000) /* Base address of Sector 9, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_10    ((rt_uint32_t)0x080C0000) /* Base address of Sector 10, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_11    ((rt_uint32_t)0x080E0000) /* Base address of Sector 11, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_12    ((rt_uint32_t)0x08100000) /* Base address of Sector 12, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_13    ((rt_uint32_t)0x08104000) /* Base address of Sector 13, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_14    ((rt_uint32_t)0x08108000) /* Base address of Sector 14, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_15    ((rt_uint32_t)0x0810C000) /* Base address of Sector 15, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_16    ((rt_uint32_t)0x08110000) /* Base address of Sector 16, 64 Kbytes */
-#define ADDR_FLASH_SECTOR_17    ((rt_uint32_t)0x08120000) /* Base address of Sector 17, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_18    ((rt_uint32_t)0x08140000) /* Base address of Sector 18, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_19    ((rt_uint32_t)0x08160000) /* Base address of Sector 19, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_20    ((rt_uint32_t)0x08180000) /* Base address of Sector 20, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_21    ((rt_uint32_t)0x081A0000) /* Base address of Sector 21, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_22    ((rt_uint32_t)0x081C0000) /* Base address of Sector 22, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_23    ((rt_uint32_t)0x081E0000) /* Base address of Sector 23, 128 Kbytes */
-#else
 #define ADDR_FLASH_SECTOR_0     ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */
 #define ADDR_FLASH_SECTOR_1     ((rt_uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */
 #define ADDR_FLASH_SECTOR_2     ((rt_uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */
@@ -60,7 +35,6 @@
 #define ADDR_FLASH_SECTOR_9     ((rt_uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */
 #define ADDR_FLASH_SECTOR_10    ((rt_uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */
 #define ADDR_FLASH_SECTOR_11    ((rt_uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */
-#endif
 /**
   * @brief  Gets the sector of a given address
   * @param  None
@@ -68,116 +42,73 @@
   */
 static rt_uint32_t GetSector(rt_uint32_t Address)
 {
-    rt_uint32_t sector = 0;
+    uint32_t sector = 0;
+  
 #if defined (FLASH_OPTCR_nDBANK)
-    if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
-    {
-        sector = FLASH_SECTOR_0;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
-    {
-        sector = FLASH_SECTOR_1;
-    }
-#if (FLASH_SECTOR_TOTAL >= 4)    
-    else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
-    {
-        sector = FLASH_SECTOR_2;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
-    {
-        sector = FLASH_SECTOR_3;
-    }
-#elif (FLASH_SECTOR_TOTAL >= 8)    
-    else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
-    {
-        sector = FLASH_SECTOR_4;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
-    {
-        sector = FLASH_SECTOR_5;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
-    {
-        sector = FLASH_SECTOR_6;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
-    {
-        sector = FLASH_SECTOR_7;
-    }
-#elif (FLASH_SECTOR_TOTAL >= 24)
-    else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
-    {
-        sector = FLASH_SECTOR_8;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
-    {
-        sector = FLASH_SECTOR_9;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
-    {
-        sector = FLASH_SECTOR_10;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
-    {
-        sector = FLASH_SECTOR_11;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
-    {
-        sector = FLASH_SECTOR_12;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13))
-    {
-        sector = FLASH_SECTOR_13;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14))
-    {
-        sector = FLASH_SECTOR_14;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15))
-    {
-        sector = FLASH_SECTOR_15;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16))
-    {
-        sector = FLASH_SECTOR_16;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17))
-    {
-        sector = FLASH_SECTOR_17;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18))
-    {
-        sector = FLASH_SECTOR_18;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19))
-    {
-        sector = FLASH_SECTOR_19;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20))
-    {
-        sector = FLASH_SECTOR_20;
-    }
-    else if ((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21))
-    {
-        sector = FLASH_SECTOR_21;
+    FLASH_OBProgramInitTypeDef OBInit;
+    uint32_t nbank = 0;
+
+    //get duel bank ability:nDBANK(Bit29)
+    HAL_FLASHEx_OBGetConfig(&OBInit);
+    nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
+    //1:single bank mode
+    if (1 == nbank)
+    {  
+        if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
+        {
+            sector = FLASH_SECTOR_0;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
+        {
+            sector = FLASH_SECTOR_1;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
+        {
+            sector = FLASH_SECTOR_2;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
+        {
+            sector = FLASH_SECTOR_3;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
+        {
+            sector = FLASH_SECTOR_4;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
+        {
+            sector = FLASH_SECTOR_5;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
+        {
+            sector = FLASH_SECTOR_6;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
+        {
+            sector = FLASH_SECTOR_7;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
+        {
+            sector = FLASH_SECTOR_8;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
+        {
+            sector = FLASH_SECTOR_9;
+        }
+        else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
+        {
+            sector = FLASH_SECTOR_10;
+        }
+        else 
+        {
+            sector = FLASH_SECTOR_11;
+        }
     }
-    else if ((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22))
-    {
-        sector = FLASH_SECTOR_22;
-    }          
-#else
-    else
+    else  //0:dual bank mode
     {
-#if (FLASH_SECTOR_TOTAL == 4) 
-        sector = FLASH_SECTOR_4;
-#elif (FLASH_SECTOR_TOTAL == 8) 
-        sector = FLASH_SECTOR_8;
-#elif (FLASH_SECTOR_TOTAL == 24) 
-        sector = FLASH_SECTOR_23;
-#endif
+        LOG_E("rtthread doesn't support duel bank mode yet!");
+        RT_ASSERT(0);
     }
-#endif
-#else
+#else //no dual bank ability
     if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
     {
         sector = FLASH_SECTOR_0;
@@ -186,7 +117,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_1;
     }
-#if (FLASH_SECTOR_TOTAL >= 4)    
     else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
     {
         sector = FLASH_SECTOR_2;
@@ -195,7 +125,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_3;
     }
-#elif (FLASH_SECTOR_TOTAL >= 8)    
     else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
     {
         sector = FLASH_SECTOR_4;
@@ -212,7 +141,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_7;
     }
-#elif (FLASH_SECTOR_TOTAL >= 24)
     else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
     {
         sector = FLASH_SECTOR_8;
@@ -225,22 +153,15 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_10;
     }
-#else
-    else
+    else 
     {
-#if (FLASH_SECTOR_TOTAL == 4) 
-        sector = FLASH_SECTOR_4;
-#elif (FLASH_SECTOR_TOTAL == 8) 
-        sector = FLASH_SECTOR_8;
-#elif (FLASH_SECTOR_TOTAL == 24) 
         sector = FLASH_SECTOR_11;
-#endif
     }
-#endif
 #endif
     return sector;
 }
 
+
 /**
  * Read data from flash.
  * @note This operation's units is word.
@@ -386,6 +307,13 @@ __exit:
 }
 
 #if defined(PKG_USING_FAL)
+#define FLASH_SIZE_GRANULARITY_32K      (4 * 32 * 1024)
+#define FLASH_SIZE_GRANULARITY_128K     (128 * 1024)
+#define FLASH_SIZE_GRANULARITY_256K     (7 * 256 *1024)
+
+#define STM32_FLASH_START_ADRESS_32K    (STM32_FLASH_START_ADRESS)
+#define STM32_FLASH_START_ADRESS_128K   (STM32_FLASH_START_ADRESS_32K + FLASH_SIZE_GRANULARITY_32K)
+#define STM32_FLASH_START_ADRESS_256K   (STM32_FLASH_START_ADRESS_128K + FLASH_SIZE_GRANULARITY_128K)
 
 static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
 static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c

@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-27     NU-LL        first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+// #define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t addr)
+{
+    uint32_t page = 0;
+    page = RT_ALIGN_DOWN(addr-STM32_FLASH_START_ADRESS, FLASH_PAGE_SIZE)/FLASH_PAGE_SIZE;
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(rt_uint32_t addr, const uint8_t *buf, size_t size)
+{
+    size_t i, j;
+    rt_err_t result = 0;
+    rt_uint64_t write_data = 0, temp_data = 0;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: write outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if(addr % 8 != 0)
+    {
+        LOG_E("write addr must be 8-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR);
+
+    if (size < 1)
+    {
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < size;)
+    {
+        if ((size - i) < 8)
+        {
+            for (j = 0; (size - i) > 0; i++, j++)
+            {
+                temp_data = *buf;
+                write_data = (write_data) | (temp_data << 8 * j);
+                buf ++;
+            }
+        }
+        else
+        {
+            for (j = 0; j < 8; j++, i++)
+            {
+                temp_data = *buf;
+                write_data = (write_data) | (temp_data << 8 * j);
+                buf ++;
+            }
+        }
+
+        /* write data */
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr, write_data) == HAL_OK)
+        {
+            /* Check the written value */
+            if (*(uint64_t*)addr != write_data)
+            {
+                LOG_E("ERROR: write data != read data\n");
+                result = -RT_ERROR;
+                goto __exit;
+            }
+        }
+        else
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        temp_data = 0;
+        write_data = 0;
+
+        addr += 8;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+    if (result != 0)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(rt_uint32_t addr, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    uint32_t PAGEError = 0;
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.Page        = GetPage(addr);
+    EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+    return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
+}
+
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */