移除非 4.1.1 文件

.gitee/ISSUE_TEMPLATE.en.md

@@ -1,9 +0,0 @@
-### How is this problem caused?
-
-
-
-### Steps to reproduce
-
-
-
-### Error message

.gitee/ISSUE_TEMPLATE.zh-CN.md

@@ -1,9 +0,0 @@
-### 该问题是怎么引起的？
-
-
-
-### 重现步骤
-
-
-
-### 报错信息

.gitee/PULL_REQUEST_TEMPLATE.en.md

@@ -1,30 +0,0 @@
-## PR description
-
-[
-The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
-
-Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
-
-And confirm in which case or board has been tested.
-]
-
-The following content must not be changed in the submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use a web browser to visit PR, and check items one by one, and ticked them if no problem.
-
-### The intent for your PR
-
-Choose one (Mandatory):
-
-- [ ] This PR is for a code-review and is intended to get feedback.
-- [ ] This PR is mature, and ready to be integrated into the repo.
-
-### Code Quality：
-
-As part of this pull request, I've considered the following:
-
-- [ ] Already check the difference between PR and old code.
-- [ ] The style guide is adhered to, including spacing, naming and other styles.
-- [ ] All redundant code is removed and cleaned up.
-- [ ] All modifications to BSP are justified and do not affect other components or BSPs.
-- [ ] I've commented appropriately where code is tricky.
-- [ ] Code in this PR is of high quality.
-- [ ] This PR complies with [RT-Thread code specification](../documentation/contribution_guide/coding_style_en.txt)

.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md

@@ -1,30 +0,0 @@
-## 拉取/合并请求描述：
-
-[
-这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
-
-请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
-
-并确认并列出已经在什么情况或板卡上进行了测试。
-]
-
-以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
-
-### 当前拉取/合并请求的状态：
-
-必须选择一项:
-
-- [ ] 本拉取/合并请求是一个草稿版本
-- [ ] 本拉取/合并请求是一个成熟版本
-
-### 代码质量：
-
-我在这个拉取/合并请求中已经考虑了:
-
-- [ ] 已经仔细查看过代码改动的对比
-- [ ] 代码风格正确，包括缩进空格，命名及其他风格
-- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码
-- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或
-- [ ] 对难懂代码均提供对应的注释
-- [ ] 本拉取/合并请求代码是高质量的
-- [ ] 本拉取/合并符合[RT-Thread代码规范](../documentation/contribution_guide/coding_style_cn.md)

bsp/ESP32_C3/.vscode/launch.json

@@ -0,0 +1,10 @@
+{
+  "version": "0.2.0",
+  "configurations": [
+    {
+      "type": "espidf",
+      "name": "Launch",
+      "request": "launch"
+    }
+  ]
+}

bsp/ESP32_C3/.vscode/settings.json

@@ -0,0 +1,26 @@
+{
+  "C_Cpp.intelliSenseEngine": "Tag Parser",
+  "idf.adapterTargetName": "esp32c3",
+  "idf.openOcdConfigs": [
+    "board/esp32c3-builtin.cfg"
+  ],
+  "idf.portWin": "COM7",
+  "idf.flashType": "UART",
+  "files.associations": {
+    "panic_internal.h": "c",
+    "rtthread.h": "c",
+    "bitset": "c",
+    "chrono": "c",
+    "algorithm": "c",
+    "rtdebug.h": "c",
+    "rtservice.h": "c",
+    "rtdef.h": "c",
+    "rtconfig.h": "c",
+    "thread": "c",
+    "rthw.h": "c",
+    "typeinfo": "c",
+    "serial.h": "c",
+    "timer.h": "c"
+  },
+  "RTT_Studio.Build.Parallel_Jobs": "4"
+}

bsp/ESP32_C3/.vscode/tasks.json

@@ -0,0 +1,300 @@
+{
+    "version": "2.0.0",
+    "tasks": [
+        {
+            "label": "Build - Build project",
+            "type": "shell",
+            "command": "${config:idf.pythonBinPath} ${config:idf.espIdfPath}/tools/idf.py build",
+            "windows": {
+                "command": "${config:idf.pythonBinPathWin} ${config:idf.espIdfPathWin}\\tools\\idf.py build",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}"
+                    }
+                }
+            },
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}"
+                }
+            },
+            "problemMatcher": [
+                {
+                    "owner": "cpp",
+                    "fileLocation": [
+                        "relative",
+                        "${workspaceFolder}"
+                    ],
+                    "pattern": {
+                        "regexp": "^\\.\\.(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                },
+                {
+                    "owner": "cpp",
+                    "fileLocation": "absolute",
+                    "pattern": {
+                        "regexp": "^[^\\.](.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                }
+            ],
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
+        {
+            "label": "Set ESP-IDF Target",
+            "type": "shell",
+            "command": "${command:espIdf.setTarget}",
+            "problemMatcher": {
+                "owner": "cpp",
+                "fileLocation": "absolute",
+                "pattern": {
+                    "regexp": "^(.*):(//d+):(//d+)://s+(warning|error)://s+(.*)$",
+                    "file": 1,
+                    "line": 2,
+                    "column": 3,
+                    "severity": 4,
+                    "message": 5
+                }
+            }
+        },
+        {
+            "label": "Clean - Clean the project",
+            "type": "shell",
+            "command": "${config:idf.pythonBinPath} ${config:idf.espIdfPath}/tools/idf.py fullclean",
+            "windows": {
+                "command": "${config:idf.pythonBinPathWin} ${config:idf.espIdfPathWin}\\tools\\idf.py fullclean",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}"
+                    }
+                }
+            },
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}"
+                }
+            },
+            "problemMatcher": [
+                {
+                    "owner": "cpp",
+                    "fileLocation": [
+                        "relative",
+                        "${workspaceFolder}"
+                    ],
+                    "pattern": {
+                        "regexp": "^\\.\\.(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                },
+                {
+                    "owner": "cpp",
+                    "fileLocation": "absolute",
+                    "pattern": {
+                        "regexp": "^[^\\.](.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                }
+            ]
+        },
+        {
+            "label": "Flash - Flash the device",
+            "type": "shell",
+            "command": "${config:idf.pythonBinPath} ${config:idf.espIdfPath}/tools/idf.py -p ${config:idf.port} -b ${config:idf.flashBaudRate} flash",
+            "windows": {
+                "command": "${config:idf.pythonBinPathWin} ${config:idf.espIdfPathWin}\\tools\\idf.py flash -p ${config:idf.portWin} -b ${config:idf.flashBaudRate}",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}"
+                    }
+                }
+            },
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}"
+                }
+            },
+            "problemMatcher": [
+                {
+                    "owner": "cpp",
+                    "fileLocation": [
+                        "relative",
+                        "${workspaceFolder}"
+                    ],
+                    "pattern": {
+                        "regexp": "^\\.\\.(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                },
+                {
+                    "owner": "cpp",
+                    "fileLocation": "absolute",
+                    "pattern": {
+                        "regexp": "^[^\\.](.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                }
+            ]
+        },
+        {
+            "label": "Monitor: Start the monitor",
+            "type": "shell",
+            "command": "${config:idf.pythonBinPath} ${config:idf.espIdfPath}/tools/idf.py -p ${config:idf.port} monitor",
+            "windows": {
+                "command": "${config:idf.pythonBinPathWin} ${config:idf.espIdfPathWin}\\tools\\idf.py -p ${config:idf.portWin} monitor",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}"
+                    }
+                }
+            },
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}"
+                }
+            },
+            "problemMatcher": [
+                {
+                    "owner": "cpp",
+                    "fileLocation": [
+                        "relative",
+                        "${workspaceFolder}"
+                    ],
+                    "pattern": {
+                        "regexp": "^\\.\\.(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                },
+                {
+                    "owner": "cpp",
+                    "fileLocation": "absolute",
+                    "pattern": {
+                        "regexp": "^[^\\.](.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                        "file": 1,
+                        "line": 2,
+                        "column": 3,
+                        "severity": 4,
+                        "message": 5
+                    }
+                }
+            ],
+            "dependsOn": "Flash - Flash the device"
+        },
+        {
+            "label": "OpenOCD: Start openOCD",
+            "type": "shell",
+            "presentation": {
+                "echo": true,
+                "reveal": "never",
+                "focus": false,
+                "panel": "new"
+            },
+            "command": "openocd -s ${command:espIdf.getOpenOcdScriptValue} ${command:espIdf.getOpenOcdConfigs}",
+            "windows": {
+                "command": "openocd.exe -s ${command:espIdf.getOpenOcdScriptValue} ${command:espIdf.getOpenOcdConfigs}",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}"
+                    }
+                }
+            },
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}"
+                }
+            },
+            "problemMatcher": {
+                "owner": "cpp",
+                "fileLocation": "absolute",
+                "pattern": {
+                    "regexp": "^(.*):(\\d+):(\\d+):\\s+(warning|error):\\s+(.*)$",
+                    "file": 1,
+                    "line": 2,
+                    "column": 3,
+                    "severity": 4,
+                    "message": 5
+                }
+            }
+        },
+        {
+            "label": "adapter",
+            "type": "shell",
+            "command": "${config:idf.pythonBinPath}",
+            "isBackground": true,
+            "options": {
+                "env": {
+                    "PATH": "${env:PATH}:${config:idf.customExtraPaths}",
+                    "PYTHONPATH": "${command:espIdf.getExtensionPath}/esp_debug_adapter/debug_adapter"
+                }
+            },
+            "problemMatcher": {
+                "background": {
+                    "beginsPattern": "\bDEBUG_ADAPTER_STARTED\b",
+                    "endsPattern": "DEBUG_ADAPTER_READY2CONNECT",
+                    "activeOnStart": true
+                },
+                "pattern": {
+                    "regexp": "(\\d+)-(\\d+)-(\\d+)\\s(\\d+):(\\d+):(\\d+),(\\d+)\\s-(.+)\\s(ERROR)",
+                    "file": 8,
+                    "line": 2,
+                    "column": 3,
+                    "severity": 4,
+                    "message": 9
+                }
+            },
+            "args": [
+                "${command:espIdf.getExtensionPath}/esp_debug_adapter/debug_adapter_main.py",
+                "-e",
+                "${workspaceFolder}/build/${command:espIdf.getProjectName}.elf",
+                "-s",
+                "${command:espIdf.getOpenOcdScriptValue}",
+                "-ip",
+                "localhost",
+                "-dn",
+                "${config:idf.adapterTargetName}",
+                "-om",
+                "connect_to_instance"
+            ],
+            "windows": {
+                "command": "${config:idf.pythonBinPathWin}",
+                "options": {
+                    "env": {
+                        "PATH": "${env:PATH};${config:idf.customExtraPaths}",
+                        "PYTHONPATH": "${command:espIdf.getExtensionPath}/esp_debug_adapter/debug_adapter"
+                    }
+                }
+            }
+        }
+    ]
+}

bsp/ESP32_C3/CMakeLists.txt

@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(rtthread)

bsp/ESP32_C3/main/CMakeLists.txt

@@ -0,0 +1,49 @@
+idf_component_register(SRCS "board.c" "main.c"
+                    "drv_gpio.c"
+                    "drv_uart.c"
+                    "../../../libcpu/risc-v/common/cpuport.c"
+                    "../../../libcpu/risc-v/common/context_gcc.S"
+                    "../../../src/components.c"
+                    "../../../src/scheduler.c"
+                    "../../../src/device.c"
+                    "../../../src/clock.c"
+                    "../../../src/irq.c"
+                    "../../../src/thread.c"
+                    "../../../src/mempool.c"
+                    "../../../src/ipc.c"
+                    "../../../src/mem.c"
+                    "../../../src/object.c"
+                    "../../../src/idle.c"
+                    "../../../src/timer.c"
+                    "../../../src/kservice.c"
+                    "../../../src/device.c"
+                    "../../../components/drivers/misc/pin.c"
+                    "../../../components/drivers/ipc/pipe.c"
+                    "../../../components/drivers/ipc/ringblk_buf.c"
+                    "../../../components/drivers/ipc/waitqueue.c"
+                    "../../../components/drivers/ipc/completion.c"
+                    "../../../components/drivers/ipc/dataqueue.c"
+                    "../../../components/drivers/ipc/ringbuffer.c"
+                    "../../../components/drivers/ipc/workqueue.c"
+                    "../../../components/drivers/serial/serial.c"
+                    "../../../components/finsh/cmd.c"
+                    "../../../components/finsh/msh_file.c"
+                    "../../../components/finsh/msh_parse.c"
+                    "../../../components/finsh/msh.c"
+                    "../../../components/finsh/shell.c"
+
+                    INCLUDE_DIRS 
+                    "../../../components/drivers/include/drivers"
+
+                    "../../../components/drivers/include"
+                    "../../../components/finsh"
+                    "."
+                    "../../../include" 
+                    "../../../libcpu/risc-v/common" 
+                    "../")
+ADD_DEFINITIONS(
+	-D__RTTHREAD__
+)
+#TODO
+#list(APPEND LINK_FLAGS "-u __rt_init_desc_rt_hw_pin_init")
+#set(compile_options "-u __rt_init_desc_rt_hw_pin_init")

bsp/apm32/apm32f103xe-minibroard/.gitignore

@@ -1,42 +0,0 @@
-*.pyc
-*.map
-*.dblite
-*.elf
-*.bin
-*.hex
-*.axf
-*.exe
-*.pdb
-*.idb
-*.ilk
-*.old
-build
-Debug
-documentation/html
-packages/
-*~
-*.o
-*.obj
-*.out
-*.bak
-*.dep
-*.lib
-*.i
-*.d
-.DS_Stor*
-.config 3
-.config 4
-.config 5
-Midea-X1
-*.uimg
-GPATH
-GRTAGS
-GTAGS
-.vscode
-JLinkLog.txt
-JLinkSettings.ini
-DebugConfig/
-RTE/
-settings/
-*.uvguix*
-cconfig.h

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h

@@ -1,33 +0,0 @@
-/*!
- * @file        usbd_class_cdc.h
- *
- * @brief       CDC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __CDC_CLASS_
-#define __CDC_CLASS_
-
-#include "usbd_core.h"
-
-void USBD_ClassHandler(USBD_DevReqData_T *reqData);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c

@@ -1,71 +0,0 @@
-/*!
- * @file        usbd_class_cdc.c
- *
- * @brief       CDC Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_cdc.h"
-
-static uint8_t cmdBuf[8] = {0};
-
-/*!
- * @brief       USB CDC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                      reqData->byte.wLength[0] ;
-
-    if (!length)
-    {
-        if (!reqData->byte.bmRequestType.bit.dir)
-        {
-            USBD_CtrlTxStatus();
-        }
-        else
-        {
-            USBD_CtrlRxStatus();
-        }
-    }
-    else
-    {
-        switch (reqData->byte.bRequest)
-        {
-
-        case 0x20:
-            USBD_CtrlOutData(cmdBuf, length);
-            break;
-        case 0x21:
-            USBD_CtrlInData(cmdBuf, length);
-            break;
-        case 0x22:
-            USBD_CtrlOutData(cmdBuf, length);
-            break;
-        default:
-            break;
-        }
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_hid.h
- *
- * @brief       HID Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#define HID_CLASS_REQ_SET_PROTOCOL          0x0B
-#define HID_CLASS_REQ_GET_PROTOCOL          0x03
-
-#define HID_CLASS_REQ_SET_IDLE              0x0A
-#define HID_CLASS_REQ_GET_IDLE              0x02
-
-#define HID_CLASS_REQ_SET_REPORT            0x09
-#define HID_CLASS_REQ_GET_REPORT            0x01
-
-void USBD_ClassHandler(USBD_DevReqData_T *reqData);

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c

@@ -1,63 +0,0 @@
-/*!
- * @file        usbd_class_hid.c
- *
- * @brief       HID Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_hid.h"
-
-static uint8_t s_hidIdleState;
-static uint8_t s_hidProtocol;
-
-/*!
- * @brief       USB HID Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    switch (reqData->byte.bRequest)
-    {
-    case HID_CLASS_REQ_SET_IDLE:
-        s_hidIdleState = reqData->byte.wValue[1];
-        USBD_CtrlInData(NULL, 0);
-        break;
-
-    case HID_CLASS_REQ_GET_IDLE:
-        USBD_CtrlInData(&s_hidIdleState, 1);
-        break;
-
-    case HID_CLASS_REQ_SET_PROTOCOL:
-        s_hidProtocol = reqData->byte.wValue[0];
-        USBD_CtrlInData(NULL, 0);
-        break;
-
-    case HID_CLASS_REQ_GET_PROTOCOL:
-        USBD_CtrlInData(&s_hidProtocol, 1);
-        break;
-
-    default:
-        break;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_msc.h
- *
- * @brief       MSC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_CLASS_MSC
-#define __USBD_CLASS_MSC
-
-#include "usbd_core.h"
-
-
-#define BOT_GET_MAX_LUN              0xFE
-#define BOT_RESET                    0xFF
-
-void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h

@@ -1,106 +0,0 @@
-/*!
- * @file        usbd_msc_bot.h
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-#define MSC_BOT_CBW_SIGNATURE             (uint32_t)(0x43425355)
-#define MSC_BOT_CBW_LENGTH                31
-
-#define MSC_BOT_CSW_SIGNATURE             (uint32_t)(0x53425355)
-#define MSC_BOT_CSW_LENGTH                13
-
-typedef enum
-{
-    BOT_STATE_IDLE,          //!< Idle state
-    BOT_STATE_DATA_OUT,      //!< Data Out state
-    BOT_STATE_DATA_IN,       //!< Data In state
-    BOT_STATE_LAST_DATA_IN,  //!< Last Data In Last
-    BOT_STATE_SEND_DATA      //!< Send Immediate data
-} BOT_STATE_T;
-
-typedef enum
-{
-    BOT_STATUS_NORMAL,
-    BOT_STATUS_RECOVERY,
-    BOT_STATUS_ERROR
-} BOT_STATUS_T;
-
-typedef enum
-{
-    BOT_CSW_STATUS_CMD_OK,
-    BOT_CSW_STATUS_CMD_FAIL,
-    BOT_CSW_STATUS_PHASE_ERROR
-} BOT_CSW_STATUS_T;
-
-
-/**
- * @brief   Command Block Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataXferLen;
-    uint8_t  bmFlags;
-    uint8_t  bLUN;
-    uint8_t  bCBLen;
-    uint8_t  CB[16];
-} BOT_CBW_T;
-
-/**
- * @brief   Command Status Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataResidue;
-    uint8_t  bStatus;
-} BOT_CSW_T;
-
-typedef struct
-{
-    uint8_t   state;
-    uint8_t   status;
-    uint16_t  dataLen;
-    BOT_CBW_T CBW;
-    BOT_CSW_T CSW;
-    uint8_t   data[MSC_MEDIA_PACKET];
-} BOT_Info_T;
-
-extern BOT_Info_T g_BOTInfo;
-
-void USBD_MSC_BOT_Reset(void);
-void USBD_MSC_BOT_Init(void);
-void USBD_MSC_BOT_OutData(uint8_t ep);
-void USBD_MSC_BOT_InData(uint8_t ep);
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus);
-void USBD_MSC_BOT_Stall(void);
-void USBD_MSV_BOT_ClearFeatureHandler(void);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h

@@ -1,132 +0,0 @@
-/*!
- * @file        usbd_msc_scsi.h
- *
- * @brief       MSC scsi
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-#ifndef __USBD_MSC_SCSI_H_
-#define __USBD_MSC_SCSI_H_
-
-/**
- * @brief   SCSI function status
- */
-enum
-{
-    SCSI_OK,
-    SCSI_FAIL
-};
-
-/**
- * @brief   SCSI Sense Key
- */
-typedef enum
-{
-    SCSI_SKEY_NO_SENSE,
-    SCSI_SKEY_RECOVERED_ERROR,
-    SCSI_SKEY_NOT_READY,
-    SCSI_SKEY_MEDIUM_ERROR,
-    SCSI_SKEY_HARDWARE_ERROR,
-    SCSI_SKEY_ILLEGAL_REQUEST,
-    SCSI_SKEY_UNIT_ATTENTION,
-    SCSI_SKEY_DATA_PROTECT,
-    SCSI_SKEY_BLANK_CHECK,
-    SCSI_SKEY_VENDOR_SPECIFIC,
-    SCSI_SKEY_COPY_ABORTED,
-    SCSI_SKEY_ABORTED_COMMAND,
-    SCSI_SKEY_VOLUME_OVERFLOW = 13,
-    SCSI_SKEY_MISCOMPARE      = 14
-} SCSI_SKEY_T;
-
-/**
- * @brief   SCSI Sense
- */
-typedef struct
-{
-    uint8_t sensekey;
-    uint8_t ASC;
-    uint8_t ASCQ;
-} SCSI_Sense_T;
-
-
-#define SCSI_SENSE_LIST_NUMBER                      4
-#define SCSI_INQUIRY_LENGTH                         36
-
-/** SCSI Commands */
-#define SCSI_CMD_FORMAT_UNIT                        ((uint8_t)0x04)
-#define SCSI_CMD_INQUIRY                            ((uint8_t)0x12)
-#define SCSI_CMD_MODE_SELECT_6                      ((uint8_t)0x15)
-#define SCSI_CMD_MODE_SELECT_10                     ((uint8_t)0x55)
-#define SCSI_CMD_MODE_SENSE_6                       ((uint8_t)0x1A)
-#define SCSI_CMD_MODE_SENSE_10                      ((uint8_t)0x5A)
-#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL               ((uint8_t)0x1E)
-#define SCSI_CMD_READ_6                             ((uint8_t)0x08)
-#define SCSI_CMD_READ_10                            ((uint8_t)0x28)
-#define SCSI_CMD_READ_12                            ((uint8_t)0xA8)
-#define SCSI_CMD_READ_16                            ((uint8_t)0x88)
-
-#define SCSI_CMD_READ_CAPACITY_10                   ((uint8_t)0x25)
-#define SCSI_CMD_READ_CAPACITY_16                   ((uint8_t)0x9E)
-
-#define SCSI_CMD_REQUEST_SENSE                      ((uint8_t)0x03)
-#define SCSI_CMD_START_STOP_UNIT                    ((uint8_t)0x1B)
-#define SCSI_CMD_TEST_UNIT_READY                    ((uint8_t)0x00)
-#define SCSI_CMD_WRITE6                             ((uint8_t)0x0A)
-#define SCSI_CMD_WRITE10                            ((uint8_t)0x2A)
-#define SCSI_CMD_WRITE12                            ((uint8_t)0xAA)
-#define SCSI_CMD_WRITE16                            ((uint8_t)0x8A)
-
-#define SCSI_CMD_VERIFY_10                          ((uint8_t)0x2F)
-#define SCSI_CMD_VERIFY_12                          ((uint8_t)0xAF)
-#define SCSI_CMD_VERIFY_16                          ((uint8_t)0x8F)
-
-#define SCSI_CMD_SEND_DIAGNOSTIC                    ((uint8_t)0x1D)
-#define SCSI_CMD_READ_FORMAT_CAPACITIES             ((uint8_t)0x23)
-
-
-#define SCSI_ASC_INVALID_CDB                         0x20
-#define SCSI_ASC_INVALID_FIELED_IN_COMMAND           0x24
-#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR         0x1A
-#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST     0x26
-#define SCSI_ASC_ADDRESS_OUT_OF_RANGE                0x21
-#define SCSI_ASC_MEDIUM_NOT_PRESENT                  0x3A
-#define SCSI_ASC_MEDIUM_HAVE_CHANGED                 0x28
-#define SCSI_ASC_WRITE_PROTECTED                     0x27
-#define SCSI_ASC_UNRECOVERED_READ_ERROR              0x11
-#define SCSI_ASC_WRITE_FAULT                         0x03
-
-#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN           0x0C
-#define SCSI_READ_CAPACITY10_DATA_LEN                0x08
-#define SCSI_MODE_SENSE10_DATA_LEN                   0x08
-#define SCSI_MODE_SENSE6_DATA_LEN                    0x04
-#define SCSI_REQUEST_SENSE_DATA_LEN                  0x12
-#define SCSI_STANDARD_INQUIRY_DATA_LEN               0x24
-#define SCSI_BLKVFY                                  0x04
-
-extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER];
-extern uint8_t g_senseTxCnt;
-extern uint8_t g_sensePutCnt;
-
-uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd);
-void   SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c

@@ -1,79 +0,0 @@
-/*!
- * @file        usbd_class_msc.c
- *
- * @brief       MSC Class file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_msc.h"
-#include "usbd_msc_bot.h"
-
-static uint8_t s_mscMaxLen = 0;
-
-/*!
- * @brief       USB MSC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \
-                      reqData->byte.wValue[0];
-    uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                       reqData->byte.wLength[0];
-
-    switch (reqData->byte.bRequest)
-    {
-    case BOT_GET_MAX_LUN :
-        if ((wValue == 0) && (wLength == 1) && \
-                (reqData->byte.bmRequestType.bit.dir == 1))
-        {
-            s_mscMaxLen = STORAGE_MAX_LUN - 1;
-
-            USBD_CtrlInData(&s_mscMaxLen, 1);
-        }
-        else
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-        break;
-    case BOT_RESET :
-        if ((wValue == 0) && (wLength == 0) && \
-                (reqData->byte.bmRequestType.bit.dir == 0))
-        {
-            USBD_CtrlInData(NULL, 0);
-            /** Reset */
-            USBD_MSC_BOT_Reset();
-        }
-        else
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-
-        break;
-
-    default:
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        break;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c

@@ -1,242 +0,0 @@
-/*!
- * @file        usbd_msv_bot.c
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_msc_bot.h"
-#include "usbd_core.h"
-#include "usbd_storage_disk.h"
-#include "usbd_msc_scsi.h"
-
-BOT_Info_T g_BOTInfo;
-
-static void USBD_MSC_BOT_DecodeCBW(void);
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len);
-static void USBD_MSC_BOT_Stall(void);
-
-/*!
- * @brief       BOT Process Reset.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Reset(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_RECOVERY;
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       BOT Process initialization.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Init(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_NORMAL;
-
-    g_storageCallBack.Init(0);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       Bulk OUT data handler.
- *
- * @param       ep : OUT endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_OutData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        USBD_MSC_BOT_DecodeCBW();
-    }
-    else if (g_BOTInfo.state == BOT_STATE_DATA_OUT)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-}
-
-/*!
- * @brief       Bulk IN data handler.
- *
- * @param       ep : IN endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_InData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_DATA_IN)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-    else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \
-             (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN))
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-    }
-}
-
-/*!
- * @brief       Decode CBW.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_DecodeCBW(void)
-{
-    uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt;
-
-    g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag;
-    g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen;
-
-    if ((xferCnt != MSC_BOT_CBW_LENGTH) || \
-            (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \
-            (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \
-            (g_BOTInfo.CBW.bCBLen > 16))
-    {
-        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-
-        g_BOTInfo.status = BOT_STATUS_ERROR;
-    }
-    else
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_Stall();
-        }
-        else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \
-                 (g_BOTInfo.state == BOT_STATE_SEND_DATA))
-        {
-            if (g_BOTInfo.dataLen)
-            {
-                USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen);
-            }
-            else
-            {
-                USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-            }
-        }
-    }
-}
-
-/*!
- * @brief       MSC send data.
- *
- * @param       txBuf : buffer to send
- *
- * @param       len : buffer length
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len)
-{
-    len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen);
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-    g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK;
-    g_BOTInfo.state = BOT_STATE_SEND_DATA;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len);
-}
-
-/*!
- * @brief       Send CSW.
- *
- * @param       cswStatus : status of CSW
- *
- * @retval      None
- */
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus)
-{
-    g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE;
-    g_BOTInfo.CSW.bStatus = cswStatus;
-    g_BOTInfo.state = BOT_STATE_IDLE;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t *)&g_BOTInfo.CSW,
-                MSC_BOT_CSW_LENGTH);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
-                MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       handler clearFeature in standard request.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSV_BOT_ClearFeatureHandler(void)
-{
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK);
-        g_BOTInfo.status = BOT_STATUS_NORMAL;
-    }
-    else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \
-             g_BOTInfo.status != BOT_STATUS_RECOVERY)
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-    }
-}
-
-/*!
- * @brief       Stall MSC.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_Stall(void)
-{
-    if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \
-            (g_BOTInfo.status == BOT_STATUS_NORMAL))
-    {
-        USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL);
-    }
-
-    USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL);
-
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
-                    MSC_BOT_CBW_LENGTH);
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c

@@ -1,701 +0,0 @@
-/*!
- * @file        usbd_msc_scsi.c
- *
- * @brief       MSC scsi
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_storage_disk.h"
-
-SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER];
-uint8_t g_senseTxCnt;
-uint8_t g_sensePutCnt;
-
-static uint32_t  s_blkSize;
-static uint32_t  s_blkNbr;
-
-static uint32_t  s_blkAddr;
-static uint32_t  s_blkLen;
-
-/** USB Mass storage Page 0 Inquiry Data */
-static const uint8_t  s_page00InquiryData[] =
-{
-    0x00,
-    0x00,
-    0x00,
-    (7 - 4),
-    0x00,
-    0x80,
-    0x83
-};
-/** USB Mass storage sense 6 Data */
-static const uint8_t  s_modeSense6Data[] =
-{
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00
-};
-/** USB Mass storage sense 10 Data */
-static const uint8_t  s_modeSense10Data[] =
-{
-    0x00,
-    0x06,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00
-};
-
-static uint8_t SCSI_TestUnitReady(uint8_t lun);
-static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command);
-
-static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command);
-
-static uint8_t SCSI_StartStopUnit(void);
-static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command);
-static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command);
-
-static uint8_t SCSI_Read(uint8_t lun);
-static uint8_t SCSI_Write(uint8_t lun);
-static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr);
-
-/*!
- * @brief       SCSI command handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: Command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *command)
-{
-    uint8_t ret = SCSI_OK;
-
-    switch (command[0])
-    {
-    case SCSI_CMD_TEST_UNIT_READY:
-        ret = SCSI_TestUnitReady(lun);
-        break;
-
-    case SCSI_CMD_INQUIRY:
-        ret = SCSI_Inquiry(lun, command);
-        break;
-
-    case SCSI_CMD_REQUEST_SENSE:
-        ret = SCSI_RequestSense(lun, command);
-        break;
-
-    case SCSI_CMD_READ_FORMAT_CAPACITIES:
-        ret = SCSI_ReadFormatCapacity(lun, command);
-        break;
-
-    case SCSI_CMD_READ_CAPACITY_10:
-        ret = SCSI_ReadCapacity10(lun, command);
-        break;
-
-    case SCSI_CMD_READ_10:
-        ret = SCSI_Read10(lun, command);
-        break;
-
-    case SCSI_CMD_WRITE10:
-        ret = SCSI_Write10(lun, command);
-        break;
-
-    case SCSI_CMD_VERIFY_10:
-        ret = SCSI_Verify10(lun, command);
-        break;
-    case SCSI_CMD_ALLOW_MEDIUM_REMOVAL:
-    case SCSI_CMD_START_STOP_UNIT:
-        ret = SCSI_StartStopUnit();
-        break;
-
-    case SCSI_CMD_MODE_SENSE_6:
-        ret = SCSI_ModeSense6(lun, command);
-        break;
-
-    case SCSI_CMD_MODE_SENSE_10:
-        ret = SCSI_ModeSense10(lun, command);
-        break;
-
-    default:
-        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-        ret = SCSI_FAIL;
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Put the sense code to array.
- *
- * @param       sKey: sense Key
- *
- * @param       ASC: Additional Sense Code
- *
- * @param       ASCQ: Additional Sense Code Qualifier
- *
- * @retval      None
- */
-void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ)
-{
-    g_scsiSenseCode[g_sensePutCnt].sensekey = sKey;
-    g_scsiSenseCode[g_sensePutCnt].ASC = ASC;
-    g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ;
-
-    if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER)
-    {
-        g_sensePutCnt = 0;
-    }
-}
-
-/*!
- * @brief       SCSI Test Unit Ready handler.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_TestUnitReady(uint8_t lun)
-{
-    if (g_BOTInfo.CBW.dDataXferLen)
-    {
-        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-
-        return SCSI_FAIL;
-    }
-    else if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        g_BOTInfo.dataLen = 0;
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Inquiry handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command)
-{
-    uint16_t i;
-    uint8_t *pInquiryData;
-
-    if (command[1] & 0x01)
-    {
-        pInquiryData = (uint8_t *)s_page00InquiryData;
-        g_BOTInfo.dataLen = s_page00InquiryData[3] + 4;
-    }
-    else
-    {
-        pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH];
-
-        g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]);
-    }
-
-    for (i = 0; i < g_BOTInfo.dataLen; i++)
-    {
-        g_BOTInfo.data[i] = pInquiryData[i];
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Request Sense handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command)
-{
-    uint8_t i = 0;
-
-    while (i < SCSI_REQUEST_SENSE_DATA_LEN)
-    {
-        g_BOTInfo.data[i++] = 0;
-    }
-
-    g_BOTInfo.data[0] = 0x70;
-    g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6;
-
-    if (g_senseTxCnt != g_sensePutCnt)
-    {
-        g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey;
-        g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC;
-        g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ;
-
-        if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER)
-        {
-            g_senseTxCnt = 0;
-        }
-    }
-
-    g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \
-                        SCSI_REQUEST_SENSE_DATA_LEN : command[4];
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Read Format Capacity handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command)
-{
-    uint16_t i = 0;
-    uint32_t blkSize;
-    uint32_t blkNbr;
-
-    while (i < 12)
-    {
-        g_BOTInfo.data[i++] = 0;
-    }
-
-    if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        blkNbr--;
-
-        g_BOTInfo.data[3] = 0x08;
-        g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24);
-        g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16);
-        g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8);
-        g_BOTInfo.data[7] = (uint8_t)(blkNbr);
-        g_BOTInfo.data[8] = 0x02;
-        g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16);
-        g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8);
-        g_BOTInfo.data[11] = (uint8_t)blkSize;
-
-        g_BOTInfo.dataLen = 12;
-
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Read Capacity10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command)
-{
-    if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24);
-        g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16);
-        g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >>  8);
-        g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1);
-        g_BOTInfo.data[4] = (uint8_t)(s_blkSize >>  24);
-        g_BOTInfo.data[5] = (uint8_t)(s_blkSize >>  16);
-        g_BOTInfo.data[6] = (uint8_t)(s_blkSize >>  8);
-        g_BOTInfo.data[7] = (uint8_t)(s_blkSize);
-
-        g_BOTInfo.dataLen = 8;
-
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Read10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command)
-{
-    uint8_t ret = SCSI_OK;
-
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                              SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                              SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr = ((uint32_t)command[2] << 24) | \
-                    ((uint32_t)command[3] << 16) | \
-                    ((uint32_t)command[4] << 8)  | \
-                    (uint32_t)command[5];
-
-        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
-
-        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-        {
-            return SCSI_FAIL;
-        }
-
-        g_BOTInfo.state = BOT_STATE_DATA_IN;
-        s_blkAddr *= s_blkSize;
-        s_blkLen *= s_blkSize;
-
-        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                              SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-    }
-
-    g_BOTInfo.dataLen = MSC_MEDIA_PACKET;
-
-    ret = SCSI_Read(lun);
-
-    return ret;
-}
-
-/*!
- * @brief       SCSI write10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command)
-{
-    uint8_t ret = SCSI_OK;
-    uint32_t len;
-
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        if (g_BOTInfo.CBW.bmFlags & 0x80)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                              SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                              SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckWPR(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                              SCSI_ASC_WRITE_PROTECTED, 0);
-
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr = ((uint32_t)command[2] << 24) | \
-                    ((uint32_t)command[3] << 16) | \
-                    ((uint32_t)command[4] << 8)  | \
-                    (uint32_t)command[5];
-
-        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
-
-        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-        {
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr *= s_blkSize;
-        s_blkLen  *= s_blkSize;
-
-        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                              SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        g_BOTInfo.state = BOT_STATE_DATA_OUT;
-        len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET);
-
-        USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len);
-
-    }
-    else
-    {
-        ret = SCSI_Write(lun);
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       SCSI Verify10 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command)
-{
-    if (command[1] & 0x02)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0);
-
-        return SCSI_FAIL;
-    }
-
-    s_blkAddr = ((uint32_t)command[2] << 24) | \
-                ((uint32_t)command[3] << 16) | \
-                ((uint32_t)command[4] << 8)  | \
-                (uint32_t)command[5];
-
-    s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
-
-    if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-    {
-        return SCSI_FAIL;
-    }
-
-    g_BOTInfo.dataLen = 0;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Start Stop Unit Handler.
- *
- * @param       None
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_StartStopUnit(void)
-{
-    g_BOTInfo.dataLen = 0;
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Mode Sense6 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command)
-{
-    for (uint16_t i = 0; i < 8; i++)
-    {
-        g_BOTInfo.data[i] = s_modeSense6Data[i];
-    }
-
-    g_BOTInfo.dataLen = 8;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Mode Sense10 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command)
-{
-    for (uint16_t i = 0; i < 8; i++)
-    {
-        g_BOTInfo.data[i] = s_modeSense10Data[i];
-    }
-
-    g_BOTInfo.dataLen = 8;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Read Process.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Read(uint8_t lun)
-{
-    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-    if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize),
-                                   (len / s_blkSize)) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR,
-                          SCSI_ASC_UNRECOVERED_READ_ERROR, 0);
-
-        return SCSI_FAIL;
-    }
-
-    USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len);
-
-    s_blkAddr += len;
-    s_blkLen  -= len;
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-
-    if (s_blkLen == 0)
-    {
-        g_BOTInfo.state = BOT_STATE_LAST_DATA_IN;
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Write Process.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Write(uint8_t lun)
-{
-    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-    if (s_blkLen - len)
-    {
-        __NOP();
-    }
-    if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize,
-                                    len / s_blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0);
-
-        return SCSI_FAIL;
-    }
-
-    s_blkAddr += len;
-    s_blkLen  -= len;
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-
-    if (s_blkLen)
-    {
-        len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-        USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len);
-    }
-    else
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Check Address Range.
- *
- * @param       lun: Logical unit number
- *
- * @param       blkOffset: first block address
- *
- * @param       blkNbr: number of block to be processed
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr)
-{
-    if (s_blkNbr < (blkNbr + blkOffset))
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0);
-
-        return SCSI_FAIL;
-    }
-
-    return SCSI_OK;
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h

@@ -1,312 +0,0 @@
-/*!
- * @file        usbd_core.h
- *
- * @brief       USB protocol core handler head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_CORE_H_
-#define __USBD_CORE_H_
-
-#include "drv_usb_device.h"
-
-/** Get minimum value */
-#define USB_MIN(a, b)      (a >= b ? b : a)
-
-/** Get maximum value */
-#define USB_MAX(a, b)      (a >= b ? a : b)
-
-/**
- * @brief   USB request type
- */
-enum
-{
-    USBD_REQ_TYPE_STANDARD   = 0,
-    USBD_REQ_TYPE_CLASS      = 1,
-    USBD_REQ_TYPE_VENDOR     = 2,
-    USBD_REQ_TYPE_RESERVED   = 3
-};
-
-/**
- * @brief   USB recipient
- */
-enum
-{
-    USBD_RECIPIENT_DEVICE    = 0,
-    USBD_RECIPIENT_INTERFACE = 1,
-    USBD_RECIPIENT_ENDPOINT  = 2,
-    USBD_RECIPIENT_OTHER     = 3,
-};
-
-/**
- * @brief   USB standard device requests
- */
-enum
-{
-    USBD_GET_STATUS          = 0,
-    USBD_CLEAR_FEATURE       = 1,
-    USBD_SET_FEATURE         = 3,
-    USBD_SET_ADDRESS         = 5,
-    USBD_GET_DESCRIPTOR      = 6,
-    USBD_SET_DESCRIPTOR      = 7,
-    USBD_GET_CONFIGURATION   = 8,
-    USBD_SET_CONFIGURATION   = 9,
-    USBD_GET_INTERFACE       = 10,
-    USBD_SET_INTERFACE       = 11,
-    USBD_SYNCH_FRAME         = 12,
-};
-
-/**
- * @brief   USB descriptor types
- */
-enum
-{
-    USBD_DESC_DEVICE             = 1,
-    USBD_DESC_CONFIGURATION      = 2,
-    USBD_DESC_STRING             = 3,
-    USBD_DESC_INTERFACE          = 4,
-    USBD_DESC_ENDPOINT           = 5,
-    USBD_DESC_DEVICE_QUALIFIER   = 6,
-    USBD_DESC_OTHER_SPEED        = 7,
-    USBD_INTERFACE_POWER         = 8,
-};
-
-/**
- * @brief   USB standard feature
- */
-enum
-{
-    USBD_FEATURE_ENDPOINT_HALT   = 0,
-    USBD_FEATURE_REMOTE_WAKEUP   = 1,
-    USBD_FEATURE_TEST_MODE       = 2
-};
-
-/**
- * @brief   USB internal state machine
- */
-typedef enum
-{
-    USBD_CTRL_STATE_WAIT_SETUP,
-    USBD_CTRL_STATE_DATA_IN,
-    USBD_CTRL_STATE_DATA_OUT,
-    USBD_CTRL_STATE_WAIT_STATUS_IN,
-    USBD_CTRL_STATE_WAIT_STATUS_OUT,
-    USBD_CTRL_STATE_STALLED,
-} USBD_CTRL_STATE_T;
-
-/**
- * @brief   USBD Endpoint type for USB protocol
- */
-typedef enum
-{
-    USBD_EP_TYPE_CONTROL,
-    USBD_EP_TYPE_ISO,
-    USBD_EP_TYPE_BULK,
-    USBD_EP_TYPE_INTERRUPT
-} USBD_EP_TYPE_T;
-
-/**
- * @brief   USB request type
- */
-typedef union
-{
-    uint8_t byte;
-
-    struct
-    {
-        uint8_t recipient       : 5;
-        uint8_t type            : 2;
-        uint8_t dir             : 1;
-    } bit;
-} USBD_REQ_TYPE_T;
-
-/**
- * @brief   USB device request data
- */
-typedef struct
-{
-    union
-    {
-        uint8_t pack[8];
-
-        struct
-        {
-            USBD_REQ_TYPE_T bmRequestType;
-            uint8_t         bRequest;
-            uint8_t         wValue[2];
-            uint8_t         wIndex[2];
-            uint8_t         wLength[2];
-        } byte;
-    };
-} USBD_DevReqData_T;
-
-/**
- * @brief   Descriptor structure
- */
-typedef struct
-{
-    const uint8_t *pDesc;
-    uint8_t size;
-} USBD_Descriptor_T;
-
-/** USB standard request callback handler */
-typedef void (*USBD_StdReqHandler_T)(void);
-
-/** USB request handler */
-typedef void (*USBD_ReqHandler_T)(USBD_DevReqData_T *);
-
-/** Ctrl Tx Status handler function define */
-typedef void (*USBD_CtrlTxStatusHandler_T)(void);
-
-/** Ctrl Rx Status handler function define */
-typedef void (*USBD_CtrlRxStatusHandler_T)(void);
-
-/** Endpoint handler */
-typedef void (*USBD_EPHandler_T)(uint8_t ep);
-
-/** Reset handler */
-typedef void (*USBD_ResetHandler_T)(void);
-
-/** Interrupt handler function define */
-typedef void (*USBD_InterruptHandler_T)(void);
-
-/**
- * @brief   USB Class Request handler
- */
-typedef struct
-{
-    USBD_StdReqHandler_T getConfigurationHandler;
-    USBD_StdReqHandler_T getDescriptorHandler;
-    USBD_StdReqHandler_T getInterfaceHandler;
-    USBD_StdReqHandler_T getStatusHandler;
-    USBD_StdReqHandler_T setAddressHandler;
-
-    USBD_StdReqHandler_T setConfigurationHandler;
-    USBD_StdReqHandler_T setDescriptorHandler;
-    USBD_StdReqHandler_T setFeatureHandler;
-    USBD_StdReqHandler_T setInterfaceHandler;
-    USBD_StdReqHandler_T clearFeatureHandler;
-} USBD_StdReqCallback_T;
-
-/**
- * @brief   Control transfer buffer
- */
-typedef struct
-{
-    uint8_t *pBuf;         //!< Data buffer
-    uint32_t bufLen;       //!< Length of the data buffer
-    uint8_t  packNum;      //!< Packet number of the data
-    uint8_t  zeroPackFill; //!< Fill a zero pack for IN transfer or not
-    uint16_t maxPackSize;  //!< Max pack size of this endpoint
-    uint32_t xferCnt;      //!< Data count of one pack on from tansfer
-} USBD_CtrlBuf_T;
-
-/**
- * @brief   USB init parameter
- */
-typedef struct
-{
-    USBD_Descriptor_T *pDeviceDesc;              //!< Device descriptor pointer
-    USBD_Descriptor_T *pConfigurationDesc;       //!< Configuration descriptor pointer
-    USBD_Descriptor_T *pStringDesc;              //!< String descriptor pointer
-    USBD_Descriptor_T *pQualifierDesc;           //!< Device Qualifier descriptor pointer
-    USBD_Descriptor_T *pHidReportDesc;           //!< HID report descriptor pointer
-
-
-    USBD_StdReqCallback_T *pStdReqCallback;
-    USBD_ReqHandler_T stdReqExceptionHandler;    //!< Standard request exception handler
-    USBD_ReqHandler_T classReqHandler;           //!< Class request handler
-    USBD_ReqHandler_T vendorReqHandler;          //!< vendor request handler
-
-    USBD_CtrlTxStatusHandler_T txStatusHandler;  //!< Send IN status early handler
-    USBD_CtrlRxStatusHandler_T rxStatusHandler;  //!< Receive OUT status early handler
-
-    USBD_EPHandler_T    outEpHandler;            //!< OUT EP transfer done handler except EP0
-    USBD_EPHandler_T    inEpHandler;             //!< IN EP transfer done handler except EP0
-    USBD_ResetHandler_T resetHandler;            //!< Reset handler
-    USBD_InterruptHandler_T intHandler;          //!< Hadler the rest of interrupt.
-} USBD_InitParam_T;
-
-/**
- * @brief   USB infomation
- */
-typedef struct
-{
-    USBD_CTRL_STATE_T ctrlState;
-
-    uint8_t curFeature;
-    uint8_t curInterface;
-    uint8_t curAlternateSetting;
-    uint8_t curConfiguration;
-    uint8_t configurationNum;
-
-    /** Setup request data buffer */
-    USBD_DevReqData_T reqData;
-
-    /** Endpoint buffer management */
-    USBD_CtrlBuf_T inBuf[USB_EP_MAX_NUM];
-    USBD_CtrlBuf_T outBuf[USB_EP_MAX_NUM];
-
-    /** Descriptor pointer */
-    USBD_Descriptor_T *pDeviceDesc;
-    USBD_Descriptor_T *pConfigurationDesc;
-    USBD_Descriptor_T *pStringDesc;
-    USBD_Descriptor_T *pQualifierDesc;
-    USBD_Descriptor_T *pHidReportDesc;
-
-    /** Setup request callback handler */
-    USBD_StdReqCallback_T *pStdReqCallback;
-    USBD_ReqHandler_T     stdReqExceptionHandler;
-    USBD_ReqHandler_T     classReqHandler;
-    USBD_ReqHandler_T     vendorReqHandler;
-
-    /** Control transfer status stage handler */
-    USBD_CtrlTxStatusHandler_T txStatusHandler;
-    USBD_CtrlRxStatusHandler_T rxStatusHandler;
-
-    /** Endpoint transfer done handler */
-    USBD_EPHandler_T      outEpHandler;
-    USBD_EPHandler_T      inEpHandler;
-
-    USBD_ResetHandler_T   resetHandler;
-    USBD_InterruptHandler_T intHandler;
-} USBD_Info_T;
-
-extern USBD_Info_T g_usbDev;
-
-/** control status function */
-#define USBD_CtrlTxStatus()         USBD_CtrlInData(NULL, 0);
-#define USBD_CtrlRxStatus()         USBD_CtrlOutData(NULL, 0)
-
-/** Handler Endpoint 0 control transfer */
-void USBD_SetupProcess(void);
-void USBD_CtrlInProcess(void);
-void USBD_CtrlOutProcess(void);
-void USBD_CtrlOutData(uint8_t *buf, uint32_t len);
-void USBD_CtrlInData(uint8_t *buf, uint32_t len);
-
-/** Handler other Endpoint data transfer */
-void USBD_DataInProcess(USBD_EP_T ep);
-void USBD_DataOutProcess(USBD_EP_T ep);
-void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len);
-void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h

@@ -1,64 +0,0 @@
-/*!
- * @file        usbd_init.h
- *
- * @brief       USB initialization management head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef USBD_INIT_H_
-#define USBD_INIT_H_
-
-#include "usbd_core.h"
-
-/**
- * @brief   Endpoint Configuration Info
- */
-typedef struct
-{
-    USBD_EP_T      epNum;      //!< endpoint number
-    USBD_EP_TYPE_T epType;     //!< endpoint type
-    uint8_t        epKind;     /**
-                                * Which could be ENABLE or DISABLE, it is valid only for
-                                * control and bulk Endpoint. The mean of ENABLE for them like :
-                                * 1. Control endpoint : Only for OUT status which is zero data.
-                                * 2. Bulk endpoint : Enable the double-buffer feature
-                               */
-    USBD_EP_STATUS_T epStatus; //!< Endpoint status
-    uint16_t epBufAddr;        //!< buffer address for the endpoint
-    uint16_t maxPackSize;      //!< max packet size for the endpoint
-} USBD_EPConfig_T;
-
-/** USB init */
-void USBD_Init(USBD_InitParam_T *param);
-void USBD_InitParamStructInit(USBD_InitParam_T *param);
-
-/** power */
-void USBD_PowerOn(void);
-void USBD_PowerOff(void);
-
-/** Endpoint init */
-void USBD_OpenOutEP(USBD_EPConfig_T *epConfig);
-void USBD_OpenInEP(USBD_EPConfig_T *epConfig);
-
-void USBD_CloseOutEP(USBD_EP_T ep);
-void USBD_CloseInEP(USBD_EP_T ep);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h

@@ -1,31 +0,0 @@
-/*!
- * @file        usbd_interrupt.h
- *
- * @brief       USB interrupt service routine header file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_INTERRUPT_H_
-#define __USBD_INTERRUPT_H_
-
-#include "apm32f10x.h"
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h

@@ -1,31 +0,0 @@
-/*!
- * @file        usbd_stdReq.h
- *
- * @brief       USB standard request process head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-30
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_STDREQ_H_
-#define __USBD_STDREQ_H_
-
-void USBD_StandardReqeust(void);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c

@@ -1,405 +0,0 @@
-/*!
- * @file        usbd_core.c
- *
- * @brief       USB protocol core handler
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-#include "usbd_stdReq.h"
-
-/** USB information */
-USBD_Info_T g_usbDev;
-
-/*!
- * @brief       Endpoint 0 Setup process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_SetupProcess(void)
-{
-    uint8_t reqType;
-    uint8_t dataBuf[8];
-    USBD_DevReqData_T *pReqData = &g_usbDev.reqData;
-    uint16_t xferLen = USBD_ReadEPRxCnt(USBD_EP_0);
-
-    if (xferLen)
-    {
-        USBD_ReadDataFromEP(USBD_EP_0, (uint8_t *)dataBuf, xferLen);
-    }
-    else
-    {
-        return;
-    }
-
-    pReqData->byte.bmRequestType.byte = dataBuf[0];
-    pReqData->byte.bRequest = dataBuf[1];
-    pReqData->byte.wValue[0] = dataBuf[2];
-    pReqData->byte.wValue[1] = dataBuf[3];
-    pReqData->byte.wIndex[0] = dataBuf[4];
-    pReqData->byte.wIndex[1] = dataBuf[5];
-    pReqData->byte.wLength[0] = dataBuf[6];
-    pReqData->byte.wLength[1] = dataBuf[7];
-
-    reqType = pReqData->byte.bmRequestType.bit.type;
-
-    if (reqType == USBD_REQ_TYPE_STANDARD)
-    {
-        USBD_StandardReqeust();
-    }
-    else if (reqType == USBD_REQ_TYPE_CLASS)
-    {
-        if (g_usbDev.classReqHandler)
-        {
-            g_usbDev.classReqHandler(pReqData);
-        }
-    }
-    else if (reqType == USBD_REQ_TYPE_VENDOR)
-    {
-        if (g_usbDev.vendorReqHandler)
-        {
-            g_usbDev.vendorReqHandler(pReqData);
-        }
-    }
-    else
-    {
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-    }
-}
-
-
-/*!
- * @brief       Endpoint 0 USB Control in process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_CtrlInProcess(void)
-{
-    uint32_t tmp;
-
-    if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_IN)
-    {
-        if (g_usbDev.inBuf[0].packNum)
-        {
-            tmp = USB_MIN(g_usbDev.inBuf[0].bufLen, g_usbDev.inBuf[0].maxPackSize);
-
-            USBD_WriteDataToEP(USBD_EP_0, g_usbDev.inBuf[0].pBuf, tmp);
-            USBD_SetEPTxCnt(USBD_EP_0, tmp);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            g_usbDev.inBuf[0].pBuf += tmp;
-            g_usbDev.inBuf[0].bufLen -= tmp;
-            g_usbDev.inBuf[0].packNum--;
-        }
-        else
-        {
-            if (g_usbDev.inBuf[USBD_EP_0].zeroPackFill)
-            {
-                USBD_SetEPTxCnt(USBD_EP_0, 0);
-                USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
-                g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 0;
-            }
-            else
-            {
-                if (g_usbDev.rxStatusHandler)
-                {
-                    g_usbDev.rxStatusHandler();
-                }
-
-                g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
-                USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-            }
-
-        }
-    }
-    else if (g_usbDev.ctrlState == USBD_CTRL_STATE_WAIT_STATUS_IN)
-    {
-        if (g_usbDev.reqData.byte.bRequest == USBD_SET_ADDRESS)
-        {
-            USBD_SetDeviceAddr(g_usbDev.reqData.byte.wValue[0]);
-        }
-    }
-}
-
-/*!
- * @brief       Endpoint 0 USB Control out process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_CtrlOutProcess(void)
-{
-    uint32_t len;
-
-    if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_OUT)
-    {
-        if (g_usbDev.outBuf[0].packNum)
-        {
-            len = USB_MIN(g_usbDev.outBuf[0].bufLen, g_usbDev.outBuf[0].maxPackSize);
-
-            USBD_ReadDataFromEP(USBD_EP_0, g_usbDev.outBuf[0].pBuf, len);
-
-            g_usbDev.outBuf[0].bufLen -= len;
-            g_usbDev.outBuf[0].pBuf += len;
-            g_usbDev.outBuf[0].packNum--;
-
-            if (g_usbDev.outBuf[0].packNum)
-            {
-                USBD_CtrlOutData(g_usbDev.outBuf[0].pBuf, g_usbDev.outBuf[0].bufLen);
-            }
-            else
-            {
-                USBD_CtrlTxStatus();
-            }
-        }
-        else
-        {
-            if (g_usbDev.txStatusHandler)
-            {
-                g_usbDev.txStatusHandler();
-            }
-
-            USBD_CtrlTxStatus();
-        }
-    }
-}
-
-/*!
- * @brief       Send data or status in control in transation
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_CtrlInData(uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.inBuf[0].maxPackSize;
-    uint16_t reqLen = *(uint16_t *)g_usbDev.reqData.byte.wLength;
-
-    if (len)
-    {
-        if ((len < reqLen) && ((len % maxPackSize) == 0))
-        {
-            g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 1;
-        }
-
-        if (len >= g_usbDev.inBuf[0].maxPackSize)
-        {
-            /** Send a packet */
-            USBD_WriteDataToEP(USBD_EP_0, buf, g_usbDev.inBuf[0].maxPackSize);
-            USBD_SetEPTxCnt(USBD_EP_0, g_usbDev.inBuf[0].maxPackSize);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            /** deal with buffer */
-            g_usbDev.inBuf[0].bufLen = len - g_usbDev.inBuf[0].maxPackSize;
-            g_usbDev.inBuf[0].pBuf = buf + g_usbDev.inBuf[0].maxPackSize;
-            g_usbDev.inBuf[0].packNum = (g_usbDev.inBuf[0].bufLen + (maxPackSize - 1)) / maxPackSize;
-
-            g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_IN;
-        }
-        else
-        {
-            USBD_WriteDataToEP(USBD_EP_0, buf, len);
-            USBD_SetEPTxCnt(USBD_EP_0, len);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
-                                 USBD_CTRL_STATE_DATA_IN : \
-                                 USBD_CTRL_STATE_WAIT_STATUS_IN;
-        }
-    }
-    else
-    {
-        USBD_SetEPTxCnt(USBD_EP_0, 0);
-        USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
-
-        g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
-                             USBD_CTRL_STATE_DATA_IN : \
-                             USBD_CTRL_STATE_WAIT_STATUS_IN;
-    }
-}
-
-/*!
- * @brief       Read data or status in control out transation
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_CtrlOutData(uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
-
-    if (len)
-    {
-        g_usbDev.outBuf[USBD_EP_0].pBuf = buf;
-        g_usbDev.outBuf[USBD_EP_0].bufLen = len;
-        g_usbDev.outBuf[USBD_EP_0].packNum = (len + (maxPackSize - 1)) / maxPackSize;
-
-        len = USB_MIN(g_usbDev.outBuf[0].bufLen, maxPackSize);
-
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-
-        g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_OUT;
-    }
-    else
-    {
-        g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
-    }
-
-    USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-}
-
-/*!
- * @brief       USB Data in process except endpoint 0
- *
- * @param       ep : endpoint Number except endpoint 0
- *
- * @retval      None
- */
-void USBD_DataInProcess(USBD_EP_T ep)
-{
-    uint16_t len;
-
-    if (g_usbDev.inBuf[ep].packNum)
-    {
-        len = g_usbDev.inBuf[ep].bufLen > g_usbDev.inBuf[ep].maxPackSize ? \
-              g_usbDev.inBuf[ep].maxPackSize : g_usbDev.inBuf[ep].bufLen;
-
-
-        USBD_WriteDataToEP(ep, g_usbDev.inBuf[ep].pBuf, len);
-        USBD_SetEPTxCnt(ep, len);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].pBuf += len;
-        g_usbDev.inBuf[ep].bufLen -= len;
-        g_usbDev.inBuf[ep].packNum--;
-    }
-    else
-    {
-        if (g_usbDev.inEpHandler)
-        {
-            g_usbDev.inEpHandler(ep);
-        }
-    }
-}
-
-/*!
- * @brief       USB Data out process except endpoint 0
- *
- * @param       ep : endpoint Number except endpoint 0
- *
- * @retval      None
- */
-void USBD_DataOutProcess(USBD_EP_T ep)
-{
-    if (g_usbDev.outBuf[ep].packNum)
-    {
-        g_usbDev.outBuf[ep].xferCnt = USBD_ReadEPRxCnt(ep);
-
-        if ((g_usbDev.outBuf[ep].xferCnt != 0) && (g_usbDev.outBuf[ep].pBuf != NULL))
-        {
-            USBD_ReadDataFromEP(ep, g_usbDev.outBuf[ep].pBuf, g_usbDev.outBuf[ep].xferCnt);
-
-            g_usbDev.outBuf[ep].bufLen -= g_usbDev.outBuf[ep].xferCnt;
-            g_usbDev.outBuf[ep].pBuf += g_usbDev.outBuf[ep].xferCnt;
-            g_usbDev.outBuf[ep].packNum--;
-        }
-        if (g_usbDev.outBuf[ep].packNum)
-        {
-            USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
-        }
-    }
-
-    if (g_usbDev.outEpHandler && !g_usbDev.outBuf[ep].packNum)
-    {
-        g_usbDev.outEpHandler(ep);
-    }
-}
-
-/*!
- * @brief       Transfer data to host(except endpoint 0)
- *
- * @param       ep:     Endpoint number except endpoint 0
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.inBuf[ep].maxPackSize;
-
-    if (len >= maxPackSize)
-    {
-        USBD_WriteDataToEP(ep, buf, maxPackSize);
-        USBD_SetEPTxCnt(ep, maxPackSize);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].pBuf = buf + maxPackSize;
-        g_usbDev.inBuf[ep].bufLen = len - maxPackSize;
-        g_usbDev.inBuf[ep].packNum = (g_usbDev.inBuf[ep].bufLen + (maxPackSize - 1)) / maxPackSize;
-    }
-    else
-    {
-        USBD_WriteDataToEP(ep, buf, len);
-        USBD_SetEPTxCnt(ep, len);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].packNum = 0;
-        g_usbDev.inBuf[ep].bufLen = 0;
-    }
-}
-
-/*!
- * @brief       Receive data from host(except endpoint 0)
- *
- * @param       ep:     Endpoint number except endpoint 0
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.outBuf[ep].maxPackSize;
-
-    g_usbDev.outBuf[ep].pBuf = buf;
-    g_usbDev.outBuf[ep].bufLen = len;
-    g_usbDev.outBuf[ep].packNum = (len + (maxPackSize - 1)) / maxPackSize;
-
-    USBD_SetEPRxCnt(ep, USB_MIN(len, maxPackSize));
-
-    USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c

@@ -1,237 +0,0 @@
-/*!
- * @file        usbd_init.c
- *
- * @brief       USB initialization management
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_init.h"
-#include "usb_bsp.h"
-
-static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType);
-
-/*!
- * @brief       USB initialization
- *
- * @param       param: Initialization parameter
- *
- * @retval      None
- */
-void USBD_Init(USBD_InitParam_T *param)
-{
-    g_usbDev.pDeviceDesc = param->pDeviceDesc;
-    g_usbDev.pConfigurationDesc = param->pConfigurationDesc;
-    g_usbDev.pStringDesc = param->pStringDesc;
-    g_usbDev.pQualifierDesc = param->pQualifierDesc;
-    g_usbDev.pHidReportDesc = param->pHidReportDesc;
-
-    g_usbDev.pStdReqCallback = param->pStdReqCallback;
-    g_usbDev.classReqHandler = param->classReqHandler;
-    g_usbDev.vendorReqHandler = param->vendorReqHandler;
-    g_usbDev.stdReqExceptionHandler = param->stdReqExceptionHandler;
-
-    g_usbDev.txStatusHandler = param->txStatusHandler;
-    g_usbDev.rxStatusHandler = param->rxStatusHandler;
-
-    g_usbDev.inEpHandler = param->inEpHandler;
-    g_usbDev.outEpHandler = param->outEpHandler;
-
-    g_usbDev.resetHandler = param->resetHandler;
-    g_usbDev.intHandler = param->intHandler;
-
-    USBD_HardWareInit();
-
-#ifndef APM32F0xx_USB
-#if USB_SELECT == USB1
-    USBD2_Disable();
-#else
-    USB2_Enable();
-#endif
-#endif
-
-    USBD_PowerOn();
-}
-
-/*!
- * @brief       Init parameter in param
- *
- * @param       param: Initialization parameter
- *
- * @retval      None
- */
-void USBD_InitParamStructInit(USBD_InitParam_T *param)
-{
-    param->pStdReqCallback = NULL;
-    param->stdReqExceptionHandler = NULL;
-    param->classReqHandler = NULL;
-    param->vendorReqHandler = NULL;
-
-    param->txStatusHandler = NULL;
-    param->rxStatusHandler = NULL;
-
-    param->outEpHandler = NULL;
-    param->inEpHandler = NULL;
-
-    param->resetHandler = NULL;
-    param->intHandler = NULL;
-}
-
-/*!
- * @brief       USB Power on
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_PowerOn(void)
-{
-    USBD_ResetPowerDown();
-
-    USBD_SetForceReset();
-    USBD_ResetForceReset();
-
-    USBD_DisableInterrupt(USBD_INT_ALL);
-    USBD_ClearIntFlag(USBD_INT_ALL);
-
-    USBD_EnableInterrupt(USB_INT_SOURCE);
-}
-
-/*!
- * @brief       USB Power off
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_PowerOff(void)
-{
-    USBD_DisableInterrupt(USBD_INT_ALL);
-    USBD_ClearIntFlag(USBD_INT_ALL);
-
-    /** Power down and Force USB Reset */
-    USBD_SetRegCTRL(0X03);
-}
-
-
-/*!
- * @brief       Open OUT endpoint.
- *
- * @param       epConfig: Point to USBD_EPConfig_T structure
- *
- * @retval      None
- */
-void USBD_OpenOutEP(USBD_EPConfig_T *epConfig)
-{
-    g_usbDev.outBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
-
-    USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
-
-    if (epConfig->epKind)
-    {
-        USBD_SetEPKind(epConfig->epNum);
-    }
-    else
-    {
-        USBD_ResetEPKind(epConfig->epNum);
-    }
-
-    USBD_SetEPRxAddr(epConfig->epNum, epConfig->epBufAddr);
-    USBD_SetEPRxCnt(epConfig->epNum, epConfig->maxPackSize);
-    USBD_SetEPRxStatus(epConfig->epNum, epConfig->epStatus);
-}
-
-/*!
- * @brief       Open IN endpoint.
- *
- * @param       epConfig: Point to USBD_EPConfig_T structure
- *
- * @retval      None
- */
-void USBD_OpenInEP(USBD_EPConfig_T *epConfig)
-{
-    g_usbDev.inBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
-
-    USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
-
-    if (epConfig->epKind)
-    {
-        USBD_SetEPKind(epConfig->epNum);
-    }
-    else
-    {
-        USBD_ResetEPKind(epConfig->epNum);
-    }
-
-    USBD_SetEPTxAddr(epConfig->epNum, epConfig->epBufAddr);
-    USBD_SetEPTxStatus(epConfig->epNum, epConfig->epStatus);
-}
-
-/*!
- * @brief       Close OUT endpoint.
- *
- * @param       ep: OUT endpoint Number
- *
- * @retval      None
- */
-void USBD_CloseOutEP(USBD_EP_T ep)
-{
-    g_usbDev.outBuf[ep].maxPackSize = 0;
-
-    USBD_SetEPRxStatus(ep, USBD_EP_STATUS_DISABLE);
-}
-
-/*!
- * @brief       Close IN endpoint.
- *
- * @param       ep: IN endpoint Number
- *
- * @retval      None
- */
-void USBD_CloseInEP(USBD_EP_T ep)
-{
-    g_usbDev.inBuf[ep].maxPackSize = 0;
-
-    USBD_SetEPTxStatus(ep, USBD_EP_STATUS_DISABLE);
-}
-
-/*!
- * @brief       Convert endpoint Type.
- *
- * @param       epType: endpoint type
- *
- * @retval      Value of USBD_REG_EP_TYPE_T
- */
-static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType)
-{
-    switch (epType)
-    {
-    case USBD_EP_TYPE_CONTROL :
-        return USBD_REG_EP_TYPE_CONTROL;
-    case USBD_EP_TYPE_ISO :
-        return USBD_REG_EP_TYPE_ISO;
-    case USBD_EP_TYPE_BULK :
-        return USBD_REG_EP_TYPE_BULK;
-    case USBD_EP_TYPE_INTERRUPT :
-        return USBD_REG_EP_TYPE_INTERRUPT;
-    default :
-        return USBD_REG_EP_TYPE_CONTROL;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c

@@ -1,349 +0,0 @@
-/*!
- * @file        usbd_interrupt.c
- *
- * @brief       USB interrupt service routine
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_init.h"
-
-static void USBD_LowPriorityProc(void);
-
-static void USBD_ResetIsrHandler(void);
-static void USBD_SuspendIsrHandler(void);
-static void USBD_ResumeIsrHandler(void);
-
-/*!
- * @brief       USB interrupt service routine
- *
- * @param       None
- *
- * @retval      None
- */
-#ifdef APM32F0xx_USB
-    void USB_IRQHandler(void)
-
-#else //!< APM32F10x_USB
-    #if USB_SELECT == USB1
-        void USBD1_LP_CAN1_RX0_IRQHandler(void)
-    #else
-        void USB2_LP_IRQHandler(void)
-    #endif
-#endif
-{
-#if (USB_INT_SOURCE & USBD_INT_CTR)
-    if (USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        USBD_LowPriorityProc();
-    }
-#endif
-
-#if (USB_INT_SOURCE & USBD_INT_RST)
-    if (USBD_ReadIntFlag(USBD_INT_RST))
-    {
-        USBD_ClearIntFlag(USBD_INT_RST);
-        USBD_ResetIsrHandler();
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_PMAOU
-    if (USB_ReadIntFlag(USB_INT_PMAOU))
-    {
-        USB_ClearIntFlag(USB_INT_PMAOU);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_ERR
-
-    if (USB_ReadIntFlag(USB_INT_ERROR))
-    {
-        USB_ClearIntFlag(USB_INT_ERROR);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_WKUP
-    if (USBD_ReadIntFlag(USBD_INT_WKUP))
-    {
-        USBD_ResumeIsrHandler();
-        USBD_ClearIntFlag(USBD_INT_WKUP);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_SUS
-    if (USBD_ReadIntFlag(USBD_INT_SUS))
-    {
-        USBD_SuspendIsrHandler();
-        USBD_ClearIntFlag(USBD_INT_SUS);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_SOF
-    if (USB_ReadIntFlag(USB_INT_SOF))
-    {
-        USB_ClearIntFlag(USB_INT_SOF);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_ESOF
-    if (USB_ReadIntFlag(USB_INT_ESOF))
-    {
-        USB_ClearIntFlag(USB_INT_ESOF);
-    }
-#endif
-}
-
-/*!
- * @brief       USB low priority process
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_LowPriorityProc(void)
-{
-    USBD_EP_T ep;
-
-    while (USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        ep = (USBD_EP_T)USBD_ReadEP();
-
-        /** Endpoint 0 */
-        if (ep == 0)
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_NAK);
-
-            /** Control in */
-            if (USBD_ReadDir() == 0)
-            {
-                USBD_ResetEPTxFlag(USBD_EP_0);
-                USBD_CtrlInProcess();
-            }
-            else
-            {
-                /** Setup */
-                if (USBD_ReadEPSetup(USBD_EP_0) == SET)
-                {
-                    USBD_ResetEPRxFlag(USBD_EP_0);
-                    USBD_SetupProcess();
-                }
-                /** Control out */
-                else
-                {
-                    USBD_ResetEPRxFlag(USBD_EP_0);
-                    USBD_CtrlOutProcess();
-                }
-            }
-        }
-        /** Transfer Handler Except endpoint 0 */
-        else
-        {
-            if (USBD_ReadEPRxFlag(ep))
-            {
-                USBD_ResetEPRxFlag(ep);
-                USBD_DataOutProcess(ep);
-            }
-
-            if (USBD_ReadEPTxFlag(ep))
-            {
-                USBD_ResetEPTxFlag(ep);
-                USBD_DataInProcess(ep);
-            }
-        }
-    }
-}
-
-
-/*!
- * @brief      USB Device Reset
- *
- * @param      None
- *
- * @retval     None
- */
-static void USBD_ResetIsrHandler(void)
-{
-    uint8_t i;
-    USBD_EPConfig_T epConfig;
-
-    g_usbDev.configurationNum = USB_CONFIGURATION_NUM;
-    g_usbDev.curConfiguration = 0;
-    g_usbDev.curInterface = 0;
-    g_usbDev.curAlternateSetting = 0;
-    g_usbDev.curFeature = 0;
-    g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_SETUP;
-
-    g_usbDev.inBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
-    g_usbDev.outBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
-
-    USBD_SetBufferTable(USB_BUFFER_TABLE_ADDR);
-
-    /** Endpoint 0 IN */
-    epConfig.epNum = USBD_EP_0;
-    epConfig.epType = USBD_EP_TYPE_CONTROL;
-    epConfig.epKind = DISABLE;
-    epConfig.epBufAddr = USB_EP0_TX_ADDR;
-    epConfig.maxPackSize = g_usbDev.inBuf[USBD_EP_0].maxPackSize;
-    epConfig.epStatus = USBD_EP_STATUS_NAK;
-    USBD_OpenInEP(&epConfig);
-
-    /** Endpoint 0 OUT */
-    epConfig.epBufAddr = USB_EP0_RX_ADDR;
-    epConfig.maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
-    epConfig.epStatus = USBD_EP_STATUS_VALID;
-    USBD_OpenOutEP(&epConfig);
-
-    if (g_usbDev.resetHandler)
-    {
-        g_usbDev.resetHandler();
-    }
-
-    for (i = 0; i < USB_EP_MAX_NUM; i++)
-    {
-        USBD_SetEpAddr((USBD_EP_T)i, i);
-    }
-
-    USBD_SetDeviceAddr(0);
-    USBD_Enable();
-}
-
-/*!
- * @brief       USB Suspend
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_SuspendIsrHandler(void)
-{
-    uint8_t i;
-    uint16_t bakEP[8];
-#if USB_LOW_POWER_SWITCH
-    uint32_t bakPwrCR;
-    uint32_t tmp;
-#endif
-
-    for (i = 0; i < 8; i++)
-    {
-        bakEP[i] = (uint16_t)USBD->EP[i].EP;
-    }
-
-    USBD_EnableInterrupt(USBD_INT_RST);
-
-    USBD_SetForceReset();
-    USBD_ResetForceReset();
-
-    while (USBD_ReadIntFlag(USBD_INT_RST) == RESET);
-
-    for (i = 0; i < 8; i++)
-    {
-        USBD->EP[i].EP = bakEP[i];
-    }
-
-    USBD_SetForceSuspend();
-
-#if USB_LOW_POWER_SWITCH
-    USBD_SetLowerPowerMode();
-
-    bakPwrCR = PMU->CTRL;
-    tmp = PMU->CTRL;
-    tmp &= (uint32_t)0xfffffffc;
-    tmp |= PMU_REGULATOR_LOWPOWER;
-    PMU->CTRL = tmp;
-
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-    if (USBD_ReadIntFlag(USBD_INT_WKUP) == RESET)
-    {
-        __WFI();
-        SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-    }
-    else
-    {
-        USBD_ClearIntFlag(USBD_INT_WKUP);
-        USBD_ResetForceSuspend();
-        PMU->CTRL = bakPwrCR;
-        SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-    }
-#endif
-}
-
-/*!
- * @brief       Resume
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_ResumeIsrHandler(void)
-{
-#if USB_LOW_POWER_SWITCH
-    USBD_ResetLowerPowerMode();
-#endif
-
-    SystemInit();
-
-    USBD_SetRegCTRL(USB_INT_SOURCE);
-}
-
-#ifndef APM32F0xx_USB
-/*!
- * @brief       USB High priority process
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_HighPriorityProc(void)
-{
-    USBD_EP_T ep;
-
-    while (USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        USBD_ClearIntFlag(USBD_INT_CTR);
-
-        ep = USBD_ReadEP();
-
-        if (USBD_ReadEPRxFlag(ep))
-        {
-            USBD_ResetEPRxFlag(ep);
-
-            g_usbDev.outEpHandler(ep);
-        }
-
-        if (USBD_ReadEPTxFlag(ep))
-        {
-            USBD_ResetEPTxFlag(ep);
-
-            g_usbDev.inEpHandler(ep);
-        }
-    }
-}
-
-#if USB_SELECT == USB1
-    void USBD1_HP_CAN1_TX_IRQHandler(void)
-#else
-    void USB2_HP_IRQHandler(void)
-#endif
-{
-    USBD_HighPriorityProc();
-}
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c

@@ -1,369 +0,0 @@
-/*!
- * @file        usbd_stdReq.c
- *
- * @brief       USB standard request process
- *
- * @version     V1.0.0
- *
- * @date        2021-12-30
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_stdReq.h"
-#include "usbd_core.h"
-#include "usbd_descriptor.h"
-
-static uint8_t USBD_StandardGetConfiguration(void);
-static uint8_t USBD_StandardGetDescriptor(void);
-static uint8_t USBD_StandardGetInterface(void);
-static uint8_t USBD_StandardGetStatus(void);
-
-static uint8_t USBD_StandardSetAddress(void);
-static uint8_t USBD_StandardSetConfiguration(void);
-static uint8_t USBD_StandardSetDescriptor(void);
-static uint8_t USBD_StandardSetFeature(void);
-static uint8_t USBD_StandardSetInterface(void);
-
-static uint8_t USBD_StandardClearFeature(void);
-
-
-/*!
- * @brief       USB request standard request
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_StandardReqeust(void)
-{
-    uint8_t result = 1;
-
-    uint8_t bRequest = g_usbDev.reqData.byte.bRequest;
-
-    switch (bRequest)
-    {
-    case USBD_GET_CONFIGURATION:
-        result = USBD_StandardGetConfiguration();
-        break;
-
-    case USBD_GET_DESCRIPTOR:
-        result = USBD_StandardGetDescriptor();
-        break;
-
-    case USBD_GET_INTERFACE:
-        result = USBD_StandardGetInterface();
-        break;
-
-    case USBD_GET_STATUS:
-        result = USBD_StandardGetStatus();
-        break;
-
-    case USBD_SET_ADDRESS:
-        result = USBD_StandardSetAddress();
-        break;
-
-    case USBD_SET_CONFIGURATION:
-        result = USBD_StandardSetConfiguration();
-        break;
-
-    case USBD_SET_DESCRIPTOR:
-        result = USBD_StandardSetDescriptor();
-        break;
-
-    case USBD_SET_FEATURE:
-        result = USBD_StandardSetFeature();
-        break;
-
-    case USBD_SET_INTERFACE:
-        result = USBD_StandardSetInterface();
-
-        break;
-
-    case USBD_CLEAR_FEATURE:
-        result = USBD_StandardClearFeature();
-        break;
-
-    default:
-
-        break;
-    }
-
-    if (!result)
-    {
-        if (g_usbDev.stdReqExceptionHandler != NULL)
-        {
-            g_usbDev.stdReqExceptionHandler(&g_usbDev.reqData);
-        }
-    }
-}
-
-/*!
- * @brief       Standard request get configuration
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetConfiguration(void)
-{
-    uint8_t recipient = g_usbDev.reqData.byte.bmRequestType.bit.recipient;
-
-    if (recipient == USBD_RECIPIENT_DEVICE)
-    {
-        USBD_CtrlInData(&g_usbDev.curConfiguration, 1);
-
-        if (g_usbDev.pStdReqCallback->getConfigurationHandler)
-        {
-            g_usbDev.pStdReqCallback->getConfigurationHandler();
-        }
-
-
-        return SUCCESS;
-    }
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request get descriptor
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetDescriptor(void)
-{
-    uint8_t ret = SUCCESS;
-    uint32_t len = 0;
-    uint8_t wValue0 = g_usbDev.reqData.byte.wValue[0];
-    uint8_t wValue1 = g_usbDev.reqData.byte.wValue[1];
-
-    if (wValue1 == USBD_DESC_DEVICE)
-    {
-        len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pDeviceDesc->size);
-        USBD_CtrlInData((uint8_t *)g_usbDev.pDeviceDesc->pDesc, len);
-    }
-    else if (wValue1 == USBD_DESC_CONFIGURATION)
-    {
-        len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pConfigurationDesc->size);
-        USBD_CtrlInData((uint8_t *)g_usbDev.pConfigurationDesc->pDesc, len);
-    }
-    else if (wValue1 == USBD_DESC_STRING)
-    {
-        if (wValue0 < SRTING_DESC_NUM)
-        {
-            len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pStringDesc[wValue0].size);
-            USBD_CtrlInData((uint8_t *)g_usbDev.pStringDesc[wValue0].pDesc, len);
-        }
-        else
-        {
-            ret = ERROR;
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-
-    }
-    else
-    {
-        ret = ERROR;
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request get interface
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetInterface(void)
-{
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request get status
- *
- * @param       None
- *
- * @retval      ERROR: 0; SUCCESS : 1
- */
-static uint8_t USBD_StandardGetStatus(void)
-{
-    uint8_t ret = 1;
-
-
-    uint8_t status[2] = {0, 0};
-
-    if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_DEVICE)
-    {
-        if (g_usbDev.curFeature & (1 << 5))
-        {
-            status[0] |= 0x02;
-        }
-
-        if (g_usbDev.curFeature & (1 << 6))
-        {
-            status[0] |= 0x01;
-        }
-
-        USBD_CtrlInData(status, 2);
-
-
-    }
-
-    else if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_INTERFACE)
-    {
-        USBD_CtrlInData(status, 2);
-
-
-    }
-
-    else if ((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_ENDPOINT)
-    {
-
-        if (g_usbDev.reqData.byte.wIndex[0] & 0x80)
-        {
-            if (USBD_ReadEPTxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
-            {
-                status[0] |= 0x01;
-            }
-        }
-        else
-        {
-            if (USBD_ReadEPRxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
-            {
-                status[0] |= 0x01;
-            }
-
-        }
-        USBD_CtrlInData(status, 2);
-
-    }
-    else
-    {
-        ret = 0;
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request set address
- *
- * @param       None
- *
- * @retval      ERROR: 0; SUCCESS : 1
- */
-static uint8_t USBD_StandardSetAddress(void)
-{
-    USBD_DevReqData_T *reqData = &g_usbDev.reqData;
-
-    if ((reqData->byte.wValue[0] < 127) && (reqData->byte.wValue[1] == 0) &&
-            (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
-    {
-        USBD_CtrlInData((void *)0, 0);
-
-        return 1;
-    }
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request set configuration
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardSetConfiguration(void)
-{
-    USBD_DevReqData_T *reqData = &g_usbDev.reqData;
-
-    if ((reqData->byte.wValue[0] <= g_usbDev.configurationNum) && \
-            (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
-    {
-        g_usbDev.curConfiguration = reqData->byte.wValue[0];
-
-        if (g_usbDev.pStdReqCallback->setConfigurationHandler)
-        {
-            g_usbDev.pStdReqCallback->setConfigurationHandler();
-        }
-
-        USBD_CtrlInData((void *)0, 0);
-
-        return 1;
-    }
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request set descriptor
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetDescriptor(void)
-{
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request set feature
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetFeature(void)
-{
-    uint8_t ret = 1;
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request set interface
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetInterface(void)
-{
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request clear feature
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardClearFeature(void)
-{
-    return 0;
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h

@@ -1,942 +0,0 @@
-/*!
- * @file        drv_usb_device.h
- *
- * @brief       This file contains all the prototypes,enumeration and macros for USBD peripheral
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __DRV_USB_DEVICE_H_
-#define __DRV_USB_DEVICE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(APM32F070xB) || defined(APM32F072x8) || defined(APM32F072xB)
-#define APM32F0xx_USB
-#else
-#define APM32F10x_USB
-#endif
-
-#ifdef APM32F0xx_USB
-#include "apm32f0xx.h"
-#include "apm32f0xx_pmu.h"
-#include "apm32f0xx_eint.h"
-#include "apm32f0xx_gpio.h"
-#include "apm32f0xx_rcm.h"
-#include "apm32f0xx_misc.h"
-#include "usb_config.h"
-#else
-#include "apm32f10x.h"
-#include "apm32f10x_pmu.h"
-#include "apm32f10x_eint.h"
-#include "apm32f10x_gpio.h"
-#include "apm32f10x_rcm.h"
-#include "apm32f10x_misc.h"
-#include "usb_config.h"
-#endif
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
-  @{
-*/
-
-/** @addtogroup USBD_Driver USBD Driver
-  @{
-*/
-
-/** @addtogroup USBD_Enumerations Enumerations
-  @{
-*/
-
-/**
- * @brief   USBD Endpoint register bit definition
- */
-typedef enum
-{
-    USBD_EP_BIT_ADDR     = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3),
-    USBD_EP_BIT_TXSTS    = (uint32_t)(BIT4 | BIT5),
-    USBD_EP_BIT_TXDTOG   = (uint32_t)(BIT6),
-    USBD_EP_BIT_CTFT     = (uint32_t)(BIT7),
-    USBD_EP_BIT_KIND     = (uint32_t)(BIT8),
-    USBD_EP_BIT_TYPE     = (uint32_t)(BIT9 | BIT10),
-    USBD_EP_BIT_SETUP    = (uint32_t)(BIT11),
-    USBD_EP_BIT_RXSTS    = (uint32_t)(BIT12 | BIT13),
-    USBD_EP_BIT_RXDTOG   = (uint32_t)(BIT14),
-    USBD_EP_BIT_CTFR     = (uint32_t)(BIT15)
-} USBD_EP_BIT_T;
-
-/**
- * @brief   Endpoint id
- */
-typedef enum
-{
-    USBD_EP_0,
-    USBD_EP_1,
-    USBD_EP_2,
-    USBD_EP_3,
-    USBD_EP_4,
-    USBD_EP_5,
-    USBD_EP_6,
-    USBD_EP_7,
-} USBD_EP_T;
-
-/**
- * @brief   Endpoint status
- */
-typedef enum
-{
-    USBD_EP_STATUS_DISABLE   = ((uint32_t)0),
-    USBD_EP_STATUS_STALL     = ((uint32_t)1),
-    USBD_EP_STATUS_NAK       = ((uint32_t)2),
-    USBD_EP_STATUS_VALID     = ((uint32_t)3),
-} USBD_EP_STATUS_T;
-
-/**
- * @brief   USBD Endpoint type for register
- */
-typedef enum
-{
-    USBD_REG_EP_TYPE_BULK,
-    USBD_REG_EP_TYPE_CONTROL,
-    USBD_REG_EP_TYPE_ISO,
-    USBD_REG_EP_TYPE_INTERRUPT
-} USBD_REG_EP_TYPE_T;
-
-/**@} end of group USBD_Enumerations*/
-
-
-/** @addtogroup USBD_Macros Macros
-  @{
-*/
-
-/** USBD packet memory area base address */
-#define USBD_PMA_ADDR            (0x40006000L)
-
-/** Endpoint register mask value default */
-#define USBD_EP_MASK_DEFAULT     (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR)
-
-/**
- * @brief   USBD interrupt source
- */
-#define USBD_INT_ESOF            0X100
-#define USBD_INT_SOF             0X200
-#define USBD_INT_RST             0X400
-#define USBD_INT_SUS             0x800
-#define USBD_INT_WKUP            0X1000
-#define USBD_INT_ERR             0X2000
-#define USBD_INT_PMAOU           0X4000
-#define USBD_INT_CTR             0X8000
-#define USBD_INT_ALL             0XFF00
-
-/**@} end of group USBD_Macros*/
-
-
-/** @addtogroup USBD_Fuctions Fuctions
-  @{
-*/
-
-/*!
- * @brief       Set CTRL register
- *
- * @param       val:    Register value
- *
- * @retval      None
- *
- */
-#define USBD_SetRegCTRL(val)         (USBD->CTRL = val)
-
-/*!
- * @brief       Set INTSTS register
- *
- * @param       val:    Register value
- *
- * @retval      None
- */
-#define USBD_SetRegINTSTS(val)       (USBD->INTSTS = val)
-
-/*!
- * @brief       Set force reset
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetForceReset()         (USBD->CTRL_B.FORRST = BIT_SET)
-
-/*!
- * @brief       Reset force reset
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetForceReset()       (USBD->CTRL_B.FORRST = BIT_RESET)
-
-/*!
- * @brief       Set power down
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetPowerDown()          (USBD->CTRL_B.PWRDOWN = BIT_SET)
-
-/*!
- * @brief       Reset power down
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetPowerDown()        (USBD->CTRL_B.PWRDOWN = BIT_RESET)
-
-/*!
- * @brief       Set low power mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetLowerPowerMode()     (USBD->CTRL_B.LPWREN = BIT_SET)
-
-/*!
- * @brief       Ret low power mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetLowerPowerMode()   (USBD->CTRL_B.LPWREN = BIT_RESET)
-
-/*!
- * @brief       Set force suspend
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetForceSuspend()       (USBD->CTRL_B.FORSUS = BIT_SET)
-
-/*!
- * @brief       Reset force suspend
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetForceSuspend()     (USBD->CTRL_B.FORSUS = BIT_RESET)
-
-/*!
- * @brief       Read force suspend status
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ReadForceSuspend()      (USBD->CTRL_B.FORSUS)
-
-/*!
- * @brief       Set resume
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetResume()             (USBD->CTRL_B.WUPREQ = BIT_SET)
-
-/*!
- * @brief       Reset resume
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetResume()           (USBD->CTRL_B.WUPREQ = BIT_RESET)
-
-/*!
- * @brief       Enable interrupt
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_EnableInterrupt(int)    (USBD->CTRL |= int)
-
-/*!
- * @brief       Disable interrupt
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_DisableInterrupt(int)   (USBD->CTRL &= (uint32_t)~int)
-
-/*!
- * @brief       Read the specified interrupt flag status
- *
- * @param       int:    Interrupt source
- *
- * @retval      Flag status.0 or not 0
- */
-#define USBD_ReadIntFlag(int)        (USBD->INTSTS & int)
-
-/*!
- * @brief       Clear the specified interrupt flag status
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_ClearIntFlag(int)       (USBD->INTSTS &= (uint32_t)~int)
-
-/*!
- * @brief       Read DOT field value in INTSTS rigister
- *
- * @param       None
- *
- * @retval      DOT field value
- */
-#define USBD_ReadDir()               (USBD->INTSTS_B.DOT)
-
-/*!
- * @brief       Read EPID field value in INTSTS rigister
- *
- * @param       None
- *
- * @retval      EPIDfield value
- */
-#define USBD_ReadEP()                ((USBD_EP_T)(USBD->INTSTS_B.EPID))
-
-/*!
- * @brief       Read EP type
- *
- * @param       ep:     EP number
- *
- * @retval      EP type
- */
-#define USBD_ReadEPType(ep)          (USBD->EP[ep].EP_B.TYPE)
-
-/*!
- * @brief       Read EP Tx status
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx status
- */
-#define USBD_ReadEPTxStatus(ep)      ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS))
-
-/*!
- * @brief       Read EP Rx status
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx status
- */
-#define USBD_ReadEPRxStatus(ep)      ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS))
-
-/*!
- * @brief       Read SETUP field value in EP register
- *
- * @param       ep:     EP number
- *
- * @retval      SETUP field value
- */
-#define USBD_ReadEPSetup(ep)         (USBD->EP[ep].EP_B.SETUP)
-
-/*!
- * @brief       Set buffer table value
- *
- * @param       tab:    Buffer table value
- *
- * @retval      None
- */
-#define USBD_SetBufferTable(tab)     (USBD->BUFFTB_B.BUFFTB = tab)
-
-/*!
- * @brief       Set device address
- *
- * @param       addr:   Device address
- *
- * @retval      None
- */
-#define USBD_SetDeviceAddr(addr)     (USBD->ADDR_B.ADDR = addr)
-
-/*!
- * @brief       Read CTFR field value in EP register
- *
- * @param       ep: Endpoint number
- *
- * @retval      CTFR field value
- */
-#define USBD_ReadEPRxFlag(ep)        (USBD->EP[ep].EP_B.CTFR)
-
-/*!
- * @brief       Read CTFT field value in EP register
- *
- * @param       ep: Endpoint number
- *
- * @retval      CTFT field value
- */
-#define USBD_ReadEPTxFlag(ep)        (USBD->EP[ep].EP_B.CTFT)
-
-/*!
- * @brief       Enable USBD peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_Enable()                (USBD->ADDR_B.USBDEN = BIT_SET)
-
-/*!
- * @brief       Disable USBD peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_Disable()               (USBD->ADDR_B.USBDEN = BIT_RESET)
-
-/*!
- * @brief       Enable USBD2 peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD2_Enable()               (USBD->SWITCH = BIT_SET)
-
-/*!
- * @brief       Disable USBD2 peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD2_Disable()              (USBD->SWITCH = BIT_RESET)
-
-/*!
- * @brief       Read RXDPSTS field value in FRANUM register
- *
- * @param       None
- *
- * @retval      RXDPSTS field value
- */
-#define USBD_ReadRDPS()              (USBD->FRANUM_B.RXDPSTS)
-
-/*!
- * @brief       Read RXDMSTS field value in FRANUM register
- *
- * @param       None
- *
- * @retval      RXDMSTS field value
- */
-#define USBD_ReadRDMS()              (USBD->FRANUM_B.RXDMSTS)
-
-/*!
- * @brief       Read LOCK field value in FRANUM register
- *
- * @param       None
- *
- * @retval      LOCK field value
- */
-#define USBD_ReadLOCK()              (USBD->FRANUM_B.LOCK)
-
-/*!
- * @brief       Read LSOFNUM field value in FRANUM register
- *
- * @param       None
- *
- * @retval      LSOFNUM field value
- */
-#define USBD_ReadLSOF()              (USBD->FRANUM_B.LSOFNUM)
-
-/*!
- * @brief       Read FRANUM field value in FRANUM register
- *
- * @param       None
- *
- * @retval      FRANUM field value
- */
-#define USBD_ReadFRANUM()              (USBD->FRANUM_B.FRANUM)
-
-#ifdef APM32F0xx_USB
-/*!
- * @brief       Read EP Tx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx address pointer
- */
-#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Tx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count pointer
- */
-#define USBD_ReadEPTxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx address pointer
- */
-#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count pointer
- */
-#define USBD_ReadEPRxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Tx addr
- *
- * @retval      None
- */
-#define USBD_SetEPTxAddr(ep, addr)   (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Set EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Rx addr
- *
- * @retval      None
- */
-#define USBD_SetEPRxAddr(ep, addr)   (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Read EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx addr
- */
-#define USBD_ReadEPTxAddr(ep)        ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx addr
- */
-#define USBD_ReadEPRxAddr(ep)        ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Tx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx Buffer Pointer
- */
-#define USBD_ReadEPTxBufferPointer(ep)   (uint16_t *)(USBD_ReadEPTxAddr(ep) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx Buffer Pointer
- */
-#define USBD_ReadEPRxBufferPointer(ep)   (uint16_t *)(USBD_ReadEPRxAddr(ep) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx Count
- *
- * @param       ep:     EP number
- *
- * @param       cnt:    Tx count
- *
- * @retval      None
- */
-#define USBD_SetEPTxCnt(ep, cnt)     (*USBD_ReadEPTxCntPointer(ep) = cnt)
-
-/*!
- * @brief       Read EP Tx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count
- */
-#define USBD_ReadEPTxCnt(ep)        ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Read EP Rx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count
- */
-#define USBD_ReadEPRxCnt(ep)        ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Set BESL Value
- *
- * @param       val: 4-bits BESL Value to be set
- *
- * @retval      None
- */
-#define USBD_SetBESL(val)            (USBD->LPMCTRLSTS_B.BESL = val)
-
-/*!
- * @brief       Set bRemoteWakew Value
- *
- * @param       val: 1-bit bRemoteWakew Value to be set
- *
- * @retval      None
- */
-#define USBD_SetRemoteWakeVal(val)   (USBD->LPMCTRLSTS_B.REMWAKE = val)
-
-/*!
- * @brief       Enable LPM ACK
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableAckLPM()          (USBD->LPMCTRLSTS_B.LPMACKEN = 1)
-
-/*!
- * @brief       Disable LPM ACK
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableAckLPM()         (USBD->LPMCTRLSTS_B.LPMACKEN = 0)
-
-/*!
- * @brief       Disable LPM
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableLPM()             (USBD->LPMCTRLSTS_B.LPMEN = 1)
-
-/*!
- * @brief       Disable LPM
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableLPM()            (USBD->LPMCTRLSTS_B.LPMEN = 0)
-
-/*!
- * @brief       Enable Pull-up of DP line
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnablePullUpDP()        (USBD->BCD_B.DPPUCTRL = 1)
-
-/*!
- * @brief       Disable Pull-up of DP line
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisablePullUpDP()       (USBD->BCD_B.DPPUCTRL = 0)
-
-/*!
- * @brief       Read DM Pull-up Detection Status Flag
- *
- * @param       None
- *
- * @retval      DM Pull-up Detection Status Flag
- */
-#define USBD_DMPullUpStatus()        (USBD->BCD_B.DMPUDFLG)
-
-/*!
- * @brief       Read Secondary Detection Status Flag
- *
- * @param       None
- *
- * @retval      Secondary Detection Status Flag
- */
-#define USBD_SDStatus()              (USBD->BCD_B.SDFLG)
-
-/*!
- * @brief       Read Primary Detection Status Flag
- *
- * @param       None
- *
- * @retval      Primary Detection Status Flag
- */
-#define USBD_PDStatus()              (USBD->BCD_B.PDFLG)
-
-/*!
- * @brief       Read Data Contact Detection Status Flag
- *
- * @param       None
- *
- * @retval      Data Contact Detection Status Flag
- */
-#define USBD_DCDStatus()             (USBD->BCD_B.DCDFLG)
-
-/*!
- * @brief       Enable Secondary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableSDMode()          (USBD->BCD_B.SDEN = 1)
-
-/*!
- * @brief       Disable Secondary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableSDMode()         (USBD->BCD_B.SDEN = 0)
-
-/*!
- * @brief       Enable Primary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnablePDMode()          (USBD->BCD_B.PDEN = 1)
-
-/*!
- * @brief       Disable Primary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisablePDMode()         (USBD->BCD_B.PDEN = 0)
-
-/*!
- * @brief       Enable Data Contact Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableDCDMode()         (USBD->BCD_B.DCDEN = 1)
-
-/*!
- * @brief       Disable Data Contact Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableDCDMode()        (USBD->BCD_B.DCDEN = 0)
-
-/*!
- * @brief       Enable Battery Charging Detector
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableBCD()             (USBD->BCD_B.BCDEN = 1)
-
-/*!
- * @brief       Disable Battery Charging Detector
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableBCD()            (USBD->BCD_B.BCDEN = 0)
-
-#else //!< APM32F10x_USB
-/*!
- * @brief       Read EP Tx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx address pointer
- */
-#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Tx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count pointer
- */
-#define USBD_ReadEPTxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx address pointer
- */
-#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count pointer
- */
-#define USBD_ReadEPRxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Tx addr
- *
- * @retval      None
- */
-#define USBD_SetEPTxAddr(ep, addr)   (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Set EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Rx addr
- *
- * @retval      None
- */
-#define USBD_SetEPRxAddr(ep, addr)   (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Read EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx addr
- */
-#define USBD_ReadEPTxAddr(ep)        ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx addr
- */
-#define USBD_ReadEPRxAddr(ep)        ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Tx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx Buffer Pointer
- */
-#define USBD_ReadEPTxBufferPointer(ep)   (uint32_t *)(((uint32_t)USBD_ReadEPTxAddr(ep) << 1) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx Buffer Pointer
- */
-#define USBD_ReadEPRxBufferPointer(ep)   (uint32_t *)(((uint32_t)USBD_ReadEPRxAddr(ep) << 1) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx Count
- *
- * @param       ep:     EP number
- *
- * @param       cnt:    Tx count
- *
- * @retval      None
- */
-#define USBD_SetEPTxCnt(ep, cnt)     (*USBD_ReadEPTxCntPointer(ep) = cnt)
-
-/*!
- * @brief       Read EP Tx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count
- */
-#define USBD_ReadEPTxCnt(ep)        ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Read EP Rx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count
- */
-#define USBD_ReadEPRxCnt(ep)        ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
-
-#endif
-void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type);
-
-void USBD_SetEPKind(uint8_t ep);
-void USBD_ResetEPKind(uint8_t ep);
-
-void USBD_ResetEPRxFlag(uint8_t ep);
-void USBD_ResetEPTxFlag(uint8_t ep);
-
-void USBD_ToggleTx(uint8_t ep);
-void USBD_ToggleRx(uint8_t ep);
-void USBD_ResetTxToggle(uint8_t ep);
-void USBD_ResetRxToggle(uint8_t ep);
-
-void USBD_SetEpAddr(uint8_t ep, uint8_t addr);
-
-void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status);
-void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status);
-void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus);
-
-void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt);
-
-void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen);
-void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen);
-
-/**@} end of group USBD_Fuctions*/
-/**@} end of group USBD_Driver*/
-/**@} end of group Peripherals_Library*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DRV_USB_DEVICE_H */

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/src/drv_usb_device.c

@@ -1,403 +0,0 @@
-/*!
- * @file        drv_usb_device.c
- *
- * @brief       This file contains all the functions for the USBD peripheral
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "drv_usb_device.h"
-
-/*!
- * @brief       Set Endpoint type
- *
- * @param       ep: Endpoint number
- *
- * @param       type: Endpoint type
- *
- * @retval      None
- */
-void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_TYPE;
-    reg |= type << 9;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP kind
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_SetEPKind(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_KIND;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset EP kind
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPKind(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_KIND;
-
-    USBD->EP[ep].EP = reg;
-}
-
-
-/*!
- * @brief       Reset EP CTFR bit
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPRxFlag(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_CTFR;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset EP CTFT bit
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPTxFlag(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_CTFT;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Toggle Tx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ToggleTx(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_TXDTOG;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Toggle Rx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ToggleRx(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_RXDTOG;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset Toggle Tx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetTxToggle(uint8_t ep)
-{
-    if (USBD->EP[ep].EP_B.TXDTOG)
-    {
-        USBD_ToggleTx(ep);
-    }
-}
-
-/*!
- * @brief       Reset Toggle Rx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetRxToggle(uint8_t ep)
-{
-    if (USBD->EP[ep].EP_B.RXDTOG)
-    {
-        USBD_ToggleRx(ep);
-    }
-}
-
-/*!
- * @brief       Set EP address
- *
- * @param       ep: Endpoint number
- *
- * @param       addr: Address
- *
- * @retval      None
- */
-void USBD_SetEpAddr(uint8_t ep, uint8_t addr)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_ADDR;
-    reg |= addr;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Tx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status)
-{
-    __IOM uint32_t reg;
-
-    status <<= 4;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS);
-    reg ^= ((uint32_t)status & (uint32_t)USBD_EP_BIT_TXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Rx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status)
-{
-    __IOM uint32_t reg;
-    uint32_t tmp;
-
-    tmp = status << 12;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS);
-    reg ^= (tmp & USBD_EP_BIT_RXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-
-/*!
- * @brief       Set EP Tx and Rx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus)
-{
-    __IOM uint32_t reg;
-    uint32_t tmp;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS);
-
-    tmp = rxStatus << 12;
-    reg ^= (tmp & USBD_EP_BIT_RXSTS);
-
-    tmp = txStatus << 4;
-    reg ^= (tmp & USBD_EP_BIT_TXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Rx Count
- *
- * @param       ep: Endpoint number
- *
- * @param       cnt: Rx count
- *
- * @retval      None
- */
-void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt)
-{
-    __IOM uint16_t *p;
-    __IOM uint16_t block = 0;
-
-    p = USBD_ReadEPRxCntPointer(ep);
-
-    if (cnt > 62)
-    {
-        block = cnt >> 5;
-
-        if (!(cnt & 0x1f))
-        {
-            block -= 1;
-        }
-
-        *p = (block << 10) | 0x8000;
-    }
-    else
-    {
-        block = cnt >> 1;
-
-        if (cnt & 0x01)
-        {
-            block += 1;
-        }
-
-        *p = (block << 10);
-    }
-}
-
-/*!
- * @brief       Write a buffer of data to a selected endpoint
- *
- * @param       ep:   Endpoint number
- *
- * @retval      wBuf: The pointer to the buffer of data to be written to the endpoint
- *
- * @param       wLen: Number of data to be written (in bytes)
- *
- * @retval      None
- */
-void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen)
-{
-    uint32_t i;
-#ifdef APM32F0xx_USB
-    uint16_t *epAddr;
-    uint16_t tmp;
-#else
-    uint32_t *epAddr;
-    uint32_t tmp;
-#endif
-
-    wLen = (wLen + 1) >> 1;
-
-    epAddr = USBD_ReadEPTxBufferPointer(ep);
-
-    for (i = 0; i < wLen; i++)
-    {
-        tmp = *wBuf++;
-        tmp = ((*wBuf++) << 8) | tmp;
-
-        *epAddr++ = tmp;
-    }
-}
-
-/*!
- * @brief       Read a buffer of data to a selected endpoint
- *
- * @param       ep:   Endpoint number
- *
- * @retval      wBuf: The pointer to the buffer of data to be read to the endpoint
- *
- * @param       wLen: Number of data to be read (in bytes)
- *
- * @retval      None
- */
-void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen)
-{
-#ifdef APM32F0xx_USB
-    uint16_t *epAddr;
-#else
-    uint32_t *epAddr;
-#endif
-    uint32_t i, tmp, cnt;
-
-    cnt = rLen >> 1;
-
-    epAddr = USBD_ReadEPRxBufferPointer(ep);
-
-    for (i = 0; i < cnt; i++)
-    {
-        tmp = *epAddr++;
-        *rBuf++ = tmp & 0xFF;
-        *rBuf++ = (tmp >> 8) & 0xFF;
-    }
-
-    if (rLen & 1)
-    {
-        tmp = *epAddr;
-        *rBuf = tmp & 0xFF;
-    }
-}

bsp/at32/libraries/f403a_407/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- firmware

bsp/at32/libraries/f403a_407/SConscript

@@ -1,14 +0,0 @@
-# for module compiling
-import os
-from building import *
-
-cwd = GetCurrentDir()
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')

bsp/at32/libraries/f403a_407/firmware/SConscript

@@ -1,46 +0,0 @@
-import rtconfig
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-cmsis/cm4/device_support/system_at32f403a_407.c
-drivers/src/at32f403a_407_acc.c
-drivers/src/at32f403a_407_adc.c
-drivers/src/at32f403a_407_bpr.c
-drivers/src/at32f403a_407_can.c
-drivers/src/at32f403a_407_crc.c
-drivers/src/at32f403a_407_crm.c
-drivers/src/at32f403a_407_dac.c
-drivers/src/at32f403a_407_debug.c
-drivers/src/at32f403a_407_dma.c
-drivers/src/at32f403a_407_emac.c
-drivers/src/at32f403a_407_exint.c
-drivers/src/at32f403a_407_flash.c
-drivers/src/at32f403a_407_gpio.c
-drivers/src/at32f403a_407_i2c.c
-drivers/src/at32f403a_407_misc.c
-drivers/src/at32f403a_407_pwc.c
-drivers/src/at32f403a_407_rtc.c
-drivers/src/at32f403a_407_sdio.c
-drivers/src/at32f403a_407_spi.c
-drivers/src/at32f403a_407_tmr.c
-drivers/src/at32f403a_407_usart.c
-drivers/src/at32f403a_407_usb.c
-drivers/src/at32f403a_407_wdt.c
-drivers/src/at32f403a_407_wwdt.c
-drivers/src/at32f403a_407_xmc.c
-""")
-
-path = [
-    cwd + '/cmsis/cm4/device_support',
-    cwd + '/cmsis/cm4/core_support',
-    cwd + '/drivers/inc',]
-
-CPPDEFINES = ['USE_STDPERIPH_DRIVER']
-
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_common_tables.h

@@ -1,517 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-  /* Double Precision Float CFFT twiddles */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
-    extern const uint16_t armBitRevTable[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
-    extern const uint64_t twiddleCoefF64_16[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
-    extern const uint64_t twiddleCoefF64_32[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
-    extern const uint64_t twiddleCoefF64_64[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
-    extern const uint64_t twiddleCoefF64_128[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
-    extern const uint64_t twiddleCoefF64_256[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
-    extern const uint64_t twiddleCoefF64_512[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
-    extern const uint64_t twiddleCoefF64_1024[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
-    extern const uint64_t twiddleCoefF64_2048[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
-    extern const uint64_t twiddleCoefF64_4096[8192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
-    extern const float32_t twiddleCoef_16[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
-    extern const float32_t twiddleCoef_32[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
-    extern const float32_t twiddleCoef_64[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
-    extern const float32_t twiddleCoef_128[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
-    extern const float32_t twiddleCoef_256[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
-    extern const float32_t twiddleCoef_512[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
-    extern const float32_t twiddleCoef_1024[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
-    extern const float32_t twiddleCoef_2048[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
-    extern const float32_t twiddleCoef_4096[8192];
-    #define twiddleCoef twiddleCoef_4096
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
-    extern const q31_t twiddleCoef_16_q31[24];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
-    extern const q31_t twiddleCoef_32_q31[48];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
-    extern const q31_t twiddleCoef_64_q31[96];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
-    extern const q31_t twiddleCoef_128_q31[192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
-    extern const q31_t twiddleCoef_256_q31[384];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
-    extern const q31_t twiddleCoef_512_q31[768];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
-    extern const q31_t twiddleCoef_1024_q31[1536];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
-    extern const q31_t twiddleCoef_2048_q31[3072];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
-    extern const q31_t twiddleCoef_4096_q31[6144];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
-    extern const q15_t twiddleCoef_16_q15[24];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
-    extern const q15_t twiddleCoef_32_q15[48];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
-    extern const q15_t twiddleCoef_64_q15[96];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
-    extern const q15_t twiddleCoef_128_q15[192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
-    extern const q15_t twiddleCoef_256_q15[384];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
-    extern const q15_t twiddleCoef_512_q15[768];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
-    extern const q15_t twiddleCoef_1024_q15[1536];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
-    extern const q15_t twiddleCoef_2048_q15[3072];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
-    extern const q15_t twiddleCoef_4096_q15[6144];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  /* Double Precision Float RFFT twiddles */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
-    extern const uint64_t twiddleCoefF64_rfft_32[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
-    extern const uint64_t twiddleCoefF64_rfft_64[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
-    extern const uint64_t twiddleCoefF64_rfft_128[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
-    extern const uint64_t twiddleCoefF64_rfft_256[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
-    extern const uint64_t twiddleCoefF64_rfft_512[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
-    extern const uint64_t twiddleCoefF64_rfft_1024[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
-    extern const uint64_t twiddleCoefF64_rfft_2048[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
-    extern const uint64_t twiddleCoefF64_rfft_4096[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
-    extern const float32_t twiddleCoef_rfft_32[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
-    extern const float32_t twiddleCoef_rfft_64[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
-    extern const float32_t twiddleCoef_rfft_128[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
-    extern const float32_t twiddleCoef_rfft_256[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
-    extern const float32_t twiddleCoef_rfft_512[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
-    extern const float32_t twiddleCoef_rfft_1024[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
-    extern const float32_t twiddleCoef_rfft_2048[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
-    extern const float32_t twiddleCoef_rfft_4096[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  /* Double precision floating-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
-    #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
-    extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
-    #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
-    extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
-    #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
-    #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
-    extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
-    #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
-    extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
-    #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
-    extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
-    #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
-    extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
-    #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
-    extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
-    #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-  /* floating-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
-    #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-    extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
-    #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-    extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
-    #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
-    #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-    extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
-    #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-    extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
-    #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-    extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
-    #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-    extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
-    #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-    extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
-    #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  /* fixed-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
-    #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-    extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
-    #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-    extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
-    #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
-    #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-    extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
-    #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-    extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
-    #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-    extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
-    #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-    extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
-    #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-    extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
-    #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
-    extern const float32_t realCoefA[8192];
-    extern const float32_t realCoefB[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
-    extern const q31_t realCoefAQ31[8192];
-    extern const q31_t realCoefBQ31[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
-    extern const q15_t realCoefAQ15[8192];
-    extern const q15_t realCoefBQ15[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
-    extern const float32_t Weights_128[256];
-    extern const float32_t cos_factors_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
-    extern const float32_t Weights_512[1024];
-    extern const float32_t cos_factors_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
-    extern const float32_t Weights_2048[4096];
-    extern const float32_t cos_factors_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
-    extern const float32_t Weights_8192[16384];
-    extern const float32_t cos_factors_8192[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
-    extern const q15_t WeightsQ15_128[256];
-    extern const q15_t cos_factorsQ15_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
-    extern const q15_t WeightsQ15_512[1024];
-    extern const q15_t cos_factorsQ15_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
-    extern const q15_t WeightsQ15_2048[4096];
-    extern const q15_t cos_factorsQ15_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
-    extern const q15_t WeightsQ15_8192[16384];
-    extern const q15_t cos_factorsQ15_8192[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
-    extern const q31_t WeightsQ31_128[256];
-    extern const q31_t cos_factorsQ31_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
-    extern const q31_t WeightsQ31_512[1024];
-    extern const q31_t cos_factorsQ31_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
-    extern const q31_t WeightsQ31_2048[4096];
-    extern const q31_t cos_factorsQ31_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
-    extern const q31_t WeightsQ31_8192[16384];
-    extern const q31_t cos_factorsQ31_8192[8192];
-  #endif
-
-#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
-    extern const q15_t armRecipTableQ15[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
-    extern const q31_t armRecipTableQ31[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  /* Tables for Fast Math Sine and Cosine */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
-    extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
-    extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
-    extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if defined(ARM_MATH_MVEI)
-     #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
-       extern const q31_t sqrtTable_Q31[256];
-     #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-  #endif
-
-  #if defined(ARM_MATH_MVEI)
-     #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
-       extern const q15_t sqrtTable_Q15[256];
-     #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-  #endif
-
-#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
-
-#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
-       extern const float32_t exp_tab[8];
-       extern const float32_t __logf_lut_f32[8];
-#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
-extern const unsigned char hwLUT[256];
-#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
-
-#endif /*  ARM_COMMON_TABLES_H */
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_const_structs.h

@@ -1,76 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_helium_utils.h

@@ -1,348 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_helium_utils.h
- * Description:  Utility functions for Helium development
- *
- * $Date:        09. September 2019
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_UTILS_HELIUM_H_
-#define _ARM_UTILS_HELIUM_H_
-
-/***************************************
-
-Definitions available for MVEF and MVEI
-
-***************************************/
-#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
-
-#define INACTIVELANE            0 /* inactive lane content */
-
-
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
-
-/***************************************
-
-Definitions available for MVEF only
-
-***************************************/
-#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)
-
-__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
-{
-    float32_t acc;
-
-    acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
-          vgetq_lane(in, 2) + vgetq_lane(in, 3);
-
-    return acc;
-}
-
-/* newton initial guess */
-#define INVSQRT_MAGIC_F32           0x5f3759df
-
-#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
-{                                                     \
-    float32x4_t tmp;                                  \
-                                                      \
-    /* tmp = xhalf * x * x */                         \
-    tmp = vmulq(xStart, xStart);                      \
-    tmp = vmulq(tmp, xHalf);                          \
-    /* (1.5f - xhalf * x * x) */                      \
-    tmp = vsubq(vdupq_n_f32(1.5f), tmp);              \
-    /* x = x*(1.5f-xhalf*x*x); */                     \
-    invSqrt = vmulq(tmp, xStart);                     \
-}
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
-
-/***************************************
-
-Definitions available for MVEI only
-
-***************************************/
-#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)
-
-
-#include "arm_common_tables.h"
-
-/* Following functions are used to transpose matrix in f32 and q31 cases */
-__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
-    uint32_t * pDataSrc,
-    uint32_t * pDataDest)
-{
-    static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
-    /*
-     *
-     * | 0   1 |   =>  |  0   2 |
-     * | 2   3 |       |  1   3 |
-     *
-     */
-    uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
-    uint32_t * pDataSrc,
-    uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    /*
-     *
-     *  | 0   1   2 |       | 0   3   6 |  4 x 32 flattened version | 0   3   6   1 |
-     *  | 3   4   5 |   =>  | 1   4   7 |            =>             | 4   7   2   5 |
-     *  | 6   7   8 |       | 2   5   8 |       (row major)         | 8   .   .   . |
-     *
-     */
-    uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
-
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
-
-    pDataDest[8] = pDataSrc[8];
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    /*
-     * 4x4 Matrix transposition
-     * is 4 x de-interleave operation
-     *
-     * 0   1   2   3       0   4   8   12
-     * 4   5   6   7       1   5   9   13
-     * 8   9   10  11      2   6   10  14
-     * 12  13  14  15      3   7   11  15
-     */
-
-    uint32x4x4_t vecIn;
-
-    vecIn = vld4q((uint32_t const *) pDataSrc);
-    vstrwq(pDataDest, vecIn.val[0]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[1]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[2]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[3]);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
-    uint16_t    srcRows,
-    uint16_t    srcCols,
-    uint32_t  * pDataSrc,
-    uint32_t  * pDataDest)
-{
-    uint32x4_t vecOffs;
-    uint32_t  i;
-    uint32_t  blkCnt;
-    uint32_t const *pDataC;
-    uint32_t *pDataDestR;
-    uint32x4_t vecIn;
-
-    vecOffs = vidupq_u32((uint32_t)0, 1);
-    vecOffs = vecOffs * srcCols;
-
-    i = srcCols;
-    do
-    {
-        pDataC = (uint32_t const *) pDataSrc;
-        pDataDestR = pDataDest;
-
-        blkCnt = srcRows >> 2;
-        while (blkCnt > 0U)
-        {
-            vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
-            vstrwq(pDataDestR, vecIn);
-            pDataDestR += 4;
-            pDataC = pDataC + srcCols * 4;
-            /*
-             * Decrement the blockSize loop counter
-             */
-            blkCnt--;
-        }
-
-        /*
-         * tail
-         */
-        blkCnt = srcRows & 3;
-        if (blkCnt > 0U)
-        {
-            mve_pred16_t p0 = vctp32q(blkCnt);
-            vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
-            vstrwq_p(pDataDestR, vecIn, p0);
-        }
-
-        pDataSrc += 1;
-        pDataDest += srcRows;
-    }
-    while (--i);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
-__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
-{
-    q63x2_t         vecTmpLL;
-    q31x4_t         vecTmp0, vecTmp1;
-    q31_t           scale;
-    q63_t           tmp64;
-    q31x4_t         vecNrm, vecDst, vecIdx, vecSignBits;
-
-
-    vecSignBits = vclsq(vecIn);
-    vecSignBits = vbicq(vecSignBits, 1);
-    /*
-     * in = in << no_of_sign_bits;
-     */
-    vecNrm = vshlq(vecIn, vecSignBits);
-    /*
-     * index = in >> 24;
-     */
-    vecIdx = vecNrm >> 24;
-    vecIdx = vecIdx << 1;
-
-    vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
-
-    vecIdx = vecIdx + 1;
-
-    vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx);
-
-    vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
-    vecTmp0 = vecTmp0 - vecTmp1;
-    vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
-    vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
-    vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
-    vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
-    vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
-
-    /*
-     * scale elements 0, 2
-     */
-    scale = 26 + (vecSignBits[0] >> 1);
-    tmp64 = asrl(vecTmpLL[0], scale);
-    vecDst[0] = (q31_t) tmp64;
-
-    scale = 26 + (vecSignBits[2] >> 1);
-    tmp64 = asrl(vecTmpLL[1], scale);
-    vecDst[2] = (q31_t) tmp64;
-
-    vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
-
-    /*
-     * scale elements 1, 3
-     */
-    scale = 26 + (vecSignBits[1] >> 1);
-    tmp64 = asrl(vecTmpLL[0], scale);
-    vecDst[1] = (q31_t) tmp64;
-
-    scale = 26 + (vecSignBits[3] >> 1);
-    tmp64 = asrl(vecTmpLL[1], scale);
-    vecDst[3] = (q31_t) tmp64;
-    /*
-     * set negative values to 0
-     */
-    vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
-
-    return vecDst;
-}
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
-__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
-{
-    q31x4_t         vecTmpLev, vecTmpLodd, vecSignL;
-    q15x8_t         vecTmp0, vecTmp1;
-    q15x8_t         vecNrm, vecDst, vecIdx, vecSignBits;
-
-    vecDst = vuninitializedq_s16();
-
-    vecSignBits = vclsq(vecIn);
-    vecSignBits = vbicq(vecSignBits, 1);
-    /*
-     * in = in << no_of_sign_bits;
-     */
-    vecNrm = vshlq(vecIn, vecSignBits);
-
-    vecIdx = vecNrm >> 8;
-    vecIdx = vecIdx << 1;
-
-    vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
-
-    vecIdx = vecIdx + 1;
-
-    vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx);
-
-    vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
-    vecTmp0 = vecTmp0 - vecTmp1;
-    vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
-    vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
-    vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
-    vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
-
-    vecSignBits = vecSignBits >> 1;
-
-    vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
-    vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
-
-    vecTmp0 = vecSignBits + 10;
-    /*
-     * negate sign to apply register based vshl
-     */
-    vecTmp0 = -vecTmp0;
-
-    /*
-     * shift even elements
-     */
-    vecSignL = vmovlbq(vecTmp0);
-    vecTmpLev = vshlq(vecTmpLev, vecSignL);
-    /*
-     * shift odd elements
-     */
-    vecSignL = vmovltq(vecTmp0);
-    vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
-    /*
-     * merge and narrow odd and even parts
-     */
-    vecDst = vmovnbq_s32(vecDst, vecTmpLev);
-    vecDst = vmovntq_s32(vecDst, vecTmpLodd);
-    /*
-     * set negative values to 0
-     */
-    vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
-
-    return vecDst;
-}
-#endif
-
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
-
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_math.h

@@ -1,8970 +0,0 @@
-/******************************************************************************
- * @file     arm_math.h
- * @brief    Public header file for CMSIS DSP Library
- * @version  V1.7.0
- * @date     18. March 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
-   * based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filtering functions
-   * - Matrix functions
-   * - Transform functions
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   * - Support Vector Machine functions (SVM)
-   * - Bayes classifier functions
-   * - Distance functions
-   *
-   * The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   *
-   * Here is the list of pre-built libraries :
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   *
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library is now tested on Fast Models building with cmake.
-   * Core M0, M7, A5 are tested.
-   *
-   *
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP\\Projects\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
-   *
-   * There is also a work in progress cmake build. The README file is giving more details.
-   *
-   * Preprocessor Macros
-   * ------------
-   *
-   * Each library project have different preprocessor macros.
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_LOOPUNROLL:
-   *
-   * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
-   *
-   * - ARM_MATH_NEON:
-   *
-   * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
-   * It is not enabled by default when Neon is available because performances are
-   * dependent on the compiler and target architecture.
-   *
-   * - ARM_MATH_NEON_EXPERIMENTAL:
-   *
-   * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
-   * of some DSP functions. Experimental Neon versions currently do not have better
-   * performances than the scalar versions.
-   *
-   * - ARM_MATH_HELIUM:
-   *
-   * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16.
-   *
-   * - ARM_MATH_MVEF:
-   *
-   * Select Helium versions of the f32 algorithms.
-   * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
-   *
-   * - ARM_MATH_MVEI:
-   *
-   * Select Helium versions of the int and fixed point algorithms.
-   *
-   * - ARM_MATH_FLOAT16:
-   *
-   * Float16 implementations of some algorithms (Requires MVE extension).
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                      |Content                                                                 |
-   * |---------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP     | This documentation                                                     |
-   * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite                                                     |
-   * |\b CMSIS\\DSP\\Examples          | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP\\Include           | DSP_Lib include files                                                  |
-   * |\b CMSIS\\DSP\\Lib               | DSP_Lib binaries                                                       |
-   * |\b CMSIS\\DSP\\Projects          | Projects to rebuild DSP_Lib binaries                                   |
-   * |\b CMSIS\\DSP\\Source            | DSP_Lib source files                                                   |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
- * for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-
-/**
- * @defgroup groupSVM SVM Functions
- * This set of functions is implementing SVM classification on 2 classes.
- * The training must be done from scikit-learn. The parameters can be easily
- * generated from the scikit-learn object. Some examples are given in
- * DSP/Testing/PatternGeneration/SVM.py
- *
- * If more than 2 classes are needed, the functions in this folder
- * will have to be used, as building blocks, to do multi-class classification.
- *
- * No multi-class classification is provided in this SVM folder.
- *
- */
-
-
-/**
- * @defgroup groupBayes Bayesian estimators
- *
- * Implement the naive gaussian Bayes estimator.
- * The training must be done from scikit-learn.
- *
- * The parameters can be easily
- * generated from the scikit-learn object. Some examples are given in
- * DSP/Testing/PatternGeneration/Bayes.py
- */
-
-/**
- * @defgroup groupDistance Distance functions
- *
- * Distance functions for use with clustering algorithms.
- * There are distance functions for float vectors and boolean vectors.
- *
- */
-
-
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wsign-conversion"
-  #pragma GCC diagnostic ignored "-Wconversion"
-  #pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#elif defined ( _MSC_VER )
-
-#else
-  #error Unknown compiler
-#endif
-
-
-/* Included for instrinsics definitions */
-#if defined (_MSC_VER )
-#include <stdint.h>
-#define __STATIC_FORCEINLINE static __forceinline
-#define __STATIC_INLINE static __inline
-#define __ALIGNED(x) __declspec(align(x))
-
-#elif defined (__GNUC_PYTHON__)
-#include <stdint.h>
-#define  __ALIGNED(x) __attribute__((aligned(x)))
-#define __STATIC_FORCEINLINE static __attribute__((inline))
-#define __STATIC_INLINE static __attribute__((inline))
-#pragma GCC diagnostic ignored "-Wunused-function"
-#pragma GCC diagnostic ignored "-Wattributes"
-
-#else
-#include "cmsis_compiler.h"
-#endif
-
-
-
-#include <string.h>
-#include <math.h>
-#include <float.h>
-#include <limits.h>
-
-
-#define F64_MAX   ((float64_t)DBL_MAX)
-#define F32_MAX   ((float32_t)FLT_MAX)
-
-#if defined(ARM_MATH_FLOAT16)
-#define F16_MAX   ((float16_t)FLT_MAX)
-#endif
-
-#define F64_MIN   (-DBL_MAX)
-#define F32_MIN   (-FLT_MAX)
-
-#if defined(ARM_MATH_FLOAT16)
-#define F16_MIN   (-(float16_t)FLT_MAX)
-#endif
-
-#define F64_ABSMAX   ((float64_t)DBL_MAX)
-#define F32_ABSMAX   ((float32_t)FLT_MAX)
-
-#if defined(ARM_MATH_FLOAT16)
-#define F16_ABSMAX   ((float16_t)FLT_MAX)
-#endif
-
-#define F64_ABSMIN   ((float64_t)0.0)
-#define F32_ABSMIN   ((float32_t)0.0)
-
-#if defined(ARM_MATH_FLOAT16)
-#define F16_ABSMIN   ((float16_t)0.0)
-#endif
-
-#define Q31_MAX   ((q31_t)(0x7FFFFFFFL))
-#define Q15_MAX   ((q15_t)(0x7FFF))
-#define Q7_MAX    ((q7_t)(0x7F))
-#define Q31_MIN   ((q31_t)(0x80000000L))
-#define Q15_MIN   ((q15_t)(0x8000))
-#define Q7_MIN    ((q7_t)(0x80))
-
-#define Q31_ABSMAX   ((q31_t)(0x7FFFFFFFL))
-#define Q15_ABSMAX   ((q15_t)(0x7FFF))
-#define Q7_ABSMAX    ((q7_t)(0x7F))
-#define Q31_ABSMIN   ((q31_t)0)
-#define Q15_ABSMIN   ((q15_t)0)
-#define Q7_ABSMIN    ((q7_t)0)
-
-/* evaluate ARM DSP feature */
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-  #define ARM_MATH_DSP                   1
-#endif
-
-#if defined(ARM_MATH_NEON)
-#include <arm_neon.h>
-#endif
-
-#if defined (ARM_MATH_HELIUM)
-  #define ARM_MATH_MVEF
-  #define ARM_MATH_FLOAT16
-#endif
-
-#if defined (ARM_MATH_MVEF)
-  #define ARM_MATH_MVEI
-  #define ARM_MATH_FLOAT16
-#endif
-
-#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
-#include <arm_mve.h>
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31          ((q31_t)(0x100))
-#define DELTA_Q15          ((q15_t)0x5)
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-  #define PI               3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-  /**
-   * @brief Macros for complex numbers
-   */
-
-  /* Dimension C vector space */
-  #define CMPLX_DIM 2
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS        =  0,        /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR   = -2,        /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH  = -3,        /**< Size of matrices is not compatible with the operation */
-    ARM_MATH_NANINF         = -4,        /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR       = -5,        /**< Input matrix is singular and cannot be inverted */
-    ARM_MATH_TEST_FAILURE   = -6         /**< Test Failed */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief vector types
-   */
-#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI)
-  /**
-   * @brief 64-bit fractional 128-bit vector data type in 1.63 format
-   */
-  typedef int64x2_t q63x2_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
-   */
-  typedef int32x4_t q31x4_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format.
-   */
-  typedef __ALIGNED(2) int16x8_t q15x8_t;
-
- /**
-   * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format.
-   */
-  typedef __ALIGNED(1) int8x16_t q7x16_t;
-
-    /**
-   * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
-   */
-  typedef int32x4x2_t q31x4x2_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
-   */
-  typedef int32x4x4_t q31x4x4_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
-   */
-  typedef int16x8x2_t q15x8x2_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
-   */
-  typedef int16x8x4_t q15x8x4_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
-   */
-  typedef int8x16x2_t q7x16x2_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
-   */
-   typedef int8x16x4_t q7x16x4_t;
-
-  /**
-   * @brief 32-bit fractional data type in 9.23 format.
-   */
-  typedef int32_t q23_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
-   */
-  typedef int32x4_t q23x4_t;
-
-  /**
-   * @brief 64-bit status 128-bit vector data type.
-   */
-  typedef int64x2_t status64x2_t;
-
-  /**
-   * @brief 32-bit status 128-bit vector data type.
-   */
-  typedef int32x4_t status32x4_t;
-
-  /**
-   * @brief 16-bit status 128-bit vector data type.
-   */
-  typedef int16x8_t status16x8_t;
-
-  /**
-   * @brief 8-bit status 128-bit vector data type.
-   */
-  typedef int8x16_t status8x16_t;
-
-
-#endif
-
-#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
-  /**
-   * @brief 32-bit floating-point 128-bit vector type
-   */
-  typedef float32x4_t f32x4_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit floating-point 128-bit vector data type
-   */
-  typedef __ALIGNED(2) float16x8_t f16x8_t;
-#endif
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector pair data type
-   */
-  typedef float32x4x2_t f32x4x2_t;
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector quadruplet data type
-   */
-  typedef float32x4x4_t f32x4x4_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit floating-point 128-bit vector pair data type
-   */
-  typedef float16x8x2_t f16x8x2_t;
-
-  /**
-   * @brief 16-bit floating-point 128-bit vector quadruplet data type
-   */
-  typedef float16x8x4_t f16x8x4_t;
-#endif
-
-  /**
-   * @brief 32-bit ubiquitous 128-bit vector data type
-   */
-  typedef union _any32x4_t
-  {
-      float32x4_t     f;
-      int32x4_t       i;
-  } any32x4_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit ubiquitous 128-bit vector data type
-   */
-  typedef union _any16x8_t
-  {
-      float16x8_t     f;
-      int16x8_t       i;
-  } any16x8_t;
-#endif
-
-#endif
-
-#if defined(ARM_MATH_NEON)
-  /**
-   * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
-   */
-  typedef int32x2_t  q31x2_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
-   */
-  typedef  __ALIGNED(2) int16x4_t q15x4_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
-   */
-  typedef  __ALIGNED(1) int8x8_t q7x8_t;
-
-  /**
-   * @brief 32-bit float 64-bit vector data type.
-   */
-  typedef float32x2_t  f32x2_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit float 64-bit vector data type.
-   */
-  typedef  __ALIGNED(2) float16x4_t f16x4_t;
-#endif
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector triplet data type
-   */
-  typedef float32x4x3_t f32x4x3_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit floating-point 128-bit vector triplet data type
-   */
-  typedef float16x8x3_t f16x8x3_t;
-#endif
-
-  /**
-   * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
-   */
-  typedef int32x4x3_t q31x4x3_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
-   */
-  typedef int16x8x3_t q15x8x3_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
-   */
-  typedef int8x16x3_t q7x16x3_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector pair data type
-   */
-  typedef float32x2x2_t f32x2x2_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector triplet data type
-   */
-  typedef float32x2x3_t f32x2x3_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector quadruplet data type
-   */
-  typedef float32x2x4_t f32x2x4_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit floating-point 64-bit vector pair data type
-   */
-  typedef float16x4x2_t f16x4x2_t;
-
-  /**
-   * @brief 16-bit floating-point 64-bit vector triplet data type
-   */
-  typedef float16x4x3_t f16x4x3_t;
-
-  /**
-   * @brief 16-bit floating-point 64-bit vector quadruplet data type
-   */
-  typedef float16x4x4_t f16x4x4_t;
-#endif
-
-  /**
-   * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
-   */
-  typedef int32x2x2_t q31x2x2_t;
-
-  /**
-   * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
-   */
-  typedef int32x2x3_t q31x2x3_t;
-
-  /**
-   * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
-   */
-  typedef int32x4x3_t q31x2x4_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
-   */
-  typedef int16x4x2_t q15x4x2_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
-   */
-  typedef int16x4x2_t q15x4x3_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
-   */
-  typedef int16x4x3_t q15x4x4_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
-   */
-  typedef int8x8x2_t q7x8x2_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
-   */
-  typedef int8x8x3_t q7x8x3_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
-   */
-  typedef int8x8x4_t q7x8x4_t;
-
-  /**
-   * @brief 32-bit ubiquitous 64-bit vector data type
-   */
-  typedef union _any32x2_t
-  {
-      float32x2_t     f;
-      int32x2_t       i;
-  } any32x2_t;
-
-#if defined(ARM_MATH_FLOAT16)
-  /**
-   * @brief 16-bit ubiquitous 64-bit vector data type
-   */
-  typedef union _any16x4_t
-  {
-      float16x4_t     f;
-      int16x4_t       i;
-  } any16x4_t;
-#endif
-
-  /**
-   * @brief 32-bit status 64-bit vector data type.
-   */
-  typedef int32x4_t status32x2_t;
-
-  /**
-   * @brief 16-bit status 64-bit vector data type.
-   */
-  typedef int16x8_t status16x4_t;
-
-  /**
-   * @brief 8-bit status 64-bit vector data type.
-   */
-  typedef int8x16_t status8x8_t;
-
-#endif
-
-
-
-/**
-  @brief definition to read/write two 16 bit values.
-  @deprecated
- */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __un(aligned) int32_t
-#elif defined(_MSC_VER )
-  #define __SIMD32_TYPE int32_t
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ( (__SIMD32_TYPE * )   (addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE * )   (addr))
-#define __SIMD64(addr)        (*(      int64_t **) & (addr))
-
-#define STEP(x) (x) <= 0 ? 0 : 1
-#define SQ(x) ((x) * (x))
-
-/* SIMD replacement */
-
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2 (
-  q15_t * pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, pQ15, 4);
-#else
-  val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
-#endif
-
-  return (val);
-}
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer and increment pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_ia (
-  q15_t ** pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ15, 4);
-#else
-  val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
-#endif
-
- *pQ15 += 2;
- return (val);
-}
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_da (
-  q15_t ** pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ15, 4);
-#else
-  val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
-#endif
-
-  *pQ15 -= 2;
-  return (val);
-}
-
-/**
-  @brief         Write 2 Q15 to Q15 pointer and increment pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q15x2_ia (
-  q15_t ** pQ15,
-  q31_t    value)
-{
-  q31_t val = value;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (*pQ15, &val, 4);
-#else
-  (*pQ15)[0] = (val & 0x0FFFF);
-  (*pQ15)[1] = (val >> 16) & 0x0FFFF;
-#endif
-
- *pQ15 += 2;
-}
-
-/**
-  @brief         Write 2 Q15 to Q15 pointer.
-  @param[in]     pQ15      points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q15x2 (
-  q15_t * pQ15,
-  q31_t   value)
-{
-  q31_t val = value;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (pQ15, &val, 4);
-#else
-  pQ15[0] = val & 0x0FFFF;
-  pQ15[1] = val >> 16;
-#endif
-}
-
-
-/**
-  @brief         Read 4 Q7 from Q7 pointer and increment pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_ia (
-  q7_t ** pQ7)
-{
-  q31_t val;
-
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ7, 4);
-#else
-  val =(((*pQ7)[3] & 0x0FF) << 24)  | (((*pQ7)[2] & 0x0FF) << 16)  | (((*pQ7)[1] & 0x0FF) << 8)  | ((*pQ7)[0] & 0x0FF);
-#endif
-
-  *pQ7 += 4;
-
-  return (val);
-}
-
-/**
-  @brief         Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_da (
-  q7_t ** pQ7)
-{
-  q31_t val;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ7, 4);
-#else
-  val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16)   | ((((*pQ7)[1]) & 0x0FF) << 8)  | ((*pQ7)[0] & 0x0FF);
-#endif
-  *pQ7 -= 4;
-
-  return (val);
-}
-
-/**
-  @brief         Write 4 Q7 to Q7 pointer and increment pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q7x4_ia (
-  q7_t ** pQ7,
-  q31_t   value)
-{
-  q31_t val = value;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (*pQ7, &val, 4);
-#else
-  (*pQ7)[0] = val & 0x0FF;
-  (*pQ7)[1] = (val >> 8) & 0x0FF;
-  (*pQ7)[2] = (val >> 16) & 0x0FF;
-  (*pQ7)[3] = (val >> 24) & 0x0FF;
-
-#endif
-  *pQ7 += 4;
-}
-
-/*
-
-Normally those kind of definitions are in a compiler file
-in Core or Core_A.
-
-But for MSVC compiler it is a bit special. The goal is very specific
-to CMSIS-DSP and only to allow the use of this library from other
-systems like Python or Matlab.
-
-MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
-compiler file in Core or Core_A would not make sense.
-
-*/
-#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
-    __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
-    {
-      if (data == 0U) { return 32U; }
-
-      uint32_t count = 0U;
-      uint32_t mask = 0x80000000U;
-
-      while ((data & mask) == 0U)
-      {
-        count += 1U;
-        mask = mask >> 1U;
-      }
-      return count;
-    }
-
-  __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-  {
-    if ((sat >= 1U) && (sat <= 32U))
-    {
-      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-      const int32_t min = -1 - max ;
-      if (val > max)
-      {
-        return max;
-      }
-      else if (val < min)
-      {
-        return min;
-      }
-    }
-    return val;
-  }
-
-  __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-  {
-    if (sat <= 31U)
-    {
-      const uint32_t max = ((1U << sat) - 1U);
-      if (val > (int32_t)max)
-      {
-        return max;
-      }
-      else if (val < 0)
-      {
-        return 0U;
-      }
-    }
-    return (uint32_t)val;
-  }
-#endif
-
-#ifndef ARM_MATH_DSP
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-  #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                      (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-  #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                      (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-#endif
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-  #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                  (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                  (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                  (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-  #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                  (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                  (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                  (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-  __STATIC_FORCEINLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32)                * y)      )  );
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-  __STATIC_FORCEINLINE uint32_t arm_recip_q31(
-        q31_t in,
-        q31_t * dst,
-  const q31_t * pRecipTable)
-  {
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else
-    {
-      signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-      tempVal = 0x7FFFFFFFu - tempVal;
-      /*      1.31 with exp 1 */
-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1U);
-  }
-
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  __STATIC_FORCEINLINE uint32_t arm_recip_q15(
-        q15_t in,
-        q15_t * dst,
-  const q15_t * pRecipTable)
-  {
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else
-    {
-      signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFFu - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-  }
-
-/**
- * @brief Integer exponentiation
- * @param[in]    x           value
- * @param[in]    nb          integer exponent >= 1
- * @return x^nb
- *
- */
-__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
-{
-    float32_t r = x;
-    nb --;
-    while(nb > 0)
-    {
-        r = r * x;
-        nb--;
-    }
-    return(r);
-}
-
-/**
- * @brief  64-bit to 32-bit unsigned normalization
- * @param[in]  in           is input unsigned long long value
- * @param[out] normalized   is the 32-bit normalized value
- * @param[out] norm         is norm scale
- */
-__STATIC_INLINE  void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
-{
-    int32_t     n1;
-    int32_t     hi = (int32_t) (in >> 32);
-    int32_t     lo = (int32_t) ((in << 32) >> 32);
-
-    n1 = __CLZ(hi) - 32;
-    if (!n1)
-    {
-        /*
-         * input fits in 32-bit
-         */
-        n1 = __CLZ(lo);
-        if (!n1)
-        {
-            /*
-             * MSB set, need to scale down by 1
-             */
-            *norm = -1;
-            *normalized = (((uint32_t) lo) >> 1);
-        } else
-        {
-            if (n1 == 32)
-            {
-                /*
-                 * input is zero
-                 */
-                *norm = 0;
-                *normalized = 0;
-            } else
-            {
-                /*
-                 * 32-bit normalization
-                 */
-                *norm = n1 - 1;
-                *normalized = lo << *norm;
-            }
-        }
-    } else
-    {
-        /*
-         * input fits in 64-bit
-         */
-        n1 = 1 - n1;
-        *norm = -n1;
-        /*
-         * 64 bit normalization
-         */
-        *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
-    }
-}
-
-__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
-{
-    q31_t   result;
-    uint64_t   absNum;
-    int32_t   normalized;
-    int32_t   norm;
-
-    /*
-     * if sum fits in 32bits
-     * avoid costly 64-bit division
-     */
-    absNum = num > 0 ? num : -num;
-    arm_norm_64_to_32u(absNum, &normalized, &norm);
-    if (norm > 0)
-        /*
-         * 32-bit division
-         */
-        result = (q31_t) num / den;
-    else
-        /*
-         * 64-bit division
-         */
-        result = (q31_t) (num / den);
-
-    return result;
-}
-
-
-/*
- * @brief C custom defined intrinsic functions
- */
-#if !defined (ARM_MATH_DSP)
-
-  /*
-   * @brief C custom defined QADD8
-   */
-  __STATIC_FORCEINLINE uint32_t __QADD8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB8
-   */
-  __STATIC_FORCEINLINE uint32_t __QSUB8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QADD16
-   */
-  __STATIC_FORCEINLINE uint32_t __QADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHADD16
-   */
-  __STATIC_FORCEINLINE uint32_t __SHADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB16
-   */
-  __STATIC_FORCEINLINE uint32_t __QSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSUB16
-   */
-  __STATIC_FORCEINLINE uint32_t __SHSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QASX
-   */
-  __STATIC_FORCEINLINE uint32_t __QASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHASX
-   */
-  __STATIC_FORCEINLINE uint32_t __SHASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSAX
-   */
-  __STATIC_FORCEINLINE uint32_t __QSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSAX
-   */
-  __STATIC_FORCEINLINE uint32_t __SHSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSDX
-   */
-  __STATIC_FORCEINLINE uint32_t __SMUSDX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-  /*
-   * @brief C custom defined SMUADX
-   */
-  __STATIC_FORCEINLINE uint32_t __SMUADX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined QADD
-   */
-  __STATIC_FORCEINLINE int32_t __QADD(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB
-   */
-  __STATIC_FORCEINLINE int32_t __QSUB(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined SMLAD
-   */
-  __STATIC_FORCEINLINE uint32_t __SMLAD(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLADX
-   */
-  __STATIC_FORCEINLINE uint32_t __SMLADX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLSDX
-   */
-  __STATIC_FORCEINLINE uint32_t __SMLSDX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALD
-   */
-  __STATIC_FORCEINLINE uint64_t __SMLALD(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALDX
-   */
-  __STATIC_FORCEINLINE uint64_t __SMLALDX(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUAD
-   */
-  __STATIC_FORCEINLINE uint32_t __SMUAD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSD
-   */
-  __STATIC_FORCEINLINE uint32_t __SMUSD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16
-   */
-  __STATIC_FORCEINLINE uint32_t __SXTB16(
-  uint32_t x)
-  {
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-  }
-
-  /*
-   * @brief C custom defined SMMLA
-   */
-  __STATIC_FORCEINLINE int32_t __SMMLA(
-  int32_t x,
-  int32_t y,
-  int32_t sum)
-  {
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-  }
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-          q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    const q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-          q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    const q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-          q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    const q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-          float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    const float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  const q7_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed.
-   */
-  void arm_fir_init_q7(
-        arm_fir_instance_q7 * S,
-        uint16_t numTaps,
-  const q7_t * pCoeffs,
-        q7_t * pState,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in]  S          points to an instance of the Q15 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter (fast version).
-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   * @return     The function returns either
-   * <code>ARM_MATH_SUCCESS</code> if initialization was successful or
-   * <code>ARM_MATH_ARGUMENT_ERROR</code> if <code>numTaps</code> is not a supported value.
-   */
-  arm_status arm_fir_init_q15(
-        arm_fir_instance_q15 * S,
-        uint16_t numTaps,
-  const q15_t * pCoeffs,
-        q15_t * pState,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter (fast version).
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_q31(
-        arm_fir_instance_q31 * S,
-        uint16_t numTaps,
-  const q31_t * pCoeffs,
-        q31_t * pState,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in]  S          points to an instance of the floating-point FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_f32(
-        arm_fir_instance_f32 * S,
-        uint16_t numTaps,
-  const float32_t * pCoeffs,
-        float32_t * pState,
-        uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-          int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    const q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-          int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q15;
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    const q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-          uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    const float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_casd_df1_inst_f32;
-
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-  /**
-   * @brief Instance structure for the modified Biquad coefs required by vectorized code.
-   */
-  typedef struct
-  {
-      float32_t coeffs[8][4]; /**< Points to the array of modified coefficients.  The array is of length 32. There is one per stage */
-  } arm_biquad_mod_coef_f32;
-#endif
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q15(
-        arm_biquad_casd_df1_inst_q15 * S,
-        uint8_t numStages,
-  const q15_t * pCoeffs,
-        q15_t * pState,
-        int8_t postShift);
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q31(
-        arm_biquad_casd_df1_inst_q31 * S,
-        uint8_t numStages,
-  const q31_t * pCoeffs,
-        q31_t * pState,
-        int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pCoeffsMod points to the modified filter coefficients (only MVE version).
-   * @param[in]     pState     points to the state buffer.
-   */
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-  void arm_biquad_cascade_df1_mve_init_f32(
-      arm_biquad_casd_df1_inst_f32 * S,
-      uint8_t numStages,
-      const float32_t * pCoeffs,
-      arm_biquad_mod_coef_f32 * pCoeffsMod,
-      float32_t * pState);
-#endif
-
-  void arm_biquad_cascade_df1_init_f32(
-        arm_biquad_casd_df1_inst_f32 * S,
-        uint8_t numStages,
-  const float32_t * pCoeffs,
-        float32_t * pState);
-
-
-  /**
-   * @brief         Compute the logical bitwise AND of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_and_u16(
-    const uint16_t * pSrcA,
-    const uint16_t * pSrcB,
-          uint16_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise AND of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_and_u32(
-    const uint32_t * pSrcA,
-    const uint32_t * pSrcB,
-          uint32_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise AND of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_and_u8(
-    const uint8_t * pSrcA,
-    const uint8_t * pSrcB,
-          uint8_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise OR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_or_u16(
-    const uint16_t * pSrcA,
-    const uint16_t * pSrcB,
-          uint16_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise OR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_or_u32(
-    const uint32_t * pSrcA,
-    const uint32_t * pSrcB,
-          uint32_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise OR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_or_u8(
-    const uint8_t * pSrcA,
-    const uint8_t * pSrcB,
-          uint8_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise NOT of a fixed-point vector.
-   * @param[in]     pSrc       points to input vector
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_not_u16(
-    const uint16_t * pSrc,
-          uint16_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise NOT of a fixed-point vector.
-   * @param[in]     pSrc       points to input vector
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_not_u32(
-    const uint32_t * pSrc,
-          uint32_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise NOT of a fixed-point vector.
-   * @param[in]     pSrc       points to input vector
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_not_u8(
-    const uint8_t * pSrc,
-          uint8_t * pDst,
-          uint32_t blockSize);
-
-/**
-   * @brief         Compute the logical bitwise XOR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_xor_u16(
-    const uint16_t * pSrcA,
-    const uint16_t * pSrcB,
-          uint16_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise XOR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_xor_u32(
-    const uint32_t * pSrcA,
-    const uint32_t * pSrcB,
-          uint32_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @brief         Compute the logical bitwise XOR of two fixed-point vectors.
-   * @param[in]     pSrcA      points to input vector A
-   * @param[in]     pSrcB      points to input vector B
-   * @param[out]    pDst       points to output vector
-   * @param[in]     blockSize  number of samples in each vector
-   * @return        none
-   */
-  void arm_xor_u8(
-    const uint8_t * pSrcA,
-    const uint8_t * pSrcB,
-          uint8_t * pDst,
-    uint32_t blockSize);
-
-  /**
-   * @brief Struct for specifying sorting algorithm
-   */
-  typedef enum
-  {
-    ARM_SORT_BITONIC   = 0,
-             /**< Bitonic sort   */
-    ARM_SORT_BUBBLE    = 1,
-             /**< Bubble sort    */
-    ARM_SORT_HEAP      = 2,
-             /**< Heap sort      */
-    ARM_SORT_INSERTION = 3,
-             /**< Insertion sort */
-    ARM_SORT_QUICK     = 4,
-             /**< Quick sort     */
-    ARM_SORT_SELECTION = 5
-             /**< Selection sort */
-  } arm_sort_alg;
-
-  /**
-   * @brief Struct for specifying sorting algorithm
-   */
-  typedef enum
-  {
-    ARM_SORT_DESCENDING = 0,
-             /**< Descending order (9 to 0) */
-    ARM_SORT_ASCENDING = 1
-             /**< Ascending order (0 to 9) */
-  } arm_sort_dir;
-
-  /**
-   * @brief Instance structure for the sorting algorithms.
-   */
-  typedef struct
-  {
-    arm_sort_alg alg;        /**< Sorting algorithm selected */
-    arm_sort_dir dir;        /**< Sorting order (direction)  */
-  } arm_sort_instance_f32;
-
-  /**
-   * @param[in]  S          points to an instance of the sorting structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_sort_f32(
-    const arm_sort_instance_f32 * S,
-          float32_t * pSrc,
-          float32_t * pDst,
-          uint32_t blockSize);
-
-  /**
-   * @param[in,out]  S            points to an instance of the sorting structure.
-   * @param[in]      alg          Selected algorithm.
-   * @param[in]      dir          Sorting order.
-   */
-  void arm_sort_init_f32(
-    arm_sort_instance_f32 * S,
-    arm_sort_alg alg,
-    arm_sort_dir dir);
-
-  /**
-   * @brief Instance structure for the sorting algorithms.
-   */
-  typedef struct
-  {
-    arm_sort_dir dir;        /**< Sorting order (direction)  */
-    float32_t * buffer;      /**< Working buffer */
-  } arm_merge_sort_instance_f32;
-
-  /**
-   * @param[in]      S          points to an instance of the sorting structure.
-   * @param[in,out]  pSrc       points to the block of input data.
-   * @param[out]     pDst       points to the block of output data
-   * @param[in]      blockSize  number of samples to process.
-   */
-  void arm_merge_sort_f32(
-    const arm_merge_sort_instance_f32 * S,
-          float32_t *pSrc,
-          float32_t *pDst,
-          uint32_t blockSize);
-
-  /**
-   * @param[in,out]  S            points to an instance of the sorting structure.
-   * @param[in]      dir          Sorting order.
-   * @param[in]      buffer       Working buffer.
-   */
-  void arm_merge_sort_init_f32(
-    arm_merge_sort_instance_f32 * S,
-    arm_sort_dir dir,
-    float32_t * buffer);
-
-  /**
-   * @brief Struct for specifying cubic spline type
-   */
-  typedef enum
-  {
-    ARM_SPLINE_NATURAL = 0,           /**< Natural spline */
-    ARM_SPLINE_PARABOLIC_RUNOUT = 1   /**< Parabolic runout spline */
-  } arm_spline_type;
-
-  /**
-   * @brief Instance structure for the floating-point cubic spline interpolation.
-   */
-  typedef struct
-  {
-    arm_spline_type type;      /**< Type (boundary conditions) */
-    const float32_t * x;       /**< x values */
-    const float32_t * y;       /**< y values */
-    uint32_t n_x;              /**< Number of known data points */
-    float32_t * coeffs;        /**< Coefficients buffer (b,c, and d) */
-  } arm_spline_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point cubic spline interpolation.
-   * @param[in]  S          points to an instance of the floating-point spline structure.
-   * @param[in]  xq         points to the x values ot the interpolated data points.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples of output data.
-   */
-  void arm_spline_f32(
-        arm_spline_instance_f32 * S,
-  const float32_t * xq,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point cubic spline interpolation.
-   * @param[in,out] S        points to an instance of the floating-point spline structure.
-   * @param[in]     type     type of cubic spline interpolation (boundary conditions)
-   * @param[in]     x        points to the x values of the known data points.
-   * @param[in]     y        points to the y values of the known data points.
-   * @param[in]     n        number of known data points.
-   * @param[in]     coeffs   coefficients array for b, c, and d
-   * @param[in]     tempBuffer   buffer array for internal computations
-   */
-  void arm_spline_init_f32(
-          arm_spline_instance_f32 * S,
-          arm_spline_type type,
-    const float32_t * x,
-    const float32_t * y,
-          uint32_t n,
-          float32_t * coeffs,
-          float32_t * tempBuffer);
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
- /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q31;
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]   pSrcA  points to the first input matrix structure
-   * @param[in]   pSrcB  points to the second input matrix structure
-   * @param[out]  pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-        arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-        arm_matrix_instance_q15 * pDst,
-        q15_t * pScratch);
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-        arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-        arm_matrix_instance_q15 * pDst,
-        q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-        arm_matrix_instance_q15 * pDst,
-        q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-        arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  pSrc   points to the input matrix
-   * @param[in]  scale  scale factor
-   * @param[out] pDst   points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-        float32_t scale,
-        arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-        q15_t scaleFract,
-        int32_t shift,
-        arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-        q31_t scaleFract,
-        int32_t shift,
-        arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-void arm_mat_init_q31(
-        arm_matrix_instance_q31 * S,
-        uint16_t nRows,
-        uint16_t nColumns,
-        q31_t * pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-void arm_mat_init_q15(
-        arm_matrix_instance_q15 * S,
-        uint16_t nRows,
-        uint16_t nColumns,
-        q15_t * pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-void arm_mat_init_f32(
-        arm_matrix_instance_f32 * S,
-        uint16_t nRows,
-        uint16_t nColumns,
-        float32_t * pData);
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-          q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-          q15_t A1;
-          q15_t A2;
-#else
-          q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-          q15_t state[3];     /**< The state array of length 3. */
-          q15_t Kp;           /**< The proportional gain. */
-          q15_t Ki;           /**< The integral gain. */
-          q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-          q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-          q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-          q31_t A2;            /**< The derived gain, A2 = Kd . */
-          q31_t state[3];      /**< The state array of length 3. */
-          q31_t Kp;            /**< The proportional gain. */
-          q31_t Ki;            /**< The integral gain. */
-          q31_t Kd;            /**< The derivative gain. */
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-          float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-          float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-          float32_t A2;          /**< The derived gain, A2 = Kd . */
-          float32_t state[3];    /**< The state array of length 3. */
-          float32_t Kp;          /**< The proportional gain. */
-          float32_t Ki;          /**< The integral gain. */
-          float32_t Kd;          /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] S               points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_f32(
-        arm_pid_instance_f32 * S,
-        int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] S  is an instance of the floating-point PID Control structure
-   */
-  void arm_pid_reset_f32(
-        arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q31(
-        arm_pid_instance_q31 * S,
-        int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] S   points to an instance of the Q31 PID Control structure
-   */
-
-  void arm_pid_reset_q31(
-        arm_pid_instance_q31 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q15(
-        arm_pid_instance_q15 * S,
-        int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] S  points to an instance of the q15 PID Control structure
-   */
-  void arm_pid_reset_q15(
-        arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-          uint32_t nValues;           /**< nValues */
-          float32_t x1;               /**< x1 */
-          float32_t xSpacing;         /**< xSpacing */
-          float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-  typedef struct
-  {
-          uint16_t numRows;   /**< number of rows in the data table. */
-          uint16_t numCols;   /**< number of columns in the data table. */
-          float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-  typedef struct
-  {
-          uint16_t numRows;   /**< number of rows in the data table. */
-          uint16_t numCols;   /**< number of columns in the data table. */
-          q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-          uint16_t numRows;   /**< number of rows in the data table. */
-          uint16_t numCols;   /**< number of columns in the data table. */
-          q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-          uint16_t numRows;   /**< number of rows in the data table. */
-          uint16_t numCols;   /**< number of columns in the data table. */
-          q7_t *pData;        /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q7(
-  const q7_t * pSrcA,
-  const q7_t * pSrcB,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                 /**< length of the FFT. */
-          uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    const uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-        arm_cfft_radix2_instance_q15 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-        q15_t * pSrc);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                 /**< length of the FFT. */
-          uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    const uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-        arm_cfft_radix4_instance_q15 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-        q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                 /**< length of the FFT. */
-          uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-        arm_cfft_radix2_instance_q31 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-        q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                 /**< length of the FFT. */
-          uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    const uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-        q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-        arm_cfft_radix4_instance_q31 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-          uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-          float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-        arm_cfft_radix2_instance_f32 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-        float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-          uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-          uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    const float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-          uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-          uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-          float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-        arm_cfft_radix4_instance_f32 * S,
-        uint16_t fftLen,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-        float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-          uint16_t bitRevLength;             /**< bit reversal table length. */
-#if defined(ARM_MATH_MVEI)
-   const uint32_t *rearranged_twiddle_tab_stride1_arr;        /**< Per stage reordered twiddle pointer (offset 1) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride2_arr;        /**< Per stage reordered twiddle pointer (offset 2) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride3_arr;        /**< Per stage reordered twiddle pointer (offset 3) */                                                       \
-   const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */                                                                   \
-   const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */                                                                   \
-   const q15_t *rearranged_twiddle_stride3;
-#endif
-  } arm_cfft_instance_q15;
-
-arm_status arm_cfft_init_q15(
-  arm_cfft_instance_q15 * S,
-  uint16_t fftLen);
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15 * S,
-          q15_t * p1,
-          uint8_t ifftFlag,
-          uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-          uint16_t bitRevLength;             /**< bit reversal table length. */
-#if defined(ARM_MATH_MVEI)
-   const uint32_t *rearranged_twiddle_tab_stride1_arr;        /**< Per stage reordered twiddle pointer (offset 1) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride2_arr;        /**< Per stage reordered twiddle pointer (offset 2) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride3_arr;        /**< Per stage reordered twiddle pointer (offset 3) */                                                       \
-   const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */                                                                   \
-   const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */                                                                   \
-   const q31_t *rearranged_twiddle_stride3;
-#endif
-  } arm_cfft_instance_q31;
-
-arm_status arm_cfft_init_q31(
-  arm_cfft_instance_q31 * S,
-  uint16_t fftLen);
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31 * S,
-          q31_t * p1,
-          uint8_t ifftFlag,
-          uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-          uint16_t bitRevLength;             /**< bit reversal table length. */
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-   const uint32_t *rearranged_twiddle_tab_stride1_arr;        /**< Per stage reordered twiddle pointer (offset 1) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride2_arr;        /**< Per stage reordered twiddle pointer (offset 2) */                                                       \
-   const uint32_t *rearranged_twiddle_tab_stride3_arr;        /**< Per stage reordered twiddle pointer (offset 3) */                                                       \
-   const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */                                                                   \
-   const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */                                                                   \
-   const float32_t *rearranged_twiddle_stride3;
-#endif
-  } arm_cfft_instance_f32;
-
-
-  arm_status arm_cfft_init_f32(
-  arm_cfft_instance_f32 * S,
-  uint16_t fftLen);
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-        float32_t * p1,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-
-  /**
-   * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-          uint16_t fftLen;                   /**< length of the FFT. */
-    const float64_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-          uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f64;
-
-  void arm_cfft_f64(
-  const arm_cfft_instance_f64 * S,
-        float64_t * p1,
-        uint8_t ifftFlag,
-        uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-          uint32_t fftLenReal;                      /**< length of the real FFT. */
-          uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-          uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-          uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    const q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    const q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-#if defined(ARM_MATH_MVEI)
-    arm_cfft_instance_q15 cfftInst;
-#else
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-#endif
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-        arm_rfft_instance_q15 * S,
-        uint32_t fftLenReal,
-        uint32_t ifftFlagR,
-        uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-        q15_t * pSrc,
-        q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-          uint32_t fftLenReal;                        /**< length of the real FFT. */
-          uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-          uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-          uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    const q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    const q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-#if defined(ARM_MATH_MVEI)
-    arm_cfft_instance_q31 cfftInst;
-#else
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-#endif
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-        arm_rfft_instance_q31 * S,
-        uint32_t fftLenReal,
-        uint32_t ifftFlagR,
-        uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-        q31_t * pSrc,
-        q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-          uint32_t fftLenReal;                        /**< length of the real FFT. */
-          uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-          uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-          uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-          uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    const float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    const float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-          arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-        arm_rfft_instance_f32 * S,
-        arm_cfft_radix4_instance_f32 * S_CFFT,
-        uint32_t fftLenReal,
-        uint32_t ifftFlagR,
-        uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-        float32_t * pSrc,
-        float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-          arm_cfft_instance_f64 Sint;      /**< Internal CFFT structure. */
-          uint16_t fftLenRFFT;             /**< length of the real sequence */
-    const float64_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f64 ;
-
-arm_status arm_rfft_fast_init_f64 (
-         arm_rfft_fast_instance_f64 * S,
-         uint16_t fftLen);
-
-
-void arm_rfft_fast_f64(
-    arm_rfft_fast_instance_f64 * S,
-    float64_t * p, float64_t * pOut,
-    uint8_t ifftFlag);
-
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-          arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-          uint16_t fftLenRFFT;             /**< length of the real sequence */
-    const float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-         arm_rfft_fast_instance_f32 * S,
-         uint16_t fftLen);
-
-
-  void arm_rfft_fast_f32(
-        const arm_rfft_fast_instance_f32 * S,
-        float32_t * p, float32_t * pOut,
-        uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-          uint16_t N;                          /**< length of the DCT4. */
-          uint16_t Nby2;                       /**< half of the length of the DCT4. */
-          float32_t normalize;                 /**< normalizing factor. */
-    const float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    const float32_t *pCosFactor;               /**< points to the cosFactor table. */
-          arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-          arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_f32(
-        arm_dct4_instance_f32 * S,
-        arm_rfft_instance_f32 * S_RFFT,
-        arm_cfft_radix4_instance_f32 * S_CFFT,
-        uint16_t N,
-        uint16_t Nby2,
-        float32_t normalize);
-
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-        float32_t * pState,
-        float32_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-          uint16_t N;                          /**< length of the DCT4. */
-          uint16_t Nby2;                       /**< half of the length of the DCT4. */
-          q31_t normalize;                     /**< normalizing factor. */
-    const q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    const q31_t *pCosFactor;                   /**< points to the cosFactor table. */
-          arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-          arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q31(
-        arm_dct4_instance_q31 * S,
-        arm_rfft_instance_q31 * S_RFFT,
-        arm_cfft_radix4_instance_q31 * S_CFFT,
-        uint16_t N,
-        uint16_t Nby2,
-        q31_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-        q31_t * pState,
-        q31_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-          uint16_t N;                          /**< length of the DCT4. */
-          uint16_t Nby2;                       /**< half of the length of the DCT4. */
-          q15_t normalize;                     /**< normalizing factor. */
-    const q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    const q15_t *pCosFactor;                   /**< points to the cosFactor table. */
-          arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-          arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q15(
-        arm_dct4_instance_q15 * S,
-        arm_rfft_instance_q15 * S_RFFT,
-        arm_cfft_radix4_instance_q15 * S_CFFT,
-        uint16_t N,
-        uint16_t Nby2,
-        q15_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-        q15_t * pState,
-        q15_t * pInlineBuffer);
-
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q7(
-  const q7_t * pSrcA,
-  const q7_t * pSrcB,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q7(
-  const q7_t * pSrcA,
-  const q7_t * pSrcB,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  scale      scale factor to be applied
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_scale_f32(
-  const float32_t * pSrc,
-        float32_t scale,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q7(
-  const q7_t * pSrc,
-        q7_t scaleFract,
-        int8_t shift,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q15(
-  const q15_t * pSrc,
-        q15_t scaleFract,
-        int8_t shift,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q31(
-  const q31_t * pSrc,
-        q31_t scaleFract,
-        int8_t shift,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q7(
-  const q7_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        uint32_t blockSize,
-        float32_t * result);
-
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q7(
-  const q7_t * pSrcA,
-  const q7_t * pSrcB,
-        uint32_t blockSize,
-        q31_t * result);
-
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        uint32_t blockSize,
-        q63_t * result);
-
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        uint32_t blockSize,
-        q63_t * result);
-
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q7(
-  const q7_t * pSrc,
-        int8_t shiftBits,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q15(
-  const q15_t * pSrc,
-        int8_t shiftBits,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q31(
-  const q31_t * pSrc,
-        int8_t shiftBits,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_f32(
-  const float32_t * pSrc,
-        float32_t offset,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q7(
-  const q7_t * pSrc,
-        q7_t offset,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q15(
-  const q15_t * pSrc,
-        q15_t offset,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q31(
-  const q31_t * pSrc,
-        q31_t offset,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q7(
-  const q7_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q7(
-  const q7_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_f32(
-        float32_t value,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q7(
-        q7_t value,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q15(
-        q15_t value,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q31(
-        q31_t value,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_f32(
-  const float32_t * pSrcA,
-        uint32_t srcALen,
-  const float32_t * pSrcB,
-        uint32_t srcBLen,
-        float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_fast_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_f32(
-  const float32_t * pSrcA,
-        uint32_t srcALen,
-  const float32_t * pSrcB,
-        uint32_t srcBLen,
-        float32_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst,
-        uint32_t firstIndex,
-        uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-  typedef struct
-  {
-          uint8_t M;                  /**< decimation factor. */
-          uint16_t numTaps;           /**< number of coefficients in the filter. */
-    const q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-          q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-  typedef struct
-  {
-          uint8_t M;                  /**< decimation factor. */
-          uint16_t numTaps;           /**< number of coefficients in the filter. */
-    const q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-          q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q31;
-
-/**
-  @brief Instance structure for floating-point FIR decimator.
- */
-typedef struct
-  {
-          uint8_t M;                  /**< decimation factor. */
-          uint16_t numTaps;           /**< number of coefficients in the filter. */
-    const float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-          float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_f32;
-
-
-/**
-  @brief         Processing function for floating-point FIR decimator.
-  @param[in]     S         points to an instance of the floating-point FIR decimator structure
-  @param[in]     pSrc      points to the block of input data
-  @param[out]    pDst      points to the block of output data
-  @param[in]     blockSize number of samples to process
- */
-void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-/**
-  @brief         Initialization function for the floating-point FIR decimator.
-  @param[in,out] S          points to an instance of the floating-point FIR decimator structure
-  @param[in]     numTaps    number of coefficients in the filter
-  @param[in]     M          decimation factor
-  @param[in]     pCoeffs    points to the filter coefficients
-  @param[in]     pState     points to the state buffer
-  @param[in]     blockSize  number of input samples to process per call
-  @return        execution status
-                   - \ref ARM_MATH_SUCCESS      : Operation successful
-                   - \ref ARM_MATH_LENGTH_ERROR : <code>blockSize</code> is not a multiple of <code>M</code>
- */
-arm_status arm_fir_decimate_init_f32(
-        arm_fir_decimate_instance_f32 * S,
-        uint16_t numTaps,
-        uint8_t M,
-  const float32_t * pCoeffs,
-        float32_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q15(
-        arm_fir_decimate_instance_q15 * S,
-        uint16_t numTaps,
-        uint8_t M,
-  const q15_t * pCoeffs,
-        q15_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc  points to the block of input data.
-   * @param[out] pDst  points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   */
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q31(
-        arm_fir_decimate_instance_q31 * S,
-        uint16_t numTaps,
-        uint8_t M,
-  const q31_t * pCoeffs,
-        q31_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-  typedef struct
-  {
-        uint8_t L;                      /**< upsample factor. */
-        uint16_t phaseLength;           /**< length of each polyphase filter component. */
-  const q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-        q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-  typedef struct
-  {
-        uint8_t L;                      /**< upsample factor. */
-        uint16_t phaseLength;           /**< length of each polyphase filter component. */
-  const q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-        q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-  typedef struct
-  {
-        uint8_t L;                     /**< upsample factor. */
-        uint16_t phaseLength;          /**< length of each polyphase filter component. */
-  const float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-        float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q15(
-        arm_fir_interpolate_instance_q15 * S,
-        uint8_t L,
-        uint16_t numTaps,
-  const q15_t * pCoeffs,
-        q15_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q31(
-        arm_fir_interpolate_instance_q31 * S,
-        uint8_t L,
-        uint16_t numTaps,
-  const q31_t * pCoeffs,
-        q31_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_f32(
-        arm_fir_interpolate_instance_f32 * S,
-        uint8_t L,
-        uint16_t numTaps,
-  const float32_t * pCoeffs,
-        float32_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    const q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-          uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cas_df1_32x64_init_q31(
-        arm_biquad_cas_df1_32x64_ins_q31 * S,
-        uint8_t numStages,
-  const q31_t * pCoeffs,
-        q63_t * pState,
-        uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    const float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    const float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-          uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-          float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    const float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  const float64_t * pSrc,
-        float64_t * pDst,
-        uint32_t blockSize);
-
-
-#if defined(ARM_MATH_NEON)
-void arm_biquad_cascade_df2T_compute_coefs_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs);
-#endif
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f32(
-        arm_biquad_cascade_df2T_instance_f32 * S,
-        uint8_t numStages,
-  const float32_t * pCoeffs,
-        float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-        arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-        uint8_t numStages,
-  const float32_t * pCoeffs,
-        float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f64(
-        arm_biquad_cascade_df2T_instance_f64 * S,
-        uint8_t numStages,
-        const float64_t * pCoeffs,
-        float64_t * pState);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of filter stages. */
-          q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    const q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of filter stages. */
-          q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    const q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of filter stages. */
-          float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    const float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q15(
-        arm_fir_lattice_instance_q15 * S,
-        uint16_t numStages,
-  const q15_t * pCoeffs,
-        q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.   The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q31(
-        arm_fir_lattice_instance_q31 * S,
-        uint16_t numStages,
-  const q31_t * pCoeffs,
-        q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-  void arm_fir_lattice_init_f32(
-        arm_fir_lattice_instance_f32 * S,
-        uint16_t numStages,
-  const float32_t * pCoeffs,
-        float32_t * pState);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of stages in the filter. */
-          q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-          q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-          q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of stages in the filter. */
-          q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-          q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-          q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-          uint16_t numStages;                  /**< number of stages in the filter. */
-          float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-          float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-          float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_f32(
-        arm_iir_lattice_instance_f32 * S,
-        uint16_t numStages,
-        float32_t * pkCoeffs,
-        float32_t * pvCoeffs,
-        float32_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_q31(
-        arm_iir_lattice_instance_q31 * S,
-        uint16_t numStages,
-        q31_t * pkCoeffs,
-        q31_t * pvCoeffs,
-        q31_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-  void arm_iir_lattice_init_q15(
-        arm_iir_lattice_instance_q15 * S,
-        uint16_t numStages,
-        q15_t * pkCoeffs,
-        q15_t * pvCoeffs,
-        q15_t * pState,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;    /**< number of coefficients in the filter. */
-          float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-          float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pRef,
-        float32_t * pOut,
-        float32_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_init_f32(
-        arm_lms_instance_f32 * S,
-        uint16_t numTaps,
-        float32_t * pCoeffs,
-        float32_t * pState,
-        float32_t mu,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;    /**< number of coefficients in the filter. */
-          q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-          q15_t mu;            /**< step size that controls filter coefficient updates. */
-          uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] S          points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to the state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q15(
-        arm_lms_instance_q15 * S,
-        uint16_t numTaps,
-        q15_t * pCoeffs,
-        q15_t * pState,
-        q15_t mu,
-        uint32_t blockSize,
-        uint32_t postShift);
-
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pRef,
-        q15_t * pOut,
-        q15_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;    /**< number of coefficients in the filter. */
-          q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-          q31_t mu;            /**< step size that controls filter coefficient updates. */
-          uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pRef,
-        q31_t * pOut,
-        q31_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] S          points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q31(
-        arm_lms_instance_q31 * S,
-        uint16_t numTaps,
-        q31_t * pCoeffs,
-        q31_t * pState,
-        q31_t mu,
-        uint32_t blockSize,
-        uint32_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;     /**< number of coefficients in the filter. */
-          float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-          float32_t mu;         /**< step size that control filter coefficient updates. */
-          float32_t energy;     /**< saves previous frame energy. */
-          float32_t x0;         /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_f32(
-        arm_lms_norm_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pRef,
-        float32_t * pOut,
-        float32_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_norm_init_f32(
-        arm_lms_norm_instance_f32 * S,
-        uint16_t numTaps,
-        float32_t * pCoeffs,
-        float32_t * pState,
-        float32_t mu,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;     /**< number of coefficients in the filter. */
-          q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-          q31_t mu;             /**< step size that controls filter coefficient updates. */
-          uint8_t postShift;    /**< bit shift applied to coefficients. */
-    const q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-          q31_t energy;         /**< saves previous frame energy. */
-          q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q31(
-        arm_lms_norm_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pRef,
-        q31_t * pOut,
-        q31_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q31(
-        arm_lms_norm_instance_q31 * S,
-        uint16_t numTaps,
-        q31_t * pCoeffs,
-        q31_t * pState,
-        q31_t mu,
-        uint32_t blockSize,
-        uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;     /**< Number of coefficients in the filter. */
-          q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-          q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-          q15_t mu;             /**< step size that controls filter coefficient updates. */
-          uint8_t postShift;    /**< bit shift applied to coefficients. */
-    const q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
-          q15_t energy;         /**< saves previous frame energy. */
-          q15_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q15(
-        arm_lms_norm_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pRef,
-        q15_t * pOut,
-        q15_t * pErr,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q15(
-        arm_lms_norm_instance_q15 * S,
-        uint16_t numTaps,
-        q15_t * pCoeffs,
-        q15_t * pState,
-        q15_t mu,
-        uint32_t blockSize,
-        uint8_t postShift);
-
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_f32(
-  const float32_t * pSrcA,
-        uint32_t srcALen,
-  const float32_t * pSrcB,
-        uint32_t srcBLen,
-        float32_t * pDst);
-
-
-/**
- @brief Correlation of Q15 sequences
- @param[in]  pSrcA     points to the first input sequence
- @param[in]  srcALen   length of the first input sequence
- @param[in]  pSrcB     points to the second input sequence
- @param[in]  srcBLen   length of the second input sequence
- @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-*/
-void arm_correlate_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        q15_t * pScratch);
-
-
-/**
-  @brief Correlation of Q15 sequences.
-  @param[in]  pSrcA    points to the first input sequence
-  @param[in]  srcALen  length of the first input sequence
-  @param[in]  pSrcB    points to the second input sequence
-  @param[in]  srcBLen  length of the second input sequence
-  @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-  void arm_correlate_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst);
-
-
-/**
-  @brief         Correlation of Q15 sequences (fast version).
-  @param[in]     pSrcA      points to the first input sequence
-  @param[in]     srcALen    length of the first input sequence
-  @param[in]     pSrcB      points to the second input sequence
-  @param[in]     srcBLen    length of the second input sequence
-  @param[out]    pDst       points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.
-  @return        none
- */
-void arm_correlate_fast_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst);
-
-
-/**
-  @brief Correlation of Q15 sequences (fast version).
-  @param[in]  pSrcA     points to the first input sequence.
-  @param[in]  srcALen   length of the first input sequence.
-  @param[in]  pSrcB     points to the second input sequence.
-  @param[in]  srcBLen   length of the second input sequence.
-  @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-  @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
-void arm_correlate_fast_opt_q15(
-  const q15_t * pSrcA,
-        uint32_t srcALen,
-  const q15_t * pSrcB,
-        uint32_t srcBLen,
-        q15_t * pDst,
-        q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst);
-
-
-/**
-  @brief Correlation of Q31 sequences (fast version).
-  @param[in]  pSrcA    points to the first input sequence
-  @param[in]  srcALen  length of the first input sequence
-  @param[in]  pSrcB    points to the second input sequence
-  @param[in]  srcBLen  length of the second input sequence
-  @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_fast_q31(
-  const q31_t * pSrcA,
-        uint32_t srcALen,
-  const q31_t * pSrcB,
-        uint32_t srcBLen,
-        q31_t * pDst);
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_correlate_opt_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst,
-        q15_t * pScratch1,
-        q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q7(
-  const q7_t * pSrcA,
-        uint32_t srcALen,
-  const q7_t * pSrcB,
-        uint32_t srcBLen,
-        q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;             /**< number of coefficients in the filter. */
-          uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-          float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    const float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-          uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-          int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;             /**< number of coefficients in the filter. */
-          uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-          q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    const q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-          uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-          int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;             /**< number of coefficients in the filter. */
-          uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-          q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    const q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-          uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-          int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-  typedef struct
-  {
-          uint16_t numTaps;             /**< number of coefficients in the filter. */
-          uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-          q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    const q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-          uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-          int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_f32(
-        arm_fir_sparse_instance_f32 * S,
-  const float32_t * pSrc,
-        float32_t * pDst,
-        float32_t * pScratchIn,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_f32(
-        arm_fir_sparse_instance_f32 * S,
-        uint16_t numTaps,
-  const float32_t * pCoeffs,
-        float32_t * pState,
-        int32_t * pTapDelay,
-        uint16_t maxDelay,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_q31(
-        arm_fir_sparse_instance_q31 * S,
-  const q31_t * pSrc,
-        q31_t * pDst,
-        q31_t * pScratchIn,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q31(
-        arm_fir_sparse_instance_q31 * S,
-        uint16_t numTaps,
-  const q31_t * pCoeffs,
-        q31_t * pState,
-        int32_t * pTapDelay,
-        uint16_t maxDelay,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q15(
-        arm_fir_sparse_instance_q15 * S,
-  const q15_t * pSrc,
-        q15_t * pDst,
-        q15_t * pScratchIn,
-        q31_t * pScratchOut,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q15(
-        arm_fir_sparse_instance_q15 * S,
-        uint16_t numTaps,
-  const q15_t * pCoeffs,
-        q15_t * pState,
-        int32_t * pTapDelay,
-        uint16_t maxDelay,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q7(
-        arm_fir_sparse_instance_q7 * S,
-  const q7_t * pSrc,
-        q7_t * pDst,
-        q7_t * pScratchIn,
-        q31_t * pScratchOut,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q7(
-        arm_fir_sparse_instance_q7 * S,
-        uint16_t numTaps,
-  const q7_t * pCoeffs,
-        q7_t * pState,
-        int32_t * pTapDelay,
-        uint16_t maxDelay,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta   input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cos output.
-   */
-  void arm_sin_cos_f32(
-        float32_t theta,
-        float32_t * pSinVal,
-        float32_t * pCosVal);
-
-
-  /**
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cosine output.
-   */
-  void arm_sin_cos_q31(
-        q31_t theta,
-        q31_t * pSinVal,
-        q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
-   * </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief         Process function for the floating-point PID Control.
-   * @param[in,out] S   is an instance of the floating-point PID Control structure
-   * @param[in]     in  input sample to process
-   * @return        processed output sample.
-   */
-  __STATIC_FORCEINLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-/**
-  @brief         Process function for the Q31 PID Control.
-  @param[in,out] S  points to an instance of the Q31 PID Control structure
-  @param[in]     in  input sample to process
-  @return        processed output sample.
-
-  \par Scaling and Overflow Behavior
-         The function is implemented using an internal 64-bit accumulator.
-         The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-         Thus, if the accumulator result overflows it wraps around rather than clip.
-         In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-         After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-__STATIC_FORCEINLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31U);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-
-/**
-  @brief         Process function for the Q15 PID Control.
-  @param[in,out] S   points to an instance of the Q15 PID Control structure
-  @param[in]     in  input sample to process
-  @return        processed output sample.
-
-  \par Scaling and Overflow Behavior
-         The function is implemented using a 64-bit internal accumulator.
-         Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-         The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-         There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-         After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-         Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-__STATIC_FORCEINLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @return        none
-   */
-  __STATIC_FORCEINLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-  }
-
-
-/**
-  @brief  Clarke transform for Q31 version
-  @param[in]  Ia       input three-phase coordinate <code>a</code>
-  @param[in]  Ib       input three-phase coordinate <code>b</code>
-  @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-  @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-  @return     none
-
-  \par Scaling and Overflow Behavior
-         The function is implemented using an internal 32-bit accumulator.
-         The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-         There is saturation on the addition, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   * @return     none
-   */
-  __STATIC_FORCEINLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-  }
-
-
-/**
-  @brief  Inverse Clarke transform for Q31 version
-  @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-  @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-  @param[out] pIa     points to output three-phase coordinate <code>a</code>
-  @param[out] pIb     points to output three-phase coordinate <code>b</code>
-  @return     none
-
-  \par Scaling and Overflow Behavior
-         The function is implemented using an internal 32-bit accumulator.
-         The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-         There is saturation on the subtraction, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output   rotor reference frame d
-   * @param[out] pIq     points to output   rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   * @return     none
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-  __STATIC_FORCEINLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-  }
-
-
-/**
-  @brief  Park transform for Q31 version
-  @param[in]  Ialpha  input two-phase vector coordinate alpha
-  @param[in]  Ibeta   input two-phase vector coordinate beta
-  @param[out] pId     points to output rotor reference frame d
-  @param[out] pIq     points to output rotor reference frame q
-  @param[in]  sinVal  sine value of rotation angle theta
-  @param[in]  cosVal  cosine value of rotation angle theta
-  @return     none
-
-  \par Scaling and Overflow Behavior
-         The function is implemented using an internal 32-bit accumulator.
-         The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-         There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   * @return     none
-   */
-  __STATIC_FORCEINLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-  }
-
-
-/**
-  @brief  Inverse Park transform for   Q31 version
-  @param[in]  Id       input coordinate of rotor reference frame d
-  @param[in]  Iq       input coordinate of rotor reference frame q
-  @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-  @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-  @param[in]  sinVal   sine value of rotation angle theta
-  @param[in]  cosVal   cosine value of rotation angle theta
-  @return     none
-
-  @par Scaling and Overflow Behavior
-         The function is implemented using an internal 32-bit accumulator.
-         The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-         There is saturation on the addition, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
-   * @param[in]     x  input sample to process
-   * @return y processed output sample.
-   *
-   */
-  __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if ((uint32_t)i >= (S->nValues - 1))
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 +  i      * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q31 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1U);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q15 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (q15_t) (y >> 20);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q7 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-  __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (q7_t) (y >> 20);
-     }
-  }
-
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  sin(x).
-   */
-  float32_t arm_sin_f32(
-  float32_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q31_t arm_sin_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q15_t arm_sin_q15(
-  q15_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  cos(x).
-   */
-  float32_t arm_cos_f32(
-  float32_t x);
-
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q31_t arm_cos_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-/**
-  @brief         Floating-point vector of log values.
-  @param[in]     pSrc       points to the input vector
-  @param[out]    pDst       points to the output vector
-  @param[in]     blockSize  number of samples in each vector
-  @return        none
- */
-  void arm_vlog_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-/**
-  @brief         Floating-point vector of exp values.
-  @param[in]     pSrc       points to the input vector
-  @param[out]    pDst       points to the output vector
-  @param[in]     blockSize  number of samples in each vector
-  @return        none
- */
-  void arm_vexp_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-/**
-  @brief         Floating-point square root function.
-  @param[in]     in    input value
-  @param[out]    pOut  square root of input value
-  @return        execution status
-                   - \ref ARM_MATH_SUCCESS        : input value is positive
-                   - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if (in >= 0.0f)
-    {
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-      *pOut = __sqrtf(in);
-  #else
-      *pOut = sqrtf(in);
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-  #else
-      *pOut = sqrtf(in);
-  #endif
-
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-  }
-
-
-/**
-  @brief         Q31 square root function.
-  @param[in]     in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
-  @param[out]    pOut  points to square root of input value
-  @return        execution status
-                   - \ref ARM_MATH_SUCCESS        : input value is positive
-                   - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-
-/**
-  @brief         Q15 square root function.
-  @param[in]     in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF
-  @param[out]    pOut  points to square root of input value
-  @return        execution status
-                   - \ref ARM_MATH_SUCCESS        : input value is positive
-                   - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @brief  Vector Floating-point square root function.
-   * @param[in]  pIn   input vector.
-   * @param[out] pOut  vector of square roots of input elements.
-   * @param[in]  len   length of input vector.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  void arm_vsqrt_f32(
-  float32_t * pIn,
-  float32_t * pOut,
-  uint16_t len);
-
-  void arm_vsqrt_q31(
-  q31_t * pIn,
-  q31_t * pOut,
-  uint16_t len);
-
-  void arm_vsqrt_q15(
-  q15_t * pIn,
-  q15_t * pOut,
-  uint16_t len);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-  __STATIC_FORCEINLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  __STATIC_FORCEINLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t rOffset;
-    int32_t* dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = dst_base + dst_length;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-  __STATIC_FORCEINLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  __STATIC_FORCEINLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset;
-    q15_t* dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = dst_base + dst_length;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-  __STATIC_FORCEINLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  __STATIC_FORCEINLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset;
-    q7_t* dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = dst_base + dst_length;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q7(
-  const q7_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q7(
-  const q7_t * pSrc,
-        uint32_t blockSize,
-        q7_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult);
-
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_f32(
-  const float32_t * pSrc,
-        float32_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q31(
-  const q31_t * pSrc,
-        q31_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q15(
-  const q15_t * pSrc,
-        q15_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        uint32_t numSamples,
-        q31_t * realResult,
-        q31_t * imagResult);
-
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        uint32_t numSamples,
-        q63_t * realResult,
-        q63_t * imagResult);
-
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        uint32_t numSamples,
-        float32_t * realResult,
-        float32_t * imagResult);
-
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q15(
-  const q15_t * pSrcCmplx,
-  const q15_t * pSrcReal,
-        q15_t * pCmplxDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q31(
-  const q31_t * pSrcCmplx,
-  const q31_t * pSrcReal,
-        q31_t * pCmplxDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_f32(
-  const float32_t * pSrcCmplx,
-  const float32_t * pSrcReal,
-        float32_t * pCmplxDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] result     is output pointer
-   * @param[in]  index      is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q7(
-  const q7_t * pSrc,
-        uint32_t blockSize,
-        q7_t * result,
-        uint32_t * index);
-
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult,
-        uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult,
-        uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult,
-        uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q7(
-  const q7_t * pSrc,
-        uint32_t blockSize,
-        q7_t * pResult,
-        uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q15(
-  const q15_t * pSrc,
-        uint32_t blockSize,
-        q15_t * pResult,
-        uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q31(
-  const q31_t * pSrc,
-        uint32_t blockSize,
-        q31_t * pResult,
-        uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_f32(
-  const float32_t * pSrc,
-        uint32_t blockSize,
-        float32_t * pResult,
-        uint32_t * pIndex);
-
-  /**
-    @brief         Maximum value of a floating-point vector.
-    @param[in]     pSrc       points to the input vector
-    @param[in]     blockSize  number of samples in input vector
-    @param[out]    pResult    maximum value returned here
-    @return        none
-   */
-  void arm_max_no_idx_f32(
-      const float32_t *pSrc,
-      uint32_t   blockSize,
-      float32_t *pResult);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q15(
-  const q15_t * pSrcA,
-  const q15_t * pSrcB,
-        q15_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q31(
-  const q31_t * pSrcA,
-  const q31_t * pSrcB,
-        q31_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_f32(
-  const float32_t * pSrcA,
-  const float32_t * pSrcB,
-        float32_t * pDst,
-        uint32_t numSamples);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q31 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q31(
-  const float32_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q15 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q15(
-  const float32_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q7 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q7(
-  const float32_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_float(
-  const q31_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q15(
-  const q31_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q7(
-  const q31_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_float(
-  const q15_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q31(
-  const q15_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q7(
-  const q15_t * pSrc,
-        q7_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q7_to_float(
-  const q7_t * pSrc,
-        float32_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q31(
-  const q7_t * pSrc,
-        q31_t * pDst,
-        uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q15(
-  const q7_t * pSrc,
-        q15_t * pDst,
-        uint32_t blockSize);
-
-/**
- * @brief Struct for specifying SVM Kernel
- */
-typedef enum
-{
-    ARM_ML_KERNEL_LINEAR = 0,
-             /**< Linear kernel */
-    ARM_ML_KERNEL_POLYNOMIAL = 1,
-             /**< Polynomial kernel */
-    ARM_ML_KERNEL_RBF = 2,
-             /**< Radial Basis Function kernel */
-    ARM_ML_KERNEL_SIGMOID = 3
-             /**< Sigmoid kernel */
-} arm_ml_kernel_type;
-
-
-/**
- * @brief Instance structure for linear SVM prediction function.
- */
-typedef struct
-{
-  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
-  uint32_t        vectorDimension;        /**< Dimension of vector space */
-  float32_t       intercept;              /**< Intercept */
-  const float32_t *dualCoefficients;      /**< Dual coefficients */
-  const float32_t *supportVectors;        /**< Support vectors */
-  const int32_t   *classes;               /**< The two SVM classes */
-} arm_svm_linear_instance_f32;
-
-
-/**
- * @brief Instance structure for polynomial SVM prediction function.
- */
-typedef struct
-{
-  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
-  uint32_t        vectorDimension;        /**< Dimension of vector space */
-  float32_t       intercept;              /**< Intercept */
-  const float32_t *dualCoefficients;      /**< Dual coefficients */
-  const float32_t *supportVectors;        /**< Support vectors */
-  const int32_t   *classes;               /**< The two SVM classes */
-  int32_t         degree;                 /**< Polynomial degree */
-  float32_t       coef0;                  /**< Polynomial constant */
-  float32_t       gamma;                  /**< Gamma factor */
-} arm_svm_polynomial_instance_f32;
-
-/**
- * @brief Instance structure for rbf SVM prediction function.
- */
-typedef struct
-{
-  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
-  uint32_t        vectorDimension;        /**< Dimension of vector space */
-  float32_t       intercept;              /**< Intercept */
-  const float32_t *dualCoefficients;      /**< Dual coefficients */
-  const float32_t *supportVectors;        /**< Support vectors */
-  const int32_t   *classes;               /**< The two SVM classes */
-  float32_t       gamma;                  /**< Gamma factor */
-} arm_svm_rbf_instance_f32;
-
-/**
- * @brief Instance structure for sigmoid SVM prediction function.
- */
-typedef struct
-{
-  uint32_t        nbOfSupportVectors;     /**< Number of support vectors */
-  uint32_t        vectorDimension;        /**< Dimension of vector space */
-  float32_t       intercept;              /**< Intercept */
-  const float32_t *dualCoefficients;      /**< Dual coefficients */
-  const float32_t *supportVectors;        /**< Support vectors */
-  const int32_t   *classes;               /**< The two SVM classes */
-  float32_t       coef0;                  /**< Independant constant */
-  float32_t       gamma;                  /**< Gamma factor */
-} arm_svm_sigmoid_instance_f32;
-
-/**
- * @brief        SVM linear instance init function
- * @param[in]    S                      Parameters for SVM functions
- * @param[in]    nbOfSupportVectors     Number of support vectors
- * @param[in]    vectorDimension        Dimension of vector space
- * @param[in]    intercept              Intercept
- * @param[in]    dualCoefficients       Array of dual coefficients
- * @param[in]    supportVectors         Array of support vectors
- * @param[in]    classes                Array of 2 classes ID
- * @return none.
- *
- */
-
-
-void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
-  uint32_t nbOfSupportVectors,
-  uint32_t vectorDimension,
-  float32_t intercept,
-  const float32_t *dualCoefficients,
-  const float32_t *supportVectors,
-  const int32_t  *classes);
-
-/**
- * @brief SVM linear prediction
- * @param[in]    S          Pointer to an instance of the linear SVM structure.
- * @param[in]    in         Pointer to input vector
- * @param[out]   pResult    Decision value
- * @return none.
- *
- */
-
-void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
-   const float32_t * in,
-   int32_t * pResult);
-
-
-/**
- * @brief        SVM polynomial instance init function
- * @param[in]    S                      points to an instance of the polynomial SVM structure.
- * @param[in]    nbOfSupportVectors     Number of support vectors
- * @param[in]    vectorDimension        Dimension of vector space
- * @param[in]    intercept              Intercept
- * @param[in]    dualCoefficients       Array of dual coefficients
- * @param[in]    supportVectors         Array of support vectors
- * @param[in]    classes                Array of 2 classes ID
- * @param[in]    degree                 Polynomial degree
- * @param[in]    coef0                  coeff0 (scikit-learn terminology)
- * @param[in]    gamma                  gamma (scikit-learn terminology)
- * @return none.
- *
- */
-
-
-void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
-  uint32_t nbOfSupportVectors,
-  uint32_t vectorDimension,
-  float32_t intercept,
-  const float32_t *dualCoefficients,
-  const float32_t *supportVectors,
-  const int32_t   *classes,
-  int32_t      degree,
-  float32_t coef0,
-  float32_t gamma
-  );
-
-/**
- * @brief SVM polynomial prediction
- * @param[in]    S          Pointer to an instance of the polynomial SVM structure.
- * @param[in]    in         Pointer to input vector
- * @param[out]   pResult    Decision value
- * @return none.
- *
- */
-void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
-   const float32_t * in,
-   int32_t * pResult);
-
-
-/**
- * @brief        SVM radial basis function instance init function
- * @param[in]    S                      points to an instance of the polynomial SVM structure.
- * @param[in]    nbOfSupportVectors     Number of support vectors
- * @param[in]    vectorDimension        Dimension of vector space
- * @param[in]    intercept              Intercept
- * @param[in]    dualCoefficients       Array of dual coefficients
- * @param[in]    supportVectors         Array of support vectors
- * @param[in]    classes                Array of 2 classes ID
- * @param[in]    gamma                  gamma (scikit-learn terminology)
- * @return none.
- *
- */
-
-void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
-  uint32_t nbOfSupportVectors,
-  uint32_t vectorDimension,
-  float32_t intercept,
-  const float32_t *dualCoefficients,
-  const float32_t *supportVectors,
-  const int32_t   *classes,
-  float32_t gamma
-  );
-
-/**
- * @brief SVM rbf prediction
- * @param[in]    S         Pointer to an instance of the rbf SVM structure.
- * @param[in]    in        Pointer to input vector
- * @param[out]   pResult   decision value
- * @return none.
- *
- */
-void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
-   const float32_t * in,
-   int32_t * pResult);
-
-/**
- * @brief        SVM sigmoid instance init function
- * @param[in]    S                      points to an instance of the rbf SVM structure.
- * @param[in]    nbOfSupportVectors     Number of support vectors
- * @param[in]    vectorDimension        Dimension of vector space
- * @param[in]    intercept              Intercept
- * @param[in]    dualCoefficients       Array of dual coefficients
- * @param[in]    supportVectors         Array of support vectors
- * @param[in]    classes                Array of 2 classes ID
- * @param[in]    coef0                  coeff0 (scikit-learn terminology)
- * @param[in]    gamma                  gamma (scikit-learn terminology)
- * @return none.
- *
- */
-
-void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
-  uint32_t nbOfSupportVectors,
-  uint32_t vectorDimension,
-  float32_t intercept,
-  const float32_t *dualCoefficients,
-  const float32_t *supportVectors,
-  const int32_t   *classes,
-  float32_t coef0,
-  float32_t gamma
-  );
-
-/**
- * @brief SVM sigmoid prediction
- * @param[in]    S        Pointer to an instance of the rbf SVM structure.
- * @param[in]    in       Pointer to input vector
- * @param[out]   pResult  Decision value
- * @return none.
- *
- */
-void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
-   const float32_t * in,
-   int32_t * pResult);
-
-
-
-/**
- * @brief Instance structure for Naive Gaussian Bayesian estimator.
- */
-typedef struct
-{
-  uint32_t vectorDimension;  /**< Dimension of vector space */
-  uint32_t numberOfClasses;  /**< Number of different classes  */
-  const float32_t *theta;          /**< Mean values for the Gaussians */
-  const float32_t *sigma;          /**< Variances for the Gaussians */
-  const float32_t *classPriors;    /**< Class prior probabilities */
-  float32_t epsilon;         /**< Additive value to variances */
-} arm_gaussian_naive_bayes_instance_f32;
-
-/**
- * @brief Naive Gaussian Bayesian Estimator
- *
- * @param[in]  S         points to a naive bayes instance structure
- * @param[in]  in        points to the elements of the input vector.
- * @param[in]  pBuffer   points to a buffer of length numberOfClasses
- * @return The predicted class
- *
- */
-
-
-uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
-   const float32_t * in,
-   float32_t *pBuffer);
-
-/**
- * @brief Computation of the LogSumExp
- *
- * In probabilistic computations, the dynamic of the probability values can be very
- * wide because they come from gaussian functions.
- * To avoid underflow and overflow issues, the values are represented by their log.
- * In this representation, multiplying the original exp values is easy : their logs are added.
- * But adding the original exp values is requiring some special handling and it is the
- * goal of the LogSumExp function.
- *
- * If the values are x1...xn, the function is computing:
- *
- * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
- * rounding issues are minimised.
- *
- * The max xm of the values is extracted and the function is computing:
- * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
- *
- * @param[in]  *in         Pointer to an array of input values.
- * @param[in]  blockSize   Number of samples in the input array.
- * @return LogSumExp
- *
- */
-
-
-float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
-
-/**
- * @brief Dot product with log arithmetic
- *
- * Vectors are containing the log of the samples
- *
- * @param[in]       pSrcA points to the first input vector
- * @param[in]       pSrcB points to the second input vector
- * @param[in]       blockSize number of samples in each vector
- * @param[in]       pTmpBuffer temporary buffer of length blockSize
- * @return The log of the dot product .
- *
- */
-
-
-float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
-  const float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t *pTmpBuffer);
-
-/**
- * @brief Entropy
- *
- * @param[in]  pSrcA        Array of input values.
- * @param[in]  blockSize    Number of samples in the input array.
- * @return     Entropy      -Sum(p ln p)
- *
- */
-
-
-float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
-
-
-/**
- * @brief Entropy
- *
- * @param[in]  pSrcA        Array of input values.
- * @param[in]  blockSize    Number of samples in the input array.
- * @return     Entropy      -Sum(p ln p)
- *
- */
-
-
-float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
-
-
-/**
- * @brief Kullback-Leibler
- *
- * @param[in]  pSrcA         Pointer to an array of input values for probability distribution A.
- * @param[in]  pSrcB         Pointer to an array of input values for probability distribution B.
- * @param[in]  blockSize     Number of samples in the input array.
- * @return Kullback-Leibler  Divergence D(A || B)
- *
- */
-float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
-  ,const float32_t * pSrcB
-  ,uint32_t blockSize);
-
-
-/**
- * @brief Kullback-Leibler
- *
- * @param[in]  pSrcA         Pointer to an array of input values for probability distribution A.
- * @param[in]  pSrcB         Pointer to an array of input values for probability distribution B.
- * @param[in]  blockSize     Number of samples in the input array.
- * @return Kullback-Leibler  Divergence D(A || B)
- *
- */
-float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
-                const float64_t * pSrcB,
-                uint32_t blockSize);
-
-
-/**
- * @brief Weighted sum
- *
- *
- * @param[in]    *in           Array of input values.
- * @param[in]    *weigths      Weights
- * @param[in]    blockSize     Number of samples in the input array.
- * @return Weighted sum
- *
- */
-float32_t arm_weighted_sum_f32(const float32_t *in
-  , const float32_t *weigths
-  , uint32_t blockSize);
-
-
-/**
- * @brief Barycenter
- *
- *
- * @param[in]    in         List of vectors
- * @param[in]    weights    Weights of the vectors
- * @param[out]   out        Barycenter
- * @param[in]    nbVectors  Number of vectors
- * @param[in]    vecDim     Dimension of space (vector dimension)
- * @return       None
- *
- */
-void arm_barycenter_f32(const float32_t *in
-  , const float32_t *weights
-  , float32_t *out
-  , uint32_t nbVectors
-  , uint32_t vecDim);
-
-/**
- * @brief        Euclidean distance between two vectors
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-
-float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-/**
- * @brief        Bray-Curtis distance between two vectors
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-/**
- * @brief        Canberra distance between two vectors
- *
- * This function may divide by zero when samples pA[i] and pB[i] are both zero.
- * The result of the computation will be correct. So the division per zero may be
- * ignored.
- *
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-
-/**
- * @brief        Chebyshev distance between two vectors
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-
-/**
- * @brief        Cityblock (Manhattan) distance between two vectors
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-/**
- * @brief        Correlation distance between two vectors
- *
- * The input vectors are modified in place !
- *
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
-
-/**
- * @brief        Cosine distance between two vectors
- *
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-
-float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
-
-/**
- * @brief        Jensen-Shannon distance between two vectors
- *
- * This function is assuming that elements of second vector are > 0
- * and 0 only when the corresponding element of first vector is 0.
- * Otherwise the result of the computation does not make sense
- * and for speed reasons, the cases returning NaN or Infinity are not
- * managed.
- *
- * When the function is computing x log (x / y) with x 0 and y 0,
- * it will compute the right value (0) but a division per zero will occur
- * and shoudl be ignored in client code.
- *
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-
-float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
-
-/**
- * @brief        Minkowski distance between two vectors
- *
- * @param[in]    pA         First vector
- * @param[in]    pB         Second vector
- * @param[in]    n          Norm order (>= 2)
- * @param[in]    blockSize  vector length
- * @return distance
- *
- */
-
-
-
-float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
-
-/**
- * @brief        Dice distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    order           Distance order
- * @param[in]    blockSize       Number of samples
- * @return distance
- *
- */
-
-
-float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Hamming distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Jaccard distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Kulsinski distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Roger Stanimoto distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Russell-Rao distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Sokal-Michener distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Sokal-Sneath distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-/**
- * @brief        Yule distance between two vectors
- *
- * @param[in]    pA              First vector of packed booleans
- * @param[in]    pB              Second vector of packed booleans
- * @param[in]    numberOfBools   Number of booleans
- * @return distance
- *
- */
-
-float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate.
-  * @param[in]     Y  interpolation coordinate.
-  * @return out interpolated value.
-  */
-  __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex ) + (yIndex ) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex ) + (yIndex+1) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-  }
-
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U);
-    acc = ((q63_t) out * (0x0FFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-  }
-
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
-      #define LOW_OPTIMIZATION_ENTER
-      #define LOW_OPTIMIZATION_EXIT
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-      #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-#endif
-
-
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#elif defined ( _MSC_VER )
-
-#else
-  #error Unknown compiler
-#endif
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_mve_tables.h

@@ -1,235 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_mve_tables.h
- * Description:  common tables like fft twiddle factors, Bitreverse, reciprocal etc
- *               used for MVE implementation only
- *
- * $Date:        08. January 2020
- * $Revision:    V1.7.0
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #ifndef _ARM_MVE_TABLES_H
- #define _ARM_MVE_TABLES_H
-
- #include "arm_math.h"
-
-
-
-
-
-
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
-extern float32_t rearranged_twiddle_stride1_16_f32[8];
-extern float32_t rearranged_twiddle_stride2_16_f32[8];
-extern float32_t rearranged_twiddle_stride3_16_f32[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
-extern float32_t rearranged_twiddle_stride1_64_f32[40];
-extern float32_t rearranged_twiddle_stride2_64_f32[40];
-extern float32_t rearranged_twiddle_stride3_64_f32[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
-extern float32_t rearranged_twiddle_stride1_256_f32[168];
-extern float32_t rearranged_twiddle_stride2_256_f32[168];
-extern float32_t rearranged_twiddle_stride3_256_f32[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
-extern float32_t rearranged_twiddle_stride1_1024_f32[680];
-extern float32_t rearranged_twiddle_stride2_1024_f32[680];
-extern float32_t rearranged_twiddle_stride3_1024_f32[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
-extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
-extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
-extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-
-
-#if defined(ARM_MATH_MVEI)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
-extern q31_t rearranged_twiddle_stride1_16_q31[8];
-extern q31_t rearranged_twiddle_stride2_16_q31[8];
-extern q31_t rearranged_twiddle_stride3_16_q31[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
-extern q31_t rearranged_twiddle_stride1_64_q31[40];
-extern q31_t rearranged_twiddle_stride2_64_q31[40];
-extern q31_t rearranged_twiddle_stride3_64_q31[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
-extern q31_t rearranged_twiddle_stride1_256_q31[168];
-extern q31_t rearranged_twiddle_stride2_256_q31[168];
-extern q31_t rearranged_twiddle_stride3_256_q31[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
-extern q31_t rearranged_twiddle_stride1_1024_q31[680];
-extern q31_t rearranged_twiddle_stride2_1024_q31[680];
-extern q31_t rearranged_twiddle_stride3_1024_q31[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
-extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
-extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
-extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEI) */
-
-
-
-#if defined(ARM_MATH_MVEI)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
-extern q15_t rearranged_twiddle_stride1_16_q15[8];
-extern q15_t rearranged_twiddle_stride2_16_q15[8];
-extern q15_t rearranged_twiddle_stride3_16_q15[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
-extern q15_t rearranged_twiddle_stride1_64_q15[40];
-extern q15_t rearranged_twiddle_stride2_64_q15[40];
-extern q15_t rearranged_twiddle_stride3_64_q15[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
-extern q15_t rearranged_twiddle_stride1_256_q15[168];
-extern q15_t rearranged_twiddle_stride2_256_q15[168];
-extern q15_t rearranged_twiddle_stride3_256_q15[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
-extern q15_t rearranged_twiddle_stride1_1024_q15[680];
-extern q15_t rearranged_twiddle_stride2_1024_q15[680];
-extern q15_t rearranged_twiddle_stride3_1024_q15[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
-extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
-extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
-extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEI) */
-
-
-
-#if defined(ARM_MATH_MVEI)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEI) */
-
-
-
-#endif /*_ARM_MVE_TABLES_H*/
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/arm_vec_math.h

@@ -1,372 +0,0 @@
-/******************************************************************************
- * @file     arm_vec_math.h
- * @brief    Public header file for CMSIS DSP Library
- * @version  V1.7.0
- * @date     15. October 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_VEC_MATH_H
-#define _ARM_VEC_MATH_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include "arm_helium_utils.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#define INV_NEWTON_INIT_F32         0x7EF127EA
-
-static const float32_t __logf_rng_f32=0.693147180f;
-
-
-/* fast inverse approximation (3x newton) */
-__STATIC_INLINE f32x4_t vrecip_medprec_f32(
-    f32x4_t x)
-{
-    q31x4_t         m;
-    f32x4_t         b;
-    any32x4_t       xinv;
-    f32x4_t         ax = vabsq(x);
-
-    xinv.f = ax;
-    m = 0x3F800000 - (xinv.i & 0x7F800000);
-    xinv.i = xinv.i + m;
-    xinv.f = 1.41176471f - 0.47058824f * xinv.f;
-    xinv.i = xinv.i + m;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
-    /*
-     * restore sign
-     */
-    xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
-
-    return xinv.f;
-}
-
-/* fast inverse approximation (4x newton) */
-__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
-    f32x4_t x)
-{
-    q31x4_t         m;
-    f32x4_t         b;
-    any32x4_t       xinv;
-    f32x4_t         ax = vabsq(x);
-
-    xinv.f = ax;
-
-    m = 0x3F800000 - (xinv.i & 0x7F800000);
-    xinv.i = xinv.i + m;
-    xinv.f = 1.41176471f - 0.47058824f * xinv.f;
-    xinv.i = xinv.i + m;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    b = 2.0f - xinv.f * ax;
-    xinv.f = xinv.f * b;
-
-    xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
-    /*
-     * restore sign
-     */
-    xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
-
-    return xinv.f;
-}
-
-__STATIC_INLINE f32x4_t vdiv_f32(
-    f32x4_t num, f32x4_t den)
-{
-    return vmulq(num, vrecip_hiprec_f32(den));
-}
-
-/**
-  @brief         Single-precision taylor dev.
-  @param[in]     x              f32 quad vector input
-  @param[in]     coeffs         f32 quad vector coeffs
-  @return        destination    f32 quad vector
- */
-
-__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
-        f32x4_t           x,
-        const float32_t * coeffs)
-{
-    f32x4_t         A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
-    f32x4_t         B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
-    f32x4_t         C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
-    f32x4_t         D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
-    f32x4_t         x2 = vmulq(x, x);
-    f32x4_t         x4 = vmulq(x2, x2);
-    f32x4_t         res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
-
-    return res;
-}
-
-__STATIC_INLINE f32x4_t vmant_exp_f32(
-    f32x4_t     x,
-    int32x4_t * e)
-{
-    any32x4_t       r;
-    int32x4_t       n;
-
-    r.f = x;
-    n = r.i >> 23;
-    n = n - 127;
-    r.i = r.i - (n << 23);
-
-    *e = n;
-    return r.f;
-}
-
-
-__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
-{
-    q31x4_t         vecExpUnBiased;
-    f32x4_t         vecTmpFlt0, vecTmpFlt1;
-    f32x4_t         vecAcc0, vecAcc1, vecAcc2, vecAcc3;
-    f32x4_t         vecExpUnBiasedFlt;
-
-    /*
-     * extract exponent
-     */
-    vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
-
-    vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
-    /*
-     * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
-     */
-    vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
-    vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
-    /*
-     * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
-     */
-    vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
-    vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
-    /*
-     * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
-     */
-    vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
-    vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
-    /*
-     * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
-     */
-    vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
-    vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
-    /*
-     * a = a + b * xx;
-     */
-    vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
-    /*
-     * c = c + d * xx;
-     */
-    vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
-    /*
-     * xx = xx * xx;
-     */
-    vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
-    vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
-    /*
-     * r.f = a + c * xx;
-     */
-    vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
-    /*
-     * add exponent
-     * r.f = r.f + ((float32_t) m) * __logf_rng_f32;
-     */
-    vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
-    // set log0 down to -inf
-    vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
-    return vecAcc0;
-}
-
-__STATIC_INLINE f32x4_t vexpq_f32(
-    f32x4_t x)
-{
-    // Perform range reduction [-log(2),log(2)]
-    int32x4_t       m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
-    f32x4_t         val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
-
-    // Polynomial Approximation
-    f32x4_t         poly = vtaylor_polyq_f32(val, exp_tab);
-
-    // Reconstruct
-    poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
-
-    poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
-    return poly;
-}
-
-__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
-{
-    f32x4_t         r = x;
-    nb--;
-    while (nb > 0) {
-        r = vmulq(r, x);
-        nb--;
-    }
-    return (r);
-}
-
-__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
-{
-    f32x4_t     vecSx, vecW, vecTmp;
-    any32x4_t   v;
-
-    vecSx = vabsq(vecIn);
-
-    v.f = vecIn;
-    v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
-
-    vecW = vmulq(vecSx, v.f);
-
-    // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
-    vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
-    vecTmp = vfmasq(vecW, vecTmp, -28.0f);
-    vecTmp = vfmasq(vecW, vecTmp, 56.0f);
-    vecTmp = vfmasq(vecW, vecTmp, -70.0f);
-    vecTmp = vfmasq(vecW, vecTmp, 56.0f);
-    vecTmp = vfmasq(vecW, vecTmp, -28.0f);
-    vecTmp = vfmasq(vecW, vecTmp, 8.0f);
-    v.f = vmulq(v.f,  vecTmp);
-
-    v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
-    /*
-     * restore sign
-     */
-    v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
-    return v.f;
-}
-
-__STATIC_INLINE f32x4_t vtanhq_f32(
-    f32x4_t val)
-{
-    f32x4_t         x =
-        vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
-    f32x4_t         exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
-    f32x4_t         num = vsubq_n_f32(exp2x, 1.f);
-    f32x4_t         den = vaddq_n_f32(exp2x, 1.f);
-    f32x4_t         tanh = vmulq_f32(num, vrecip_f32(den));
-    return tanh;
-}
-
-__STATIC_INLINE f32x4_t vpowq_f32(
-    f32x4_t val,
-    f32x4_t n)
-{
-    return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
-}
-
-#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
-
-#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
-#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
-
-#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#include "NEMath.h"
-/**
- * @brief Vectorized integer exponentiation
- * @param[in]    x           value
- * @param[in]    nb          integer exponent >= 1
- * @return x^nb
- *
- */
-__STATIC_INLINE  float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
-{
-    float32x4_t r = x;
-    nb --;
-    while(nb > 0)
-    {
-        r = vmulq_f32(r , x);
-        nb--;
-    }
-    return(r);
-}
-
-
-__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t  x)
-{
-    float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
-    float32x4_t e = vrsqrteq_f32(x1);
-    e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
-    e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
-    return vmulq_f32(x, e);
-}
-
-__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
-{
-    float32x4_t tempF;
-    int32x4_t tempHI,tempLO;
-
-    tempLO = vmovl_s16(vget_low_s16(vec));
-    tempF = vcvtq_n_f32_s32(tempLO,15);
-    tempF = __arm_vec_sqrt_f32_neon(tempF);
-    tempLO = vcvtq_n_s32_f32(tempF,15);
-
-    tempHI = vmovl_s16(vget_high_s16(vec));
-    tempF = vcvtq_n_f32_s32(tempHI,15);
-    tempF = __arm_vec_sqrt_f32_neon(tempF);
-    tempHI = vcvtq_n_s32_f32(tempF,15);
-
-    return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
-}
-
-__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
-{
-  float32x4_t temp;
-
-  temp = vcvtq_n_f32_s32(vec,31);
-  temp = __arm_vec_sqrt_f32_neon(temp);
-  return(vcvtq_n_s32_f32(temp,31));
-}
-
-#endif /*  (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_VEC_MATH_H */
-
-/**
- *
- * End of file.
- */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_armcc.h

@@ -1,885 +0,0 @@
-/******************************************************************************
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.2.1
- * @date     26. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-  #define __ARM_ARCH_6M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-  #define __ARM_ARCH_7M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-  #define __ARM_ARCH_7EM__          1
-#endif
-
-  /* __ARM_ARCH_8M_BASE__  not applicable */
-  /* __ARM_ARCH_8M_MAIN__  not applicable */
-  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
-
-/* CMSIS compiler control DSP macros */
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __ARM_FEATURE_DSP         1
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   static __forceinline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __declspec(noreturn)
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        __packed struct
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         __packed union
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __memory_changed()
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __main
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return result;
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_armclang.h

@@ -1,1467 +0,0 @@
-/******************************************************************************
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V5.3.1
- * @date     26. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#pragma clang system_header   /* treat file as system include file */
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __main
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR()      ((uint32_t)0U)
-#endif
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __set_FPSCR      __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x)      ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF)
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF)
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV(value)   __builtin_bswap32(value)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16(value) __ROR(__REV(value), 16)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)     __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT            __builtin_arm_rbit
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
-{
-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
-     __builtin_clz(0) is undefined behaviour, so handle this case specially.
-     This guarantees ARM-compatible results if happening to compile on a non-ARM
-     target, and ensures the compiler doesn't decide to activate any
-     optimisations using the logic "value was passed to __builtin_clz, so it
-     is non-zero".
-     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
-     single CLZ instruction.
-   */
-  if (value == 0U)
-  {
-    return 32U;
-  }
-  return __builtin_clz(value);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
-           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
-
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
-           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-#define     __SADD8                 __builtin_arm_sadd8
-#define     __QADD8                 __builtin_arm_qadd8
-#define     __SHADD8                __builtin_arm_shadd8
-#define     __UADD8                 __builtin_arm_uadd8
-#define     __UQADD8                __builtin_arm_uqadd8
-#define     __UHADD8                __builtin_arm_uhadd8
-#define     __SSUB8                 __builtin_arm_ssub8
-#define     __QSUB8                 __builtin_arm_qsub8
-#define     __SHSUB8                __builtin_arm_shsub8
-#define     __USUB8                 __builtin_arm_usub8
-#define     __UQSUB8                __builtin_arm_uqsub8
-#define     __UHSUB8                __builtin_arm_uhsub8
-#define     __SADD16                __builtin_arm_sadd16
-#define     __QADD16                __builtin_arm_qadd16
-#define     __SHADD16               __builtin_arm_shadd16
-#define     __UADD16                __builtin_arm_uadd16
-#define     __UQADD16               __builtin_arm_uqadd16
-#define     __UHADD16               __builtin_arm_uhadd16
-#define     __SSUB16                __builtin_arm_ssub16
-#define     __QSUB16                __builtin_arm_qsub16
-#define     __SHSUB16               __builtin_arm_shsub16
-#define     __USUB16                __builtin_arm_usub16
-#define     __UQSUB16               __builtin_arm_uqsub16
-#define     __UHSUB16               __builtin_arm_uhsub16
-#define     __SASX                  __builtin_arm_sasx
-#define     __QASX                  __builtin_arm_qasx
-#define     __SHASX                 __builtin_arm_shasx
-#define     __UASX                  __builtin_arm_uasx
-#define     __UQASX                 __builtin_arm_uqasx
-#define     __UHASX                 __builtin_arm_uhasx
-#define     __SSAX                  __builtin_arm_ssax
-#define     __QSAX                  __builtin_arm_qsax
-#define     __SHSAX                 __builtin_arm_shsax
-#define     __USAX                  __builtin_arm_usax
-#define     __UQSAX                 __builtin_arm_uqsax
-#define     __UHSAX                 __builtin_arm_uhsax
-#define     __USAD8                 __builtin_arm_usad8
-#define     __USADA8                __builtin_arm_usada8
-#define     __SSAT16                __builtin_arm_ssat16
-#define     __USAT16                __builtin_arm_usat16
-#define     __UXTB16                __builtin_arm_uxtb16
-#define     __UXTAB16               __builtin_arm_uxtab16
-#define     __SXTB16                __builtin_arm_sxtb16
-#define     __SXTAB16               __builtin_arm_sxtab16
-#define     __SMUAD                 __builtin_arm_smuad
-#define     __SMUADX                __builtin_arm_smuadx
-#define     __SMLAD                 __builtin_arm_smlad
-#define     __SMLADX                __builtin_arm_smladx
-#define     __SMLALD                __builtin_arm_smlald
-#define     __SMLALDX               __builtin_arm_smlaldx
-#define     __SMUSD                 __builtin_arm_smusd
-#define     __SMUSDX                __builtin_arm_smusdx
-#define     __SMLSD                 __builtin_arm_smlsd
-#define     __SMLSDX                __builtin_arm_smlsdx
-#define     __SMLSLD                __builtin_arm_smlsld
-#define     __SMLSLDX               __builtin_arm_smlsldx
-#define     __SEL                   __builtin_arm_sel
-#define     __QADD                  __builtin_arm_qadd
-#define     __QSUB                  __builtin_arm_qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-  int32_t result;
-
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_armclang_ltm.h

@@ -1,1893 +0,0 @@
-/******************************************************************************
- * @file     cmsis_armclang_ltm.h
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V1.3.0
- * @date     26. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#pragma clang system_header   /* treat file as system include file */
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __main
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR()      ((uint32_t)0U)
-#endif
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __set_FPSCR      __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x)      ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF)
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF)
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV(value)   __builtin_bswap32(value)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16(value) __ROR(__REV(value), 16)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)     __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT            __builtin_arm_rbit
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
-{
-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
-     __builtin_clz(0) is undefined behaviour, so handle this case specially.
-     This guarantees ARM-compatible results if happening to compile on a non-ARM
-     target, and ensures the compiler doesn't decide to activate any
-     optimisations using the logic "value was passed to __builtin_clz, so it
-     is non-zero".
-     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
-     single CLZ instruction.
-   */
-  if (value == 0U)
-  {
-    return 32U;
-  }
-  return __builtin_clz(value);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-  return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-  int32_t result;
-
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_compiler.h

@@ -1,283 +0,0 @@
-/******************************************************************************
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.1.0
- * @date     09. October 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * Arm Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-
-/*
- * Arm Compiler 6.6 LTM (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
-  #include "cmsis_armclang_ltm.h"
-
-  /*
- * Arm Compiler above 6.10.1 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
-  #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iccarm.h>
-
-
-/*
- * TI Arm Compiler
- */
-#elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
-    #define __RESTRICT                             __restrict
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
-
- #ifndef   __ASM
-    #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    // NO RETURN is automatically detected hence no warning here
-    #define __NO_RETURN
-  #endif
-  #ifndef   __USED
-    #warning No compiler specific solution for __USED. __USED is ignored.
-    #define __USED
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
-
-
-#else
-  #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_gcc.h

@@ -1,2177 +0,0 @@
-/******************************************************************************
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.3.0
- * @date     26. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
-  #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-
-/**
-  \brief   Initializes data and bss sections
-  \details This default implementations initialized all data and additional bss
-           sections relying on .copy.table and .zero.table specified properly
-           in the used linker script.
-
- */
-__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
-{
-  extern void _start(void) __NO_RETURN;
-
-  typedef struct {
-    uint32_t const* src;
-    uint32_t* dest;
-    uint32_t  wlen;
-  } __copy_table_t;
-
-  typedef struct {
-    uint32_t* dest;
-    uint32_t  wlen;
-  } __zero_table_t;
-
-  extern const __copy_table_t __copy_table_start__;
-  extern const __copy_table_t __copy_table_end__;
-  extern const __zero_table_t __zero_table_start__;
-  extern const __zero_table_t __zero_table_end__;
-
-  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
-    for(uint32_t i=0u; i<pTable->wlen; ++i) {
-      pTable->dest[i] = pTable->src[i];
-    }
-  }
-
-  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
-    for(uint32_t i=0u; i<pTable->wlen; ++i) {
-      pTable->dest[i] = 0u;
-    }
-  }
-
-  _start();
-}
-
-#define __PROGRAM_START           __cmsis_start
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              __StackTop
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             __StackLimit
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  return __builtin_arm_get_fpscr();
-#else
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#endif
-#else
-  return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  __builtin_arm_set_fpscr(fpscr);
-#else
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP()                             __ASM volatile ("nop")
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI()                             __ASM volatile ("wfi":::"memory")
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE()                             __ASM volatile ("wfe":::"memory")
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV()                             __ASM volatile ("sev")
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (int16_t)__builtin_bswap16(value);
-#else
-  int16_t result;
-
-  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return result;
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
-{
-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
-     __builtin_clz(0) is undefined behaviour, so handle this case specially.
-     This guarantees ARM-compatible results if happening to compile on a non-ARM
-     target, and ensures the compiler doesn't decide to activate any
-     optimisations using the logic "value was passed to __builtin_clz, so it
-     is non-zero".
-     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
-     single CLZ instruction.
-   */
-  if (value == 0U)
-  {
-    return 32U;
-  }
-  return __builtin_clz(value);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1, ARG2) \
-__extension__ \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1, ARG2) \
- __extension__ \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1, ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1, ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
-{
-  uint32_t result;
-
-  __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
-
-  return result;
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_iccarm.h

@@ -1,968 +0,0 @@
-/******************************************************************************
- * @file     cmsis_iccarm.h
- * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.2.0
- * @date     28. January 2020
- ******************************************************************************/
-
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2017-2019 IAR Systems
-// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
-//
-// SPDX-License-Identifier: Apache-2.0
-//
-// Licensed under the Apache License, Version 2.0 (the "License")
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-//------------------------------------------------------------------------------
-
-
-#ifndef __CMSIS_ICCARM_H__
-#define __CMSIS_ICCARM_H__
-
-#ifndef __ICCARM__
-  #error This file should only be compiled by ICCARM
-#endif
-
-#pragma system_include
-
-#define __IAR_FT _Pragma("inline=forced") __intrinsic
-
-#if (__VER__ >= 8000000)
-  #define __ICCARM_V8 1
-#else
-  #define __ICCARM_V8 0
-#endif
-
-#ifndef __ALIGNED
-  #if __ICCARM_V8
-    #define __ALIGNED(x) __attribute__((aligned(x)))
-  #elif (__VER__ >= 7080000)
-    /* Needs IAR language extensions */
-    #define __ALIGNED(x) __attribute__((aligned(x)))
-  #else
-    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-#endif
-
-
-/* Define compiler macros for CPU architecture, used in CMSIS 5.
- */
-#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
-/* Macros already defined */
-#else
-  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #elif defined(__ARM8M_BASELINE__)
-    #define __ARM_ARCH_8M_BASE__ 1
-  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
-    #if __ARM_ARCH == 6
-      #define __ARM_ARCH_6M__ 1
-    #elif __ARM_ARCH == 7
-      #if __ARM_FEATURE_DSP
-        #define __ARM_ARCH_7EM__ 1
-      #else
-        #define __ARM_ARCH_7M__ 1
-      #endif
-    #endif /* __ARM_ARCH */
-  #endif /* __ARM_ARCH_PROFILE == 'M' */
-#endif
-
-/* Alternativ core deduction for older ICCARM's */
-#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
-    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
-  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
-    #define __ARM_ARCH_6M__ 1
-  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
-    #define __ARM_ARCH_7M__ 1
-  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
-    #define __ARM_ARCH_7EM__  1
-  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
-    #define __ARM_ARCH_8M_BASE__ 1
-  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #else
-    #error "Unknown target."
-  #endif
-#endif
-
-
-
-#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
-  #define __IAR_M0_FAMILY  1
-#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
-  #define __IAR_M0_FAMILY  1
-#else
-  #define __IAR_M0_FAMILY  0
-#endif
-
-
-#ifndef __ASM
-  #define __ASM __asm
-#endif
-
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
-#endif
-
-#ifndef __INLINE
-  #define __INLINE inline
-#endif
-
-#ifndef   __NO_RETURN
-  #if __ICCARM_V8
-    #define __NO_RETURN __attribute__((__noreturn__))
-  #else
-    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
-  #endif
-#endif
-
-#ifndef   __PACKED
-  #if __ICCARM_V8
-    #define __PACKED __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED __packed
-  #endif
-#endif
-
-#ifndef   __PACKED_STRUCT
-  #if __ICCARM_V8
-    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED_STRUCT __packed struct
-  #endif
-#endif
-
-#ifndef   __PACKED_UNION
-  #if __ICCARM_V8
-    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED_UNION __packed union
-  #endif
-#endif
-
-#ifndef   __RESTRICT
-  #if __ICCARM_V8
-    #define __RESTRICT            __restrict
-  #else
-    /* Needs IAR language extensions */
-    #define __RESTRICT            restrict
-  #endif
-#endif
-
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE       static inline
-#endif
-
-#ifndef   __FORCEINLINE
-  #define __FORCEINLINE         _Pragma("inline=forced")
-#endif
-
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
-#endif
-
-#ifndef __UNALIGNED_UINT16_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
-{
-  return *(__packed uint16_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
-#endif
-
-
-#ifndef __UNALIGNED_UINT16_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
-{
-  *(__packed uint16_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
-{
-  return *(__packed uint32_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
-#endif
-
-#ifndef __UNALIGNED_UINT32_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
-{
-  *(__packed uint32_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32   /* deprecated */
-#pragma language=save
-#pragma language=extended
-__packed struct  __iar_u32 { uint32_t v; };
-#pragma language=restore
-#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
-#endif
-
-#ifndef   __USED
-  #if __ICCARM_V8
-    #define __USED __attribute__((used))
-  #else
-    #define __USED _Pragma("__root")
-  #endif
-#endif
-
-#ifndef   __WEAK
-  #if __ICCARM_V8
-    #define __WEAK __attribute__((weak))
-  #else
-    #define __WEAK _Pragma("__weak")
-  #endif
-#endif
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __iar_program_start
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              CSTACK$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             CSTACK$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __vector_table
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
-#endif
-
-#ifndef __ICCARM_INTRINSICS_VERSION__
-  #define __ICCARM_INTRINSICS_VERSION__  0
-#endif
-
-#if __ICCARM_INTRINSICS_VERSION__ == 2
-
-  #if defined(__CLZ)
-    #undef __CLZ
-  #endif
-  #if defined(__REVSH)
-    #undef __REVSH
-  #endif
-  #if defined(__RBIT)
-    #undef __RBIT
-  #endif
-  #if defined(__SSAT)
-    #undef __SSAT
-  #endif
-  #if defined(__USAT)
-    #undef __USAT
-  #endif
-
-  #include "iccarm_builtin.h"
-
-  #define __disable_fault_irq __iar_builtin_disable_fiq
-  #define __disable_irq       __iar_builtin_disable_interrupt
-  #define __enable_fault_irq  __iar_builtin_enable_fiq
-  #define __enable_irq        __iar_builtin_enable_interrupt
-  #define __arm_rsr           __iar_builtin_rsr
-  #define __arm_wsr           __iar_builtin_wsr
-
-
-  #define __get_APSR()                (__arm_rsr("APSR"))
-  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
-  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
-  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
-
-  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
-    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
-  #else
-    #define __get_FPSCR()             ( 0 )
-    #define __set_FPSCR(VALUE)        ((void)VALUE)
-  #endif
-
-  #define __get_IPSR()                (__arm_rsr("IPSR"))
-  #define __get_MSP()                 (__arm_rsr("MSP"))
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure MSPLIM is RAZ/WI
-    #define __get_MSPLIM()            (0U)
-  #else
-    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
-  #endif
-  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
-  #define __get_PSP()                 (__arm_rsr("PSP"))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __get_PSPLIM()            (0U)
-  #else
-    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
-  #endif
-
-  #define __get_xPSR()                (__arm_rsr("xPSR"))
-
-  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
-  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
-  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
-  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure MSPLIM is RAZ/WI
-    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
-  #else
-    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
-  #endif
-  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
-  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
-  #else
-    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
-  #endif
-
-  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
-  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
-  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
-  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
-  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
-  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
-  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
-  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
-  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
-  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
-  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
-  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
-  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __TZ_get_PSPLIM_NS()      (0U)
-    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
-  #else
-    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
-    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
-  #endif
-
-  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
-  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
-
-  #define __NOP     __iar_builtin_no_operation
-
-  #define __CLZ     __iar_builtin_CLZ
-  #define __CLREX   __iar_builtin_CLREX
-
-  #define __DMB     __iar_builtin_DMB
-  #define __DSB     __iar_builtin_DSB
-  #define __ISB     __iar_builtin_ISB
-
-  #define __LDREXB  __iar_builtin_LDREXB
-  #define __LDREXH  __iar_builtin_LDREXH
-  #define __LDREXW  __iar_builtin_LDREX
-
-  #define __RBIT    __iar_builtin_RBIT
-  #define __REV     __iar_builtin_REV
-  #define __REV16   __iar_builtin_REV16
-
-  __IAR_FT int16_t __REVSH(int16_t val)
-  {
-    return (int16_t) __iar_builtin_REVSH(val);
-  }
-
-  #define __ROR     __iar_builtin_ROR
-  #define __RRX     __iar_builtin_RRX
-
-  #define __SEV     __iar_builtin_SEV
-
-  #if !__IAR_M0_FAMILY
-    #define __SSAT    __iar_builtin_SSAT
-  #endif
-
-  #define __STREXB  __iar_builtin_STREXB
-  #define __STREXH  __iar_builtin_STREXH
-  #define __STREXW  __iar_builtin_STREX
-
-  #if !__IAR_M0_FAMILY
-    #define __USAT    __iar_builtin_USAT
-  #endif
-
-  #define __WFE     __iar_builtin_WFE
-  #define __WFI     __iar_builtin_WFI
-
-  #if __ARM_MEDIA__
-    #define __SADD8   __iar_builtin_SADD8
-    #define __QADD8   __iar_builtin_QADD8
-    #define __SHADD8  __iar_builtin_SHADD8
-    #define __UADD8   __iar_builtin_UADD8
-    #define __UQADD8  __iar_builtin_UQADD8
-    #define __UHADD8  __iar_builtin_UHADD8
-    #define __SSUB8   __iar_builtin_SSUB8
-    #define __QSUB8   __iar_builtin_QSUB8
-    #define __SHSUB8  __iar_builtin_SHSUB8
-    #define __USUB8   __iar_builtin_USUB8
-    #define __UQSUB8  __iar_builtin_UQSUB8
-    #define __UHSUB8  __iar_builtin_UHSUB8
-    #define __SADD16  __iar_builtin_SADD16
-    #define __QADD16  __iar_builtin_QADD16
-    #define __SHADD16 __iar_builtin_SHADD16
-    #define __UADD16  __iar_builtin_UADD16
-    #define __UQADD16 __iar_builtin_UQADD16
-    #define __UHADD16 __iar_builtin_UHADD16
-    #define __SSUB16  __iar_builtin_SSUB16
-    #define __QSUB16  __iar_builtin_QSUB16
-    #define __SHSUB16 __iar_builtin_SHSUB16
-    #define __USUB16  __iar_builtin_USUB16
-    #define __UQSUB16 __iar_builtin_UQSUB16
-    #define __UHSUB16 __iar_builtin_UHSUB16
-    #define __SASX    __iar_builtin_SASX
-    #define __QASX    __iar_builtin_QASX
-    #define __SHASX   __iar_builtin_SHASX
-    #define __UASX    __iar_builtin_UASX
-    #define __UQASX   __iar_builtin_UQASX
-    #define __UHASX   __iar_builtin_UHASX
-    #define __SSAX    __iar_builtin_SSAX
-    #define __QSAX    __iar_builtin_QSAX
-    #define __SHSAX   __iar_builtin_SHSAX
-    #define __USAX    __iar_builtin_USAX
-    #define __UQSAX   __iar_builtin_UQSAX
-    #define __UHSAX   __iar_builtin_UHSAX
-    #define __USAD8   __iar_builtin_USAD8
-    #define __USADA8  __iar_builtin_USADA8
-    #define __SSAT16  __iar_builtin_SSAT16
-    #define __USAT16  __iar_builtin_USAT16
-    #define __UXTB16  __iar_builtin_UXTB16
-    #define __UXTAB16 __iar_builtin_UXTAB16
-    #define __SXTB16  __iar_builtin_SXTB16
-    #define __SXTAB16 __iar_builtin_SXTAB16
-    #define __SMUAD   __iar_builtin_SMUAD
-    #define __SMUADX  __iar_builtin_SMUADX
-    #define __SMMLA   __iar_builtin_SMMLA
-    #define __SMLAD   __iar_builtin_SMLAD
-    #define __SMLADX  __iar_builtin_SMLADX
-    #define __SMLALD  __iar_builtin_SMLALD
-    #define __SMLALDX __iar_builtin_SMLALDX
-    #define __SMUSD   __iar_builtin_SMUSD
-    #define __SMUSDX  __iar_builtin_SMUSDX
-    #define __SMLSD   __iar_builtin_SMLSD
-    #define __SMLSDX  __iar_builtin_SMLSDX
-    #define __SMLSLD  __iar_builtin_SMLSLD
-    #define __SMLSLDX __iar_builtin_SMLSLDX
-    #define __SEL     __iar_builtin_SEL
-    #define __QADD    __iar_builtin_QADD
-    #define __QSUB    __iar_builtin_QSUB
-    #define __PKHBT   __iar_builtin_PKHBT
-    #define __PKHTB   __iar_builtin_PKHTB
-  #endif
-
-#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
-  #if __IAR_M0_FAMILY
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
-    #define __CLZ  __cmsis_iar_clz_not_active
-    #define __SSAT __cmsis_iar_ssat_not_active
-    #define __USAT __cmsis_iar_usat_not_active
-    #define __RBIT __cmsis_iar_rbit_not_active
-    #define __get_APSR  __cmsis_iar_get_APSR_not_active
-  #endif
-
-
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
-    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
-    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
-  #endif
-
-  #ifdef __INTRINSICS_INCLUDED
-  #error intrinsics.h is already included previously!
-  #endif
-
-  #include <intrinsics.h>
-
-  #if __IAR_M0_FAMILY
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
-    #undef __CLZ
-    #undef __SSAT
-    #undef __USAT
-    #undef __RBIT
-    #undef __get_APSR
-
-    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
-    {
-      if (data == 0U) { return 32U; }
-
-      uint32_t count = 0U;
-      uint32_t mask = 0x80000000U;
-
-      while ((data & mask) == 0U)
-      {
-        count += 1U;
-        mask = mask >> 1U;
-      }
-      return count;
-    }
-
-    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
-    {
-      uint8_t sc = 31U;
-      uint32_t r = v;
-      for (v >>= 1U; v; v >>= 1U)
-      {
-        r <<= 1U;
-        r |= v & 1U;
-        sc--;
-      }
-      return (r << sc);
-    }
-
-    __STATIC_INLINE  uint32_t __get_APSR(void)
-    {
-      uint32_t res;
-      __asm("MRS      %0,APSR" : "=r" (res));
-      return res;
-    }
-
-  #endif
-
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
-    #undef __get_FPSCR
-    #undef __set_FPSCR
-    #define __get_FPSCR()       (0)
-    #define __set_FPSCR(VALUE)  ((void)VALUE)
-  #endif
-
-  #pragma diag_suppress=Pe940
-  #pragma diag_suppress=Pe177
-
-  #define __enable_irq    __enable_interrupt
-  #define __disable_irq   __disable_interrupt
-  #define __NOP           __no_operation
-
-  #define __get_xPSR      __get_PSR
-
-  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
-
-    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
-    {
-      return __LDREX((unsigned long *)ptr);
-    }
-
-    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
-    {
-      return __STREX(value, (unsigned long *)ptr);
-    }
-  #endif
-
-
-  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
-  #if (__CORTEX_M >= 0x03)
-
-    __IAR_FT uint32_t __RRX(uint32_t value)
-    {
-      uint32_t result;
-      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
-      return(result);
-    }
-
-    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
-    {
-      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
-    }
-
-
-    #define __enable_fault_irq  __enable_fiq
-    #define __disable_fault_irq __disable_fiq
-
-
-  #endif /* (__CORTEX_M >= 0x03) */
-
-  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
-  {
-    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
-  }
-
-  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-   __IAR_FT uint32_t __get_MSPLIM(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure MSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __set_MSPLIM(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure MSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t __get_PSPLIM(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __set_PSPLIM(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
-    {
-      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
-      return res;
-    }
-    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
-    {
-      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
-    {
-      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
-    {
-      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
-    {
-      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
-    }
-
-  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
-#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
-
-#if __IAR_M0_FAMILY
-  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
-  {
-    if ((sat >= 1U) && (sat <= 32U))
-    {
-      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-      const int32_t min = -1 - max ;
-      if (val > max)
-      {
-        return max;
-      }
-      else if (val < min)
-      {
-        return min;
-      }
-    }
-    return val;
-  }
-
-  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
-  {
-    if (sat <= 31U)
-    {
-      const uint32_t max = ((1U << sat) - 1U);
-      if (val > (int32_t)max)
-      {
-        return max;
-      }
-      else if (val < 0)
-      {
-        return 0U;
-      }
-    }
-    return (uint32_t)val;
-  }
-#endif
-
-#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
-
-  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return res;
-  }
-
-  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
-  {
-    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
-  }
-
-  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
-  {
-    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
-  }
-
-  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
-  {
-    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
-  }
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-
-  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return res;
-  }
-
-  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
-  {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
-  {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
-  {
-    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#undef __IAR_FT
-#undef __IAR_M0_FAMILY
-#undef __ICCARM_V8
-
-#pragma diag_default=Pe940
-#pragma diag_default=Pe177
-
-#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
-
-#endif /* __CMSIS_ICCARM_H__ */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/cmsis_version.h

@@ -1,39 +0,0 @@
-/******************************************************************************
- * @file     cmsis_version.h
- * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.4
- * @date     23. July 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CMSIS_VERSION_H
-#define __CMSIS_VERSION_H
-
-/*  CMSIS Version definitions */
-#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
-#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/core_cm4.h

@@ -1,2129 +0,0 @@
-/**************************************************************************
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.1.1
- * @date     27. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_FP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000U
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT             1U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RESERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[32U];
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
-#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
-#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    __COMPILER_BARRIER();
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __COMPILER_BARRIER();
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/mpu_armv7.h

@@ -1,275 +0,0 @@
-/******************************************************************************
- * @file     mpu_armv7.h
- * @brief    CMSIS MPU API for Armv7-M MPU
- * @version  V5.1.1
- * @date     10. February 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV7_H
-#define ARM_MPU_ARMV7_H
-
-#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
-#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
-#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
-#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
-#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
-#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
-#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
-#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
-#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
-#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
-#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
-#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
-#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
-#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
-#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
-#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
-#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
-#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
-#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
-#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
-#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
-#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
-#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
-#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
-#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
-#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
-#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
-#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
-
-#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
-#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
-#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
-#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
-#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
-#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
-
-/** MPU Region Base Address Register Value
-*
-* \param Region The region to be configured, number 0 to 15.
-* \param BaseAddress The base address for the region.
-*/
-#define ARM_MPU_RBAR(Region, BaseAddress) \
-  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
-   ((Region) & MPU_RBAR_REGION_Msk)    |  \
-   (MPU_RBAR_VALID_Msk))
-
-/**
-* MPU Memory Access Attributes
-*
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/
-#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
-  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
-   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
-   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
-   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
-
-/**
-* MPU Region Attribute and Size Register Value
-*
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
-  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
-   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
-   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
-   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
-   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
-   (((MPU_RASR_ENABLE_Msk))))
-
-/**
-* MPU Region Attribute and Size Register Value
-*
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
-  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
-
-/**
-* MPU Memory Access Attribute for strongly ordered memory.
-*  - TEX: 000b
-*  - Shareable
-*  - Non-cacheable
-*  - Non-bufferable
-*/
-#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
-
-/**
-* MPU Memory Access Attribute for device memory.
-*  - TEX: 000b (if shareable) or 010b (if non-shareable)
-*  - Shareable or non-shareable
-*  - Non-cacheable
-*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
-*
-* \param IsShareable Configures the device memory as shareable or non-shareable.
-*/
-#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
-
-/**
-* MPU Memory Access Attribute for normal memory.
-*  - TEX: 1BBb (reflecting outer cacheability rules)
-*  - Shareable or non-shareable
-*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
-*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
-*
-* \param OuterCp Configures the outer cache policy.
-* \param InnerCp Configures the inner cache policy.
-* \param IsShareable Configures the memory as shareable or non-shareable.
-*/
-#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
-
-/**
-* MPU Memory Access Attribute non-cacheable policy.
-*/
-#define ARM_MPU_CACHEP_NOCACHE 0U
-
-/**
-* MPU Memory Access Attribute write-back, write and read allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_WRA 1U
-
-/**
-* MPU Memory Access Attribute write-through, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WT_NWA 2U
-
-/**
-* MPU Memory Access Attribute write-back, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_NWA 3U
-
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR; //!< The region base address register value (RBAR)
-  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
-} ARM_MPU_Region_t;
-
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  __DMB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  __DSB();
-  __ISB();
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DMB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-  __DSB();
-  __ISB();
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  MPU->RNR = rnr;
-  MPU->RASR = 0U;
-}
-
-/** Configure an MPU region.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
-{
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
-{
-  MPU->RNR = rnr;
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i)
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  while (cnt > MPU_TYPE_RALIASES) {
-    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
-    table += MPU_TYPE_RALIASES;
-    cnt -= MPU_TYPE_RALIASES;
-  }
-  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
-}
-
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/mpu_armv8.h

@@ -1,352 +0,0 @@
-/******************************************************************************
- * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
- * @version  V5.1.2
- * @date     10. February 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV8_H
-#define ARM_MPU_ARMV8_H
-
-/** \brief Attribute for device memory (outer only) */
-#define ARM_MPU_ATTR_DEVICE                           ( 0U )
-
-/** \brief Attribute for non-cacheable, normal memory */
-#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
-
-/** \brief Attribute for normal memory (outer and inner)
-* \param NT Non-Transient: Set to 1 for non-transient data.
-* \param WB Write-Back: Set to 1 to use write-back update policy.
-* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
-* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
-*/
-#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
-  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
-
-/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
-
-/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
-
-/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
-
-/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
-
-/** \brief Memory Attribute
-* \param O Outer memory attributes
-* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
-*/
-#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
-
-/** \brief Normal memory non-shareable  */
-#define ARM_MPU_SH_NON   (0U)
-
-/** \brief Normal memory outer shareable  */
-#define ARM_MPU_SH_OUTER (2U)
-
-/** \brief Normal memory inner shareable  */
-#define ARM_MPU_SH_INNER (3U)
-
-/** \brief Memory access permissions
-* \param RO Read-Only: Set to 1 for read-only memory.
-* \param NP Non-Privileged: Set to 1 for non-privileged memory.
-*/
-#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
-
-/** \brief Region Base Address Register value
-* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
-* \param SH Defines the Shareability domain for this memory region.
-* \param RO Read-Only: Set to 1 for a read-only memory region.
-* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
-* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
-*/
-#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  (((BASE) & MPU_RBAR_BASE_Msk) | \
-  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
-  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
-  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
-
-/** \brief Region Limit Address Register value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR(LIMIT, IDX) \
-  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
-  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
-  (MPU_RLAR_EN_Msk))
-
-#if defined(MPU_RLAR_PXN_Pos)
-
-/** \brief Region Limit Address Register with PXN value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
-  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
-  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
-  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
-  (MPU_RLAR_EN_Msk))
-
-#endif
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR;                   /*!< Region Base Address Register value */
-  uint32_t RLAR;                   /*!< Region Limit Address Register value */
-} ARM_MPU_Region_t;
-
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  __DMB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  __DSB();
-  __ISB();
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DMB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-  __DSB();
-  __ISB();
-}
-
-#ifdef MPU_NS
-/** Enable the Non-secure MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
-{
-  __DMB();
-  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  __DSB();
-  __ISB();
-}
-
-/** Disable the Non-secure MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable_NS(void)
-{
-  __DMB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-  __DSB();
-  __ISB();
-}
-#endif
-
-/** Set the memory attribute encoding to the given MPU.
-* \param mpu Pointer to the MPU to be configured.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
-{
-  const uint8_t reg = idx / 4U;
-  const uint32_t pos = ((idx % 4U) * 8U);
-  const uint32_t mask = 0xFFU << pos;
-
-  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
-    return; // invalid index
-  }
-
-  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
-}
-
-/** Set the memory attribute encoding.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
-}
-
-#ifdef MPU_NS
-/** Set the memory attribute encoding to the Non-secure MPU.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
-}
-#endif
-
-/** Clear and disable the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
-{
-  mpu->RNR = rnr;
-  mpu->RLAR = 0U;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  ARM_MPU_ClrRegionEx(MPU, rnr);
-}
-
-#ifdef MPU_NS
-/** Clear and disable the given Non-secure MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{
-  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
-}
-#endif
-
-/** Configure the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  mpu->RNR = rnr;
-  mpu->RBAR = rbar;
-  mpu->RLAR = rlar;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
-}
-
-#ifdef MPU_NS
-/** Configure the given Non-secure MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
-}
-#endif
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i)
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table to the given MPU.
-* \param mpu Pointer to the MPU registers to be used.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  if (cnt == 1U) {
-    mpu->RNR = rnr;
-    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
-  } else {
-    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
-    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-
-    mpu->RNR = rnrBase;
-    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
-      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
-      table += c;
-      cnt -= c;
-      rnrOffset = 0U;
-      rnrBase += MPU_TYPE_RALIASES;
-      mpu->RNR = rnrBase;
-    }
-
-    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
-  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
-}
-
-#ifdef MPU_NS
-/** Load the given number of MPU regions from a table to the Non-secure MPU.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
-  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
-}
-#endif
-
-#endif
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/core_support/pmu_armv8.h

@@ -1,337 +0,0 @@
-/******************************************************************************
- * @file     pmu_armv8.h
- * @brief    CMSIS PMU API for Armv8.1-M PMU
- * @version  V1.0.0
- * @date     24. March 2020
- ******************************************************************************/
-/*
- * Copyright (c) 2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
-
-#ifndef ARM_PMU_ARMV8_H
-#define ARM_PMU_ARMV8_H
-
-/**
- * \brief PMU Events
- * \note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
- * */
-
-#define ARM_PMU_SW_INCR                              0x0000             /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
-#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< L1 I-Cache refill */
-#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< L1 D-Cache refill */
-#define ARM_PMU_L1D_CACHE                            0x0004             /*!< L1 D-Cache access */
-#define ARM_PMU_LD_RETIRED                           0x0006             /*!< Memory-reading instruction architecturally executed and condition code check pass */
-#define ARM_PMU_ST_RETIRED                           0x0007             /*!< Memory-writing instruction architecturally executed and condition code check pass */
-#define ARM_PMU_INST_RETIRED                         0x0008             /*!< Instruction architecturally executed */
-#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< Exception entry */
-#define ARM_PMU_EXC_RETURN                           0x000A             /*!< Exception return instruction architecturally executed and the condition code check pass */
-#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
-#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< Immediate branch architecturally executed */
-#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< Function return instruction architecturally executed and the condition code check pass */
-#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
-#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< Mispredicted or not predicted branch speculatively executed */
-#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< Cycle */
-#define ARM_PMU_BR_PRED                              0x0012             /*!< Predictable branch speculatively executed */
-#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< Data memory access */
-#define ARM_PMU_L1I_CACHE                            0x0014             /*!< Level 1 instruction cache access */
-#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< Level 1 data cache write-back */
-#define ARM_PMU_L2D_CACHE                            0x0016             /*!< Level 2 data cache access */
-#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< Level 2 data cache refill */
-#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< Level 2 data cache write-back */
-#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< Bus access */
-#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< Local memory error */
-#define ARM_PMU_INST_SPEC                            0x001B             /*!< Instruction speculatively executed */
-#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< Bus cycles */
-#define ARM_PMU_CHAIN                                0x001E             /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
-#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< Level 1 data cache allocation without refill */
-#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< Level 2 data cache allocation without refill */
-#define ARM_PMU_BR_RETIRED                           0x0021             /*!< Branch instruction architecturally executed */
-#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< Mispredicted branch instruction architecturally executed */
-#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< No operation issued because of the frontend */
-#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< No operation issued because of the backend */
-#define ARM_PMU_L2I_CACHE                            0x0027             /*!< Level 2 instruction cache access */
-#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< Level 2 instruction cache refill */
-#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< Level 3 data cache allocation without refill */
-#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< Level 3 data cache refill */
-#define ARM_PMU_L3D_CACHE                            0x002B             /*!< Level 3 data cache access */
-#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< Level 3 data cache write-back */
-#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< Last level data cache read */
-#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< Last level data cache read miss */
-#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< Level 1 data cache read miss */
-#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< Operation retired */
-#define ARM_PMU_OP_SPEC                              0x003B             /*!< Operation speculatively executed */
-#define ARM_PMU_STALL                                0x003C             /*!< Stall cycle for instruction or operation not sent for execution */
-#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
-#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
-#define ARM_PMU_STALL_OP                             0x003F             /*!< Instruction or operation slots not occupied each cycle */
-#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< Level 1 data cache read */
-#define ARM_PMU_LE_RETIRED                           0x0100             /*!< Loop end instruction executed */
-#define ARM_PMU_LE_SPEC                              0x0101             /*!< Loop end instruction speculatively executed */
-#define ARM_PMU_BF_RETIRED                           0x0104             /*!< Branch future instruction architecturally executed and condition code check pass */
-#define ARM_PMU_BF_SPEC                              0x0105             /*!< Branch future instruction speculatively executed and condition code check pass */
-#define ARM_PMU_LE_CANCEL                            0x0108             /*!< Loop end instruction not taken */
-#define ARM_PMU_BF_CANCEL                            0x0109             /*!< Branch future instruction not taken */
-#define ARM_PMU_SE_CALL_S                            0x0114             /*!< Call to secure function, resulting in Security state change */
-#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< Call to non-secure function, resulting in Security state change */
-#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< DWT comparator 0 match */
-#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< DWT comparator 1 match */
-#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< DWT comparator 2 match */
-#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< DWT comparator 3 match */
-#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< MVE instruction architecturally executed */
-#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< MVE instruction speculatively executed */
-#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< MVE floating-point instruction architecturally executed */
-#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< MVE floating-point instruction speculatively executed */
-#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< MVE half-precision floating-point instruction architecturally executed */
-#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< MVE half-precision floating-point instruction speculatively executed */
-#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< MVE single-precision floating-point instruction architecturally executed */
-#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< MVE single-precision floating-point instruction speculatively executed */
-#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
-#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
-#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< MVE integer instruction architecturally executed */
-#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< MVE integer instruction speculatively executed */
-#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
-#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
-#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< MVE load or store instruction architecturally executed */
-#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< MVE load or store instruction speculatively executed */
-#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< MVE load instruction architecturally executed */
-#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< MVE load instruction speculatively executed */
-#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< MVE store instruction architecturally executed */
-#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< MVE store instruction speculatively executed */
-#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< MVE contiguous load or store instruction architecturally executed */
-#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< MVE contiguous load or store instruction speculatively executed */
-#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< MVE contiguous load instruction architecturally executed */
-#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< MVE contiguous load instruction speculatively executed */
-#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< MVE contiguous store instruction architecturally executed */
-#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< MVE contiguous store instruction speculatively executed */
-#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< MVE non-contiguous load or store instruction architecturally executed */
-#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< MVE non-contiguous load or store instruction speculatively executed */
-#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< MVE non-contiguous load instruction architecturally executed */
-#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< MVE non-contiguous load instruction speculatively executed */
-#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< MVE non-contiguous store instruction architecturally executed */
-#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< MVE non-contiguous store instruction speculatively executed */
-#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< MVE memory instruction targeting multiple registers architecturally executed */
-#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< MVE memory instruction targeting multiple registers speculatively executed */
-#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< MVE memory load instruction targeting multiple registers architecturally executed */
-#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< MVE memory load instruction targeting multiple registers speculatively executed */
-#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< MVE memory store instruction targeting multiple registers architecturally executed */
-#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< MVE memory store instruction targeting multiple registers speculatively executed */
-#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< MVE unaligned memory load or store instruction architecturally executed */
-#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< MVE unaligned memory load or store instruction speculatively executed */
-#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< MVE unaligned load instruction architecturally executed */
-#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< MVE unaligned load instruction speculatively executed */
-#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< MVE unaligned store instruction architecturally executed */
-#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< MVE unaligned store instruction speculatively executed */
-#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
-#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
-#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< MVE vector reduction instruction architecturally executed */
-#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< MVE vector reduction instruction speculatively executed */
-#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< MVE floating-point vector reduction instruction architecturally executed */
-#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< MVE floating-point vector reduction instruction speculatively executed */
-#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< MVE integer vector reduction instruction architecturally executed */
-#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< MVE integer vector reduction instruction speculatively executed */
-#define ARM_PMU_MVE_PRED                             0x02B8             /*!< Cycles where one or more predicated beats architecturally executed */
-#define ARM_PMU_MVE_STALL                            0x02CC             /*!< Stall cycles caused by an MVE instruction */
-#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
-#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
-#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
-#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
-#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< Stall cycles caused by an MVE chain break */
-#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< Stall cycles caused by MVE register dependency */
-#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< Instruction TCM access */
-#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< Data TCM access */
-#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< ETM external output 0 */
-#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< ETM external output 1 */
-#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< ETM external output 2 */
-#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< ETM external output 3 */
-#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< Cross-trigger Interface output trigger 4 */
-#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< Cross-trigger Interface output trigger 5 */
-#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< Cross-trigger Interface output trigger 6 */
-#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< Cross-trigger Interface output trigger 7 */
-
-/** \brief PMU Functions */
-
-__STATIC_INLINE void ARM_PMU_Enable(void);
-__STATIC_INLINE void ARM_PMU_Disable(void);
-
-__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
-
-__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
-__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
-
-__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
-__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
-
-__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
-__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
-
-__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
-__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
-
-__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
-__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
-
-__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
-
-/**
-  \brief   Enable the PMU
-*/
-__STATIC_INLINE void ARM_PMU_Enable(void)
-{
-  PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
-}
-
-/**
-  \brief   Disable the PMU
-*/
-__STATIC_INLINE void ARM_PMU_Disable(void)
-{
-  PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
-}
-
-/**
-  \brief   Set event to count for PMU eventer counter
-  \param [in]    num     Event counter (0-30) to configure
-  \param [in]    type    Event to count
-*/
-__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
-{
-  PMU->EVTYPER[num] = type;
-}
-
-/**
-  \brief  Reset cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
-{
-  PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
-}
-
-/**
-  \brief  Reset all event counters
-*/
-__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
-{
-  PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
-}
-
-/**
-  \brief  Enable counters
-  \param [in]     mask    Counters to enable
-  \note   Enables one or more of the following:
-          - event counters (0-30)
-          - cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
-{
-  PMU->CNTENSET = mask;
-}
-
-/**
-  \brief  Disable counters
-  \param [in]     mask    Counters to enable
-  \note   Disables one or more of the following:
-          - event counters (0-30)
-          - cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
-{
-  PMU->CNTENCLR = mask;
-}
-
-/**
-  \brief  Read cycle counter
-  \return                 Cycle count
-*/
-__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
-{
-  return PMU->CCNTR;
-}
-
-/**
-  \brief   Read event counter
-  \param [in]     num     Event counter (0-30) to read
-  \return                 Event count
-*/
-__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
-{
-  return PMU->EVCNTR[num];
-}
-
-/**
-  \brief   Read counter overflow status
-  \return  Counter overflow status bits for the following:
-          - event counters (0-30)
-          - cycle counter
-*/
-__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
-{
-  return PMU->OVSSET;
-}
-
-/**
-  \brief   Clear counter overflow status
-  \param [in]     mask    Counter overflow status bits to clear
-  \note    Clears overflow status bits for one or more of the following:
-           - event counters (0-30)
-           - cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
-{
-  PMU->OVSCLR = mask;
-}
-
-/**
-  \brief   Enable counter overflow interrupt request
-  \param [in]     mask    Counter overflow interrupt request bits to set
-  \note    Sets overflow interrupt request bits for one or more of the following:
-           - event counters (0-30)
-           - cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
-{
-  PMU->INTENSET = mask;
-}
-
-/**
-  \brief   Disable counter overflow interrupt request
-  \param [in]     mask    Counter overflow interrupt request bits to clear
-  \note    Clears overflow interrupt request bits for one or more of the following:
-           - event counters (0-30)
-           - cycle counter
-*/
-__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
-{
-  PMU->INTENCLR = mask;
-}
-
-/**
-  \brief   Software increment event counter
-  \param [in]     mask    Counters to increment
-  \note    Software increment bits for one or more event counters (0-30)
-*/
-__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
-{
-  PMU->SWINC = mask;
-}
-
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/at32f403a_407.h

@@ -1,576 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-#ifndef __AT32F403A_407_H
-#define __AT32F403A_407_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined (__CC_ARM)
- #pragma anon_unions
-#endif
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup AT32F403A_407
-  * @{
-  */
-
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * tip: to avoid modifying this file each time you need to switch between these
-  *      devices, you can define the device in your toolchain compiler preprocessor.
-  */
-
-#if !defined (AT32F403AVCT7) && !defined (AT32F403ARCT7) && !defined (AT32F403ACCT7) && \
-    !defined (AT32F403ACCU7) && !defined (AT32F403AVGT7) && !defined (AT32F403ACGT7) && \
-    !defined (AT32F403ARGT7) && !defined (AT32F403ACGU7) && !defined (AT32F403AVET7) && \
-    !defined (AT32F403ARET7) && !defined (AT32F403ACET7) && !defined (AT32F403ACEU7) && \
-    !defined (AT32F407RGT7)  && !defined (AT32F407VGT7)  && !defined (AT32F407RCT7)  && \
-    !defined (AT32F407VCT7)  && !defined (AT32F407RET7)  && !defined (AT32F407VET7)  && \
-    !defined (AT32F407AVCT7) && !defined (AT32F407AVGT7)
-
-    #error "Please select first the target device used in your application (in at32f403a_407.h file)"
-#endif
-
-#if defined (AT32F403AVCT7) || defined (AT32F403ARCT7) || defined (AT32F403ACCT7) || \
-    defined (AT32F403ACCU7) || defined (AT32F403AVGT7) || defined (AT32F403ACGT7) || \
-    defined (AT32F403ARGT7) || defined (AT32F403ACGU7) || defined (AT32F403AVET7) || \
-    defined (AT32F403ACET7) || defined (AT32F403ARET7) || defined (AT32F403ACEU7)
-
-    #define AT32F403Axx
-#endif
-
-#if defined (AT32F407RGT7)  || defined (AT32F407VGT7)  || defined (AT32F407RCT7)  || \
-    defined (AT32F407VCT7)  || defined (AT32F407VET7)  || defined (AT32F407RET7)  || \
-    defined (AT32F407AVCT7) || defined (AT32F407AVGT7)
-
-    #define AT32F407xx
-#endif
-
-#ifndef USE_STDPERIPH_DRIVER
-/**
-  * @brief comment the line below if you will not use the peripherals drivers.
-  * in this case, these drivers will not be included and the application code will
-  * be based on direct access to peripherals registers
-  */
-  #ifdef _RTE_
-    #include "RTE_Components.h"
-    #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
-      #define USE_STDPERIPH_DRIVER
-    #endif
-  #endif
-#endif
-
-/**
-  * @brief at32f403a_407 standard peripheral library version number
-  */
-#define __AT32F403A_407_LIBRARY_VERSION_MAJOR    (0x02) /*!< [31:24] major version */
-#define __AT32F403A_407_LIBRARY_VERSION_MIDDLE   (0x00) /*!< [23:16] middle version */
-#define __AT32F403A_407_LIBRARY_VERSION_MINOR    (0x07) /*!< [15:8]  minor version */
-#define __AT32F403A_407_LIBRARY_VERSION_RC       (0x00) /*!< [7:0]  release candidate */
-#define __AT32F403A_407_LIBRARY_VERSION          ((__AT32F403A_407_LIBRARY_VERSION_MAJOR << 24)  | \
-                                                  (__AT32F403A_407_LIBRARY_VERSION_MIDDLE << 16) | \
-                                                  (__AT32F403A_407_LIBRARY_VERSION_MINOR << 8)   | \
-                                                  (__AT32F403A_407_LIBRARY_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief configuration of the cortex-m4 processor and core peripherals
-  */
-#define __CM4_REV                 0x0001U  /*!< core revision r0p1                           */
-#define __MPU_PRESENT             1        /*!< mpu present                                  */
-#define __NVIC_PRIO_BITS          4        /*!< at32 uses 4 bits for the priority levels     */
-#define __Vendor_SysTickConfig    0        /*!< set to 1 if different systick config is used */
-#define __FPU_PRESENT             1U       /*!< fpu present                                  */
-
-/**
-  * @brief at32f403a_407 interrupt number definition, according to the selected device
-  *        in @ref Library_configuration_section
-  */
-typedef enum IRQn
-{
-    /******  cortex-m4 processor exceptions numbers ***************************************************/
-    Reset_IRQn                  = -15,    /*!< 1 reset vector, invoked on power up and warm reset   */
-    NonMaskableInt_IRQn         = -14,    /*!< 2 non maskable interrupt                             */
-    HardFault_IRQn              = -13,    /*!< 3 hard fault, all classes of fault                   */
-    MemoryManagement_IRQn       = -12,    /*!< 4 cortex-m4 memory management interrupt              */
-    BusFault_IRQn               = -11,    /*!< 5 cortex-m4 bus fault interrupt                      */
-    UsageFault_IRQn             = -10,    /*!< 6 cortex-m4 usage fault interrupt                    */
-    SVCall_IRQn                 = -5,     /*!< 11 cortex-m4 sv call interrupt                       */
-    DebugMonitor_IRQn           = -4,     /*!< 12 cortex-m4 debug monitor interrupt                 */
-    PendSV_IRQn                 = -2,     /*!< 14 cortex-m4 pend sv interrupt                       */
-    SysTick_IRQn                = -1,     /*!< 15 cortex-m4 system tick interrupt                   */
-
-    /******  at32 specific interrupt numbers *********************************************************/
-    WWDT_IRQn                   = 0,      /*!< window watchdog timer interrupt                      */
-    PVM_IRQn                    = 1,      /*!< pvm through exint line detection interrupt           */
-    TAMPER_IRQn                 = 2,      /*!< tamper interrupt                                     */
-    RTC_IRQn                    = 3,      /*!< rtc global interrupt                                 */
-    FLASH_IRQn                  = 4,      /*!< flash global interrupt                               */
-    CRM_IRQn                    = 5,      /*!< crm global interrupt                                 */
-    EXINT0_IRQn                 = 6,      /*!< external line0 interrupt                             */
-    EXINT1_IRQn                 = 7,      /*!< external line1 interrupt                             */
-    EXINT2_IRQn                 = 8,      /*!< external line2 interrupt                             */
-    EXINT3_IRQn                 = 9,      /*!< external line3 interrupt                             */
-    EXINT4_IRQn                 = 10,     /*!< external line4 interrupt                             */
-    DMA1_Channel1_IRQn          = 11,     /*!< dma1 channel 1 global interrupt                      */
-    DMA1_Channel2_IRQn          = 12,     /*!< dma1 channel 2 global interrupt                      */
-    DMA1_Channel3_IRQn          = 13,     /*!< dma1 channel 3 global interrupt                      */
-    DMA1_Channel4_IRQn          = 14,     /*!< dma1 channel 4 global interrupt                      */
-    DMA1_Channel5_IRQn          = 15,     /*!< dma1 channel 5 global interrupt                      */
-    DMA1_Channel6_IRQn          = 16,     /*!< dma1 channel 6 global interrupt                      */
-    DMA1_Channel7_IRQn          = 17,     /*!< dma1 channel 7 global interrupt                      */
-
-#if defined (AT32F403Axx)
-    ADC1_2_IRQn                 = 18,     /*!< adc1 and adc2 global interrupt                       */
-    USBFS_H_CAN1_TX_IRQn        = 19,     /*!< usb device high priority or can1 tx interrupts       */
-    USBFS_L_CAN1_RX0_IRQn       = 20,     /*!< usb device low priority or can1 rx0 interrupts       */
-    CAN1_RX1_IRQn               = 21,     /*!< can1 rx1 interrupt                                   */
-    CAN1_SE_IRQn                = 22,     /*!< can1 se interrupt                                    */
-    EXINT9_5_IRQn               = 23,     /*!< external line[9:5] interrupts                        */
-    TMR1_BRK_TMR9_IRQn          = 24,     /*!< tmr1 brake interrupt                                 */
-    TMR1_OVF_TMR10_IRQn         = 25,     /*!< tmr1 overflow interrupt                              */
-    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< tmr1 trigger and hall interrupt                      */
-    TMR1_CH_IRQn                = 27,     /*!< tmr1 channel interrupt                               */
-    TMR2_GLOBAL_IRQn            = 28,     /*!< tmr2 global interrupt                                */
-    TMR3_GLOBAL_IRQn            = 29,     /*!< tmr3 global interrupt                                */
-    TMR4_GLOBAL_IRQn            = 30,     /*!< tmr4 global interrupt                                */
-    I2C1_EVT_IRQn               = 31,     /*!< i2c1 event interrupt                                 */
-    I2C1_ERR_IRQn               = 32,     /*!< i2c1 error interrupt                                 */
-    I2C2_EVT_IRQn               = 33,     /*!< i2c2 event interrupt                                 */
-    I2C2_ERR_IRQn               = 34,     /*!< i2c2 error interrupt                                 */
-    SPI1_IRQn                   = 35,     /*!< spi1 global interrupt                                */
-    SPI2_I2S2EXT_IRQn           = 36,     /*!< spi2 global interrupt                                */
-    USART1_IRQn                 = 37,     /*!< usart1 global interrupt                              */
-    USART2_IRQn                 = 38,     /*!< usart2 global interrupt                              */
-    USART3_IRQn                 = 39,     /*!< usart3 global interrupt                              */
-    EXINT15_10_IRQn             = 40,     /*!< external line[15:10] interrupts                      */
-    RTCAlarm_IRQn               = 41,     /*!< rtc alarm through exint line interrupt               */
-    USBFSWakeUp_IRQn            = 42,     /*!< usb device wakeup from suspend through exint line interrupt */
-    TMR8_BRK_TMR12_IRQn         = 43,     /*!< tmr8 brake interrupt                                 */
-    TMR8_OVF_TMR13_IRQn         = 44,     /*!< tmr8 overflow interrupt                              */
-    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< tmr8 trigger and hall interrupt                      */
-    TMR8_CH_IRQn                = 46,     /*!< tmr8 channel interrupt                               */
-    ADC3_IRQn                   = 47,     /*!< adc3 global interrupt                                */
-    XMC_IRQn                    = 48,     /*!< xmc global interrupt                                 */
-    SDIO1_IRQn                  = 49,     /*!< sdio1 global interrupt                               */
-    TMR5_GLOBAL_IRQn            = 50,     /*!< tmr5 global interrupt                                */
-    SPI3_I2S3EXT_IRQn           = 51,     /*!< spi3 global interrupt                                */
-    UART4_IRQn                  = 52,     /*!< uart4 global interrupt                               */
-    UART5_IRQn                  = 53,     /*!< uart5 global interrupt                               */
-    TMR6_GLOBAL_IRQn            = 54,     /*!< tmr6 global interrupt                                */
-    TMR7_GLOBAL_IRQn            = 55,     /*!< tmr7 global interrupt                                */
-    DMA2_Channel1_IRQn          = 56,     /*!< dma2 channel 1 global interrupt                      */
-    DMA2_Channel2_IRQn          = 57,     /*!< dma2 channel 2 global interrupt                      */
-    DMA2_Channel3_IRQn          = 58,     /*!< dma2 channel 3 global interrupt                      */
-    DMA2_Channel4_5_IRQn        = 59,     /*!< dma2 channel 4 and channel 5 global interrupt        */
-    SDIO2_IRQn                  = 60,     /*!< sdio2 global interrupt                               */
-    I2C3_EVT_IRQn               = 61,     /*!< i2c3 event interrupt                                 */
-    I2C3_ERR_IRQn               = 62,     /*!< i2c3 error interrupt                                 */
-    SPI4_IRQn                   = 63,     /*!< spi4 global interrupt                                */
-    CAN2_TX_IRQn                = 68,     /*!< can2 tx interrupt                                    */
-    CAN2_RX0_IRQn               = 69,     /*!< can2 rx0 interrupt                                   */
-    CAN2_RX1_IRQn               = 70,     /*!< can2 rx1 interrupt                                   */
-    CAN2_SE_IRQn                = 71,     /*!< can2 se interrupt                                    */
-    ACC_IRQn                    = 72,     /*!< acc interrupt                                        */
-    USBFS_MAPH_IRQn             = 73,     /*!< usb map hp interrupt                                 */
-    USBFS_MAPL_IRQn             = 74,     /*!< usb map lp interrupt                                 */
-    DMA2_Channel6_7_IRQn        = 75,     /*!< dma2 channel 6 and channel 7 global interrupt        */
-    USART6_IRQn                 = 76,     /*!< usart6 interrupt                                     */
-    UART7_IRQn                  = 77,     /*!< uart7 interrupt                                      */
-    UART8_IRQn                  = 78,     /*!< uart8 interrupt                                      */
-#endif
-
-#if defined (AT32F407xx)
-    ADC1_2_IRQn                 = 18,     /*!< adc1 and adc2 global interrupt                       */
-    USBFS_H_CAN1_TX_IRQn        = 19,     /*!< usb device high priority or can1 tx interrupts       */
-    USBFS_L_CAN1_RX0_IRQn       = 20,     /*!< usb device low priority or can1 rx0 interrupts       */
-    CAN1_RX1_IRQn               = 21,     /*!< can1 rx1 interrupt                                   */
-    CAN1_SE_IRQn                = 22,     /*!< can1 se interrupt                                    */
-    EXINT9_5_IRQn               = 23,     /*!< external line[9:5] interrupts                        */
-    TMR1_BRK_TMR9_IRQn          = 24,     /*!< tmr1 brake interrupt                                 */
-    TMR1_OVF_TMR10_IRQn         = 25,     /*!< tmr1 overflow interrupt                              */
-    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< tmr1 trigger and hall interrupt                      */
-    TMR1_CH_IRQn                = 27,     /*!< tmr1 channel interrupt                               */
-    TMR2_GLOBAL_IRQn            = 28,     /*!< tmr2 global interrupt                                */
-    TMR3_GLOBAL_IRQn            = 29,     /*!< tmr3 global interrupt                                */
-    TMR4_GLOBAL_IRQn            = 30,     /*!< tmr4 global interrupt                                */
-    I2C1_EVT_IRQn               = 31,     /*!< i2c1 event interrupt                                 */
-    I2C1_ERR_IRQn               = 32,     /*!< i2c1 error interrupt                                 */
-    I2C2_EVT_IRQn               = 33,     /*!< i2c2 event interrupt                                 */
-    I2C2_ERR_IRQn               = 34,     /*!< i2c2 error interrupt                                 */
-    SPI1_IRQn                   = 35,     /*!< spi1 global interrupt                                */
-    SPI2_I2S2EXT_IRQn           = 36,     /*!< spi2 global interrupt                                */
-    USART1_IRQn                 = 37,     /*!< usart1 global interrupt                              */
-    USART2_IRQn                 = 38,     /*!< usart2 global interrupt                              */
-    USART3_IRQn                 = 39,     /*!< usart3 global interrupt                              */
-    EXINT15_10_IRQn             = 40,     /*!< external line[15:10] interrupts                      */
-    RTCAlarm_IRQn               = 41,     /*!< rtc alarm through exint line interrupt               */
-    USBFSWakeUp_IRQn            = 42,     /*!< usb device wakeup from suspend through exint line interrupt */
-    TMR8_BRK_TMR12_IRQn         = 43,     /*!< tmr8 brake interrupt                                 */
-    TMR8_OVF_TMR13_IRQn         = 44,     /*!< tmr8 overflow interrupt                              */
-    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< tmr8 trigger and hall interrupt                      */
-    TMR8_CH_IRQn                = 46,     /*!< tmr8 channel interrupt                               */
-    ADC3_IRQn                   = 47,     /*!< adc3 global interrupt                                */
-    XMC_IRQn                    = 48,     /*!< xmc global interrupt                                 */
-    SDIO1_IRQn                  = 49,     /*!< sdio1 global interrupt                               */
-    TMR5_GLOBAL_IRQn            = 50,     /*!< tmr5 global interrupt                                */
-    SPI3_I2S3EXT_IRQn           = 51,     /*!< spi3 global interrupt                                */
-    UART4_IRQn                  = 52,     /*!< uart4 global interrupt                               */
-    UART5_IRQn                  = 53,     /*!< uart5 global interrupt                               */
-    TMR6_GLOBAL_IRQn            = 54,     /*!< tmr6 global interrupt                                */
-    TMR7_GLOBAL_IRQn            = 55,     /*!< tmr7 global interrupt                                */
-    DMA2_Channel1_IRQn          = 56,     /*!< dma2 channel 1 global interrupt                      */
-    DMA2_Channel2_IRQn          = 57,     /*!< dma2 channel 2 global interrupt                      */
-    DMA2_Channel3_IRQn          = 58,     /*!< dma2 channel 3 global interrupt                      */
-    DMA2_Channel4_5_IRQn        = 59,     /*!< dma2 channel 4 and channel 5 global interrupt        */
-    SDIO2_IRQn                  = 60,     /*!< sdio2 global interrupt                               */
-    I2C3_EVT_IRQn               = 61,     /*!< i2c3 event interrupt                                 */
-    I2C3_ERR_IRQn               = 62,     /*!< i2c3 error interrupt                                 */
-    SPI4_IRQn                   = 63,     /*!< spi4 global interrupt                                */
-    CAN2_TX_IRQn                = 68,     /*!< can2 tx interrupt                                    */
-    CAN2_RX0_IRQn               = 69,     /*!< can2 rx0 interrupt                                   */
-    CAN2_RX1_IRQn               = 70,     /*!< can2 rx1 interrupt                                   */
-    CAN2_SE_IRQn                = 71,     /*!< can2 se interrupt                                    */
-    ACC_IRQn                    = 72,     /*!< acc interrupt                                        */
-    USBFS_MAPH_IRQn             = 73,     /*!< usb map hp interrupt                                 */
-    USBFS_MAPL_IRQn             = 74,     /*!< usb map lp interrupt                                 */
-    DMA2_Channel6_7_IRQn        = 75,     /*!< dma2 channel 6 and channel 7 global interrupt        */
-    USART6_IRQn                 = 76,     /*!< usart6 interrupt                                     */
-    UART7_IRQn                  = 77,     /*!< uart7 interrupt                                      */
-    UART8_IRQn                  = 78,     /*!< uart8 interrupt                                      */
-    EMAC_IRQn                   = 79,     /*!< emac interrupt                                       */
-    EMAC_WKUP_IRQn              = 80,     /*!< emac wakeup interrupt                                */
-#endif
-
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"
-#include "system_at32f403a_407.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */
-
-typedef int32_t  INT32;
-typedef int16_t  INT16;
-typedef int8_t   INT8;
-typedef uint32_t UINT32;
-typedef uint16_t UINT16;
-typedef uint8_t  UINT8;
-
-typedef int32_t  s32;
-typedef int16_t  s16;
-typedef int8_t   s8;
-
-typedef const int32_t sc32;   /*!< read only */
-typedef const int16_t sc16;   /*!< read only */
-typedef const int8_t  sc8;    /*!< read only */
-
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef __I int32_t vsc32;    /*!< read only */
-typedef __I int16_t vsc16;    /*!< read only */
-typedef __I int8_t  vsc8;     /*!< read only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef const uint32_t uc32;  /*!< read only */
-typedef const uint16_t uc16;  /*!< read only */
-typedef const uint8_t  uc8;   /*!< read only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef __I uint32_t vuc32;   /*!< read only */
-typedef __I uint16_t vuc16;   /*!< read only */
-typedef __I uint8_t  vuc8;    /*!< read only */
-
-/**
-  * @brief flag status
-  */
-typedef enum {RESET = 0, SET = !RESET} flag_status;
-
-/**
-  * @brief confirm state
-  */
-typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
-
-/**
-  * @brief error status
-  */
-typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-
-#define REG8(addr)                       *(volatile uint8_t *)(addr)
-#define REG16(addr)                      *(volatile uint16_t *)(addr)
-#define REG32(addr)                      *(volatile uint32_t *)(addr)
-
-#define MAKE_VALUE(reg_offset, bit_num)  (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
-
-#define PERIPH_REG(periph_base, value)   REG32((periph_base + (value >> 16)))
-#define PERIPH_REG_BIT(value)            (0x1U << (value & 0x1F))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE                       ((uint32_t)0x08000000)
-#define SPIM_FLASH_BASE                  ((uint32_t)0x08400000)
-#define USD_BASE                         ((uint32_t)0x1FFFF800)
-#define SRAM_BASE                        ((uint32_t)0x20000000)
-#define PERIPH_BASE                      ((uint32_t)0x40000000)
-#define XMC_REG_BASE                     ((uint32_t)0xA0000000)
-#define DEBUG_BASE                       ((uint32_t)0xE0042000)
-
-#define APB1PERIPH_BASE                  (PERIPH_BASE + 0x00000)
-#define APB2PERIPH_BASE                  (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE                   (PERIPH_BASE + 0x20000)
-
-#if defined (AT32F403Axx)
-/* apb1 bus base address */
-#define TMR2_BASE                        (APB1PERIPH_BASE + 0x0000)
-#define TMR3_BASE                        (APB1PERIPH_BASE + 0x0400)
-#define TMR4_BASE                        (APB1PERIPH_BASE + 0x0800)
-#define TMR5_BASE                        (APB1PERIPH_BASE + 0x0C00)
-#define TMR6_BASE                        (APB1PERIPH_BASE + 0x1000)
-#define TMR7_BASE                        (APB1PERIPH_BASE + 0x1400)
-#define TMR12_BASE                       (APB1PERIPH_BASE + 0x1800)
-#define TMR13_BASE                       (APB1PERIPH_BASE + 0x1C00)
-#define TMR14_BASE                       (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE                         (APB1PERIPH_BASE + 0x2800)
-#define WWDT_BASE                        (APB1PERIPH_BASE + 0x2C00)
-#define WDT_BASE                         (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE                        (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE                        (APB1PERIPH_BASE + 0x3C00)
-#define SPI4_BASE                        (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE                      (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE                      (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE                       (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE                       (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE                        (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE                        (APB1PERIPH_BASE + 0x5800)
-#define USBFS_BASE                       (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE                        (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE                        (APB1PERIPH_BASE + 0x6800)
-#define BPR_BASE                         (APB1PERIPH_BASE + 0x6C00)
-#define PWC_BASE                         (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE                         (APB1PERIPH_BASE + 0x7400)
-/* apb2 bus base address */
-#define IOMUX_BASE                       (APB2PERIPH_BASE + 0x0000)
-#define EXINT_BASE                       (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE                       (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE                       (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE                       (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE                       (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE                       (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE                        (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE                        (APB2PERIPH_BASE + 0x2800)
-#define TMR1_BASE                        (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE                        (APB2PERIPH_BASE + 0x3000)
-#define TMR8_BASE                        (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE                      (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE                        (APB2PERIPH_BASE + 0x3C00)
-#define TMR9_BASE                        (APB2PERIPH_BASE + 0x4C00)
-#define TMR10_BASE                       (APB2PERIPH_BASE + 0x5000)
-#define TMR11_BASE                       (APB2PERIPH_BASE + 0x5400)
-#define ACC_BASE                         (APB2PERIPH_BASE + 0x5800)
-#define I2C3_BASE                        (APB2PERIPH_BASE + 0x5C00)
-#define USART6_BASE                      (APB2PERIPH_BASE + 0x6000)
-#define UART7_BASE                       (APB2PERIPH_BASE + 0x6400)
-#define UART8_BASE                       (APB2PERIPH_BASE + 0x6800)
-#define I2S2EXT_BASE                     (APB2PERIPH_BASE + 0x6C00)
-#define I2S3EXT_BASE                     (APB2PERIPH_BASE + 0x7000)
-#define SDIO1_BASE                       (APB2PERIPH_BASE + 0x8000)
-/* ahb bus base address */
-#define DMA1_BASE                        (AHBPERIPH_BASE + 0x0000)
-#define DMA1_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0008)
-#define DMA1_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x001C)
-#define DMA1_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0030)
-#define DMA1_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0044)
-#define DMA1_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0058)
-#define DMA1_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x006C)
-#define DMA1_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE                        (AHBPERIPH_BASE + 0x0400)
-#define DMA2_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0408)
-#define DMA2_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x041C)
-#define DMA2_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0430)
-#define DMA2_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0444)
-#define DMA2_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0458)
-#define DMA2_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x046C)
-#define DMA2_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0480)
-#define CRM_BASE                         (AHBPERIPH_BASE + 0x1000)
-#define FLASH_REG_BASE                   (AHBPERIPH_BASE + 0x2000)
-#define CRC_BASE                         (AHBPERIPH_BASE + 0x3000)
-#define SDIO2_BASE                       (AHBPERIPH_BASE + 0x3400)
-#define XMC_BANK1_REG_BASE               (XMC_REG_BASE + 0x0000)
-#define XMC_BANK1E_REG_BASE              (XMC_REG_BASE + 0x0104)
-#define XMC_BANK1E_H_BASE                (XMC_REG_BASE + 0x0220)
-#define XMC_BANK2_REG_BASE               (XMC_REG_BASE + 0x0060)
-#define XMC_BANK3_REG_BASE               (XMC_REG_BASE + 0x0080)
-#define XMC_BANK4_REG_BASE               (XMC_REG_BASE + 0x00A0)
-#endif
-
-#if defined (AT32F407xx)
-/* apb1 bus base address */
-#define TMR2_BASE                        (APB1PERIPH_BASE + 0x0000)
-#define TMR3_BASE                        (APB1PERIPH_BASE + 0x0400)
-#define TMR4_BASE                        (APB1PERIPH_BASE + 0x0800)
-#define TMR5_BASE                        (APB1PERIPH_BASE + 0x0C00)
-#define TMR6_BASE                        (APB1PERIPH_BASE + 0x1000)
-#define TMR7_BASE                        (APB1PERIPH_BASE + 0x1400)
-#define TMR12_BASE                       (APB1PERIPH_BASE + 0x1800)
-#define TMR13_BASE                       (APB1PERIPH_BASE + 0x1C00)
-#define TMR14_BASE                       (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE                         (APB1PERIPH_BASE + 0x2800)
-#define WWDT_BASE                        (APB1PERIPH_BASE + 0x2C00)
-#define WDT_BASE                         (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE                        (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE                        (APB1PERIPH_BASE + 0x3C00)
-#define SPI4_BASE                        (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE                      (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE                      (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE                       (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE                       (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE                        (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE                        (APB1PERIPH_BASE + 0x5800)
-#define USBFS_BASE                       (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE                        (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE                        (APB1PERIPH_BASE + 0x6800)
-#define BPR_BASE                         (APB1PERIPH_BASE + 0x6C00)
-#define PWC_BASE                         (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE                         (APB1PERIPH_BASE + 0x7400)
-/* apb2 bus base address */
-#define IOMUX_BASE                       (APB2PERIPH_BASE + 0x0000)
-#define EXINT_BASE                       (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE                       (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE                       (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE                       (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE                       (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE                       (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE                        (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE                        (APB2PERIPH_BASE + 0x2800)
-#define TMR1_BASE                        (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE                        (APB2PERIPH_BASE + 0x3000)
-#define TMR8_BASE                        (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE                      (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE                        (APB2PERIPH_BASE + 0x3C00)
-#define TMR9_BASE                        (APB2PERIPH_BASE + 0x4C00)
-#define TMR10_BASE                       (APB2PERIPH_BASE + 0x5000)
-#define TMR11_BASE                       (APB2PERIPH_BASE + 0x5400)
-#define ACC_BASE                         (APB2PERIPH_BASE + 0x5800)
-#define I2C3_BASE                        (APB2PERIPH_BASE + 0x5C00)
-#define USART6_BASE                      (APB2PERIPH_BASE + 0x6000)
-#define UART7_BASE                       (APB2PERIPH_BASE + 0x6400)
-#define UART8_BASE                       (APB2PERIPH_BASE + 0x6800)
-#define I2S2EXT_BASE                     (APB2PERIPH_BASE + 0x6C00)
-#define I2S3EXT_BASE                     (APB2PERIPH_BASE + 0x7000)
-#define SDIO1_BASE                       (APB2PERIPH_BASE + 0x8000)
-/* ahb bus base address */
-#define DMA1_BASE                        (AHBPERIPH_BASE + 0x0000)
-#define DMA1_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0008)
-#define DMA1_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x001C)
-#define DMA1_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0030)
-#define DMA1_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0044)
-#define DMA1_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0058)
-#define DMA1_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x006C)
-#define DMA1_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE                        (AHBPERIPH_BASE + 0x0400)
-#define DMA2_CHANNEL1_BASE               (AHBPERIPH_BASE + 0x0408)
-#define DMA2_CHANNEL2_BASE               (AHBPERIPH_BASE + 0x041C)
-#define DMA2_CHANNEL3_BASE               (AHBPERIPH_BASE + 0x0430)
-#define DMA2_CHANNEL4_BASE               (AHBPERIPH_BASE + 0x0444)
-#define DMA2_CHANNEL5_BASE               (AHBPERIPH_BASE + 0x0458)
-#define DMA2_CHANNEL6_BASE               (AHBPERIPH_BASE + 0x046C)
-#define DMA2_CHANNEL7_BASE               (AHBPERIPH_BASE + 0x0480)
-#define CRM_BASE                         (AHBPERIPH_BASE + 0x1000)
-#define FLASH_REG_BASE                   (AHBPERIPH_BASE + 0x2000)
-#define CRC_BASE                         (AHBPERIPH_BASE + 0x3000)
-#define SDIO2_BASE                       (AHBPERIPH_BASE + 0x3400)
-#define EMAC_BASE                        (AHBPERIPH_BASE + 0x8000)
-#define XMC_BANK1_REG_BASE               (XMC_REG_BASE + 0x0000)
-#define XMC_BANK2_REG_BASE               (XMC_REG_BASE + 0x0060)
-#define EMAC_MMC_BASE                    (EMAC_BASE + 0x0100)
-#define EMAC_PTP_BASE                    (EMAC_BASE + 0x0700)
-#define EMAC_DMA_BASE                    (EMAC_BASE + 0x1000)
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#include "at32f403a_407_def.h"
-#include "at32f403a_407_conf.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/at32f403a_407_conf_template.h

@@ -1,163 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_conf.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 config header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_CONF_H
-#define __AT32F403A_407_CONF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
-  * @brief in the following line adjust the value of high speed exernal crystal (hext)
-  * used in your application
-  * tip: to avoid modifying this file each time you need to use different hext, you
-  *      can define the hext value in your toolchain compiler preprocessor.
-  */
-#if !defined  HEXT_VALUE
-#define HEXT_VALUE               ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
-#endif
-
-/**
-  * @brief in the following line adjust the high speed exernal crystal (hext) startup
-  * timeout value
-  */
-#define HEXT_STARTUP_TIMEOUT     ((uint16_t)0x3000) /*!< time out for hext start up */
-#define HICK_VALUE               ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
-
-/* module define -------------------------------------------------------------*/
-#define CRM_MODULE_ENABLED
-#define TMR_MODULE_ENABLED
-#define RTC_MODULE_ENABLED
-#define BPR_MODULE_ENABLED
-#define GPIO_MODULE_ENABLED
-#define I2C_MODULE_ENABLED
-#define USART_MODULE_ENABLED
-#define PWC_MODULE_ENABLED
-#define CAN_MODULE_ENABLED
-#define ADC_MODULE_ENABLED
-#define DAC_MODULE_ENABLED
-#define SPI_MODULE_ENABLED
-#define DMA_MODULE_ENABLED
-#define DEBUG_MODULE_ENABLED
-#define FLASH_MODULE_ENABLED
-#define CRC_MODULE_ENABLED
-#define WWDT_MODULE_ENABLED
-#define WDT_MODULE_ENABLED
-#define EXINT_MODULE_ENABLED
-#define SDIO_MODULE_ENABLED
-#define XMC_MODULE_ENABLED
-#define USB_MODULE_ENABLED
-#define ACC_MODULE_ENABLED
-#define MISC_MODULE_ENABLED
-#define EMAC_MODULE_ENABLED
-
-/* includes ------------------------------------------------------------------*/
-#ifdef CRM_MODULE_ENABLED
-#include "at32f403a_407_crm.h"
-#endif
-#ifdef TMR_MODULE_ENABLED
-#include "at32f403a_407_tmr.h"
-#endif
-#ifdef RTC_MODULE_ENABLED
-#include "at32f403a_407_rtc.h"
-#endif
-#ifdef BPR_MODULE_ENABLED
-#include "at32f403a_407_bpr.h"
-#endif
-#ifdef GPIO_MODULE_ENABLED
-#include "at32f403a_407_gpio.h"
-#endif
-#ifdef I2C_MODULE_ENABLED
-#include "at32f403a_407_i2c.h"
-#endif
-#ifdef USART_MODULE_ENABLED
-#include "at32f403a_407_usart.h"
-#endif
-#ifdef PWC_MODULE_ENABLED
-#include "at32f403a_407_pwc.h"
-#endif
-#ifdef CAN_MODULE_ENABLED
-#include "at32f403a_407_can.h"
-#endif
-#ifdef ADC_MODULE_ENABLED
-#include "at32f403a_407_adc.h"
-#endif
-#ifdef DAC_MODULE_ENABLED
-#include "at32f403a_407_dac.h"
-#endif
-#ifdef SPI_MODULE_ENABLED
-#include "at32f403a_407_spi.h"
-#endif
-#ifdef DMA_MODULE_ENABLED
-#include "at32f403a_407_dma.h"
-#endif
-#ifdef DEBUG_MODULE_ENABLED
-#include "at32f403a_407_debug.h"
-#endif
-#ifdef FLASH_MODULE_ENABLED
-#include "at32f403a_407_flash.h"
-#endif
-#ifdef CRC_MODULE_ENABLED
-#include "at32f403a_407_crc.h"
-#endif
-#ifdef WWDT_MODULE_ENABLED
-#include "at32f403a_407_wwdt.h"
-#endif
-#ifdef WDT_MODULE_ENABLED
-#include "at32f403a_407_wdt.h"
-#endif
-#ifdef EXINT_MODULE_ENABLED
-#include "at32f403a_407_exint.h"
-#endif
-#ifdef SDIO_MODULE_ENABLED
-#include "at32f403a_407_sdio.h"
-#endif
-#ifdef XMC_MODULE_ENABLED
-#include "at32f403a_407_xmc.h"
-#endif
-#ifdef ACC_MODULE_ENABLED
-#include "at32f403a_407_acc.h"
-#endif
-#ifdef MISC_MODULE_ENABLED
-#include "at32f403a_407_misc.h"
-#endif
-#ifdef USB_MODULE_ENABLED
-#include "at32f403a_407_usb.h"
-#endif
-#ifdef EMAC_MODULE_ENABLED
-#include "at32f403a_407_emac.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AT32F403A_407_CONF_H */
-
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F403AxC_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F403AxC_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F403AxC Device with
-**                256KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F403AxE_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F403AxE_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F403AxE Device with
-**                512KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F403AxG_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F403AxG_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F403AxG Device with
-**                1000KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F407xC_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F407xC_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F407xC Device with
-**                256KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F407xE_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F407xE_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F407xE Device with
-**                512KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/linker/AT32F407xG_FLASH.ld

@@ -1,154 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : AT32F407xG_FLASH.ld
-**
-**  Abstract    : Linker script for AT32F407xG Device with
-**                1000KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : Artery Tek AT32
-**
-**  Environment : Arm gcc toolchain
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20017FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/gcc/startup_at32f403a_407.s

@@ -1,480 +0,0 @@
-/**
-  ******************************************************************************
-  * @file     startup_at32f403a_407.s
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407xx devices vector table for gcc toolchain.
-  *           this module performs:
-  *           - set the initial sp
-  *           - set the initial pc == reset_handler,
-  *           - set the vector table entries with the exceptions isr address
-  *           - configure the clock system and the external sram to
-  *             be used as data memory (optional, to be enabled by user)
-  *           - branches to main in the c library (which eventually
-  *             calls main()).
-  *           after reset the cortex-m4 processor is in thread mode,
-  *           priority is privileged, and the stack is set to main.
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m4
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  entry
-  bx  lr
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-
-  /* External Interrupts */
-  .word  WWDT_IRQHandler                     /* Window Watchdog Timer                   */
-  .word  PVM_IRQHandler                      /* PVM through EXINT Line detect           */
-  .word  TAMPER_IRQHandler                   /* Tamper                                  */
-  .word  RTC_IRQHandler                      /* RTC                                     */
-  .word  FLASH_IRQHandler                    /* Flash                                   */
-  .word  CRM_IRQHandler                      /* CRM                                     */
-  .word  EXINT0_IRQHandler                   /* EXINT Line 0                            */
-  .word  EXINT1_IRQHandler                   /* EXINT Line 1                            */
-  .word  EXINT2_IRQHandler                   /* EXINT Line 2                            */
-  .word  EXINT3_IRQHandler                   /* EXINT Line 3                            */
-  .word  EXINT4_IRQHandler                   /* EXINT Line 4                            */
-  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
-  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
-  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
-  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
-  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
-  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
-  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
-  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
-  .word  USBFS_H_CAN1_TX_IRQHandler          /* USB High Priority or CAN1 TX            */
-  .word  USBFS_L_CAN1_RX0_IRQHandler         /* USB Low  Priority or CAN1 RX0           */
-  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
-  .word  CAN1_SE_IRQHandler                  /* CAN1 SE                                 */
-  .word  EXINT9_5_IRQHandler                 /* EXINT Line [9:5]                        */
-  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Brake and TMR9                     */
-  .word  TMR1_OVF_TMR10_IRQHandler           /* TMR1 Overflow and TMR10                 */
-  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and hall and TMR11         */
-  .word  TMR1_CH_IRQHandler                  /* TMR1 Channel                            */
-  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
-  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
-  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
-  .word  I2C1_EVT_IRQHandler                 /* I2C1 Event                              */
-  .word  I2C1_ERR_IRQHandler                 /* I2C1 Error                              */
-  .word  I2C2_EVT_IRQHandler                 /* I2C2 Event                              */
-  .word  I2C2_ERR_IRQHandler                 /* I2C2 Error                              */
-  .word  SPI1_IRQHandler                     /* SPI1                                    */
-  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
-  .word  USART1_IRQHandler                   /* USART1                                  */
-  .word  USART2_IRQHandler                   /* USART2                                  */
-  .word  USART3_IRQHandler                   /* USART3                                  */
-  .word  EXINT15_10_IRQHandler               /* EXINT Line [15:10]                      */
-  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXINT Line            */
-  .word  USBFSWakeUp_IRQHandler              /* USB Wakeup from suspend                 */
-  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Brake and TMR12                    */
-  .word  TMR8_OVF_TMR13_IRQHandler           /* TMR8 Overflow and TMR13                 */
-  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and hall and TMR14         */
-  .word  TMR8_CH_IRQHandler                  /* TMR8 Channel                            */
-  .word  ADC3_IRQHandler                     /* ADC3                                    */
-  .word  XMC_IRQHandler                      /* XMC                                     */
-  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
-  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
-  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
-  .word  UART4_IRQHandler                    /* UART4                                   */
-  .word  UART5_IRQHandler                    /* UART5                                   */
-  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
-  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
-  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
-  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
-  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
-  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
-  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
-  .word  I2C3_EVT_IRQHandler                 /* I2C3 Event                              */
-  .word  I2C3_ERR_IRQHandler                 /* I2C3 Error                              */
-  .word  SPI4_IRQHandler                     /* SPI4                                    */
-  .word  0                                   /* Reserved                                */
-  .word  0                                   /* Reserved                                */
-  .word  0                                   /* Reserved                                */
-  .word  0                                   /* Reserved                                */
-  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
-  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
-  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
-  .word  CAN2_SE_IRQHandler                  /* CAN2 SE                                 */
-  .word  ACC_IRQHandler                      /* ACC                                     */
-  .word  USBFS_MAPH_IRQHandler               /* USB Map HP                              */
-  .word  USBFS_MAPL_IRQHandler               /* USB Map LP                              */
-  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
-  .word  USART6_IRQHandler                   /* USART6                                  */
-  .word  UART7_IRQHandler                    /* UART7                                   */
-  .word  UART8_IRQHandler                    /* UART8                                   */
-  .word  EMAC_IRQHandler                     /* EMAC                                    */
-  .word  EMAC_WKUP_IRQHandler                /* EMAC Wakeup                             */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      MemManage_Handler
-   .thumb_set MemManage_Handler,Default_Handler
-
-   .weak      BusFault_Handler
-   .thumb_set BusFault_Handler,Default_Handler
-
-   .weak      UsageFault_Handler
-   .thumb_set UsageFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      DebugMon_Handler
-   .thumb_set DebugMon_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDT_IRQHandler
-   .thumb_set WWDT_IRQHandler,Default_Handler
-
-   .weak      PVM_IRQHandler
-   .thumb_set PVM_IRQHandler,Default_Handler
-
-   .weak      TAMPER_IRQHandler
-   .thumb_set TAMPER_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      CRM_IRQHandler
-   .thumb_set CRM_IRQHandler,Default_Handler
-
-   .weak      EXINT0_IRQHandler
-   .thumb_set EXINT0_IRQHandler,Default_Handler
-
-   .weak      EXINT1_IRQHandler
-   .thumb_set EXINT1_IRQHandler,Default_Handler
-
-   .weak      EXINT2_IRQHandler
-   .thumb_set EXINT2_IRQHandler,Default_Handler
-
-   .weak      EXINT3_IRQHandler
-   .thumb_set EXINT3_IRQHandler,Default_Handler
-
-   .weak      EXINT4_IRQHandler
-   .thumb_set EXINT4_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_IRQHandler
-   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel3_IRQHandler
-   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_IRQHandler
-   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel5_IRQHandler
-   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel6_IRQHandler
-   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel7_IRQHandler
-   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-   .weak      ADC1_2_IRQHandler
-   .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-   .weak      USBFS_H_CAN1_TX_IRQHandler
-   .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler
-
-   .weak      USBFS_L_CAN1_RX0_IRQHandler
-   .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler
-
-   .weak      CAN1_RX1_IRQHandler
-   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-   .weak      CAN1_SE_IRQHandler
-   .thumb_set CAN1_SE_IRQHandler,Default_Handler
-
-   .weak      EXINT9_5_IRQHandler
-   .thumb_set EXINT9_5_IRQHandler,Default_Handler
-
-   .weak      TMR1_BRK_TMR9_IRQHandler
-   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
-
-   .weak      TMR1_OVF_TMR10_IRQHandler
-   .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
-
-   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
-   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
-
-   .weak      TMR1_CH_IRQHandler
-   .thumb_set TMR1_CH_IRQHandler,Default_Handler
-
-   .weak      TMR2_GLOBAL_IRQHandler
-   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      TMR3_GLOBAL_IRQHandler
-   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      TMR4_GLOBAL_IRQHandler
-   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      I2C1_EVT_IRQHandler
-   .thumb_set I2C1_EVT_IRQHandler,Default_Handler
-
-   .weak      I2C1_ERR_IRQHandler
-   .thumb_set I2C1_ERR_IRQHandler,Default_Handler
-
-   .weak      I2C2_EVT_IRQHandler
-   .thumb_set I2C2_EVT_IRQHandler,Default_Handler
-
-   .weak      I2C2_ERR_IRQHandler
-   .thumb_set I2C2_ERR_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_I2S2EXT_IRQHandler
-   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      USART3_IRQHandler
-   .thumb_set USART3_IRQHandler,Default_Handler
-
-   .weak      EXINT15_10_IRQHandler
-   .thumb_set EXINT15_10_IRQHandler,Default_Handler
-
-   .weak      RTCAlarm_IRQHandler
-   .thumb_set RTCAlarm_IRQHandler,Default_Handler
-
-   .weak      USBFSWakeUp_IRQHandler
-   .thumb_set USBFSWakeUp_IRQHandler,Default_Handler
-
-   .weak      TMR8_BRK_TMR12_IRQHandler
-   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
-
-   .weak      TMR8_OVF_TMR13_IRQHandler
-   .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler
-
-   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
-   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
-
-   .weak      TMR8_CH_IRQHandler
-   .thumb_set TMR8_CH_IRQHandler,Default_Handler
-
-   .weak      ADC3_IRQHandler
-   .thumb_set ADC3_IRQHandler,Default_Handler
-
-   .weak      XMC_IRQHandler
-   .thumb_set XMC_IRQHandler,Default_Handler
-
-   .weak      SDIO1_IRQHandler
-   .thumb_set SDIO1_IRQHandler,Default_Handler
-
-   .weak      TMR5_GLOBAL_IRQHandler
-   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      SPI3_I2S3EXT_IRQHandler
-   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
-
-   .weak      UART4_IRQHandler
-   .thumb_set UART4_IRQHandler,Default_Handler
-
-   .weak      UART5_IRQHandler
-   .thumb_set UART5_IRQHandler,Default_Handler
-
-   .weak      TMR6_GLOBAL_IRQHandler
-   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      TMR7_GLOBAL_IRQHandler
-   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
-
-   .weak      DMA2_Channel1_IRQHandler
-   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA2_Channel2_IRQHandler
-   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-   .weak      DMA2_Channel3_IRQHandler
-   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-   .weak      DMA2_Channel4_5_IRQHandler
-   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-
-   .weak      SDIO2_IRQHandler
-   .thumb_set SDIO2_IRQHandler,Default_Handler
-
-   .weak      I2C3_EVT_IRQHandler
-   .thumb_set I2C3_EVT_IRQHandler,Default_Handler
-
-   .weak      I2C3_ERR_IRQHandler
-   .thumb_set I2C3_ERR_IRQHandler,Default_Handler
-
-   .weak      SPI4_IRQHandler
-   .thumb_set SPI4_IRQHandler,Default_Handler
-
-   .weak      CAN2_TX_IRQHandler
-   .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-   .weak      CAN2_RX0_IRQHandler
-   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
-
-   .weak      CAN2_RX1_IRQHandler
-   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
-
-   .weak      CAN2_SE_IRQHandler
-   .thumb_set CAN2_SE_IRQHandler,Default_Handler
-
-   .weak      ACC_IRQHandler
-   .thumb_set ACC_IRQHandler,Default_Handler
-
-   .weak      USBFS_MAPH_IRQHandler
-   .thumb_set USBFS_MAPH_IRQHandler,Default_Handler
-
-   .weak      USBFS_MAPL_IRQHandler
-   .thumb_set USBFS_MAPL_IRQHandler,Default_Handler
-
-   .weak      DMA2_Channel6_7_IRQHandler
-   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
-
-   .weak      USART6_IRQHandler
-   .thumb_set USART6_IRQHandler,Default_Handler
-
-   .weak      UART7_IRQHandler
-   .thumb_set UART7_IRQHandler,Default_Handler
-
-   .weak      UART8_IRQHandler
-   .thumb_set UART8_IRQHandler,Default_Handler
-
-   .weak      EMAC_IRQHandler
-   .thumb_set EMAC_IRQHandler,Default_Handler
-
-   .weak      EMAC_WKUP_IRQHandler
-   .thumb_set EMAC_WKUP_IRQHandler,Default_Handler

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/linker/AT32F407xG.icf

@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/iar/startup_at32f403a_407.s

@@ -1,573 +0,0 @@
-;**************************************************************************
-;* @file     startup_at32f403a_407.s
-;* @version  v2.0.7
-;* @date     2022-02-11
-;* @brief    at32f403a_407 startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                       ; Reset Handler
-        DCD     NMI_Handler                         ; NMI Handler
-        DCD     HardFault_Handler                   ; Hard Fault Handler
-        DCD     MemManage_Handler                   ; MPU Fault Handler
-        DCD     BusFault_Handler                    ; Bus Fault Handler
-        DCD     UsageFault_Handler                  ; Usage Fault Handler
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     SVC_Handler                         ; SVCall Handler
-        DCD     DebugMon_Handler                    ; Debug Monitor Handler
-        DCD     0                                   ; Reserved
-        DCD     PendSV_Handler                      ; PendSV Handler
-        DCD     SysTick_Handler                     ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDT_IRQHandler                     ; Window Watchdog Timer
-        DCD     PVM_IRQHandler                      ; PVM through EXINT Line detect
-        DCD     TAMPER_IRQHandler                   ; Tamper
-        DCD     RTC_IRQHandler                      ; RTC
-        DCD     FLASH_IRQHandler                    ; Flash
-        DCD     CRM_IRQHandler                      ; CRM
-        DCD     EXINT0_IRQHandler                   ; EXINT Line 0
-        DCD     EXINT1_IRQHandler                   ; EXINT Line 1
-        DCD     EXINT2_IRQHandler                   ; EXINT Line 2
-        DCD     EXINT3_IRQHandler                   ; EXINT Line 3
-        DCD     EXINT4_IRQHandler                   ; EXINT Line 4
-        DCD     DMA1_Channel1_IRQHandler            ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler            ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler            ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler            ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler            ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler            ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler            ; DMA1 Channel 7
-        DCD     ADC1_2_IRQHandler                   ; ADC1 & ADC2
-        DCD     USBFS_H_CAN1_TX_IRQHandler          ; USB High Priority or CAN1 TX
-        DCD     USBFS_L_CAN1_RX0_IRQHandler         ; USB Low  Priority or CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler                 ; CAN1 RX1
-        DCD     CAN1_SE_IRQHandler                  ; CAN1 SE
-        DCD     EXINT9_5_IRQHandler                 ; EXINT Line [9:5]
-        DCD     TMR1_BRK_TMR9_IRQHandler            ; TMR1 Brake and TMR9
-        DCD     TMR1_OVF_TMR10_IRQHandler           ; TMR1 Overflow and TMR10
-        DCD     TMR1_TRG_HALL_TMR11_IRQHandler      ; TMR1 Trigger and hall and TMR11
-        DCD     TMR1_CH_IRQHandler                  ; TMR1 Channel
-        DCD     TMR2_GLOBAL_IRQHandler              ; TMR2
-        DCD     TMR3_GLOBAL_IRQHandler              ; TMR3
-        DCD     TMR4_GLOBAL_IRQHandler              ; TMR4
-        DCD     I2C1_EVT_IRQHandler                 ; I2C1 Event
-        DCD     I2C1_ERR_IRQHandler                 ; I2C1 Error
-        DCD     I2C2_EVT_IRQHandler                 ; I2C2 Event
-        DCD     I2C2_ERR_IRQHandler                 ; I2C2 Error
-        DCD     SPI1_IRQHandler                     ; SPI1
-        DCD     SPI2_I2S2EXT_IRQHandler             ; SPI2 & I2S2EXT
-        DCD     USART1_IRQHandler                   ; USART1
-        DCD     USART2_IRQHandler                   ; USART2
-        DCD     USART3_IRQHandler                   ; USART3
-        DCD     EXINT15_10_IRQHandler               ; EXINT Line [15:10]
-        DCD     RTCAlarm_IRQHandler                 ; RTC Alarm through EXINT Line
-        DCD     USBFSWakeUp_IRQHandler              ; USB Wakeup from suspend
-        DCD     TMR8_BRK_TMR12_IRQHandler           ; TMR8 Brake and TMR12
-        DCD     TMR8_OVF_TMR13_IRQHandler           ; TMR8 Overflow and TMR13
-        DCD     TMR8_TRG_HALL_TMR14_IRQHandler      ; TMR8 Trigger and hall and TMR14
-        DCD     TMR8_CH_IRQHandler                  ; TMR8 Channel
-        DCD     ADC3_IRQHandler                     ; ADC3
-        DCD     XMC_IRQHandler                      ; XMC
-        DCD     SDIO1_IRQHandler                    ; SDIO1
-        DCD     TMR5_GLOBAL_IRQHandler              ; TMR5
-        DCD     SPI3_I2S3EXT_IRQHandler             ; SPI3 & I2S3EXT
-        DCD     UART4_IRQHandler                    ; UART4
-        DCD     UART5_IRQHandler                    ; UART5
-        DCD     TMR6_GLOBAL_IRQHandler              ; TMR6
-        DCD     TMR7_GLOBAL_IRQHandler              ; TMR7
-        DCD     DMA2_Channel1_IRQHandler            ; DMA2 Channel1
-        DCD     DMA2_Channel2_IRQHandler            ; DMA2 Channel2
-        DCD     DMA2_Channel3_IRQHandler            ; DMA2 Channel3
-        DCD     DMA2_Channel4_5_IRQHandler          ; DMA2 Channel4 & Channel5
-        DCD     SDIO2_IRQHandler                    ; SDIO2
-        DCD     I2C3_EVT_IRQHandler                 ; I2C3 Event
-        DCD     I2C3_ERR_IRQHandler                 ; I2C3 Error
-        DCD     SPI4_IRQHandler                     ; SPI4
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     0                                   ; Reserved
-        DCD     CAN2_TX_IRQHandler                  ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler                 ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler                 ; CAN2 RX1
-        DCD     CAN2_SE_IRQHandler                  ; CAN2 SE
-        DCD     ACC_IRQHandler                      ; ACC
-        DCD     USBFS_MAPH_IRQHandler               ; USB Map HP
-        DCD     USBFS_MAPL_IRQHandler               ; USB Map LP
-        DCD     DMA2_Channel6_7_IRQHandler          ; DMA2 Channel6 & Channel7
-        DCD     USART6_IRQHandler                   ; USART6
-        DCD     UART7_IRQHandler                    ; UART7
-        DCD     UART8_IRQHandler                    ; UART8
-        DCD     EMAC_IRQHandler                     ; EMAC
-        DCD     EMAC_WKUP_IRQHandler                ; EMAC_WKUP
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDT_IRQHandler
-        B WWDT_IRQHandler
-
-        PUBWEAK PVM_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVM_IRQHandler
-        B PVM_IRQHandler
-
-        PUBWEAK TAMPER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
-        B TAMPER_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK CRM_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRM_IRQHandler
-        B CRM_IRQHandler
-
-        PUBWEAK EXINT0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT0_IRQHandler
-        B EXINT0_IRQHandler
-
-        PUBWEAK EXINT1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT1_IRQHandler
-        B EXINT1_IRQHandler
-
-        PUBWEAK EXINT2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT2_IRQHandler
-        B EXINT2_IRQHandler
-
-        PUBWEAK EXINT3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT3_IRQHandler
-        B EXINT3_IRQHandler
-
-        PUBWEAK EXINT4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT4_IRQHandler
-        B EXINT4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC1_2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
-        B ADC1_2_IRQHandler
-
-        PUBWEAK USBFS_H_CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBFS_H_CAN1_TX_IRQHandler
-        B USBFS_H_CAN1_TX_IRQHandler
-
-        PUBWEAK USBFS_L_CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBFS_L_CAN1_RX0_IRQHandler
-        B USBFS_L_CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SE_IRQHandler
-        B CAN1_SE_IRQHandler
-
-        PUBWEAK EXINT9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT9_5_IRQHandler
-        B EXINT9_5_IRQHandler
-
-        PUBWEAK TMR1_BRK_TMR9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
-        B TMR1_BRK_TMR9_IRQHandler
-
-        PUBWEAK TMR1_OVF_TMR10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OVF_TMR10_IRQHandler
-        B TMR1_OVF_TMR10_IRQHandler
-
-        PUBWEAK TMR1_TRG_HALL_TMR11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_HALL_TMR11_IRQHandler
-        B TMR1_TRG_HALL_TMR11_IRQHandler
-
-        PUBWEAK TMR1_CH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CH_IRQHandler
-        B TMR1_CH_IRQHandler
-
-        PUBWEAK TMR2_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
-        B TMR2_GLOBAL_IRQHandler
-
-        PUBWEAK TMR3_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
-        B TMR3_GLOBAL_IRQHandler
-
-        PUBWEAK TMR4_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
-        B TMR4_GLOBAL_IRQHandler
-
-        PUBWEAK I2C1_EVT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EVT_IRQHandler
-        B I2C1_EVT_IRQHandler
-
-        PUBWEAK I2C1_ERR_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ERR_IRQHandler
-        B I2C1_ERR_IRQHandler
-
-        PUBWEAK I2C2_EVT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EVT_IRQHandler
-        B I2C2_EVT_IRQHandler
-
-        PUBWEAK I2C2_ERR_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ERR_IRQHandler
-        B I2C2_ERR_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_I2S2EXT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
-        B SPI2_I2S2EXT_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-
-        PUBWEAK EXINT15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXINT15_10_IRQHandler
-        B EXINT15_10_IRQHandler
-
-        PUBWEAK RTCAlarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
-        B RTCAlarm_IRQHandler
-
-        PUBWEAK USBFSWakeUp_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBFSWakeUp_IRQHandler
-        B USBFSWakeUp_IRQHandler
-
-        PUBWEAK TMR8_BRK_TMR12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
-        B TMR8_BRK_TMR12_IRQHandler
-
-        PUBWEAK TMR8_OVF_TMR13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OVF_TMR13_IRQHandler
-        B TMR8_OVF_TMR13_IRQHandler
-
-        PUBWEAK TMR8_TRG_HALL_TMR14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_HALL_TMR14_IRQHandler
-        B TMR8_TRG_HALL_TMR14_IRQHandler
-
-        PUBWEAK TMR8_CH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CH_IRQHandler
-        B TMR8_CH_IRQHandler
-
-        PUBWEAK ADC3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
-        B ADC3_IRQHandler
-
-        PUBWEAK XMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
-        B XMC_IRQHandler
-
-        PUBWEAK SDIO1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
-        B SDIO1_IRQHandler
-
-        PUBWEAK TMR5_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
-        B TMR5_GLOBAL_IRQHandler
-
-        PUBWEAK SPI3_I2S3EXT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
-        B SPI3_I2S3EXT_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TMR6_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
-        B TMR6_GLOBAL_IRQHandler
-
-        PUBWEAK TMR7_GLOBAL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
-        B TMR7_GLOBAL_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
-        B DMA2_Channel4_5_IRQHandler
-
-        PUBWEAK SDIO2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
-        B SDIO2_IRQHandler
-
-        PUBWEAK I2C3_EVT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EVT_IRQHandler
-        B I2C3_EVT_IRQHandler
-
-        PUBWEAK I2C3_ERR_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ERR_IRQHandler
-        B I2C3_ERR_IRQHandler
-
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
-        B SPI4_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SE_IRQHandler
-        B CAN2_SE_IRQHandler
-
-        PUBWEAK ACC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
-        B ACC_IRQHandler
-
-        PUBWEAK USBFS_MAPH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBFS_MAPH_IRQHandler
-        B USBFS_MAPH_IRQHandler
-
-        PUBWEAK USBFS_MAPL_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBFS_MAPL_IRQHandler
-        B USBFS_MAPL_IRQHandler
-
-        PUBWEAK DMA2_Channel6_7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
-        B DMA2_Channel6_7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
-        B USART6_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
-        B UART7_IRQHandler
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
-        B UART8_IRQHandler
-
-        PUBWEAK EMAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EMAC_IRQHandler
-        B EMAC_IRQHandler
-
-        PUBWEAK EMAC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EMAC_WKUP_IRQHandler
-        B EMAC_WKUP_IRQHandler
-
-        END

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/startup/mdk/startup_at32f403a_407.s

@@ -1,391 +0,0 @@
-;**************************************************************************
-;* @file     startup_at32f403a_407.s
-;* @version  v2.0.7
-;* @date     2022-02-11
-;* @brief    at32f403a_407 startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                        ; Top of Stack
-                DCD     Reset_Handler                       ; Reset Handler
-                DCD     NMI_Handler                         ; NMI Handler
-                DCD     HardFault_Handler                   ; Hard Fault Handler
-                DCD     MemManage_Handler                   ; MPU Fault Handler
-                DCD     BusFault_Handler                    ; Bus Fault Handler
-                DCD     UsageFault_Handler                  ; Usage Fault Handler
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     SVC_Handler                         ; SVCall Handler
-                DCD     DebugMon_Handler                    ; Debug Monitor Handler
-                DCD     0                                   ; Reserved
-                DCD     PendSV_Handler                      ; PendSV Handler
-                DCD     SysTick_Handler                     ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDT_IRQHandler                     ; Window Watchdog Timer
-                DCD     PVM_IRQHandler                      ; PVM through EXINT Line detect
-                DCD     TAMPER_IRQHandler                   ; Tamper
-                DCD     RTC_IRQHandler                      ; RTC
-                DCD     FLASH_IRQHandler                    ; Flash
-                DCD     CRM_IRQHandler                      ; CRM
-                DCD     EXINT0_IRQHandler                   ; EXINT Line 0
-                DCD     EXINT1_IRQHandler                   ; EXINT Line 1
-                DCD     EXINT2_IRQHandler                   ; EXINT Line 2
-                DCD     EXINT3_IRQHandler                   ; EXINT Line 3
-                DCD     EXINT4_IRQHandler                   ; EXINT Line 4
-                DCD     DMA1_Channel1_IRQHandler            ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler            ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler            ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler            ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler            ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler            ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler            ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler                   ; ADC1 & ADC2
-                DCD     USBFS_H_CAN1_TX_IRQHandler          ; USB High Priority or CAN1 TX
-                DCD     USBFS_L_CAN1_RX0_IRQHandler         ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler                 ; CAN1 RX1
-                DCD     CAN1_SE_IRQHandler                  ; CAN1 SE
-                DCD     EXINT9_5_IRQHandler                 ; EXINT Line [9:5]
-                DCD     TMR1_BRK_TMR9_IRQHandler            ; TMR1 Brake and TMR9
-                DCD     TMR1_OVF_TMR10_IRQHandler           ; TMR1 overflow and TMR10
-                DCD     TMR1_TRG_HALL_TMR11_IRQHandler      ; TMR1 Trigger and hall and TMR11
-                DCD     TMR1_CH_IRQHandler                  ; TMR1 channel
-                DCD     TMR2_GLOBAL_IRQHandler              ; TMR2
-                DCD     TMR3_GLOBAL_IRQHandler              ; TMR3
-                DCD     TMR4_GLOBAL_IRQHandler              ; TMR4
-                DCD     I2C1_EVT_IRQHandler                 ; I2C1 Event
-                DCD     I2C1_ERR_IRQHandler                 ; I2C1 Error
-                DCD     I2C2_EVT_IRQHandler                 ; I2C2 Event
-                DCD     I2C2_ERR_IRQHandler                 ; I2C2 Error
-                DCD     SPI1_IRQHandler                     ; SPI1
-                DCD     SPI2_I2S2EXT_IRQHandler             ; SPI2 & I2S2EXT
-                DCD     USART1_IRQHandler                   ; USART1
-                DCD     USART2_IRQHandler                   ; USART2
-                DCD     USART3_IRQHandler                   ; USART3
-                DCD     EXINT15_10_IRQHandler               ; EXINT Line [15:10]
-                DCD     RTCAlarm_IRQHandler                 ; RTC Alarm through EXINT Line
-                DCD     USBFSWakeUp_IRQHandler              ; USB Wakeup from suspend
-                DCD     TMR8_BRK_TMR12_IRQHandler           ; TMR8 Brake and TMR12
-                DCD     TMR8_OVF_TMR13_IRQHandler           ; TMR8 overflow and TMR13
-                DCD     TMR8_TRG_HALL_TMR14_IRQHandler      ; TMR8 Trigger and hall and TMR14
-                DCD     TMR8_CH_IRQHandler                  ; TMR8 channel
-                DCD     ADC3_IRQHandler                     ; ADC3
-                DCD     XMC_IRQHandler                      ; XMC
-                DCD     SDIO1_IRQHandler                    ; SDIO1
-                DCD     TMR5_GLOBAL_IRQHandler              ; TMR5
-                DCD     SPI3_I2S3EXT_IRQHandler             ; SPI3 & I2S3EXT
-                DCD     UART4_IRQHandler                    ; UART4
-                DCD     UART5_IRQHandler                    ; UART5
-                DCD     TMR6_GLOBAL_IRQHandler              ; TMR6
-                DCD     TMR7_GLOBAL_IRQHandler              ; TMR7
-                DCD     DMA2_Channel1_IRQHandler            ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler            ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler            ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler          ; DMA2 Channel4 & Channel5
-                DCD     SDIO2_IRQHandler                    ; SDIO2
-                DCD     I2C3_EVT_IRQHandler                 ; I2C3 Event
-                DCD     I2C3_ERR_IRQHandler                 ; I2C3 Error
-                DCD     SPI4_IRQHandler                     ; SPI4
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     0                                   ; Reserved
-                DCD     CAN2_TX_IRQHandler                  ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler                 ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler                 ; CAN2 RX1
-                DCD     CAN2_SE_IRQHandler                  ; CAN2 SE
-                DCD     ACC_IRQHandler                      ; ACC
-                DCD     USBFS_MAPH_IRQHandler               ; USB Map High
-                DCD     USBFS_MAPL_IRQHandler               ; USB Map Low
-                DCD     DMA2_Channel6_7_IRQHandler          ; DMA2 Channel6 & Channel7
-                DCD     USART6_IRQHandler                   ; USART6
-                DCD     UART7_IRQHandler                    ; UART7
-                DCD     UART8_IRQHandler                    ; UART8
-                DCD     EMAC_IRQHandler                     ; EMAC
-                DCD     EMAC_WKUP_IRQHandler                ; EMAC_WKUP
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler                       [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                         [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                   [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                   [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                    [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler                  [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                         [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                      [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                     [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDT_IRQHandler                     [WEAK]
-                EXPORT  PVM_IRQHandler                      [WEAK]
-                EXPORT  TAMPER_IRQHandler                   [WEAK]
-                EXPORT  RTC_IRQHandler                      [WEAK]
-                EXPORT  FLASH_IRQHandler                    [WEAK]
-                EXPORT  CRM_IRQHandler                      [WEAK]
-                EXPORT  EXINT0_IRQHandler                   [WEAK]
-                EXPORT  EXINT1_IRQHandler                   [WEAK]
-                EXPORT  EXINT2_IRQHandler                   [WEAK]
-                EXPORT  EXINT3_IRQHandler                   [WEAK]
-                EXPORT  EXINT4_IRQHandler                   [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler            [WEAK]
-                EXPORT  ADC1_2_IRQHandler                   [WEAK]
-                EXPORT  USBFS_H_CAN1_TX_IRQHandler          [WEAK]
-                EXPORT  USBFS_L_CAN1_RX0_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler                 [WEAK]
-                EXPORT  CAN1_SE_IRQHandler                  [WEAK]
-                EXPORT  EXINT9_5_IRQHandler                 [WEAK]
-                EXPORT  TMR1_BRK_TMR9_IRQHandler            [WEAK]
-                EXPORT  TMR1_OVF_TMR10_IRQHandler           [WEAK]
-                EXPORT  TMR1_TRG_HALL_TMR11_IRQHandler      [WEAK]
-                EXPORT  TMR1_CH_IRQHandler                  [WEAK]
-                EXPORT  TMR2_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  TMR3_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  TMR4_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  I2C1_EVT_IRQHandler                 [WEAK]
-                EXPORT  I2C1_ERR_IRQHandler                 [WEAK]
-                EXPORT  I2C2_EVT_IRQHandler                 [WEAK]
-                EXPORT  I2C2_ERR_IRQHandler                 [WEAK]
-                EXPORT  SPI1_IRQHandler                     [WEAK]
-                EXPORT  SPI2_I2S2EXT_IRQHandler             [WEAK]
-                EXPORT  USART1_IRQHandler                   [WEAK]
-                EXPORT  USART2_IRQHandler                   [WEAK]
-                EXPORT  USART3_IRQHandler                   [WEAK]
-                EXPORT  EXINT15_10_IRQHandler               [WEAK]
-                EXPORT  RTCAlarm_IRQHandler                 [WEAK]
-                EXPORT  USBFSWakeUp_IRQHandler              [WEAK]
-                EXPORT  TMR8_BRK_TMR12_IRQHandler           [WEAK]
-                EXPORT  TMR8_OVF_TMR13_IRQHandler           [WEAK]
-                EXPORT  TMR8_TRG_HALL_TMR14_IRQHandler      [WEAK]
-                EXPORT  TMR8_CH_IRQHandler                  [WEAK]
-                EXPORT  ADC3_IRQHandler                     [WEAK]
-                EXPORT  XMC_IRQHandler                      [WEAK]
-                EXPORT  SDIO1_IRQHandler                    [WEAK]
-                EXPORT  TMR5_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  SPI3_I2S3EXT_IRQHandler             [WEAK]
-                EXPORT  UART4_IRQHandler                    [WEAK]
-                EXPORT  UART5_IRQHandler                    [WEAK]
-                EXPORT  TMR6_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  TMR7_GLOBAL_IRQHandler              [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler          [WEAK]
-                EXPORT  SDIO2_IRQHandler                    [WEAK]
-                EXPORT  I2C3_EVT_IRQHandler                 [WEAK]
-                EXPORT  I2C3_ERR_IRQHandler                 [WEAK]
-                EXPORT  SPI4_IRQHandler                     [WEAK]
-                EXPORT  CAN2_TX_IRQHandler                  [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler                 [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler                 [WEAK]
-                EXPORT  CAN2_SE_IRQHandler                  [WEAK]
-                EXPORT  ACC_IRQHandler                      [WEAK]
-                EXPORT  USBFS_MAPH_IRQHandler               [WEAK]
-                EXPORT  USBFS_MAPL_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel6_7_IRQHandler          [WEAK]
-                EXPORT  USART6_IRQHandler                   [WEAK]
-                EXPORT  UART7_IRQHandler                    [WEAK]
-                EXPORT  UART8_IRQHandler                    [WEAK]
-                EXPORT  EMAC_IRQHandler                     [WEAK]
-                EXPORT  EMAC_WKUP_IRQHandler                [WEAK]
-
-WWDT_IRQHandler
-PVM_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-CRM_IRQHandler
-EXINT0_IRQHandler
-EXINT1_IRQHandler
-EXINT2_IRQHandler
-EXINT3_IRQHandler
-EXINT4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USBFS_H_CAN1_TX_IRQHandler
-USBFS_L_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SE_IRQHandler
-EXINT9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OVF_TMR10_IRQHandler
-TMR1_TRG_HALL_TMR11_IRQHandler
-TMR1_CH_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EVT_IRQHandler
-I2C1_ERR_IRQHandler
-I2C2_EVT_IRQHandler
-I2C2_ERR_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXINT15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBFSWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OVF_TMR13_IRQHandler
-TMR8_TRG_HALL_TMR14_IRQHandler
-TMR8_CH_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EVT_IRQHandler
-I2C3_ERR_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SE_IRQHandler
-ACC_IRQHandler
-USBFS_MAPH_IRQHandler
-USBFS_MAPL_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
-EMAC_IRQHandler
-EMAC_WKUP_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, = Heap_Mem
-                 LDR     R1, = (Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/system_at32f403a_407.c

@@ -1,193 +0,0 @@
-/**
-  **************************************************************************
-  * @file     system_at32f403a_407.c
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    contains all the functions for cmsis cortex-m4 system source file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup AT32F403A_407_system
-  * @{
-  */
-
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_system_private_defines
-  * @{
-  */
-#define VECT_TAB_OFFSET                  0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup AT32F403A_407_system_private_variables
-  * @{
-  */
-unsigned int system_core_clock           = HICK_VALUE; /*!< system clock frequency (core clock) */
-/**
-  * @}
-  */
-
-/** @addtogroup AT32F403A_407_system_private_functions
-  * @{
-  */
-
-/**
-  * @brief  setup the microcontroller system
-  *         initialize the flash interface.
-  * @note   this function should be used only after reset.
-  * @param  none
-  * @retval none
-  */
-void SystemInit (void)
-{
-#if defined (__FPU_USED) && (__FPU_USED == 1U)
-  SCB->CPACR |= ((3U << 10U * 2U) |         /* set cp10 full access */
-                 (3U << 11U * 2U)  );       /* set cp11 full access */
-#endif
-
-  /* reset the crm clock configuration to the default reset state(for debug purpose) */
-  /* set hicken bit */
-  CRM->ctrl_bit.hicken = TRUE;
-
-  /* wait hick stable */
-  while(CRM->ctrl_bit.hickstbl != SET);
-
-  /* hick used as system clock */
-  CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
-
-  /* wait sclk switch status */
-  while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
-
-  /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
-     clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
-  CRM->cfg = 0;
-
-  /* reset hexten, hextbyps, cfden and pllen bits */
-  CRM->ctrl &= ~(0x010D0000U);
-
-  /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
-  CRM->misc1 = 0;
-
-  /* disable all interrupts enable and clear pending bits  */
-  CRM->clkint = 0x009F0000;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE  | VECT_TAB_OFFSET;  /* vector table relocation in internal sram. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;  /* vector table relocation in internal flash. */
-#endif
-}
-
-/**
-  * @brief  update system_core_clock variable according to clock register values.
-  *         the system_core_clock variable contains the core clock (hclk), it can
-  *         be used by the user application to setup the systick timer or configure
-  *         other parameters.
-  * @param  none
-  * @retval none
-  */
-void system_core_clock_update(void)
-{
-  uint32_t hext_prediv = 0, pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
-  crm_sclk_type sclk_source;
-
-  static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-  /* get sclk source */
-  sclk_source = crm_sysclk_switch_status_get();
-
-  switch(sclk_source)
-  {
-    case CRM_SCLK_HICK:
-      if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
-        system_core_clock = HICK_VALUE * 6;
-      else
-        system_core_clock = HICK_VALUE;
-      break;
-    case CRM_SCLK_HEXT:
-      system_core_clock = HEXT_VALUE;
-      break;
-    case CRM_SCLK_PLL:
-      pll_clock_source = CRM->cfg_bit.pllrcs;
-      {
-        /* get multiplication factor */
-        pll_mult = CRM->cfg_bit.pllmult_l;
-        pll_mult_h = CRM->cfg_bit.pllmult_h;
-        /* process high bits */
-        if((pll_mult_h != 0U) || (pll_mult == 15U)){
-            pll_mult += ((16U * pll_mult_h) + 1U);
-        }
-        else
-        {
-            pll_mult += 2U;
-        }
-
-        if (pll_clock_source == 0x00)
-        {
-          /* hick divided by 2 selected as pll clock entry */
-          system_core_clock = (HICK_VALUE >> 1) * pll_mult;
-        }
-        else
-        {
-          /* hext selected as pll clock entry */
-          if (CRM->cfg_bit.pllhextdiv != RESET)
-          {
-            hext_prediv = CRM->misc3_bit.hextdiv;
-
-            /* hext clock divided by 2 */
-            system_core_clock = (HEXT_VALUE / (hext_prediv + 2)) * pll_mult;
-          }
-          else
-          {
-            system_core_clock = HEXT_VALUE * pll_mult;
-          }
-        }
-      }
-      break;
-    default:
-      system_core_clock = HICK_VALUE;
-      break;
-  }
-
-  /* compute sclk, ahbclk frequency */
-  /* get ahb division */
-  temp = CRM->cfg_bit.ahbdiv;
-  div_value = sys_ahb_div_table[temp];
-  /* ahbclk frequency */
-  system_core_clock = system_core_clock >> div_value;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-

bsp/at32/libraries/f403a_407/firmware/cmsis/cm4/device_support/system_at32f403a_407.h

@@ -1,86 +0,0 @@
-/**
-  **************************************************************************
-  * @file     system_at32f403a_407.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    cmsis cortex-m4 system header file.
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-#ifndef __SYSTEM_AT32F403A_407_H
-#define __SYSTEM_AT32F403A_407_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup AT32F403A_407_system
-  * @{
-  */
-
-/** @defgroup AT32F403A_407_system_clock_stable_definition
-  * @{
-  */
-
-#define HEXT_STABLE_DELAY                (5000u)
-#define PLL_STABLE_DELAY                 (500u)
-
-/**
-  * @}
-  */
-
-/** @defgroup AT32F403A_407_system_exported_variables
-  * @{
-  */
-
-extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
-
-/**
-  * @}
-  */
-
-/** @defgroup AT32F403A_407_system_exported_functions
-  * @{
-  */
-
-extern void SystemInit(void);
-extern void system_core_clock_update(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_acc.h

@@ -1,202 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_acc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 acc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_ACC_H
-#define __AT32F403A_407_ACC_H
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup ACC
-  * @{
-  */
-
-/** @defgroup ACC_exported_constants
-  * @{
-  */
-
-#define ACC_CAL_HICKCAL                  ((uint16_t)0x0000) /*!< acc hick calibration */
-#define ACC_CAL_HICKTRIM                 ((uint16_t)0x0002) /*!< acc hick trim */
-
-#define ACC_RSLOST_FLAG                  ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
-#define ACC_CALRDY_FLAG                  ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
-
-#define ACC_CALRDYIEN_INT                ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
-#define ACC_EIEN_INT                     ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
-
-/**
-  * @}
-  */
-
-/** @defgroup ACC_exported_types
-  * @{
-  */
-
-/**
-  * @brief type define acc register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief acc sts register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t calrdy               : 1; /* [0] */
-      __IO uint32_t rslost               : 1; /* [1] */
-      __IO uint32_t reserved1            : 30;/* [31:2] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief acc ctrl1 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t calon                : 1; /* [0] */
-      __IO uint32_t entrim               : 1; /* [1] */
-      __IO uint32_t reserved1            : 2; /* [3:2] */
-      __IO uint32_t eien                 : 1; /* [4] */
-      __IO uint32_t calrdyien            : 1; /* [5] */
-      __IO uint32_t reserved2            : 2; /* [7:6] */
-      __IO uint32_t step                 : 4; /* [11:8] */
-      __IO uint32_t reserved3            : 20;/* [31:12] */
-    } ctrl1_bit;
-  };
-
-   /**
-    * @brief acc ctrl2 register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t hickcal              : 8; /* [7:0] */
-      __IO uint32_t hicktrim             : 6; /* [13:8] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } ctrl2_bit;
-  };
-
-  /**
-  * @brief acc acc_c1 register, offset:0x0C
-  */
-  union
-  {
-    __IO uint32_t c1;
-    struct
-    {
-      __IO uint32_t c1                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } c1_bit;
-  };
-
-  /**
-  * @brief acc acc_c2 register, offset:0x10
-  */
-  union
-  {
-    __IO uint32_t c2;
-    struct
-    {
-      __IO uint32_t c2                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } c2_bit;
-  };
-
-  /**
-  * @brief acc acc_c3 register, offset:0x14
-  */
-  union
-  {
-    __IO uint32_t c3;
-    struct
-    {
-      __IO uint32_t c3                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } c3_bit;
-  };
-} acc_type;
-
-/**
-  * @}
-  */
-
-#define ACC                             ((acc_type *) ACC_BASE)
-
-/** @defgroup ACC_exported_functions
-  * @{
-  */
-
-void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
-void acc_step_set(uint8_t step_value);
-void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
-uint8_t acc_hicktrim_get(void);
-uint8_t acc_hickcal_get(void);
-void acc_write_c1(uint16_t acc_c1_value);
-void acc_write_c2(uint16_t acc_c2_value);
-void acc_write_c3(uint16_t acc_c3_value);
-uint16_t acc_read_c1(void);
-uint16_t acc_read_c2(void);
-uint16_t acc_read_c3(void);
-flag_status acc_flag_get(uint16_t acc_flag);
-void acc_flag_clear(uint16_t acc_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_adc.h

@@ -1,642 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_adc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 adc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_ADC_H
-#define __AT32F403A_407_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/** @defgroup ADC_interrupts_definition
-  * @brief adc interrupt
-  * @{
-  */
-
-#define ADC_CCE_INT                      ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
-#define ADC_VMOR_INT                     ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
-#define ADC_PCCE_INT                     ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition
-  * @brief adc flag
-  * @{
-  */
-
-#define ADC_VMOR_FLAG                    ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
-#define ADC_CCE_FLAG                     ((uint8_t)0x02) /*!< channels conversion end flag */
-#define ADC_PCCE_FLAG                    ((uint8_t)0x04) /*!< preempt channels conversion end flag */
-#define ADC_PCCS_FLAG                    ((uint8_t)0x08) /*!< preempt channel conversion start flag */
-#define ADC_OCCS_FLAG                    ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_exported_types
-  * @{
-  */
-
-/**
-  * @brief adc combine mode type(these options are reserved in adc2 and adc3)
-  */
-typedef enum
-{
-  ADC_INDEPENDENT_MODE                      = 0x00, /*!< independent mode */
-  ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE       = 0x01, /*!< combined ordinary simultaneous + preempt simultaneous mode */
-  ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE = 0x02, /*!< combined ordinary simultaneous + preempt interleaved trigger mode */
-  ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE = 0x03, /*!< combined ordinary short shifting + preempt simultaneous mode */
-  ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE  = 0x04, /*!< combined ordinary long shifting + preempt simultaneous mode */
-  ADC_PREEMPT_SMLT_ONLY_MODE                = 0x05, /*!< preempt simultaneous mode only */
-  ADC_ORDINARY_SMLT_ONLY_MODE               = 0x06, /*!< ordinary simultaneous mode only */
-  ADC_ORDINARY_SHORTSHIFT_ONLY_MODE         = 0x07, /*!< ordinary short shifting mode only */
-  ADC_ORDINARY_LONGSHIFT_ONLY_MODE          = 0x08, /*!< slow interleaved mode only */
-  ADC_PREEMPT_INTERLTRIG_ONLY_MODE          = 0x09  /*!< alternate trigger mode only */
-} adc_combine_mode_type;
-
-/**
-  * @brief adc data align type
-  */
-typedef enum
-{
-  ADC_RIGHT_ALIGNMENT                    = 0x00, /*!< data right alignment */
-  ADC_LEFT_ALIGNMENT                     = 0x01  /*!< data left alignment */
-} adc_data_align_type;
-
-/**
-  * @brief adc channel select type
-  */
-typedef enum
-{
-  ADC_CHANNEL_0                          = 0x00, /*!< adc channel 0 */
-  ADC_CHANNEL_1                          = 0x01, /*!< adc channel 1 */
-  ADC_CHANNEL_2                          = 0x02, /*!< adc channel 2 */
-  ADC_CHANNEL_3                          = 0x03, /*!< adc channel 3 */
-  ADC_CHANNEL_4                          = 0x04, /*!< adc channel 4 */
-  ADC_CHANNEL_5                          = 0x05, /*!< adc channel 5 */
-  ADC_CHANNEL_6                          = 0x06, /*!< adc channel 6 */
-  ADC_CHANNEL_7                          = 0x07, /*!< adc channel 7 */
-  ADC_CHANNEL_8                          = 0x08, /*!< adc channel 8 */
-  ADC_CHANNEL_9                          = 0x09, /*!< adc channel 9 */
-  ADC_CHANNEL_10                         = 0x0A, /*!< adc channel 10 */
-  ADC_CHANNEL_11                         = 0x0B, /*!< adc channel 11 */
-  ADC_CHANNEL_12                         = 0x0C, /*!< adc channel 12 */
-  ADC_CHANNEL_13                         = 0x0D, /*!< adc channel 13 */
-  ADC_CHANNEL_14                         = 0x0E, /*!< adc channel 14 */
-  ADC_CHANNEL_15                         = 0x0F, /*!< adc channel 15 */
-  ADC_CHANNEL_16                         = 0x10, /*!< adc channel 16 */
-  ADC_CHANNEL_17                         = 0x11  /*!< adc channel 17 */
-} adc_channel_select_type;
-
-/**
-  * @brief adc sampletime select type
-  */
-typedef enum
-{
-  ADC_SAMPLETIME_1_5                     = 0x00, /*!< adc sample time 1.5 cycle */
-  ADC_SAMPLETIME_7_5                     = 0x01, /*!< adc sample time 7.5 cycle */
-  ADC_SAMPLETIME_13_5                    = 0x02, /*!< adc sample time 13.5 cycle */
-  ADC_SAMPLETIME_28_5                    = 0x03, /*!< adc sample time 28.5 cycle */
-  ADC_SAMPLETIME_41_5                    = 0x04, /*!< adc sample time 41.5 cycle */
-  ADC_SAMPLETIME_55_5                    = 0x05, /*!< adc sample time 55.5 cycle */
-  ADC_SAMPLETIME_71_5                    = 0x06, /*!< adc sample time 71.5 cycle */
-  ADC_SAMPLETIME_239_5                   = 0x07  /*!< adc sample time 239.5 cycle */
-} adc_sampletime_select_type;
-
-/**
-  * @brief adc ordinary group trigger event select type
-  */
-typedef enum
-{
-  /*adc1 and adc2 ordinary trigger event*/
-  ADC12_ORDINARY_TRIG_TMR1CH1            = 0x00, /*!< timer1 ch1 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR1CH2            = 0x01, /*!< timer1 ch2 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR1CH3            = 0x02, /*!< timer1 ch3 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR2CH2            = 0x03, /*!< timer2 ch2 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR3TRGOUT         = 0x04, /*!< timer3 trgout event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR4CH4            = 0x05, /*!< timer4 ch4 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT = 0x06, /*!< exint line11/timer8 trgout event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_SOFTWARE           = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR1TRGOUT         = 0x0D, /*!< timer1 trgout event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR8CH1            = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 ordinary sequence */
-  ADC12_ORDINARY_TRIG_TMR8CH2            = 0x0F, /*!< timer8 ch2 event as trigger source of adc1/adc2 ordinary sequence */
-  /*adc3 ordinary trigger event*/
-  ADC3_ORDINARY_TRIG_TMR3CH1             = 0x00, /*!< timer3 ch1 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR2CH3             = 0x01, /*!< timer2 ch3 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR1CH3             = 0x02, /*!< timer1 ch3 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR8CH1             = 0x03, /*!< timer8 ch1 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR8TRGOUT          = 0x04, /*!< timer8 trgout event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR5CH1             = 0x05, /*!< timer5 ch1 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR5CH3             = 0x06, /*!< timer5 ch3 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_SOFTWARE            = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR1TRGOUT          = 0x0D, /*!< timer1 trgout event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR1CH1             = 0x0E, /*!< timer1 ch1 event as trigger source of adc3 ordinary sequence */
-  ADC3_ORDINARY_TRIG_TMR8CH3             = 0x0F  /*!< timer8 ch3 event as trigger source of adc3 ordinary sequence */
-} adc_ordinary_trig_select_type;
-
-/**
-  * @brief adc preempt group trigger event select type
-  */
-typedef enum
-{
-  /*adc1 and adc2 preempt trigger event*/
-  ADC12_PREEMPT_TRIG_TMR1TRGOUT          = 0x00, /*!< timer1 trgout event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR1CH4             = 0x01, /*!< timer1 ch4 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR2TRGOUT          = 0x02, /*!< timer2 trgout event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR2CH1             = 0x03, /*!< timer2 ch1 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR3CH4             = 0x04, /*!< timer3 ch4 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR4TRGOUT          = 0x05, /*!< timer4 trgout event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4     = 0x06, /*!< exint line15/timer8 ch4 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_SOFTWARE            = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR1CH1             = 0x0D, /*!< timer1 ch1 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR8CH1             = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 preempt sequence */
-  ADC12_PREEMPT_TRIG_TMR8TRGOUT          = 0x0F, /*!< timer8 trgout event as trigger source of adc1/adc2 preempt sequence */
-  /*adc3 preempt trigger event*/
-  ADC3_PREEMPT_TRIG_TMR1TRGOUT           = 0x00, /*!< timer1 trgout event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR1CH4              = 0x01, /*!< timer1 ch4 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR4CH3              = 0x02, /*!< timer4 ch3 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR8CH2              = 0x03, /*!< timer8 ch2 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR8CH4              = 0x04, /*!< timer8 ch4 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR5TRGOUT           = 0x05, /*!< timer5 trgout event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR5CH4              = 0x06, /*!< timer5 ch4 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_SOFTWARE             = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR1CH1              = 0x0D, /*!< timer1 ch1 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR1CH2              = 0x0E, /*!< timer1 ch2 event as trigger source of adc3 preempt sequence */
-  ADC3_PREEMPT_TRIG_TMR8TRGOUT           = 0x0F  /*!< timer8 trgout event as trigger source of adc3 preempt sequence */
-} adc_preempt_trig_select_type;
-
-/**
-  * @brief adc preempt channel type
-  */
-typedef enum
-{
-  ADC_PREEMPT_CHANNEL_1                  = 0x00, /*!< adc preempt channel 1 */
-  ADC_PREEMPT_CHANNEL_2                  = 0x01, /*!< adc preempt channel 2 */
-  ADC_PREEMPT_CHANNEL_3                  = 0x02, /*!< adc preempt channel 3 */
-  ADC_PREEMPT_CHANNEL_4                  = 0x03  /*!< adc preempt channel 4 */
-} adc_preempt_channel_type;
-
-/**
-  * @brief adc voltage_monitoring type
-  */
-typedef enum
-{
-  ADC_VMONITOR_SINGLE_ORDINARY           = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
-  ADC_VMONITOR_SINGLE_PREEMPT            = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
-  ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT   = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
-  ADC_VMONITOR_ALL_ORDINARY              = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
-  ADC_VMONITOR_ALL_PREEMPT               = 0x00400000, /*!< voltage_monitoring on all preempt channel */
-  ADC_VMONITOR_ALL_ORDINARY_PREEMPT      = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
-  ADC_VMONITOR_NONE                      = 0x00000000  /*!< no channel guarded by the voltage_monitoring */
-} adc_voltage_monitoring_type;
-
-/**
-  * @brief adc base config type
-  */
-typedef struct
-{
-  confirm_state                          sequence_mode;           /*!< adc sequence mode */
-  confirm_state                          repeat_mode;             /*!< adc repeat mode */
-  adc_data_align_type                    data_align;              /*!< adc data alignment */
-  uint8_t                                ordinary_channel_length; /*!< adc ordinary channel sequence length*/
-} adc_base_config_type;
-
-/**
-  * @brief type define adc register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief adc sts register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t vmor                 : 1; /* [0] */
-      __IO uint32_t cce                  : 1; /* [1] */
-      __IO uint32_t pcce                 : 1; /* [2] */
-      __IO uint32_t pccs                 : 1; /* [3] */
-      __IO uint32_t occs                 : 1; /* [4] */
-      __IO uint32_t reserved1            : 27;/* [31:5] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief adc ctrl1 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t vmcsel               : 5; /* [4:0] */
-      __IO uint32_t cceien               : 1; /* [5] */
-      __IO uint32_t vmorien              : 1; /* [6] */
-      __IO uint32_t pcceien              : 1; /* [7] */
-      __IO uint32_t sqen                 : 1; /* [8] */
-      __IO uint32_t vmsgen               : 1; /* [9] */
-      __IO uint32_t pcautoen             : 1; /* [10] */
-      __IO uint32_t ocpen                : 1; /* [11] */
-      __IO uint32_t pcpen                : 1; /* [12] */
-      __IO uint32_t ocpcnt               : 3; /* [15:13] */
-      __IO uint32_t mssel                : 4; /* [19:16] */
-      __IO uint32_t reserved1            : 2; /* [21:20] */
-      __IO uint32_t pcvmen               : 1; /* [22] */
-      __IO uint32_t ocvmen               : 1; /* [23] */
-      __IO uint32_t reserved2            : 8; /* [31:24] */
-    } ctrl1_bit;
-  };
-
-   /**
-    * @brief adc ctrl2 register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t adcen                : 1; /* [0] */
-      __IO uint32_t rpen                 : 1; /* [1] */
-      __IO uint32_t adcal                : 1; /* [2] */
-      __IO uint32_t adcalinit            : 1; /* [3] */
-      __IO uint32_t reserved1            : 4; /* [7:4] */
-      __IO uint32_t ocdmaen              : 1; /* [8] */
-      __IO uint32_t reserved2            : 2; /* [10:9] */
-      __IO uint32_t dtalign              : 1; /* [11] */
-      __IO uint32_t pctesel_l            : 3; /* [14:12] */
-      __IO uint32_t pcten                : 1; /* [15] */
-      __IO uint32_t reserved3            : 1; /* [16] */
-      __IO uint32_t octesel_l            : 3; /* [19:17] */
-      __IO uint32_t octen                : 1; /* [20] */
-      __IO uint32_t pcswtrg              : 1; /* [21] */
-      __IO uint32_t ocswtrg              : 1; /* [22] */
-      __IO uint32_t itsrven              : 1; /* [23] */
-      __IO uint32_t pctesel_h            : 1; /* [24] */
-      __IO uint32_t octesel_h            : 1; /* [25] */
-      __IO uint32_t reserved4            : 6; /* [31:26] */
-    } ctrl2_bit;
-  };
-
-  /**
-  * @brief adc spt1 register, offset:0x0C
-  */
-  union
-  {
-    __IO uint32_t spt1;
-    struct
-    {
-      __IO uint32_t cspt10               : 3; /* [2:0] */
-      __IO uint32_t cspt11               : 3; /* [5:3] */
-      __IO uint32_t cspt12               : 3; /* [8:6] */
-      __IO uint32_t cspt13               : 3; /* [11:9] */
-      __IO uint32_t cspt14               : 3; /* [14:12] */
-      __IO uint32_t cspt15               : 3; /* [17:15] */
-      __IO uint32_t cspt16               : 3; /* [20:18] */
-      __IO uint32_t cspt17               : 3; /* [23:21] */
-      __IO uint32_t reserved1            : 8;/* [31:24] */
-    } spt1_bit;
-  };
-
-  /**
-  * @brief adc spt2 register, offset:0x10
-  */
-  union
-  {
-    __IO uint32_t spt2;
-    struct
-    {
-      __IO uint32_t cspt0                : 3;/* [2:0] */
-      __IO uint32_t cspt1                : 3;/* [5:3] */
-      __IO uint32_t cspt2                : 3;/* [8:6] */
-      __IO uint32_t cspt3                : 3;/* [11:9] */
-      __IO uint32_t cspt4                : 3;/* [14:12] */
-      __IO uint32_t cspt5                : 3;/* [17:15] */
-      __IO uint32_t cspt6                : 3;/* [20:18] */
-      __IO uint32_t cspt7                : 3;/* [23:21] */
-      __IO uint32_t cspt8                : 3;/* [26:24] */
-      __IO uint32_t cspt9                : 3;/* [29:27] */
-      __IO uint32_t reserved1            : 2;/* [31:30] */
-    } spt2_bit;
-  };
-
-  /**
-  * @brief adc pcdto1 register, offset:0x14
-  */
-  union
-  {
-    __IO uint32_t pcdto1;
-    struct
-    {
-      __IO uint32_t pcdto1               : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } pcdto1_bit;
-  };
-
-  /**
-  * @brief adc pcdto2 register, offset:0x18
-  */
-  union
-  {
-    __IO uint32_t pcdto2;
-    struct
-    {
-      __IO uint32_t pcdto2               : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } pcdto2_bit;
-  };
-
-  /**
-  * @brief adc pcdto3 register, offset:0x1C
-  */
-  union
-  {
-    __IO uint32_t pcdto3;
-    struct
-    {
-      __IO uint32_t pcdto3               : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } pcdto3_bit;
-  };
-
-  /**
-  * @brief adc pcdto4 register, offset:0x20
-  */
-  union
-  {
-    __IO uint32_t pcdto4;
-    struct
-    {
-      __IO uint32_t pcdto4               : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } pcdto4_bit;
-  };
-
-  /**
-  * @brief adc vmhb register, offset:0x24
-  */
-  union
-  {
-    __IO uint32_t vmhb;
-    struct
-    {
-      __IO uint32_t vmhb                 : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } vmhb_bit;
-  };
-
-  /**
-  * @brief adc vmlb register, offset:0x28
-  */
-  union
-  {
-    __IO uint32_t vmlb;
-    struct
-    {
-      __IO uint32_t vmlb                 : 12; /* [11:0] */
-      __IO uint32_t reserved1            : 20; /* [31:12] */
-    } vmlb_bit;
-  };
-
-  /**
-  * @brief adc osq1 register, offset:0x2C
-  */
-  union
-  {
-    __IO uint32_t osq1;
-    struct
-    {
-      __IO uint32_t osn13                : 5; /* [4:0] */
-      __IO uint32_t osn14                : 5; /* [9:5] */
-      __IO uint32_t osn15                : 5; /* [14:10] */
-      __IO uint32_t osn16                : 5; /* [19:15] */
-      __IO uint32_t oclen                : 4; /* [23:20] */
-      __IO uint32_t reserved1            : 8; /* [31:24] */
-    } osq1_bit;
-  };
-
-  /**
-  * @brief adc osq2 register, offset:0x30
-  */
-  union
-  {
-    __IO uint32_t osq2;
-    struct
-    {
-      __IO uint32_t osn7                 : 5; /* [4:0] */
-      __IO uint32_t osn8                 : 5; /* [9:5] */
-      __IO uint32_t osn9                 : 5; /* [14:10] */
-      __IO uint32_t osn10                : 5; /* [19:15] */
-      __IO uint32_t osn11                : 5; /* [24:20] */
-      __IO uint32_t osn12                : 5; /* [29:25] */
-      __IO uint32_t reserved1            : 2; /* [31:30] */
-    } osq2_bit;
-  };
-
-  /**
-  * @brief adc osq3 register, offset:0x34
-  */
-  union
-  {
-    __IO uint32_t osq3;
-    struct
-    {
-      __IO uint32_t osn1                 : 5; /* [4:0] */
-      __IO uint32_t osn2                 : 5; /* [9:5] */
-      __IO uint32_t osn3                 : 5; /* [14:10] */
-      __IO uint32_t osn4                 : 5; /* [19:15] */
-      __IO uint32_t osn5                 : 5; /* [24:20] */
-      __IO uint32_t osn6                 : 5; /* [29:25] */
-      __IO uint32_t reserved1            : 2; /* [31:30] */
-    } osq3_bit;
-  };
-
-  /**
-  * @brief adc psq register, offset:0x38
-  */
-  union
-  {
-    __IO uint32_t psq;
-    struct
-    {
-      __IO uint32_t psn1                 : 5; /* [4:0] */
-      __IO uint32_t psn2                 : 5; /* [9:5] */
-      __IO uint32_t psn3                 : 5; /* [14:10] */
-      __IO uint32_t psn4                 : 5; /* [19:15] */
-      __IO uint32_t pclen                : 2; /* [21:20] */
-      __IO uint32_t reserved1            : 10;/* [31:22] */
-    } psq_bit;
-  };
-
-  /**
-  * @brief adc pdt1 register, offset:0x3C
-  */
-  union
-  {
-    __IO uint32_t pdt1;
-    struct
-    {
-      __IO uint32_t pdt1                 : 16; /* [15:0] */
-      __IO uint32_t reserved1            : 16; /* [31:16] */
-    } pdt1_bit;
-  };
-
-  /**
-  * @brief adc pdt2 register, offset:0x40
-  */
-  union
-  {
-    __IO uint32_t pdt2;
-    struct
-    {
-      __IO uint32_t pdt2                 : 16; /* [15:0] */
-      __IO uint32_t reserved1            : 16; /* [31:16] */
-    } pdt2_bit;
-  };
-
-  /**
-  * @brief adc pdt3 register, offset:0x44
-  */
-  union
-  {
-    __IO uint32_t pdt3;
-    struct
-    {
-      __IO uint32_t pdt3                 : 16; /* [15:0] */
-      __IO uint32_t reserved1            : 16; /* [31:16] */
-    } pdt3_bit;
-  };
-
-  /**
-  * @brief adc pdt4 register, offset:0x48
-  */
-  union
-  {
-    __IO uint32_t pdt4;
-    struct
-    {
-      __IO uint32_t pdt4                 : 16; /* [15:0] */
-      __IO uint32_t reserved1            : 16; /* [31:16] */
-    } pdt4_bit;
-  };
-
-  /**
-  * @brief adc odt register, offset:0x4C
-  */
-  union
-  {
-    __IO uint32_t odt;
-    struct
-    {
-      __IO uint32_t odt                  : 16; /* [15:0] */
-      __IO uint32_t adc2odt              : 16; /* [31:16] */
-    } odt_bit;
-  };
-
-} adc_type;
-
-/**
-  * @}
-  */
-
-#define ADC1                             ((adc_type *) ADC1_BASE)
-#define ADC2                             ((adc_type *) ADC2_BASE)
-#define ADC3                             ((adc_type *) ADC3_BASE)
-
-/** @defgroup ADC_exported_functions
-  * @{
-  */
-
-void adc_reset(adc_type *adc_x);
-void adc_enable(adc_type *adc_x, confirm_state new_state);
-void adc_combine_mode_select(adc_combine_mode_type combine_mode);
-void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
-void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
-void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
-void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
-void adc_calibration_init(adc_type *adc_x);
-flag_status adc_calibration_init_status_get(adc_type *adc_x);
-void adc_calibration_start(adc_type *adc_x);
-flag_status adc_calibration_status_get(adc_type *adc_x);
-void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
-void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
-void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
-void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
-void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
-void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
-void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state);
-void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state);
-void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
-void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
-void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
-void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
-void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
-void adc_tempersensor_vintrv_enable(confirm_state new_state);
-void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
-flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
-void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
-flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
-uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
-uint32_t adc_combine_ordinary_conversion_data_get(void);
-uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
-flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
-void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_bpr.h

@@ -1,789 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_bpr.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 bpr header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_BPR_H
-#define __AT32F403A_407_BPR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup BPR
-  * @{
-  */
-
-/** @defgroup BPR_flags_definition
-  * @brief bpr flag
-  * @{
-  */
-
-#define BPR_TAMPER_INTERRUPT_FLAG        ((uint32_t)0x00000001) /*!< bpr tamper interrupt flag */
-#define BPR_TAMPER_EVENT_FLAG            ((uint32_t)0x00000002) /*!< bpr tamper event flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup BPR_exported_types
-  * @{
-  */
-
-/**
-  * @brief battery powered register data type
-  */
-typedef enum
-{
-  BPR_DATA1                              = 0x04, /*!< bpr data register 1 */
-  BPR_DATA2                              = 0x08, /*!< bpr data register 2 */
-  BPR_DATA3                              = 0x0C, /*!< bpr data register 3 */
-  BPR_DATA4                              = 0x10, /*!< bpr data register 4 */
-  BPR_DATA5                              = 0x14, /*!< bpr data register 5 */
-  BPR_DATA6                              = 0x18, /*!< bpr data register 6 */
-  BPR_DATA7                              = 0x1C, /*!< bpr data register 7 */
-  BPR_DATA8                              = 0x20, /*!< bpr data register 8 */
-  BPR_DATA9                              = 0x24, /*!< bpr data register 9 */
-  BPR_DATA10                             = 0x28, /*!< bpr data register 10 */
-  BPR_DATA11                             = 0x40, /*!< bpr data register 11 */
-  BPR_DATA12                             = 0x44, /*!< bpr data register 12 */
-  BPR_DATA13                             = 0x48, /*!< bpr data register 13 */
-  BPR_DATA14                             = 0x4C, /*!< bpr data register 14 */
-  BPR_DATA15                             = 0x50, /*!< bpr data register 15 */
-  BPR_DATA16                             = 0x54, /*!< bpr data register 16 */
-  BPR_DATA17                             = 0x58, /*!< bpr data register 17 */
-  BPR_DATA18                             = 0x5C, /*!< bpr data register 18 */
-  BPR_DATA19                             = 0x60, /*!< bpr data register 19 */
-  BPR_DATA20                             = 0x64, /*!< bpr data register 20 */
-  BPR_DATA21                             = 0x68, /*!< bpr data register 21 */
-  BPR_DATA22                             = 0x6C, /*!< bpr data register 22 */
-  BPR_DATA23                             = 0x70, /*!< bpr data register 23 */
-  BPR_DATA24                             = 0x74, /*!< bpr data register 24 */
-  BPR_DATA25                             = 0x78, /*!< bpr data register 25 */
-  BPR_DATA26                             = 0x7C, /*!< bpr data register 26 */
-  BPR_DATA27                             = 0x80, /*!< bpr data register 27 */
-  BPR_DATA28                             = 0x84, /*!< bpr data register 28 */
-  BPR_DATA29                             = 0x88, /*!< bpr data register 29 */
-  BPR_DATA30                             = 0x8C, /*!< bpr data register 30 */
-  BPR_DATA31                             = 0x90, /*!< bpr data register 31 */
-  BPR_DATA32                             = 0x94, /*!< bpr data register 32 */
-  BPR_DATA33                             = 0x98, /*!< bpr data register 33 */
-  BPR_DATA34                             = 0x9C, /*!< bpr data register 34 */
-  BPR_DATA35                             = 0xA0, /*!< bpr data register 35 */
-  BPR_DATA36                             = 0xA4, /*!< bpr data register 36 */
-  BPR_DATA37                             = 0xA8, /*!< bpr data register 37 */
-  BPR_DATA38                             = 0xAC, /*!< bpr data register 38 */
-  BPR_DATA39                             = 0xB0, /*!< bpr data register 39 */
-  BPR_DATA40                             = 0xB4, /*!< bpr data register 40 */
-  BPR_DATA41                             = 0xB8, /*!< bpr data register 41 */
-  BPR_DATA42                             = 0xBC  /*!< bpr data register 42 */
-} bpr_data_type;
-
-/**
-  * @brief bpr rtc output type
-  */
-typedef enum
-{
-  BPR_RTC_OUTPUT_NONE                    = 0x000, /*!< output disable */
-  BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE        = 0x080, /*!< output clock before calibration */
-  BPR_RTC_OUTPUT_ALARM                   = 0x100, /*!< output alarm event with pluse mode */
-  BPR_RTC_OUTPUT_SECOND                  = 0x300, /*!< output second event with pluse mode */
-  BPR_RTC_OUTPUT_CLOCK_CAL_AFTER         = 0x480, /*!< output clock after calibration */
-  BPR_RTC_OUTPUT_ALARM_TOGGLE            = 0x900, /*!< output alarm event with toggle mode */
-  BPR_RTC_OUTPUT_SECOND_TOGGLE           = 0xB00  /*!< output second event with toggle mode */
-} bpr_rtc_output_type;
-
-/**
-  * @brief tamper pin active level type
-  */
-typedef enum
-{
-  BPR_TAMPER_PIN_ACTIVE_HIGH             = 0x00, /*!< tamper pin input active level is high */
-  BPR_TAMPER_PIN_ACTIVE_LOW              = 0x01  /*!< tamper pin input active level is low */
-} bpr_tamper_pin_active_level_type;
-
-/**
-  * @brief type define bpr register all
-  */
-typedef struct
-{
-  /**
-    * @brief reserved, offset:0x00
-    */
-  __IO uint32_t reserved1;
-
-  /**
-    * @brief bpr dt1 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t dt1;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt1_bit;
-  };
-
-  /**
-    * @brief bpr dt2 register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t dt2;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt2_bit;
-  };
-
-  /**
-    * @brief bpr dt3 register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t dt3;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt3_bit;
-  };
-
-  /**
-    * @brief bpr dt4 register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t dt4;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt4_bit;
-  };
-
-  /**
-    * @brief bpr dt5 register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t dt5;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt5_bit;
-  };
-
-  /**
-    * @brief bpr dt6 register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t dt6;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt6_bit;
-  };
-
-  /**
-    * @brief bpr dt7 register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t dt7;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt7_bit;
-  };
-
-  /**
-    * @brief bpr dt8 register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t dt8;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt8_bit;
-  };
-
-  /**
-    * @brief bpr dt9 register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t dt9;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt9_bit;
-  };
-
-  /**
-    * @brief bpr dt10 register, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t dt10;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt10_bit;
-  };
-
-  /**
-    * @brief bpr rtccal register, offset:0x2C
-    */
-  union
-  {
-    __IO uint32_t rtccal;
-    struct
-    {
-      __IO uint32_t calval               : 7; /* [6:0] */
-      __IO uint32_t calout               : 1; /* [7] */
-      __IO uint32_t outen                : 1; /* [8] */
-      __IO uint32_t outsel               : 1; /* [9] */
-      __IO uint32_t ccos                 : 1; /* [10] */
-      __IO uint32_t outm                 : 1; /* [11] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } rtccal_bit;
-  };
-
-  /**
-    * @brief bpr ctrl register, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t tpen                 : 1; /* [0] */
-      __IO uint32_t tpp                  : 1; /* [1] */
-      __IO uint32_t reserved1            : 30;/* [31:2] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief bpr ctrlsts register, offset:0x34
-    */
-  union
-  {
-    __IO uint32_t ctrlsts;
-    struct
-    {
-      __IO uint32_t tpefclr              : 1;/* [0] */
-      __IO uint32_t tpifclr              : 1;/* [1] */
-      __IO uint32_t tpien                : 1;/* [2] */
-      __IO uint32_t reserved1            : 5;/* [7:3] */
-      __IO uint32_t tpef                 : 1;/* [8] */
-      __IO uint32_t tpif                 : 1;/* [9] */
-      __IO uint32_t reserved2            : 22;/* [31:10] */
-    } ctrlsts_bit;
-  };
-
-  /**
-    * @brief reserved, offset:0x38
-    */
-  __IO uint32_t reserved2;
-
-  /**
-    * @brief reserved, offset:0x3C
-    */
-  __IO uint32_t reserved3;
-
-  /**
-    * @brief bpr dt11 register, offset:0x40
-    */
-  union
-  {
-    __IO uint32_t dt11;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt11_bit;
-  };
-
-  /**
-    * @brief bpr dt12 register, offset:0x44
-    */
-  union
-  {
-    __IO uint32_t dt12;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt12_bit;
-  };
-
-  /**
-    * @brief bpr dt13 register, offset:0x48
-    */
-  union
-  {
-    __IO uint32_t dt13;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt13_bit;
-  };
-
-  /**
-    * @brief bpr dt14 register, offset:0x4C
-    */
-  union
-  {
-    __IO uint32_t dt14;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt14_bit;
-  };
-
-  /**
-    * @brief bpr dt15 register, offset:0x50
-    */
-  union
-  {
-    __IO uint32_t dt15;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt15_bit;
-  };
-
-  /**
-    * @brief bpr dt16 register, offset:0x54
-    */
-  union
-  {
-    __IO uint32_t dt16;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt16_bit;
-  };
-
-  /**
-    * @brief bpr dt17 register, offset:0x58
-    */
-  union
-  {
-    __IO uint32_t dt17;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt17_bit;
-  };
-
-  /**
-    * @brief bpr dt18 register, offset:0x5C
-    */
-  union
-  {
-    __IO uint32_t dt18;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt18_bit;
-  };
-
-  /**
-    * @brief bpr dt19 register, offset:0x60
-    */
-  union
-  {
-    __IO uint32_t dt19;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt19_bit;
-  };
-
-  /**
-    * @brief bpr dt20 register, offset:0x64
-    */
-  union
-  {
-    __IO uint32_t dt20;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt20_bit;
-  };
-
-  /**
-    * @brief bpr dt21 register, offset:0x68
-    */
-  union
-  {
-    __IO uint32_t dt21;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt21_bit;
-  };
-
-  /**
-    * @brief bpr dt22 register, offset:6C
-    */
-  union
-  {
-    __IO uint32_t dt22;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt22_bit;
-  };
-
-  /**
-    * @brief bpr dt23 register, offset:0x70
-    */
-  union
-  {
-    __IO uint32_t dt23;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt23_bit;
-  };
-
-  /**
-    * @brief bpr dt24 register, offset:0x74
-    */
-  union
-  {
-    __IO uint32_t dt24;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt24_bit;
-  };
-
-  /**
-    * @brief bpr dt25 register, offset:0x78
-    */
-  union
-  {
-    __IO uint32_t dt25;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt25_bit;
-  };
-
-  /**
-    * @brief bpr dt26 register, offset:0x7C
-    */
-  union
-  {
-    __IO uint32_t dt26;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt26_bit;
-  };
-
-  /**
-    * @brief bpr dt27 register, offset:0x80
-    */
-  union
-  {
-    __IO uint32_t dt27;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt27_bit;
-  };
-
-  /**
-    * @brief bpr dt28 register, offset:0x84
-    */
-  union
-  {
-    __IO uint32_t dt28;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt28_bit;
-  };
-
-  /**
-    * @brief bpr dt29 register, offset:0x88
-    */
-  union
-  {
-    __IO uint32_t dt29;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt29_bit;
-  };
-
-  /**
-    * @brief bpr dt30 register, offset:0x8C
-    */
-  union
-  {
-    __IO uint32_t dt30;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt30_bit;
-  };
-
-  /**
-    * @brief bpr dt31 register, offset:0x90
-    */
-  union
-  {
-    __IO uint32_t dt31;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt31_bit;
-  };
-
-  /**
-    * @brief bpr dt32 register, offset:0x94
-    */
-  union
-  {
-    __IO uint32_t dt32;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt32_bit;
-  };
-
-  /**
-    * @brief bpr dt33 register, offset:0x98
-    */
-  union
-  {
-    __IO uint32_t dt33;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt33_bit;
-  };
-
-  /**
-    * @brief bpr dt34 register, offset:0x9C
-    */
-  union
-  {
-    __IO uint32_t dt34;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt34_bit;
-  };
-
-  /**
-    * @brief bpr dt35 register, offset:0xA0
-    */
-  union
-  {
-    __IO uint32_t dt35;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt35_bit;
-  };
-
-  /**
-    * @brief bpr dt36 register, offset:0xA4
-    */
-  union
-  {
-    __IO uint32_t dt36;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt36_bit;
-  };
-
-  /**
-    * @brief bpr dt37 register, offset:0xA8
-    */
-  union
-  {
-    __IO uint32_t dt37;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt37_bit;
-  };
-
-  /**
-    * @brief bpr dt38 register, offset:0xAC
-    */
-  union
-  {
-    __IO uint32_t dt38;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt38_bit;
-  };
-
-  /**
-    * @brief bpr dt39 register, offset:0xB0
-    */
-  union
-  {
-    __IO uint32_t dt39;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt39_bit;
-  };
-
-  /**
-    * @brief bpr dt40 register, offset:0xB4
-    */
-  union
-  {
-    __IO uint32_t dt40;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt40_bit;
-  };
-
-  /**
-    * @brief bpr dt41 register, offset:0xB8
-    */
-  union
-  {
-    __IO uint32_t dt41;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt41_bit;
-  };
-
-  /**
-    * @brief bpr dt42 register, offset:0xBC
-    */
-  union
-  {
-    __IO uint32_t dt42;
-    struct
-    {
-      __IO uint32_t dt                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } dt42_bit;
-  };
-} bpr_type;
-
-/**
-  * @}
-  */
-
-#define BPR                              ((bpr_type *) BPR_BASE)
-
-/** @defgroup BPR_exported_functions
-  * @{
-  */
-
-void bpr_reset(void);
-flag_status bpr_flag_get(uint32_t flag);
-void bpr_flag_clear(uint32_t flag);
-void bpr_interrupt_enable(confirm_state new_state);
-uint16_t bpr_data_read(bpr_data_type bpr_data);
-void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value);
-void bpr_rtc_output_select(bpr_rtc_output_type output_source);
-void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value);
-void bpr_tamper_pin_enable(confirm_state new_state);
-void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_can.h

@@ -1,986 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_can.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 can header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_CAN_H
-#define __AT32F403A_407_CAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-
-/** @defgroup CAN_timeout_count
-  * @{
-  */
-
-#define FZC_TIMEOUT                      ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
-#define DZC_TIMEOUT                      ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags_definition
-  * @brief can flag
-  * @{
-  */
-
-#define CAN_EAF_FLAG                     ((uint32_t)0x01) /*!< error active flag */
-#define CAN_EPF_FLAG                     ((uint32_t)0x02) /*!< error passive flag */
-#define CAN_BOF_FLAG                     ((uint32_t)0x03) /*!< bus-off flag */
-#define CAN_ETR_FLAG                     ((uint32_t)0x04) /*!< error type record flag */
-#define CAN_EOIF_FLAG                    ((uint32_t)0x05) /*!< error occur interrupt flag */
-#define CAN_TM0TCF_FLAG                  ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
-#define CAN_TM1TCF_FLAG                  ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
-#define CAN_TM2TCF_FLAG                  ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
-#define CAN_RF0MN_FLAG                   ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
-#define CAN_RF0FF_FLAG                   ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
-#define CAN_RF0OF_FLAG                   ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
-#define CAN_RF1MN_FLAG                   ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
-#define CAN_RF1FF_FLAG                   ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
-#define CAN_RF1OF_FLAG                   ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
-#define CAN_QDZIF_FLAG                   ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
-#define CAN_EDZC_FLAG                    ((uint32_t)0x10) /*!< enter doze mode confirm flag */
-#define CAN_TMEF_FLAG                    ((uint32_t)0x11) /*!< transmit mailbox empty flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_interrupts_definition
-  * @brief can interrupt
-  * @{
-  */
-
-#define CAN_TCIEN_INT                    ((uint32_t)0x00000001) /*!< transmission complete interrupt */
-#define CAN_RF0MIEN_INT                  ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
-#define CAN_RF0FIEN_INT                  ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
-#define CAN_RF0OIEN_INT                  ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
-#define CAN_RF1MIEN_INT                  ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
-#define CAN_RF1FIEN_INT                  ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
-#define CAN_RF1OIEN_INT                  ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
-#define CAN_EAIEN_INT                    ((uint32_t)0x00000100) /*!< error active interrupt */
-#define CAN_EPIEN_INT                    ((uint32_t)0x00000200) /*!< error passive interrupt */
-#define CAN_BOIEN_INT                    ((uint32_t)0x00000400) /*!< bus-off interrupt */
-#define CAN_ETRIEN_INT                   ((uint32_t)0x00000800) /*!< error type record interrupt */
-#define CAN_EOIEN_INT                    ((uint32_t)0x00008000) /*!< error occur interrupt */
-#define CAN_QDZIEN_INT                   ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
-#define CAN_EDZIEN_INT                   ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  can flag clear operation macro definition val
-  */
-#define CAN_MSTS_EOIF_VAL                ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
-#define CAN_MSTS_QDZIF_VAL               ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
-#define CAN_MSTS_EDZIF_VAL               ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
-#define CAN_TSTS_TM0TCF_VAL              ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
-#define CAN_TSTS_TM1TCF_VAL              ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
-#define CAN_TSTS_TM2TCF_VAL              ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
-#define CAN_TSTS_TM0CT_VAL               ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
-#define CAN_TSTS_TM1CT_VAL               ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
-#define CAN_TSTS_TM2CT_VAL               ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
-#define CAN_RF0_RF0FF_VAL                ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
-#define CAN_RF0_RF0OF_VAL                ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
-#define CAN_RF0_RF0R_VAL                 ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
-#define CAN_RF1_RF1FF_VAL                ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
-#define CAN_RF1_RF1OF_VAL                ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
-#define CAN_RF1_RF1R_VAL                 ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
-
-/** @defgroup CAN_exported_types
-  * @{
-  */
-
-/**
-  * @brief  can filter fifo
-  */
-typedef enum
-{
-  CAN_FILTER_FIFO0                       = 0x00, /*!< filter fifo 0 assignment for filter x */
-  CAN_FILTER_FIFO1                       = 0x01  /*!< filter fifo 1 assignment for filter x */
-} can_filter_fifo_type;
-
-/**
-  * @brief  can filter mode
-  */
-typedef enum
-{
-  CAN_FILTER_MODE_ID_MASK                = 0x00, /*!< identifier mask mode */
-  CAN_FILTER_MODE_ID_LIST                = 0x01  /*!< identifier list mode */
-} can_filter_mode_type;
-
-/**
-  * @brief  can filter bit width select
-  */
-typedef enum
-{
-  CAN_FILTER_16BIT                       = 0x00, /*!< two 16-bit filters */
-  CAN_FILTER_32BIT                       = 0x01  /*!< one 32-bit filter */
-} can_filter_bit_width_type;
-
-/**
-  * @brief  can mode
-  */
-typedef enum
-{
-  CAN_MODE_COMMUNICATE                   = 0x00, /*!< communication mode */
-  CAN_MODE_LOOPBACK                      = 0x01, /*!< loopback mode */
-  CAN_MODE_LISTENONLY                    = 0x02, /*!< listen-only mode */
-  CAN_MODE_LISTENONLY_LOOPBACK           = 0x03  /*!< loopback combined with listen-only mode */
-} can_mode_type;
-
-/**
-  * @brief  can operating mode
-  */
-typedef enum
-{
-  CAN_OPERATINGMODE_FREEZE               = 0x00, /*!< freeze mode */
-  CAN_OPERATINGMODE_DOZE                 = 0x01, /*!< doze mode */
-  CAN_OPERATINGMODE_COMMUNICATE          = 0x02  /*!< communication mode */
-} can_operating_mode_type;
-
-/**
-  * @brief  can resynchronization adjust width
-  */
-typedef enum
-{
-  CAN_RSAW_1TQ                           = 0x00, /*!< 1 time quantum */
-  CAN_RSAW_2TQ                           = 0x01, /*!< 2 time quantum */
-  CAN_RSAW_3TQ                           = 0x02, /*!< 3 time quantum */
-  CAN_RSAW_4TQ                           = 0x03  /*!< 4 time quantum */
-} can_rsaw_type;
-
-/**
-  * @brief  can bit time segment 1
-  */
-typedef enum
-{
-  CAN_BTS1_1TQ                           = 0x00, /*!< 1 time quantum */
-  CAN_BTS1_2TQ                           = 0x01, /*!< 2 time quantum */
-  CAN_BTS1_3TQ                           = 0x02, /*!< 3 time quantum */
-  CAN_BTS1_4TQ                           = 0x03, /*!< 4 time quantum */
-  CAN_BTS1_5TQ                           = 0x04, /*!< 5 time quantum */
-  CAN_BTS1_6TQ                           = 0x05, /*!< 6 time quantum */
-  CAN_BTS1_7TQ                           = 0x06, /*!< 7 time quantum */
-  CAN_BTS1_8TQ                           = 0x07, /*!< 8 time quantum */
-  CAN_BTS1_9TQ                           = 0x08, /*!< 9 time quantum */
-  CAN_BTS1_10TQ                          = 0x09, /*!< 10 time quantum */
-  CAN_BTS1_11TQ                          = 0x0A, /*!< 11 time quantum */
-  CAN_BTS1_12TQ                          = 0x0B, /*!< 12 time quantum */
-  CAN_BTS1_13TQ                          = 0x0C, /*!< 13 time quantum */
-  CAN_BTS1_14TQ                          = 0x0D, /*!< 14 time quantum */
-  CAN_BTS1_15TQ                          = 0x0E, /*!< 15 time quantum */
-  CAN_BTS1_16TQ                          = 0x0F  /*!< 16 time quantum */
-} can_bts1_type;
-
-/**
-  * @brief  can bit time segment 2
-  */
-typedef enum
-{
-  CAN_BTS2_1TQ                           = 0x00, /*!< 1 time quantum */
-  CAN_BTS2_2TQ                           = 0x01, /*!< 2 time quantum */
-  CAN_BTS2_3TQ                           = 0x02, /*!< 3 time quantum */
-  CAN_BTS2_4TQ                           = 0x03, /*!< 4 time quantum */
-  CAN_BTS2_5TQ                           = 0x04, /*!< 5 time quantum */
-  CAN_BTS2_6TQ                           = 0x05, /*!< 6 time quantum */
-  CAN_BTS2_7TQ                           = 0x06, /*!< 7 time quantum */
-  CAN_BTS2_8TQ                           = 0x07  /*!< 8 time quantum */
-} can_bts2_type;
-
-/**
-  * @brief  can identifier type
-  */
-typedef enum
-{
-  CAN_ID_STANDARD                        = 0x00, /*!< standard Id */
-  CAN_ID_EXTENDED                        = 0x01  /*!< extended Id */
-} can_identifier_type;
-
-/**
-  * @brief  can transmission frame type
-  */
-typedef enum
-{
-  CAN_TFT_DATA                           = 0x00, /*!< data frame */
-  CAN_TFT_REMOTE                         = 0x01  /*!< remote frame */
-} can_trans_frame_type;
-
-/**
-  * @brief  can tx mailboxes
-  */
-typedef enum
-{
-  CAN_TX_MAILBOX0                        = 0x00, /*!< can tx mailbox 0 */
-  CAN_TX_MAILBOX1                        = 0x01, /*!< can tx mailbox 1 */
-  CAN_TX_MAILBOX2                        = 0x02  /*!< can tx mailbox 2 */
-} can_tx_mailbox_num_type;
-
-/**
-  * @brief  can receive fifo
-  */
-typedef enum
-{
-  CAN_RX_FIFO0                           = 0x00, /*!< can fifo 0 used to receive */
-  CAN_RX_FIFO1                           = 0x01  /*!< can fifo 1 used to receive */
-} can_rx_fifo_num_type;
-
-/**
-  * @brief  can transmit status
-  */
-typedef enum
-{
-  CAN_TX_STATUS_FAILED                   = 0x00, /*!< can transmission failed */
-  CAN_TX_STATUS_SUCCESSFUL               = 0x01, /*!< can transmission successful */
-  CAN_TX_STATUS_PENDING                  = 0x02, /*!< can transmission pending */
-  CAN_TX_STATUS_NO_EMPTY                 = 0x04  /*!< can transmission no empty mailbox */
-} can_transmit_status_type;
-
-/**
-  * @brief  can enter doze mode status
-  */
-typedef enum
-{
-  CAN_ENTER_DOZE_FAILED                  = 0x00, /*!< can enter the doze mode failed */
-  CAN_ENTER_DOZE_SUCCESSFUL              = 0x01  /*!< can enter the doze mode successful */
-} can_enter_doze_status_type;
-
-/**
-  * @brief  can quit doze mode status
-  */
-typedef enum
-{
-  CAN_QUIT_DOZE_FAILED                   = 0x00, /*!< can quit doze mode failed */
-  CAN_QUIT_DOZE_SUCCESSFUL               = 0x01  /*!< can quit doze mode successful */
-} can_quit_doze_status_type;
-
-/**
-  * @brief  can message discarding rule select when overflow
-  */
-typedef enum
-{
-  CAN_DISCARDING_FIRST_RECEIVED          = 0x00, /*!< can discarding the first received message */
-  CAN_DISCARDING_LAST_RECEIVED           = 0x01  /*!< can discarding the last received message */
-} can_msg_discarding_rule_type;
-
-/**
-  * @brief  can multiple message sending sequence rule
-  */
-typedef enum
-{
-  CAN_SENDING_BY_ID                      = 0x00, /*!< can sending the minimum id message first*/
-  CAN_SENDING_BY_REQUEST                 = 0x01  /*!< can sending the first request message first */
-} can_msg_sending_rule_type;
-
-/**
-  * @brief  can error type record
-  */
-typedef enum
-{
-  CAN_ERRORRECORD_NOERR                  = 0x00, /*!< no error */
-  CAN_ERRORRECORD_STUFFERR               = 0x01, /*!< stuff error */
-  CAN_ERRORRECORD_FORMERR                = 0x02, /*!< form error */
-  CAN_ERRORRECORD_ACKERR                 = 0x03, /*!< acknowledgment error */
-  CAN_ERRORRECORD_BITRECESSIVEERR        = 0x04, /*!< bit recessive error */
-  CAN_ERRORRECORD_BITDOMINANTERR         = 0x05, /*!< bit dominant error */
-  CAN_ERRORRECORD_CRCERR                 = 0x06, /*!< crc error */
-  CAN_ERRORRECORD_SOFTWARESETERR         = 0x07  /*!< software set error */
-} can_error_record_type;
-
-/**
-  * @brief  can init structure definition
-  */
-typedef struct
-{
-  can_mode_type mode_selection;          /*!< specifies the can mode.*/
-
-  confirm_state ttc_enable;              /*!< time triggered communication mode enable */
-
-  confirm_state aebo_enable;             /*!< automatic exit bus-off enable */
-
-  confirm_state aed_enable;              /*!< automatic exit doze mode enable */
-
-  confirm_state prsf_enable;             /*!< prohibit retransmission when sending fails enable */
-
-  can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
-
-  can_msg_sending_rule_type mmssr_selection;     /*!< multiple message sending sequence rule */
-
-} can_base_type;
-
-/**
-  * @brief  can baudrate structure definition
-  */
-typedef struct
-{
-  uint16_t baudrate_div;                  /*!< baudrate division,this parameter can be 0x001~0x400.*/
-
-  can_rsaw_type rsaw_size;                /*!< resynchronization adjust width */
-
-  can_bts1_type bts1_size;                /*!< bit time segment 1 */
-
-  can_bts2_type bts2_size;                /*!< bit time segment 2 */
-
-} can_baudrate_type;
-
-/**
-  * @brief  can filter init structure definition
-  */
-typedef struct
-{
-  confirm_state filter_activate_enable;  /*!< enable or disable the filter activate.*/
-
-  can_filter_mode_type filter_mode;      /*!< config the filter mode mask or list.*/
-
-  can_filter_fifo_type filter_fifo;      /*!< config the fifo which will be assigned to the filter. */
-
-  uint8_t filter_number;                 /*!< config the filter number, parameter ranges from 0 to 13. */
-
-  can_filter_bit_width_type filter_bit;  /*!< config the filter bit width 16bit or 32bit.*/
-
-  uint16_t filter_id_high;               /*!< config the filter identification, for 32-bit configuration
-                                              it's high 16 bits, for 16-bit configuration it's first. */
-
-  uint16_t filter_id_low;                /*!< config the filter identification, for 32-bit configuration
-                                              it's low 16 bits, for 16-bit configuration it's second. */
-
-  uint16_t filter_mask_high;             /*!< config the filter mask or identification, according to the filtering mode,
-                                              for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
-
-  uint16_t filter_mask_low;              /*!< config the filter mask or identification, according to the filtering mode,
-                                              for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
-} can_filter_init_type;
-
-/**
-  * @brief  can tx message structure definition
-  */
-typedef struct
-{
-  uint32_t standard_id;                  /*!< specifies the 11 bits standard identifier.
-                                              this parameter can be a value between 0 to 0x7FF. */
-
-  uint32_t extended_id;                  /*!< specifies the 29 bits extended identifier.
-                                              this parameter can be a value between 0 to 0x1FFFFFFF. */
-
-  can_identifier_type id_type;           /*!< specifies identifier type for the transmit message.*/
-
-  can_trans_frame_type frame_type;       /*!< specifies frame type for the transmit message.*/
-
-  uint8_t dlc;                           /*!< specifies frame data length that will be transmitted.
-                                              this parameter can be a value between 0 to 8 */
-
-  uint8_t data[8];                       /*!< contains the transmit data. it ranges from 0 to 0xFF. */
-
-} can_tx_message_type;
-
-/**
-  * @brief  can rx message structure definition
-  */
-typedef struct
-{
-    uint32_t standard_id;                /*!< specifies the 11 bits standard identifier
-                                              this parameter can be a value between 0 to 0x7FF. */
-
-    uint32_t extended_id;                /*!< specifies the 29 bits extended identifier.
-                                              this parameter can be a value between 0 to 0x1FFFFFFF. */
-
-    can_identifier_type id_type;         /*!< specifies identifier type for the receive message.*/
-
-    can_trans_frame_type frame_type;     /*!< specifies frame type for the receive message.*/
-
-    uint8_t dlc;                         /*!< specifies the frame data length that will be received.
-                                              this parameter can be a value between 0 to 8 */
-
-    uint8_t data[8];                     /*!< contains the receive data. it ranges from 0 to 0xFF.*/
-
-    uint8_t filter_index;                /*!< specifies the message stored in which filter
-                                              this parameter can be a value between 0 to 0xFF */
-} can_rx_message_type;
-
-/**
-  * @brief can controller area network tx mailbox
-  */
-typedef struct
-{
-  /**
-    * @brief can tmi register
-    */
-  union
-  {
-    __IO uint32_t tmi;
-    struct
-    {
-      __IO uint32_t tmsr                 : 1; /* [0] */
-      __IO uint32_t tmfrsel              : 1; /* [1] */
-      __IO uint32_t tmidsel              : 1; /* [2] */
-      __IO uint32_t tmeid                : 18;/* [20:3] */
-      __IO uint32_t tmsid                : 11;/* [31:21] */
-    } tmi_bit;
-  };
-
-  /**
-    * @brief can tmc register
-    */
-  union
-  {
-    __IO uint32_t tmc;
-    struct
-    {
-      __IO uint32_t tmdtbl               : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 4; /* [7:4] */
-      __IO uint32_t tmtsten              : 1; /* [8] */
-      __IO uint32_t reserved2            : 7; /* [15:9] */
-      __IO uint32_t tmts                 : 16;/* [31:16] */
-    } tmc_bit;
-  };
-
-  /**
-    * @brief can tmdtl register
-    */
-  union
-  {
-    __IO uint32_t tmdtl;
-    struct
-    {
-      __IO uint32_t tmdt0                : 8; /* [7:0] */
-      __IO uint32_t tmdt1                : 8; /* [15:8] */
-      __IO uint32_t tmdt2                : 8; /* [23:16] */
-      __IO uint32_t tmdt3                : 8; /* [31:24] */
-    } tmdtl_bit;
-  };
-
-  /**
-    * @brief can tmdth register
-    */
-  union
-  {
-    __IO uint32_t tmdth;
-    struct
-    {
-      __IO uint32_t tmdt4                : 8; /* [7:0] */
-      __IO uint32_t tmdt5                : 8; /* [15:8] */
-      __IO uint32_t tmdt6                : 8; /* [23:16] */
-      __IO uint32_t tmdt7                : 8; /* [31:24] */
-    } tmdth_bit;
-  };
-} can_tx_mailbox_type;
-
-/**
-  * @brief can controller area network fifo mailbox
-  */
-typedef struct
-{
-  /**
-    * @brief can rfi register
-    */
-  union
-  {
-    __IO uint32_t rfi;
-    struct
-    {
-      __IO uint32_t reserved1            : 1; /* [0] */
-      __IO uint32_t rffri                : 1; /* [1] */
-      __IO uint32_t rfidi                : 1; /* [2] */
-      __IO uint32_t rfeid                : 18;/* [20:3] */
-      __IO uint32_t rfsid                : 11;/* [31:21] */
-    } rfi_bit;
-  };
-
-  /**
-    * @brief can rfc register
-    */
-  union
-  {
-    __IO uint32_t rfc;
-    struct
-    {
-      __IO uint32_t rfdtl                : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 4; /* [7:4] */
-      __IO uint32_t rffmn                : 8; /* [15:8] */
-      __IO uint32_t rfts                 : 16;/* [31:16] */
-    } rfc_bit;
-  };
-
-  /**
-    * @brief can rfdtl register
-    */
-  union
-  {
-    __IO uint32_t rfdtl;
-    struct
-    {
-      __IO uint32_t rfdt0                : 8; /* [7:0] */
-      __IO uint32_t rfdt1                : 8; /* [15:8] */
-      __IO uint32_t rfdt2                : 8; /* [23:16] */
-      __IO uint32_t rfdt3                : 8; /* [31:24] */
-    } rfdtl_bit;
-  };
-
-  /**
-    * @brief can rfdth register
-    */
-  union
-  {
-    __IO uint32_t rfdth;
-    struct
-    {
-      __IO uint32_t rfdt4                : 8; /* [7:0] */
-      __IO uint32_t rfdt5                : 8; /* [15:8] */
-      __IO uint32_t rfdt6                : 8; /* [23:16] */
-      __IO uint32_t rfdt7                : 8; /* [31:24] */
-    } rfdth_bit;
-  };
-} can_fifo_mailbox_type;
-
-/**
-  * @brief can controller area network filter bit register
-  */
-typedef struct
-{
-  __IO uint32_t ffdb1;
-  __IO uint32_t ffdb2;
-} can_filter_register_type;
-
-/**
-  * @brief type define can register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief can mctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t mctrl;
-    struct
-    {
-      __IO uint32_t fzen                 : 1; /* [0] */
-      __IO uint32_t dzen                 : 1; /* [1] */
-      __IO uint32_t mmssr                : 1; /* [2] */
-      __IO uint32_t mdrsel               : 1; /* [3] */
-      __IO uint32_t prsfen               : 1; /* [4] */
-      __IO uint32_t aeden                : 1; /* [5] */
-      __IO uint32_t aeboen               : 1; /* [6] */
-      __IO uint32_t ttcen                : 1; /* [7] */
-      __IO uint32_t reserved1            : 7; /* [14:8] */
-      __IO uint32_t sprst                : 1; /* [15] */
-      __IO uint32_t ptd                  : 1; /* [16] */
-      __IO uint32_t reserved2            : 15;/*[31:17] */
-    } mctrl_bit;
-  };
-
-  /**
-    * @brief can msts register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t msts;
-    struct
-    {
-      __IO uint32_t fzc                  : 1; /* [0] */
-      __IO uint32_t dzc                  : 1; /* [1] */
-      __IO uint32_t eoif                 : 1; /* [2] */
-      __IO uint32_t qdzif                : 1; /* [3] */
-      __IO uint32_t edzif                : 1; /* [4] */
-      __IO uint32_t reserved1            : 3; /* [7:5] */
-      __IO uint32_t cuss                 : 1; /* [8] */
-      __IO uint32_t curs                 : 1; /* [9] */
-      __IO uint32_t lsamprx              : 1; /* [10] */
-      __IO uint32_t realrx               : 1; /* [11] */
-      __IO uint32_t reserved2            : 20;/*[31:12] */
-    } msts_bit;
-  };
-
-   /**
-     * @brief can tsts register, offset:0x08
-     */
-  union
-  {
-    __IO uint32_t tsts;
-    struct
-    {
-      __IO uint32_t tm0tcf               : 1; /* [0] */
-      __IO uint32_t tm0tsf               : 1; /* [1] */
-      __IO uint32_t tm0alf               : 1; /* [2] */
-      __IO uint32_t tm0tef               : 1; /* [3] */
-      __IO uint32_t reserved1            : 3; /* [6:4] */
-      __IO uint32_t tm0ct                : 1; /* [7] */
-      __IO uint32_t tm1tcf               : 1; /* [8] */
-      __IO uint32_t tm1tsf               : 1; /* [9] */
-      __IO uint32_t tm1alf               : 1; /* [10] */
-      __IO uint32_t tm1tef               : 1; /* [11] */
-      __IO uint32_t reserved2            : 3; /* [14:12] */
-      __IO uint32_t tm1ct                : 1; /* [15] */
-      __IO uint32_t tm2tcf               : 1; /* [16] */
-      __IO uint32_t tm2tsf               : 1; /* [17] */
-      __IO uint32_t tm2alf               : 1; /* [18] */
-      __IO uint32_t tm2tef               : 1; /* [19] */
-      __IO uint32_t reserved3            : 3; /* [22:20] */
-      __IO uint32_t tm2ct                : 1; /* [23] */
-      __IO uint32_t tmnr                 : 2; /* [25:24] */
-      __IO uint32_t tm0ef                : 1; /* [26] */
-      __IO uint32_t tm1ef                : 1; /* [27] */
-      __IO uint32_t tm2ef                : 1; /* [28] */
-      __IO uint32_t tm0lpf               : 1; /* [29] */
-      __IO uint32_t tm1lpf               : 1; /* [30] */
-      __IO uint32_t tm2lpf               : 1; /* [31] */
-    } tsts_bit;
-  };
-
-  /**
-    * @brief can rf0 register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t rf0;
-    struct
-    {
-      __IO uint32_t rf0mn                : 2; /* [1:0] */
-      __IO uint32_t reserved1            : 1; /* [2] */
-      __IO uint32_t rf0ff                : 1; /* [3] */
-      __IO uint32_t rf0of                : 1; /* [4] */
-      __IO uint32_t rf0r                 : 1; /* [5] */
-      __IO uint32_t reserved2            : 26;/* [31:6] */
-    } rf0_bit;
-  };
-
-  /**
-    * @brief can rf1 register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t rf1;
-    struct
-    {
-      __IO uint32_t rf1mn                : 2; /* [1:0] */
-      __IO uint32_t reserved1            : 1; /* [2] */
-      __IO uint32_t rf1ff                : 1; /* [3] */
-      __IO uint32_t rf1of                : 1; /* [4] */
-      __IO uint32_t rf1r                 : 1; /* [5] */
-      __IO uint32_t reserved2            : 26;/* [31:6] */
-    } rf1_bit;
-  };
-
-  /**
-    * @brief can inten register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t inten;
-    struct
-    {
-      __IO uint32_t tcien               : 1; /* [0] */
-      __IO uint32_t rf0mien              : 1; /* [1] */
-      __IO uint32_t rf0fien              : 1; /* [2] */
-      __IO uint32_t rf0oien              : 1; /* [3] */
-      __IO uint32_t rf1mien              : 1; /* [4] */
-      __IO uint32_t rf1fien              : 1; /* [5] */
-      __IO uint32_t rf1oien              : 1; /* [6] */
-      __IO uint32_t reserved1            : 1; /* [7] */
-      __IO uint32_t eaien                : 1; /* [8] */
-      __IO uint32_t epien                : 1; /* [9] */
-      __IO uint32_t boien                : 1; /* [10] */
-      __IO uint32_t etrien               : 1; /* [11] */
-      __IO uint32_t reserved2            : 3; /* [14:12] */
-      __IO uint32_t eoien                : 1; /* [15] */
-      __IO uint32_t qdzien               : 1; /* [16] */
-      __IO uint32_t edzien               : 1; /* [17] */
-      __IO uint32_t reserved3            : 14;/* [31:18] */
-    } inten_bit;
-  };
-
-  /**
-    * @brief can ests register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t ests;
-    struct
-    {
-      __IO uint32_t eaf                  : 1; /* [0] */
-      __IO uint32_t epf                  : 1; /* [1] */
-      __IO uint32_t bof                  : 1; /* [2] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t etr                  : 3; /* [6:4] */
-      __IO uint32_t reserved2            : 9; /* [15:7] */
-      __IO uint32_t tec                  : 8; /* [23:16] */
-      __IO uint32_t rec                  : 8; /* [31:24] */
-    } ests_bit;
-  };
-
-  /**
-    * @brief can btmg register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t btmg;
-    struct
-    {
-      __IO uint32_t brdiv                : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 4; /* [15:12] */
-      __IO uint32_t bts1                 : 4; /* [19:16] */
-      __IO uint32_t bts2                 : 3; /* [22:20] */
-      __IO uint32_t reserved2            : 1; /* [23] */
-      __IO uint32_t rsaw                 : 2; /* [25:24] */
-      __IO uint32_t reserved3            : 4; /* [29:26] */
-      __IO uint32_t lben                 : 1; /* [30] */
-      __IO uint32_t loen                 : 1; /* [31] */
-    } btmg_bit;
-  };
-
-  /**
-    * @brief can reserved register, offset:0x20~0x17C
-    */
-  __IO uint32_t reserved1[88];
-
-  /**
-    * @brief can controller area network tx mailbox register, offset:0x180~0x1AC
-    */
-  can_tx_mailbox_type tx_mailbox[3];
-
-  /**
-    * @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
-    */
-  can_fifo_mailbox_type fifo_mailbox[2];
-
-  /**
-    * @brief can reserved register, offset:0x1D0~0x1FC
-    */
-  __IO uint32_t reserved2[12];
-
-  /**
-    * @brief can fctrl register, offset:0x200
-    */
-  union
-  {
-    __IO uint32_t fctrl;
-    struct
-    {
-      __IO uint32_t fcs                  : 1; /* [0] */
-      __IO uint32_t reserved1            : 31;/* [31:1] */
-    } fctrl_bit;
-  };
-
-  /**
-    * @brief can fmcfg register, offset:0x204
-    */
-  union
-  {
-    __IO uint32_t fmcfg;
-    struct
-    {
-      __IO uint32_t fmsel0               : 1; /* [0] */
-      __IO uint32_t fmsel1               : 1; /* [1] */
-      __IO uint32_t fmsel2               : 1; /* [2] */
-      __IO uint32_t fmsel3               : 1; /* [3] */
-      __IO uint32_t fmsel4               : 1; /* [4] */
-      __IO uint32_t fmsel5               : 1; /* [5] */
-      __IO uint32_t fmsel6               : 1; /* [6] */
-      __IO uint32_t fmsel7               : 1; /* [7] */
-      __IO uint32_t fmsel8               : 1; /* [8] */
-      __IO uint32_t fmsel9               : 1; /* [9] */
-      __IO uint32_t fmsel10              : 1; /* [10] */
-      __IO uint32_t fmsel11              : 1; /* [11] */
-      __IO uint32_t fmsel12              : 1; /* [12] */
-      __IO uint32_t fmsel13              : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } fmcfg_bit;
-  };
-
-  /**
-    * @brief can reserved register, offset:0x208
-    */
-  __IO uint32_t reserved3;
-
-  /**
-    * @brief can fbwcfg register, offset:0x20C
-    */
-  union
-  {
-    __IO uint32_t fbwcfg;
-    struct
-    {
-      __IO uint32_t fbwsel0              : 1; /* [0] */
-      __IO uint32_t fbwsel1              : 1; /* [1] */
-      __IO uint32_t fbwsel2              : 1; /* [2] */
-      __IO uint32_t fbwsel3              : 1; /* [3] */
-      __IO uint32_t fbwsel4              : 1; /* [4] */
-      __IO uint32_t fbwsel5              : 1; /* [5] */
-      __IO uint32_t fbwsel6              : 1; /* [6] */
-      __IO uint32_t fbwsel7              : 1; /* [7] */
-      __IO uint32_t fbwsel8              : 1; /* [8] */
-      __IO uint32_t fbwsel9              : 1; /* [9] */
-      __IO uint32_t fbwsel10             : 1; /* [10] */
-      __IO uint32_t fbwsel11             : 1; /* [11] */
-      __IO uint32_t fbwsel12             : 1; /* [12] */
-      __IO uint32_t fbwsel13             : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } fbwcfg_bit;
-  };
-
-  /**
-    * @brief can reserved register, offset:0x210
-    */
-  __IO uint32_t reserved4;
-
-  /**
-    * @brief can frf register, offset:0x214
-    */
-  union
-  {
-    __IO uint32_t frf;
-    struct
-    {
-      __IO uint32_t frfsel0              : 1; /* [0] */
-      __IO uint32_t frfsel1              : 1; /* [1] */
-      __IO uint32_t frfsel2              : 1; /* [2] */
-      __IO uint32_t frfsel3              : 1; /* [3] */
-      __IO uint32_t frfsel4              : 1; /* [4] */
-      __IO uint32_t frfsel5              : 1; /* [5] */
-      __IO uint32_t frfsel6              : 1; /* [6] */
-      __IO uint32_t frfsel7              : 1; /* [7] */
-      __IO uint32_t frfsel8              : 1; /* [8] */
-      __IO uint32_t frfsel9              : 1; /* [9] */
-      __IO uint32_t frfsel10             : 1; /* [10] */
-      __IO uint32_t frfsel11             : 1; /* [11] */
-      __IO uint32_t frfsel12             : 1; /* [12] */
-      __IO uint32_t frfsel13             : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } frf_bit;
-  };
-
-  /**
-    * @brief can reserved register, offset:0x218
-    */
-  __IO uint32_t reserved5;
-
-  /**
-    * @brief can facfg register, offset:0x21C
-    */
-  union
-  {
-    __IO uint32_t facfg;
-    struct
-    {
-      __IO uint32_t faen0                : 1; /* [0] */
-      __IO uint32_t faen1                : 1; /* [1] */
-      __IO uint32_t faen2                : 1; /* [2] */
-      __IO uint32_t faen3                : 1; /* [3] */
-      __IO uint32_t faen4                : 1; /* [4] */
-      __IO uint32_t faen5                : 1; /* [5] */
-      __IO uint32_t faen6                : 1; /* [6] */
-      __IO uint32_t faen7                : 1; /* [7] */
-      __IO uint32_t faen8                : 1; /* [8] */
-      __IO uint32_t faen9                : 1; /* [9] */
-      __IO uint32_t faen10               : 1; /* [10] */
-      __IO uint32_t faen11               : 1; /* [11] */
-      __IO uint32_t faen12               : 1; /* [12] */
-      __IO uint32_t faen13               : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } facfg_bit;
-  };
-
-  /**
-    * @brief can reserved register, offset:0x220~0x23C
-    */
-  __IO uint32_t reserved6[8];
-
-  /**
-    * @brief can ffb register, offset:0x240~0x2AC
-    */
-  can_filter_register_type ffb[14];
-} can_type;
-
-/**
-  * @}
-  */
-
-#define CAN1                             ((can_type *) CAN1_BASE)
-#define CAN2                             ((can_type *) CAN2_BASE)
-
-/** @defgroup CAN_exported_functions
-  * @{
-  */
-
-void can_reset(can_type* can_x);
-void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
-error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
-void can_default_para_init(can_base_type* can_base_struct);
-error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
-void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
-void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
-void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
-void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
-uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
-can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
-void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
-void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
-void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
-uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
-error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
-can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
-can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
-can_error_record_type can_error_type_record_get(can_type* can_x);
-uint8_t can_receive_error_counter_get(can_type* can_x);
-uint8_t can_transmit_error_counter_get(can_type* can_x);
-void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
-flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
-void can_flag_clear(can_type* can_x, uint32_t can_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_crc.h

@@ -1,172 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_crc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 crc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_CRC_H
-#define __AT32F403A_407_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup  CRC
-  * @{
-  */
-
-/** @defgroup CRC_exported_types
-  * @{
-  */
-
-/**
-  * @brief crc reverse input data
-  */
-typedef enum
-{
-  CRC_REVERSE_INPUT_NO_AFFECTE           = 0x00, /*!< input data no reverse */
-  CRC_REVERSE_INPUT_BY_BYTE              = 0x01, /*!< input data reverse by byte */
-  CRC_REVERSE_INPUT_BY_HALFWORD          = 0x02, /*!< input data reverse by half word */
-  CRC_REVERSE_INPUT_BY_WORD              = 0x03  /*!< input data reverse by word */
-} crc_reverse_input_type;
-
-/**
-  * @brief crc reverse output data
-  */
-typedef enum
-{
-  CRC_REVERSE_OUTPUT_NO_AFFECTE          = 0x00, /*!< output data no reverse */
-  CRC_REVERSE_OUTPUT_DATA                = 0x01  /*!< output data reverse by word */
-} crc_reverse_output_type;
-
-/**
- * @brief type define crc register all
- */
-typedef struct
-{
-  /**
-    * @brief crc dt register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t dt;
-    struct
-    {
-      __IO uint32_t dt                   : 32; /* [31:0] */
-    } dt_bit;
-  };
-
-  /**
-    * @brief crc cdt register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t cdt;
-    struct
-    {
-      __IO uint32_t cdt                  : 8 ; /* [7:0] */
-      __IO uint32_t reserved1            : 24 ;/* [31:8] */
-    } cdt_bit;
-  };
-
-  /**
-    * @brief crc ctrl register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t rst                  : 1 ; /* [0] */
-      __IO uint32_t reserved1            : 4 ; /* [4:1] */
-      __IO uint32_t revid                : 2 ; /* [6:5] */
-      __IO uint32_t revod                : 1 ; /* [7] */
-      __IO uint32_t reserved2            : 24 ;/* [31:8] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief crm reserved1 register, offset:0x0C
-    */
-  __IO uint32_t reserved1;
-
-  /**
-    * @brief crc idt register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t idt;
-    struct
-    {
-      __IO uint32_t idt                  : 32; /* [31:0] */
-    } idt_bit;
-  };
-
-} crc_type;
-
-/**
-  * @}
-  */
-
-#define CRC                              ((crc_type *) CRC_BASE)
-
-/** @defgroup CRC_exported_functions
-  * @{
-  */
-
-void crc_data_reset(void);
-uint32_t crc_one_word_calculate(uint32_t data);
-uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
-uint32_t crc_data_get(void);
-void crc_common_data_set(uint8_t cdt_value);
-uint8_t crc_common_date_get(void);
-void crc_init_data_set(uint32_t value);
-void crc_reverse_input_data_set(crc_reverse_input_type value);
-void crc_reverse_output_data_set(crc_reverse_output_type value);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_crm.h

@@ -1,1142 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_crm.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 crm header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_CRM_H
-#define __AT32F403A_407_CRM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup CRM
-  * @{
-  */
-
-#define CRM_REG(value)                   PERIPH_REG(CRM_BASE, value)
-#define CRM_REG_BIT(value)               PERIPH_REG_BIT(value)
-
-/** @defgroup CRM_flags_definition
-  * @brief crm flag
-  * @{
-  */
-
-#define CRM_HICK_STABLE_FLAG             MAKE_VALUE(0x00, 1)  /*!< high speed internal clock stable flag */
-#define CRM_HEXT_STABLE_FLAG             MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
-#define CRM_PLL_STABLE_FLAG              MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
-#define CRM_LEXT_STABLE_FLAG             MAKE_VALUE(0x20, 1)  /*!< low speed external crystal stable flag */
-#define CRM_LICK_STABLE_FLAG             MAKE_VALUE(0x24, 1)  /*!< low speed internal clock stable flag */
-#define CRM_ALL_RESET_FLAG               MAKE_VALUE(0x24, 24) /*!< all reset flag */
-#define CRM_NRST_RESET_FLAG              MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
-#define CRM_POR_RESET_FLAG               MAKE_VALUE(0x24, 27) /*!< power on reset flag */
-#define CRM_SW_RESET_FLAG                MAKE_VALUE(0x24, 28) /*!< software reset flag */
-#define CRM_WDT_RESET_FLAG               MAKE_VALUE(0x24, 29) /*!< watchdog timer reset flag */
-#define CRM_WWDT_RESET_FLAG              MAKE_VALUE(0x24, 30) /*!< window watchdog timer reset flag */
-#define CRM_LOWPOWER_RESET_FLAG          MAKE_VALUE(0x24, 31) /*!< low-power reset flag */
-#define CRM_LICK_READY_INT_FLAG          MAKE_VALUE(0x08, 0)  /*!< low speed internal clock stable interrupt ready flag */
-#define CRM_LEXT_READY_INT_FLAG          MAKE_VALUE(0x08, 1)  /*!< low speed external crystal stable interrupt ready flag */
-#define CRM_HICK_READY_INT_FLAG          MAKE_VALUE(0x08, 2)  /*!< high speed internal clock stable interrupt ready flag */
-#define CRM_HEXT_READY_INT_FLAG          MAKE_VALUE(0x08, 3)  /*!< high speed external crystal stable interrupt ready flag */
-#define CRM_PLL_READY_INT_FLAG           MAKE_VALUE(0x08, 4)  /*!< phase locking loop stable interrupt ready flag */
-#define CRM_CLOCK_FAILURE_INT_FLAG       MAKE_VALUE(0x08, 7)  /*!< clock failure interrupt ready flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRM_interrupts_definition
-  * @brief crm interrupt
-  * @{
-  */
-
-#define CRM_LICK_STABLE_INT              ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
-#define CRM_LEXT_STABLE_INT              ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
-#define CRM_HICK_STABLE_INT              ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
-#define CRM_HEXT_STABLE_INT              ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
-#define CRM_PLL_STABLE_INT               ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
-#define CRM_CLOCK_FAILURE_INT            ((uint32_t)0x00800000) /*!< clock failure interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRM_exported_types
-  * @{
-  */
-
-/**
-  * @brief crm periph clock
-  */
-typedef enum
-{
-#if defined (AT32F403Axx)
-  /* ahb periph */
-  CRM_DMA1_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 0),  /*!< dma1 periph clock */
-  CRM_DMA2_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 1),  /*!< dma2 periph clock */
-  CRM_CRC_PERIPH_CLOCK                   = MAKE_VALUE(0x14, 6),  /*!< crc periph clock */
-  CRM_XMC_PERIPH_CLOCK                   = MAKE_VALUE(0x14, 8),  /*!< xmc periph clock */
-  CRM_SDIO1_PERIPH_CLOCK                 = MAKE_VALUE(0x14, 10), /*!< sdio1 periph clock */
-  CRM_SDIO2_PERIPH_CLOCK                 = MAKE_VALUE(0x14, 11), /*!< sdio2 periph clock */
-  /* apb2 periph */
-  CRM_IOMUX_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 0),  /*!< iomux periph clock */
-  CRM_GPIOA_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 2),  /*!< gpioa periph clock */
-  CRM_GPIOB_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 3),  /*!< gpiob periph clock */
-  CRM_GPIOC_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 4),  /*!< gpioc periph clock */
-  CRM_GPIOD_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 5),  /*!< gpiod periph clock */
-  CRM_GPIOE_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 6),  /*!< gpioe periph clock */
-  CRM_ADC1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 9),  /*!< adc1 periph clock */
-  CRM_ADC2_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 10), /*!< adc2 periph clock */
-  CRM_TMR1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
-  CRM_SPI1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
-  CRM_TMR8_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 13), /*!< tmr8 periph clock */
-  CRM_USART1_PERIPH_CLOCK                = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
-  CRM_ADC3_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 15), /*!< adc3 periph clock */
-  CRM_TMR9_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 19), /*!< tmr9 periph clock */
-  CRM_TMR10_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 20), /*!< tmr10 periph clock */
-  CRM_TMR11_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 21), /*!< tmr11 periph clock */
-  CRM_ACC_PERIPH_CLOCK                   = MAKE_VALUE(0x18, 22), /*!< acc periph clock */
-  CRM_I2C3_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 23), /*!< i2c3 periph clock */
-  CRM_USART6_PERIPH_CLOCK                = MAKE_VALUE(0x18, 24), /*!< usart6 periph clock */
-  CRM_UART7_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 25), /*!< uart7 periph clock */
-  CRM_UART8_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 26), /*!< uart8 periph clock */
-  /* apb1 periph */
-  CRM_TMR2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 0),  /*!< tmr2 periph clock */
-  CRM_TMR3_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 1),  /*!< tmr3 periph clock */
-  CRM_TMR4_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 2),  /*!< tmr4 periph clock */
-  CRM_TMR5_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 3),  /*!< tmr5 periph clock */
-  CRM_TMR6_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 4),  /*!< tmr6 periph clock */
-  CRM_TMR7_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 5),  /*!< tmr7 periph clock */
-  CRM_TMR12_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 6),  /*!< tmr12 periph clock */
-  CRM_TMR13_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 7),  /*!< tmr13 periph clock */
-  CRM_TMR14_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 8),  /*!< tmr14 periph clock */
-  CRM_WWDT_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
-  CRM_SPI2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
-  CRM_SPI3_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 15), /*!< spi3 periph clock */
-  CRM_SPI4_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 16), /*!< spi4 periph clock */
-  CRM_USART2_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
-  CRM_USART3_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 18), /*!< usart3 periph clock */
-  CRM_UART4_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 19), /*!< uart4 periph clock */
-  CRM_UART5_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 20), /*!< uart5 periph clock */
-  CRM_I2C1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
-  CRM_I2C2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
-  CRM_USB_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 23), /*!< usb periph clock */
-  CRM_CAN1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
-  CRM_CAN2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 26), /*!< can2 periph clock */
-  CRM_BPR_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */
-  CRM_PWC_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */
-  CRM_DAC_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 29)  /*!< dac periph clock */
-#endif
-
-#if defined (AT32F407xx)
-  /* ahb periph */
-  CRM_DMA1_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 0),  /*!< dma1 periph clock */
-  CRM_DMA2_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 1),  /*!< dma2 periph clock */
-  CRM_CRC_PERIPH_CLOCK                   = MAKE_VALUE(0x14, 6),  /*!< crc periph clock */
-  CRM_XMC_PERIPH_CLOCK                   = MAKE_VALUE(0x14, 8),  /*!< xmc periph clock */
-  CRM_SDIO1_PERIPH_CLOCK                 = MAKE_VALUE(0x14, 10), /*!< sdio1 periph clock */
-  CRM_SDIO2_PERIPH_CLOCK                 = MAKE_VALUE(0x14, 11), /*!< sdio2 periph clock */
-  CRM_EMAC_PERIPH_CLOCK                  = MAKE_VALUE(0x14, 14), /*!< emac periph clock */
-  CRM_EMACTX_PERIPH_CLOCK                = MAKE_VALUE(0x14, 15), /*!< emac tx periph clock */
-  CRM_EMACRX_PERIPH_CLOCK                = MAKE_VALUE(0x14, 16), /*!< emac rx periph clock */
-  CRM_EMACPTP_PERIPH_CLOCK               = MAKE_VALUE(0x14, 28), /*!< emac ptp periph clock */
-  /* apb2 periph */
-  CRM_IOMUX_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 0),  /*!< iomux periph clock */
-  CRM_GPIOA_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 2),  /*!< gpioa periph clock */
-  CRM_GPIOB_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 3),  /*!< gpiob periph clock */
-  CRM_GPIOC_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 4),  /*!< gpioc periph clock */
-  CRM_GPIOD_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 5),  /*!< gpiod periph clock */
-  CRM_GPIOE_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 6),  /*!< gpioe periph clock */
-  CRM_ADC1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 9),  /*!< adc1 periph clock */
-  CRM_ADC2_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 10), /*!< adc2 periph clock */
-  CRM_TMR1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
-  CRM_SPI1_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
-  CRM_TMR8_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 13), /*!< tmr8 periph clock */
-  CRM_USART1_PERIPH_CLOCK                = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
-  CRM_ADC3_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 15), /*!< adc3 periph clock */
-  CRM_TMR9_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 19), /*!< tmr9 periph clock */
-  CRM_TMR10_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 20), /*!< tmr10 periph clock */
-  CRM_TMR11_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 21), /*!< tmr11 periph clock */
-  CRM_ACC_PERIPH_CLOCK                   = MAKE_VALUE(0x18, 22), /*!< acc periph clock */
-  CRM_I2C3_PERIPH_CLOCK                  = MAKE_VALUE(0x18, 23), /*!< i2c3 periph clock */
-  CRM_USART6_PERIPH_CLOCK                = MAKE_VALUE(0x18, 24), /*!< usart6 periph clock */
-  CRM_UART7_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 25), /*!< uart7 periph clock */
-  CRM_UART8_PERIPH_CLOCK                 = MAKE_VALUE(0x18, 26), /*!< uart8 periph clock */
-  /* apb1 periph */
-  CRM_TMR2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 0),  /*!< tmr2 periph clock */
-  CRM_TMR3_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 1),  /*!< tmr3 periph clock */
-  CRM_TMR4_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 2),  /*!< tmr4 periph clock */
-  CRM_TMR5_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 3),  /*!< tmr5 periph clock */
-  CRM_TMR6_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 4),  /*!< tmr6 periph clock */
-  CRM_TMR7_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 5),  /*!< tmr7 periph clock */
-  CRM_TMR12_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 6),  /*!< tmr12 periph clock */
-  CRM_TMR13_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 7),  /*!< tmr13 periph clock */
-  CRM_TMR14_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 8),  /*!< tmr14 periph clock */
-  CRM_WWDT_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
-  CRM_SPI2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
-  CRM_SPI3_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 15), /*!< spi3 periph clock */
-  CRM_SPI4_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 16), /*!< spi4 periph clock */
-  CRM_USART2_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
-  CRM_USART3_PERIPH_CLOCK                = MAKE_VALUE(0x1C, 18), /*!< usart3 periph clock */
-  CRM_UART4_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 19), /*!< uart4 periph clock */
-  CRM_UART5_PERIPH_CLOCK                 = MAKE_VALUE(0x1C, 20), /*!< uart5 periph clock */
-  CRM_I2C1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
-  CRM_I2C2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
-  CRM_USB_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 23), /*!< usb periph clock */
-  CRM_CAN1_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */
-  CRM_CAN2_PERIPH_CLOCK                  = MAKE_VALUE(0x1C, 26), /*!< can2 periph clock */
-  CRM_BPR_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */
-  CRM_PWC_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */
-  CRM_DAC_PERIPH_CLOCK                   = MAKE_VALUE(0x1C, 29)  /*!< dac periph clock */
-#endif
-
-} crm_periph_clock_type;
-
-/**
-  * @brief crm periph reset
-  */
-typedef enum
-{
-#if defined (AT32F403Axx)
-  /* apb2 periph */
-  CRM_IOMUX_PERIPH_RESET                 = MAKE_VALUE(0x0C, 0),  /*!< iomux periph reset */
-  CRM_EXINT_PERIPH_RESET                 = MAKE_VALUE(0x0C, 1),  /*!< exint periph reset */
-  CRM_GPIOA_PERIPH_RESET                 = MAKE_VALUE(0x0C, 2),  /*!< gpioa periph reset */
-  CRM_GPIOB_PERIPH_RESET                 = MAKE_VALUE(0x0C, 3),  /*!< gpiob periph reset */
-  CRM_GPIOC_PERIPH_RESET                 = MAKE_VALUE(0x0C, 4),  /*!< gpioc periph reset */
-  CRM_GPIOD_PERIPH_RESET                 = MAKE_VALUE(0x0C, 5),  /*!< gpiod periph reset */
-  CRM_GPIOE_PERIPH_RESET                 = MAKE_VALUE(0x0C, 6),  /*!< gpioe periph reset */
-  CRM_ADC1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 9),  /*!< adc1 periph reset */
-  CRM_ADC2_PERIPH_RESET                  = MAKE_VALUE(0x0C, 10), /*!< adc2 periph reset */
-  CRM_TMR1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
-  CRM_SPI1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
-  CRM_TMR8_PERIPH_RESET                  = MAKE_VALUE(0x0C, 13), /*!< tmr8 periph reset */
-  CRM_USART1_PERIPH_RESET                = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
-  CRM_ADC3_PERIPH_RESET                  = MAKE_VALUE(0x0C, 15), /*!< adc3 periph reset */
-  CRM_TMR9_PERIPH_RESET                  = MAKE_VALUE(0x0C, 19), /*!< tmr9 periph reset */
-  CRM_TMR10_PERIPH_RESET                 = MAKE_VALUE(0x0C, 20), /*!< tmr10 periph reset */
-  CRM_TMR11_PERIPH_RESET                 = MAKE_VALUE(0x0C, 21), /*!< tmr11 periph reset */
-  CRM_ACC_PERIPH_RESET                   = MAKE_VALUE(0x0C, 22), /*!< acc periph reset */
-  CRM_I2C3_PERIPH_RESET                  = MAKE_VALUE(0x0C, 23), /*!< i2c3 periph reset */
-  CRM_USART6_PERIPH_RESET                = MAKE_VALUE(0x0C, 24), /*!< usart6 periph reset */
-  CRM_UART7_PERIPH_RESET                 = MAKE_VALUE(0x0C, 25), /*!< uart7 periph reset */
-  CRM_UART8_PERIPH_RESET                 = MAKE_VALUE(0x0C, 26), /*!< uart8 periph reset */
-  /* apb1 periph */
-  CRM_TMR2_PERIPH_RESET                  = MAKE_VALUE(0x10, 0),  /*!< tmr2 periph reset */
-  CRM_TMR3_PERIPH_RESET                  = MAKE_VALUE(0x10, 1),  /*!< tmr3 periph reset */
-  CRM_TMR4_PERIPH_RESET                  = MAKE_VALUE(0x10, 2),  /*!< tmr4 periph reset */
-  CRM_TMR5_PERIPH_RESET                  = MAKE_VALUE(0x10, 3),  /*!< tmr5 periph reset */
-  CRM_TMR6_PERIPH_RESET                  = MAKE_VALUE(0x10, 4),  /*!< tmr6 periph reset */
-  CRM_TMR7_PERIPH_RESET                  = MAKE_VALUE(0x10, 5),  /*!< tmr7 periph reset */
-  CRM_TMR12_PERIPH_RESET                 = MAKE_VALUE(0x10, 6),  /*!< tmr12 periph reset */
-  CRM_TMR13_PERIPH_RESET                 = MAKE_VALUE(0x10, 7),  /*!< tmr13 periph reset */
-  CRM_TMR14_PERIPH_RESET                 = MAKE_VALUE(0x10, 8),  /*!< tmr14 periph reset */
-  CRM_WWDT_PERIPH_RESET                  = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
-  CRM_SPI2_PERIPH_RESET                  = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
-  CRM_SPI3_PERIPH_RESET                  = MAKE_VALUE(0x10, 15), /*!< spi3 periph reset */
-  CRM_SPI4_PERIPH_RESET                  = MAKE_VALUE(0x10, 16), /*!< spi4 periph reset */
-  CRM_USART2_PERIPH_RESET                = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
-  CRM_USART3_PERIPH_RESET                = MAKE_VALUE(0x10, 18), /*!< usart3 periph reset */
-  CRM_UART4_PERIPH_RESET                 = MAKE_VALUE(0x10, 19), /*!< uart4 periph reset */
-  CRM_UART5_PERIPH_RESET                 = MAKE_VALUE(0x10, 20), /*!< uart5 periph reset */
-  CRM_I2C1_PERIPH_RESET                  = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
-  CRM_I2C2_PERIPH_RESET                  = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
-  CRM_USB_PERIPH_RESET                   = MAKE_VALUE(0x10, 23), /*!< usb periph reset */
-  CRM_CAN1_PERIPH_RESET                  = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
-  CRM_CAN2_PERIPH_RESET                  = MAKE_VALUE(0x10, 26), /*!< can2 periph reset */
-  CRM_BPR_PERIPH_RESET                   = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */
-  CRM_PWC_PERIPH_RESET                   = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */
-  CRM_DAC_PERIPH_RESET                   = MAKE_VALUE(0x10, 29)  /*!< dac periph reset */
-#endif
-
-#if defined (AT32F407xx)
-  /* ahb periph */
-  CRM_EMAC_PERIPH_RESET                  = MAKE_VALUE(0x28, 14), /*!< emac periph reset */
-  /* apb2 periph */
-  CRM_IOMUX_PERIPH_RESET                 = MAKE_VALUE(0x0C, 0),  /*!< iomux periph reset */
-  CRM_EXINT_PERIPH_RESET                 = MAKE_VALUE(0x0C, 1),  /*!< exint periph reset */
-  CRM_GPIOA_PERIPH_RESET                 = MAKE_VALUE(0x0C, 2),  /*!< gpioa periph reset */
-  CRM_GPIOB_PERIPH_RESET                 = MAKE_VALUE(0x0C, 3),  /*!< gpiob periph reset */
-  CRM_GPIOC_PERIPH_RESET                 = MAKE_VALUE(0x0C, 4),  /*!< gpioc periph reset */
-  CRM_GPIOD_PERIPH_RESET                 = MAKE_VALUE(0x0C, 5),  /*!< gpiod periph reset */
-  CRM_GPIOE_PERIPH_RESET                 = MAKE_VALUE(0x0C, 6),  /*!< gpioe periph reset */
-  CRM_ADC1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 9),  /*!< adc1 periph reset */
-  CRM_ADC2_PERIPH_RESET                  = MAKE_VALUE(0x0C, 10), /*!< adc2 periph reset */
-  CRM_TMR1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
-  CRM_SPI1_PERIPH_RESET                  = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
-  CRM_TMR8_PERIPH_RESET                  = MAKE_VALUE(0x0C, 13), /*!< tmr8 periph reset */
-  CRM_USART1_PERIPH_RESET                = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
-  CRM_ADC3_PERIPH_RESET                  = MAKE_VALUE(0x0C, 15), /*!< adc3 periph reset */
-  CRM_TMR9_PERIPH_RESET                  = MAKE_VALUE(0x0C, 19), /*!< tmr9 periph reset */
-  CRM_TMR10_PERIPH_RESET                 = MAKE_VALUE(0x0C, 20), /*!< tmr10 periph reset */
-  CRM_TMR11_PERIPH_RESET                 = MAKE_VALUE(0x0C, 21), /*!< tmr11 periph reset */
-  CRM_ACC_PERIPH_RESET                   = MAKE_VALUE(0x0C, 22), /*!< acc periph reset */
-  CRM_I2C3_PERIPH_RESET                  = MAKE_VALUE(0x0C, 23), /*!< i2c3 periph reset */
-  CRM_USART6_PERIPH_RESET                = MAKE_VALUE(0x0C, 24), /*!< usart6 periph reset */
-  CRM_UART7_PERIPH_RESET                 = MAKE_VALUE(0x0C, 25), /*!< uart7 periph reset */
-  CRM_UART8_PERIPH_RESET                 = MAKE_VALUE(0x0C, 26), /*!< uart8 periph reset */
-  /* apb1 periph */
-  CRM_TMR2_PERIPH_RESET                  = MAKE_VALUE(0x10, 0),  /*!< tmr2 periph reset */
-  CRM_TMR3_PERIPH_RESET                  = MAKE_VALUE(0x10, 1),  /*!< tmr3 periph reset */
-  CRM_TMR4_PERIPH_RESET                  = MAKE_VALUE(0x10, 2),  /*!< tmr4 periph reset */
-  CRM_TMR5_PERIPH_RESET                  = MAKE_VALUE(0x10, 3),  /*!< tmr5 periph reset */
-  CRM_TMR6_PERIPH_RESET                  = MAKE_VALUE(0x10, 4),  /*!< tmr6 periph reset */
-  CRM_TMR7_PERIPH_RESET                  = MAKE_VALUE(0x10, 5),  /*!< tmr7 periph reset */
-  CRM_TMR12_PERIPH_RESET                 = MAKE_VALUE(0x10, 6),  /*!< tmr12 periph reset */
-  CRM_TMR13_PERIPH_RESET                 = MAKE_VALUE(0x10, 7),  /*!< tmr13 periph reset */
-  CRM_TMR14_PERIPH_RESET                 = MAKE_VALUE(0x10, 8),  /*!< tmr14 periph reset */
-  CRM_WWDT_PERIPH_RESET                  = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
-  CRM_SPI2_PERIPH_RESET                  = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
-  CRM_SPI3_PERIPH_RESET                  = MAKE_VALUE(0x10, 15), /*!< spi3 periph reset */
-  CRM_SPI4_PERIPH_RESET                  = MAKE_VALUE(0x10, 16), /*!< spi4 periph reset */
-  CRM_USART2_PERIPH_RESET                = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
-  CRM_USART3_PERIPH_RESET                = MAKE_VALUE(0x10, 18), /*!< usart3 periph reset */
-  CRM_UART4_PERIPH_RESET                 = MAKE_VALUE(0x10, 19), /*!< uart4 periph reset */
-  CRM_UART5_PERIPH_RESET                 = MAKE_VALUE(0x10, 20), /*!< uart5 periph reset */
-  CRM_I2C1_PERIPH_RESET                  = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
-  CRM_I2C2_PERIPH_RESET                  = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
-  CRM_USB_PERIPH_RESET                   = MAKE_VALUE(0x10, 23), /*!< usb periph reset */
-  CRM_CAN1_PERIPH_RESET                  = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */
-  CRM_CAN2_PERIPH_RESET                  = MAKE_VALUE(0x10, 26), /*!< can2 periph reset */
-  CRM_BPR_PERIPH_RESET                   = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */
-  CRM_PWC_PERIPH_RESET                   = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */
-  CRM_DAC_PERIPH_RESET                   = MAKE_VALUE(0x10, 29)  /*!< dac periph reset */
-#endif
-
-} crm_periph_reset_type;
-
-/**
-  * @brief crm periph clock in sleep mode
-  */
-typedef enum
-{
-  /* ahb periph */
-  CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE       = MAKE_VALUE(0x14, 2), /*!< sram sleep mode periph clock */
-  CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE      = MAKE_VALUE(0x14, 4)  /*!< flash sleep mode periph clock */
-} crm_periph_clock_sleepmd_type;
-
-/**
-  * @brief crm pll mult_x
-  */
-typedef enum
-{
-  CRM_PLL_MULT_2                         = 0,  /*!< pll multiplication factor 2 */
-  CRM_PLL_MULT_3                         = 1,  /*!< pll multiplication factor 3 */
-  CRM_PLL_MULT_4                         = 2,  /*!< pll multiplication factor 4 */
-  CRM_PLL_MULT_5                         = 3,  /*!< pll multiplication factor 5 */
-  CRM_PLL_MULT_6                         = 4,  /*!< pll multiplication factor 6 */
-  CRM_PLL_MULT_7                         = 5,  /*!< pll multiplication factor 7 */
-  CRM_PLL_MULT_8                         = 6,  /*!< pll multiplication factor 8 */
-  CRM_PLL_MULT_9                         = 7,  /*!< pll multiplication factor 9 */
-  CRM_PLL_MULT_10                        = 8,  /*!< pll multiplication factor 10 */
-  CRM_PLL_MULT_11                        = 9,  /*!< pll multiplication factor 11 */
-  CRM_PLL_MULT_12                        = 10, /*!< pll multiplication factor 12 */
-  CRM_PLL_MULT_13                        = 11, /*!< pll multiplication factor 13 */
-  CRM_PLL_MULT_14                        = 12, /*!< pll multiplication factor 14 */
-  CRM_PLL_MULT_15                        = 13, /*!< pll multiplication factor 15 */
-  CRM_PLL_MULT_16                        = 15, /*!< pll multiplication factor 16 */
-  CRM_PLL_MULT_17                        = 16, /*!< pll multiplication factor 17 */
-  CRM_PLL_MULT_18                        = 17, /*!< pll multiplication factor 18 */
-  CRM_PLL_MULT_19                        = 18, /*!< pll multiplication factor 19 */
-  CRM_PLL_MULT_20                        = 19, /*!< pll multiplication factor 20 */
-  CRM_PLL_MULT_21                        = 20, /*!< pll multiplication factor 21 */
-  CRM_PLL_MULT_22                        = 21, /*!< pll multiplication factor 22 */
-  CRM_PLL_MULT_23                        = 22, /*!< pll multiplication factor 23 */
-  CRM_PLL_MULT_24                        = 23, /*!< pll multiplication factor 24 */
-  CRM_PLL_MULT_25                        = 24, /*!< pll multiplication factor 25 */
-  CRM_PLL_MULT_26                        = 25, /*!< pll multiplication factor 26 */
-  CRM_PLL_MULT_27                        = 26, /*!< pll multiplication factor 27 */
-  CRM_PLL_MULT_28                        = 27, /*!< pll multiplication factor 28 */
-  CRM_PLL_MULT_29                        = 28, /*!< pll multiplication factor 29 */
-  CRM_PLL_MULT_30                        = 29, /*!< pll multiplication factor 30 */
-  CRM_PLL_MULT_31                        = 30, /*!< pll multiplication factor 31 */
-  CRM_PLL_MULT_32                        = 31, /*!< pll multiplication factor 32 */
-  CRM_PLL_MULT_33                        = 32, /*!< pll multiplication factor 33 */
-  CRM_PLL_MULT_34                        = 33, /*!< pll multiplication factor 34 */
-  CRM_PLL_MULT_35                        = 34, /*!< pll multiplication factor 35 */
-  CRM_PLL_MULT_36                        = 35, /*!< pll multiplication factor 36 */
-  CRM_PLL_MULT_37                        = 36, /*!< pll multiplication factor 37 */
-  CRM_PLL_MULT_38                        = 37, /*!< pll multiplication factor 38 */
-  CRM_PLL_MULT_39                        = 38, /*!< pll multiplication factor 39 */
-  CRM_PLL_MULT_40                        = 39, /*!< pll multiplication factor 40 */
-  CRM_PLL_MULT_41                        = 40, /*!< pll multiplication factor 41 */
-  CRM_PLL_MULT_42                        = 41, /*!< pll multiplication factor 42 */
-  CRM_PLL_MULT_43                        = 42, /*!< pll multiplication factor 43 */
-  CRM_PLL_MULT_44                        = 43, /*!< pll multiplication factor 44 */
-  CRM_PLL_MULT_45                        = 44, /*!< pll multiplication factor 45 */
-  CRM_PLL_MULT_46                        = 45, /*!< pll multiplication factor 46 */
-  CRM_PLL_MULT_47                        = 46, /*!< pll multiplication factor 47 */
-  CRM_PLL_MULT_48                        = 47, /*!< pll multiplication factor 48 */
-  CRM_PLL_MULT_49                        = 48, /*!< pll multiplication factor 49 */
-  CRM_PLL_MULT_50                        = 49, /*!< pll multiplication factor 50 */
-  CRM_PLL_MULT_51                        = 50, /*!< pll multiplication factor 51 */
-  CRM_PLL_MULT_52                        = 51, /*!< pll multiplication factor 52 */
-  CRM_PLL_MULT_53                        = 52, /*!< pll multiplication factor 53 */
-  CRM_PLL_MULT_54                        = 53, /*!< pll multiplication factor 54 */
-  CRM_PLL_MULT_55                        = 54, /*!< pll multiplication factor 55 */
-  CRM_PLL_MULT_56                        = 55, /*!< pll multiplication factor 56 */
-  CRM_PLL_MULT_57                        = 56, /*!< pll multiplication factor 57 */
-  CRM_PLL_MULT_58                        = 57, /*!< pll multiplication factor 58 */
-  CRM_PLL_MULT_59                        = 58, /*!< pll multiplication factor 59 */
-  CRM_PLL_MULT_60                        = 59, /*!< pll multiplication factor 60 */
-  CRM_PLL_MULT_61                        = 60, /*!< pll multiplication factor 61 */
-  CRM_PLL_MULT_62                        = 61, /*!< pll multiplication factor 62 */
-  CRM_PLL_MULT_63                        = 62, /*!< pll multiplication factor 63 */
-  CRM_PLL_MULT_64                        = 63  /*!< pll multiplication factor 64 */
-} crm_pll_mult_type;
-
-/**
-  * @brief crm pll clock source
-  */
-typedef enum
-{
-  CRM_PLL_SOURCE_HICK                    = 0x00, /*!< high speed internal clock as pll reference clock source */
-  CRM_PLL_SOURCE_HEXT                    = 0x01, /*!< high speed external crystal as pll reference clock source */
-  CRM_PLL_SOURCE_HEXT_DIV                = 0x02  /*!< high speed external crystal div as pll reference clock source */
-} crm_pll_clock_source_type;
-
-/**
-  * @brief crm pll clock output range
-  */
-typedef enum
-{
-  CRM_PLL_OUTPUT_RANGE_LE72MHZ           = 0x00, /*!< pll clock output range less than or equal to 72mhz */
-  CRM_PLL_OUTPUT_RANGE_GT72MHZ           = 0x01  /*!< pll clock output range greater than 72mhz */
-} crm_pll_output_range_type;
-
-/**
-  * @brief crm clock source
-  */
-typedef enum
-{
-  CRM_CLOCK_SOURCE_HICK                  = 0x00, /*!< high speed internal clock */
-  CRM_CLOCK_SOURCE_HEXT                  = 0x01, /*!< high speed external crystal */
-  CRM_CLOCK_SOURCE_PLL                   = 0x02, /*!< phase locking loop */
-  CRM_CLOCK_SOURCE_LEXT                  = 0x03, /*!< low speed external crystal */
-  CRM_CLOCK_SOURCE_LICK                  = 0x04  /*!< low speed internal clock */
-} crm_clock_source_type;
-
-/**
-  * @brief crm ahb division
-  */
-typedef enum
-{
-  CRM_AHB_DIV_1                          = 0x00, /*!< sclk div1 to ahbclk */
-  CRM_AHB_DIV_2                          = 0x08, /*!< sclk div2 to ahbclk */
-  CRM_AHB_DIV_4                          = 0x09, /*!< sclk div4 to ahbclk */
-  CRM_AHB_DIV_8                          = 0x0A, /*!< sclk div8 to ahbclk */
-  CRM_AHB_DIV_16                         = 0x0B, /*!< sclk div16 to ahbclk */
-  CRM_AHB_DIV_64                         = 0x0C, /*!< sclk div64 to ahbclk */
-  CRM_AHB_DIV_128                        = 0x0D, /*!< sclk div128 to ahbclk */
-  CRM_AHB_DIV_256                        = 0x0E, /*!< sclk div256 to ahbclk */
-  CRM_AHB_DIV_512                        = 0x0F  /*!< sclk div512 to ahbclk */
-} crm_ahb_div_type;
-
-/**
-  * @brief crm apb1 division
-  */
-typedef enum
-{
-  CRM_APB1_DIV_1                         = 0x00, /*!< ahbclk div1 to apb1clk */
-  CRM_APB1_DIV_2                         = 0x04, /*!< ahbclk div2 to apb1clk */
-  CRM_APB1_DIV_4                         = 0x05, /*!< ahbclk div4 to apb1clk */
-  CRM_APB1_DIV_8                         = 0x06, /*!< ahbclk div8 to apb1clk */
-  CRM_APB1_DIV_16                        = 0x07  /*!< ahbclk div16 to apb1clk */
-} crm_apb1_div_type;
-
-/**
-  * @brief crm apb2 division
-  */
-typedef enum
-{
-  CRM_APB2_DIV_1                         = 0x00, /*!< ahbclk div1 to apb2clk */
-  CRM_APB2_DIV_2                         = 0x04, /*!< ahbclk div2 to apb2clk */
-  CRM_APB2_DIV_4                         = 0x05, /*!< ahbclk div4 to apb2clk */
-  CRM_APB2_DIV_8                         = 0x06, /*!< ahbclk div8 to apb2clk */
-  CRM_APB2_DIV_16                        = 0x07  /*!< ahbclk div16 to apb2clk */
-} crm_apb2_div_type;
-
-/**
-  * @brief crm adc division
-  */
-typedef enum
-{
-  CRM_ADC_DIV_2                          = 0x00, /*!< apb2clk div2 to adcclk */
-  CRM_ADC_DIV_4                          = 0x01, /*!< apb2clk div4 to adcclk */
-  CRM_ADC_DIV_6                          = 0x02, /*!< apb2clk div6 to adcclk */
-  CRM_ADC_DIV_8                          = 0x03, /*!< apb2clk div8 to adcclk */
-  CRM_ADC_DIV_12                         = 0x05, /*!< apb2clk div12 to adcclk */
-  CRM_ADC_DIV_16                         = 0x07  /*!< apb2clk div16 to adcclk */
-} crm_adc_div_type;
-
-/**
-  * @brief crm usb division
-  */
-typedef enum
-{
-  CRM_USB_DIV_1_5                        = 0x00, /*!< pllclk div1.5 to usbclk */
-  CRM_USB_DIV_1                          = 0x01, /*!< pllclk div1 to usbclk */
-  CRM_USB_DIV_2_5                        = 0x02, /*!< pllclk div2.5 to usbclk */
-  CRM_USB_DIV_2                          = 0x03, /*!< pllclk div2 to usbclk */
-  CRM_USB_DIV_3_5                        = 0x04, /*!< pllclk div3.5 to usbclk */
-  CRM_USB_DIV_3                          = 0x05, /*!< pllclk div3 to usbclk */
-  CRM_USB_DIV_4                          = 0x06  /*!< pllclk div4 to usbclk */
-} crm_usb_div_type;
-
-/**
-  * @brief crm rtc clock
-  */
-typedef enum
-{
-  CRM_RTC_CLOCK_NOCLK                    = 0x00, /*!< no clock as rtc clock source */
-  CRM_RTC_CLOCK_LEXT                     = 0x01, /*!< low speed external crystal as rtc clock source */
-  CRM_RTC_CLOCK_LICK                     = 0x02, /*!< low speed internal clock as rtc clock source */
-  CRM_RTC_CLOCK_HEXT_DIV                 = 0x03  /*!< high speed external crystal div as rtc clock source */
-} crm_rtc_clock_type;
-
-/**
-  * @brief crm hick 48mhz division
-  */
-typedef enum
-{
-  CRM_HICK48_DIV6                        = 0x00, /*!< high speed internal clock (48 mhz) div6 */
-  CRM_HICK48_NODIV                       = 0x01  /*!< high speed internal clock (48 mhz) no div */
-} crm_hick_div_6_type;
-
-/**
-  * @brief crm hext division
-  */
-typedef enum
-{
-  CRM_HEXT_DIV_2                         = 0x00, /*!< high speed external crystal div2 */
-  CRM_HEXT_DIV_3                         = 0x01, /*!< high speed external crystal div3 */
-  CRM_HEXT_DIV_4                         = 0x02, /*!< high speed external crystal div4 */
-  CRM_HEXT_DIV_5                         = 0x03  /*!< high speed external crystal div5 */
-} crm_hext_div_type;
-
-/**
-  * @brief crm sclk select
-  */
-typedef enum
-{
-  CRM_SCLK_HICK                          = 0x00, /*!< select high speed internal clock as sclk */
-  CRM_SCLK_HEXT                          = 0x01, /*!< select high speed external crystal as sclk */
-  CRM_SCLK_PLL                           = 0x02  /*!< select phase locking loop clock as sclk */
-} crm_sclk_type;
-
-/**
-  * @brief crm clkout select
-  */
-typedef enum
-{
-  CRM_CLKOUT_NOCLK                       = 0x00, /*!< output no clock to clkout pin */
-  CRM_CLKOUT_LICK                        = 0x02, /*!< output low speed internal clock to clkout pin */
-  CRM_CLKOUT_LEXT                        = 0x03, /*!< output low speed external crystal to clkout pin */
-  CRM_CLKOUT_SCLK                        = 0x04, /*!< output system clock to clkout pin */
-  CRM_CLKOUT_HICK                        = 0x05, /*!< output high speed internal clock to clkout pin */
-  CRM_CLKOUT_HEXT                        = 0x06, /*!< output high speed external crystal to clkout pin */
-  CRM_CLKOUT_PLL_DIV_2                   = 0x07, /*!< output phase locking loop clock div2 to clkout pin */
-  CRM_CLKOUT_PLL_DIV_4                   = 0x0C, /*!< output phase locking loop clock div4 to clkout pin */
-  CRM_CLKOUT_USB                         = 0x0D, /*!< output usbclk to clkout pin */
-  CRM_CLKOUT_ADC                         = 0x0E  /*!< output adcclk to clkout pin */
-} crm_clkout_select_type;
-
-/**
-  * @brief crm clkout division
-  */
-typedef enum
-{
-  CRM_CLKOUT_DIV_1                       = 0x00, /*!< clkout div1 */
-  CRM_CLKOUT_DIV_2                       = 0x08, /*!< clkout div2 */
-  CRM_CLKOUT_DIV_4                       = 0x09, /*!< clkout div4 */
-  CRM_CLKOUT_DIV_8                       = 0x0A, /*!< clkout div8 */
-  CRM_CLKOUT_DIV_16                      = 0x0B, /*!< clkout div16 */
-  CRM_CLKOUT_DIV_64                      = 0x0C, /*!< clkout div64 */
-  CRM_CLKOUT_DIV_128                     = 0x0D, /*!< clkout div128 */
-  CRM_CLKOUT_DIV_256                     = 0x0E, /*!< clkout div256 */
-  CRM_CLKOUT_DIV_512                     = 0x0F  /*!< clkout div512 */
-} crm_clkout_div_type;
-
-/**
-  * @brief crm auto step mode
-  */
-typedef enum
-{
-  CRM_AUTO_STEP_MODE_DISABLE             = 0x00, /*!< disable auto step mode */
-  CRM_AUTO_STEP_MODE_ENABLE              = 0x03  /*!< enable auto step mode */
-} crm_auto_step_mode_type;
-
-/**
-  * @brief crm usbdev interrupt remap
-  */
-typedef enum
-{
-  CRM_USB_INT19_INT20                    = 0x00, /*!< usb high and low priority irq numer use 19 and 20 */
-  CRM_USB_INT73_INT74                    = 0x01  /*!< usb high and low priority irq numer use 73 and 74 */
-} crm_usb_int_map_type;
-
-/**
-  * @brief crm usb 48 mhz clock source select
-  */
-typedef enum
-{
-  CRM_USB_CLOCK_SOURCE_PLL               = 0x00, /*!< select phase locking loop clock as usb clock source */
-  CRM_USB_CLOCK_SOURCE_HICK              = 0x01  /*!< select high speed internal clock as usb clock source */
-} crm_usb_clock_source_type;
-
-/**
-  * @brief crm hick as system clock frequency select
-  */
-typedef enum
-{
-  CRM_HICK_SCLK_8MHZ                     = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
-  CRM_HICK_SCLK_48MHZ                    = 0x01  /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
-} crm_hick_sclk_frequency_type;
-
-/**
-  * @brief crm emac output pulse width
-  */
-typedef enum
-{
-  CRM_EMAC_PULSE_125MS                   = 0x00, /*!< emac output pulse width 125ms */
-  CRM_EMAC_PULSE_1SCLK                   = 0x01  /*!< emac output pulse width 1 system clock */
-} crm_emac_output_pulse_type;
-
-/**
-  * @brief crm clocks freqency structure
-  */
-typedef struct
-{
-  uint32_t sclk_freq; /*!< system clock frequency */
-  uint32_t ahb_freq;  /*!< ahb bus clock frequency */
-  uint32_t apb2_freq; /*!< apb2 bus clock frequency */
-  uint32_t apb1_freq; /*!< apb1 bus clock frequency */
-  uint32_t adc_freq;  /*!< adc clock frequency */
-} crm_clocks_freq_type;
-
-/**
-  * @brief type define crm register all
-  */
-typedef struct
-{
-  /**
-    * @brief crm ctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t hicken               : 1; /* [0] */
-      __IO uint32_t hickstbl             : 1; /* [1] */
-      __IO uint32_t hicktrim             : 6; /* [7:2] */
-      __IO uint32_t hickcal              : 8; /* [15:8] */
-      __IO uint32_t hexten               : 1; /* [16] */
-      __IO uint32_t hextstbl             : 1; /* [17] */
-      __IO uint32_t hextbyps             : 1; /* [18] */
-      __IO uint32_t cfden                : 1; /* [19] */
-      __IO uint32_t reserved1            : 4; /* [23:20] */
-      __IO uint32_t pllen                : 1; /* [24] */
-      __IO uint32_t pllstbl              : 1; /* [25] */
-      __IO uint32_t reserved2            : 6; /* [31:26] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief crm cfg register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t cfg;
-    struct
-    {
-      __IO uint32_t sclksel              : 2; /* [1:0] */
-      __IO uint32_t sclksts              : 2; /* [3:2] */
-      __IO uint32_t ahbdiv               : 4; /* [7:4] */
-      __IO uint32_t apb1div              : 3; /* [10:8] */
-      __IO uint32_t apb2div              : 3; /* [13:11] */
-      __IO uint32_t adcdiv_l             : 2; /* [15:14] */
-      __IO uint32_t pllrcs               : 1; /* [16] */
-      __IO uint32_t pllhextdiv           : 1; /* [17] */
-      __IO uint32_t pllmult_l            : 4; /* [21:18] */
-      __IO uint32_t usbdiv_l             : 2; /* [23:22] */
-      __IO uint32_t clkout_sel           : 3; /* [26:24] */
-      __IO uint32_t usbdiv_h             : 1; /* [27] */
-      __IO uint32_t adcdiv_h             : 1; /* [28] */
-      __IO uint32_t pllmult_h            : 2; /* [30:29] */
-      __IO uint32_t pllrange             : 1; /* [31] */
-    } cfg_bit;
-  };
-
-  /**
-    * @brief crm clkint register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t clkint;
-    struct
-    {
-      __IO uint32_t lickstblf            : 1; /* [0] */
-      __IO uint32_t lextstblf            : 1; /* [1] */
-      __IO uint32_t hickstblf            : 1; /* [2] */
-      __IO uint32_t hextstblf            : 1; /* [3] */
-      __IO uint32_t pllstblf             : 1; /* [4] */
-      __IO uint32_t reserved1            : 2; /* [6:5] */
-      __IO uint32_t cfdf                 : 1; /* [7] */
-      __IO uint32_t lickstblien          : 1; /* [8] */
-      __IO uint32_t lextstblien          : 1; /* [9] */
-      __IO uint32_t hickstblien          : 1; /* [10] */
-      __IO uint32_t hextstblien          : 1; /* [11] */
-      __IO uint32_t pllstblien           : 1; /* [12] */
-      __IO uint32_t reserved2            : 3; /* [15:13] */
-      __IO uint32_t lickstblfc           : 1; /* [16] */
-      __IO uint32_t lextstblfc           : 1; /* [17] */
-      __IO uint32_t hickstblfc           : 1; /* [18] */
-      __IO uint32_t hextstblfc           : 1; /* [19] */
-      __IO uint32_t pllstblfc            : 1; /* [20] */
-      __IO uint32_t reserved3            : 2; /* [22:21] */
-      __IO uint32_t cfdfc                : 1; /* [23] */
-      __IO uint32_t reserved4            : 8; /* [31:24] */
-    } clkint_bit;
-  };
-
-  /**
-    * @brief crm apb2rst register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t apb2rst;
-    struct
-    {
-      __IO uint32_t iomuxrst             : 1; /* [0] */
-      __IO uint32_t exintrst             : 1; /* [1] */
-      __IO uint32_t gpioarst             : 1; /* [2] */
-      __IO uint32_t gpiobrst             : 1; /* [3] */
-      __IO uint32_t gpiocrst             : 1; /* [4] */
-      __IO uint32_t gpiodrst             : 1; /* [5] */
-      __IO uint32_t gpioerst             : 1; /* [6] */
-      __IO uint32_t reserved1            : 2; /* [8:7] */
-      __IO uint32_t adc1rst              : 1; /* [9] */
-      __IO uint32_t adc2rst              : 1; /* [10] */
-      __IO uint32_t tmr1rst              : 1; /* [11] */
-      __IO uint32_t spi1rst              : 1; /* [12] */
-      __IO uint32_t tmr8rst              : 1; /* [13] */
-      __IO uint32_t usart1rst            : 1; /* [14] */
-      __IO uint32_t adc3rst              : 1; /* [15] */
-      __IO uint32_t reserved2            : 3; /* [18:16] */
-      __IO uint32_t tmr9rst              : 1; /* [19] */
-      __IO uint32_t tmr10rst             : 1; /* [20] */
-      __IO uint32_t tmr11rst             : 1; /* [21] */
-      __IO uint32_t accrst               : 1; /* [22] */
-      __IO uint32_t i2c3rst              : 1; /* [23] */
-      __IO uint32_t usart6rst            : 1; /* [24] */
-      __IO uint32_t uart7rst             : 1; /* [25] */
-      __IO uint32_t uart8rst             : 1; /* [26] */
-      __IO uint32_t reserved3            : 5; /* [31:27] */
-    } apb2rst_bit;
-  };
-
-  /**
-    * @brief crm apb1rst register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t apb1rst;
-    struct
-    {
-      __IO uint32_t tmr2rst              : 1; /* [0] */
-      __IO uint32_t tmr3rst              : 1; /* [1] */
-      __IO uint32_t tmr4rst              : 1; /* [2] */
-      __IO uint32_t tmr5rst              : 1; /* [3] */
-      __IO uint32_t tmr6rst              : 1; /* [4] */
-      __IO uint32_t tmr7rst              : 1; /* [5] */
-      __IO uint32_t tmr12rst             : 1; /* [6] */
-      __IO uint32_t tmr13rst             : 1; /* [7] */
-      __IO uint32_t tmr14rst             : 1; /* [8] */
-      __IO uint32_t reserved1            : 2; /* [10:9] */
-      __IO uint32_t wwdtrst              : 1; /* [11] */
-      __IO uint32_t reserved2            : 2; /* [13:12] */
-      __IO uint32_t spi2rst              : 1; /* [14] */
-      __IO uint32_t spi3rst              : 1; /* [15] */
-      __IO uint32_t spi4rst              : 1; /* [16] */
-      __IO uint32_t usart2rst            : 1; /* [17] */
-      __IO uint32_t usart3rst            : 1; /* [18] */
-      __IO uint32_t uart4rst             : 1; /* [19] */
-      __IO uint32_t uart5rst             : 1; /* [20] */
-      __IO uint32_t i2c1rst              : 1; /* [21] */
-      __IO uint32_t i2c2rst              : 1; /* [22] */
-      __IO uint32_t usbrst               : 1; /* [23] */
-      __IO uint32_t reserved3            : 1; /* [24] */
-      __IO uint32_t can1rst              : 1; /* [25] */
-      __IO uint32_t can2rst              : 1; /* [26] */
-      __IO uint32_t bprrst               : 1; /* [27] */
-      __IO uint32_t pwcrst               : 1; /* [28] */
-      __IO uint32_t dacrst               : 1; /* [29] */
-      __IO uint32_t reserved4            : 2; /* [31:30] */
-    } apb1rst_bit;
-  };
-
-  /**
-    * @brief crm ahben register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t ahben;
-#if defined (AT32F403Axx)
-    struct
-    {
-      __IO uint32_t dma1en               : 1; /* [0] */
-      __IO uint32_t dma2en               : 1; /* [1] */
-      __IO uint32_t sramen               : 1; /* [2] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t flashen              : 1; /* [4] */
-      __IO uint32_t reserved2            : 1; /* [5] */
-      __IO uint32_t crcen                : 1; /* [6] */
-      __IO uint32_t reserved3            : 1; /* [7] */
-      __IO uint32_t xmcen                : 1; /* [8] */
-      __IO uint32_t reserved4            : 1; /* [9] */
-      __IO uint32_t sdio1en              : 1; /* [10] */
-      __IO uint32_t sdio2en              : 1; /* [11] */
-      __IO uint32_t reserved5            : 20;/* [31:12] */
-    } ahben_bit;
-#endif
-#if defined (AT32F407xx)
-    struct
-    {
-      __IO uint32_t dma1en               : 1; /* [0] */
-      __IO uint32_t dma2en               : 1; /* [1] */
-      __IO uint32_t sramen               : 1; /* [2] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t flashen              : 1; /* [4] */
-      __IO uint32_t reserved2            : 1; /* [5] */
-      __IO uint32_t crcen                : 1; /* [6] */
-      __IO uint32_t reserved3            : 1; /* [7] */
-      __IO uint32_t xmcen                : 1; /* [8] */
-      __IO uint32_t reserved4            : 1; /* [9] */
-      __IO uint32_t sdio1en              : 1; /* [10] */
-      __IO uint32_t sdio2en              : 1; /* [11] */
-      __IO uint32_t reserved5            : 2; /* [13:12] */
-      __IO uint32_t emacen               : 1; /* [14] */
-      __IO uint32_t emactxen             : 1; /* [15] */
-      __IO uint32_t emacrxen             : 1; /* [16] */
-      __IO uint32_t reserved6            : 11;/* [27:17] */
-      __IO uint32_t emacptpen            : 1; /* [28] */
-      __IO uint32_t reserved7            : 3; /* [31:29] */
-    } ahben_bit;
-#endif
-  };
-
-  /**
-    * @brief crm apb2en register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t apb2en;
-    struct
-    {
-      __IO uint32_t iomuxen              : 1; /* [0] */
-      __IO uint32_t reserved1            : 1; /* [1] */
-      __IO uint32_t gpioaen              : 1; /* [2] */
-      __IO uint32_t gpioben              : 1; /* [3] */
-      __IO uint32_t gpiocen              : 1; /* [4] */
-      __IO uint32_t gpioden              : 1; /* [5] */
-      __IO uint32_t gpioeen              : 1; /* [6] */
-      __IO uint32_t reserved2            : 2; /* [8:7] */
-      __IO uint32_t adc1en               : 1; /* [9] */
-      __IO uint32_t adc2en               : 1; /* [10] */
-      __IO uint32_t tmr1en               : 1; /* [11] */
-      __IO uint32_t spi1en               : 1; /* [12] */
-      __IO uint32_t tmr8en               : 1; /* [13] */
-      __IO uint32_t usart1en             : 1; /* [14] */
-      __IO uint32_t adc3en               : 1; /* [15] */
-      __IO uint32_t reserved3            : 3; /* [18:16] */
-      __IO uint32_t tmr9en               : 1; /* [19] */
-      __IO uint32_t tmr10en              : 1; /* [20] */
-      __IO uint32_t tmr11en              : 1; /* [21] */
-      __IO uint32_t accen                : 1; /* [22] */
-      __IO uint32_t i2c3en               : 1; /* [23] */
-      __IO uint32_t usart6en             : 1; /* [24] */
-      __IO uint32_t uart7en              : 1; /* [25] */
-      __IO uint32_t uart8en              : 1; /* [26] */
-      __IO uint32_t reserved4            : 5; /* [31:27] */
-    } apb2en_bit;
-  };
-
-  /**
-    * @brief crm apb1en register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t apb1en;
-    struct
-    {
-      __IO uint32_t tmr2en               : 1; /* [0] */
-      __IO uint32_t tmr3en               : 1; /* [1] */
-      __IO uint32_t tmr4en               : 1; /* [2] */
-      __IO uint32_t tmr5en               : 1; /* [3] */
-      __IO uint32_t tmr6en               : 1; /* [4] */
-      __IO uint32_t tmr7en               : 1; /* [5] */
-      __IO uint32_t tmr12en              : 1; /* [6] */
-      __IO uint32_t tmr13en              : 1; /* [7] */
-      __IO uint32_t tmr14en              : 1; /* [8] */
-      __IO uint32_t reserved1            : 2; /* [10:9] */
-      __IO uint32_t wwdten               : 1; /* [11] */
-      __IO uint32_t reserved2            : 2; /* [13:12] */
-      __IO uint32_t spi2en               : 1; /* [14] */
-      __IO uint32_t spi3en               : 1; /* [15] */
-      __IO uint32_t spi4en               : 1; /* [16] */
-      __IO uint32_t usart2en             : 1; /* [17] */
-      __IO uint32_t usart3en             : 1; /* [18] */
-      __IO uint32_t uart4en              : 1; /* [19] */
-      __IO uint32_t uart5en              : 1; /* [20] */
-      __IO uint32_t i2c1en               : 1; /* [21] */
-      __IO uint32_t i2c2en               : 1; /* [22] */
-      __IO uint32_t usben                : 1; /* [23] */
-      __IO uint32_t reserved3            : 1; /* [24] */
-      __IO uint32_t can1en               : 1; /* [25] */
-      __IO uint32_t can2en               : 1; /* [26] */
-      __IO uint32_t bpren                : 1; /* [27] */
-      __IO uint32_t pwcen                : 1; /* [28] */
-      __IO uint32_t dacen                : 1; /* [29] */
-      __IO uint32_t reserved4            : 2; /* [31:30] */
-    } apb1en_bit;
-  };
-
-  /**
-    * @brief crm bpdc register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t bpdc;
-    struct
-    {
-      __IO uint32_t lexten               : 1; /* [0] */
-      __IO uint32_t lextstbl             : 1; /* [1] */
-      __IO uint32_t lextbyps             : 1; /* [2] */
-      __IO uint32_t reserved1            : 5; /* [7:3] */
-      __IO uint32_t rtcsel               : 2; /* [9:8] */
-      __IO uint32_t reserved2            : 5; /* [14:10] */
-      __IO uint32_t rtcen                : 1; /* [15] */
-      __IO uint32_t bpdrst               : 1; /* [16] */
-      __IO uint32_t reserved3            : 15;/* [31:17] */
-    } bpdc_bit;
-  };
-
-  /**
-    * @brief crm ctrlsts register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t ctrlsts;
-    struct
-    {
-      __IO uint32_t licken               : 1; /* [0] */
-      __IO uint32_t lickstbl             : 1; /* [1] */
-      __IO uint32_t reserved1            : 22;/* [23:2] */
-      __IO uint32_t rstfc                : 1; /* [24] */
-      __IO uint32_t reserved2            : 1; /* [25] */
-      __IO uint32_t nrstf                : 1; /* [26] */
-      __IO uint32_t porrstf              : 1; /* [27] */
-      __IO uint32_t swrstf               : 1; /* [28] */
-      __IO uint32_t wdtrstf              : 1; /* [29] */
-      __IO uint32_t wwdtrstf             : 1; /* [30] */
-      __IO uint32_t lprstf               : 1; /* [31] */
-    } ctrlsts_bit;
-  };
-
-  /**
-    * @brief crm ahbrst register, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t ahbrst;
-#if defined (AT32F407xx)
-    struct
-    {
-      __IO uint32_t reserved1            : 14;/* [13:0] */
-      __IO uint32_t emacrst              : 1; /* [14] */
-      __IO uint32_t reserved2            : 17;/* [31:15] */
-    } ahbrst_bit;
-#endif
-  };
-
-  /**
-    * @brief crm reserved1 register, offset:0x2C
-    */
-  __IO uint32_t reserved1;
-
-  /**
-    * @brief crm misc1 register, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t misc1;
-    struct
-    {
-      __IO uint32_t hickcal_key          : 8; /* [7:0] */
-      __IO uint32_t reserved1            : 8; /* [15:8] */
-      __IO uint32_t clkout_sel           : 1; /* [16] */
-      __IO uint32_t reserved2            : 7; /* [23:17] */
-      __IO uint32_t usbbufs              : 1; /* [24] */
-      __IO uint32_t hickdiv              : 1; /* [25] */
-      __IO uint32_t reserved3            : 2; /* [27:26] */
-      __IO uint32_t clkoutdiv            : 4; /* [31:28] */
-    } misc1_bit;
-  };
-
-  /**
-    * @brief crm reserved2 register, offset:0x4C~0x34
-    */
-  __IO uint32_t reserved2[7];
-
-  /**
-    * @brief crm misc2 register, offset:0x50
-    */
-  union
-  {
-    __IO uint32_t misc2;
-    struct
-    {
-      __IO uint32_t reserved1            : 16;/* [15:0] */
-      __IO uint32_t clk_to_tmr           : 1; /* [16] */
-      __IO uint32_t reserved2            : 15;/* [31:17] */
-    } misc2_bit;
-  };
-
-  /**
-    * @brief crm misc3 register, offset:0x54
-    */
-  union
-  {
-    __IO uint32_t misc3;
-    struct
-    {
-      __IO uint32_t reserved1            : 4; /* [3:0] */
-      __IO uint32_t auto_step_en         : 2; /* [5:4] */
-      __IO uint32_t reserved2            : 2; /* [7:6] */
-      __IO uint32_t hick_to_usb          : 1; /* [8] */
-      __IO uint32_t hick_to_sclk         : 1; /* [9] */
-      __IO uint32_t reserved3            : 2; /* [11:10] */
-      __IO uint32_t hextdiv              : 2; /* [13:12] */
-      __IO uint32_t reserved4            : 1; /* [14] */
-      __IO uint32_t emac_pps_sel         : 1; /* [15] */
-      __IO uint32_t reserved5            : 16;/* [31:16] */
-    } misc3_bit;
-  };
-
-  /**
-    * @brief crm reserved3 register, offset:0x58
-    */
-  __IO uint32_t reserved3;
-
-  /**
-    * @brief crm intmap register, offset:0x5C
-    */
-  union
-  {
-    __IO uint32_t intmap;
-    struct
-    {
-      __IO uint32_t usbintmap            : 1; /* [0] */
-      __IO uint32_t reserved1            : 31;/* [31:1] */
-    } intmap_bit;
-  };
-
-} crm_type;
-
-/**
-  * @}
-  */
-
-#define CRM                              ((crm_type *) CRM_BASE)
-
-/** @defgroup CRM_exported_functions
-  * @{
-  */
-
-void crm_reset(void);
-void crm_lext_bypass(confirm_state new_state);
-void crm_hext_bypass(confirm_state new_state);
-flag_status crm_flag_get(uint32_t flag);
-error_status crm_hext_stable_wait(void);
-void crm_hick_clock_trimming_set(uint8_t trim_value);
-void crm_hick_clock_calibration_set(uint8_t cali_value);
-void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
-void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
-void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state);
-void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
-void crm_flag_clear(uint32_t flag);
-void crm_rtc_clock_select(crm_rtc_clock_type value);
-void crm_rtc_clock_enable(confirm_state new_state);
-void crm_ahb_div_set(crm_ahb_div_type value);
-void crm_apb1_div_set(crm_apb1_div_type value);
-void crm_apb2_div_set(crm_apb2_div_type value);
-void crm_adc_clock_div_set(crm_adc_div_type div_value);
-void crm_usb_clock_div_set(crm_usb_div_type div_value);
-void crm_clock_failure_detection_enable(confirm_state new_state);
-void crm_battery_powered_domain_reset(confirm_state new_state);
-void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value, crm_pll_output_range_type pll_range);
-void crm_sysclk_switch(crm_sclk_type value);
-crm_sclk_type crm_sysclk_switch_status_get(void);
-void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
-void crm_clock_out_set(crm_clkout_select_type clkout);
-void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
-void crm_auto_step_mode_enable(confirm_state new_state);
-void crm_usb_interrupt_remapping_set(crm_usb_int_map_type int_remap);
-void crm_hick_divider_select(crm_hick_div_6_type value);
-void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
-void crm_usb_clock_source_select(crm_usb_clock_source_type value);
-void crm_clkout_to_tmr10_enable(confirm_state new_state);
-void crm_hext_clock_div_set(crm_hext_div_type value);
-void crm_clkout_div_set(crm_clkout_div_type clkout_div);
-#if defined (AT32F407xx)
-void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_dac.h

@@ -1,374 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_dac.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 dac header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_DAC_H
-#define __AT32F403A_407_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-#define DAC1_D1DMAUDRF                   ((uint32_t)(0x00002000))
-#define DAC2_D2DMAUDRF                   ((uint32_t)(0x20000000))
-
-/** @defgroup DAC_exported_types
-  * @{
-  */
-
-/**
-  * @brief dac select type
-  */
-typedef enum
-{
-  DAC1_SELECT                            = 0x01, /*!< dac1 select */
-  DAC2_SELECT                            = 0x02  /*!< dac2 select */
-} dac_select_type;
-
-/**
-  * @brief dac trigger type
-  */
-typedef enum
-{
-  DAC_TMR6_TRGOUT_EVENT                  = 0x00, /*!< dac trigger selection:timer6 trgout event */
-  DAC_TMR8_TRGOUT_EVENT                  = 0x01, /*!< dac trigger selection:timer8 trgout event */
-  DAC_TMR7_TRGOUT_EVENT                  = 0x02, /*!< dac trigger selection:timer7 trgout event */
-  DAC_TMR5_TRGOUT_EVENT                  = 0x03, /*!< dac trigger selection:timer5 trgout event */
-  DAC_TMR2_TRGOUT_EVENT                  = 0x04, /*!< dac trigger selection:timer2 trgout event */
-  DAC_TMR4_TRGOUT_EVENT                  = 0x05, /*!< dac trigger selection:timer4 trgout event */
-  DAC_EXTERNAL_INTERRUPT_LINE_9          = 0x06, /*!< dac trigger selection:external line9 */
-  DAC_SOFTWARE_TRIGGER                   = 0x07  /*!< dac trigger selection:software trigger */
-} dac_trigger_type;
-
-/**
-  * @brief dac wave type
-  */
-typedef enum
-{
-  DAC_WAVE_GENERATE_NONE                 = 0x00, /*!< dac wave generation disabled */
-  DAC_WAVE_GENERATE_NOISE                = 0x01, /*!< dac noise wave generation enabled */
-  DAC_WAVE_GENERATE_TRIANGLE             = 0x02  /*!< dac triangle wave generation enabled */
-} dac_wave_type;
-
-/**
-  * @brief dac mask amplitude type
-  */
-typedef enum
-{
-  DAC_LSFR_BIT0_AMPLITUDE_1              = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
-  DAC_LSFR_BIT10_AMPLITUDE_3             = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
-  DAC_LSFR_BIT20_AMPLITUDE_7             = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
-  DAC_LSFR_BIT30_AMPLITUDE_15            = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
-  DAC_LSFR_BIT40_AMPLITUDE_31            = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
-  DAC_LSFR_BIT50_AMPLITUDE_63            = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
-  DAC_LSFR_BIT60_AMPLITUDE_127           = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
-  DAC_LSFR_BIT70_AMPLITUDE_255           = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
-  DAC_LSFR_BIT80_AMPLITUDE_511           = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
-  DAC_LSFR_BIT90_AMPLITUDE_1023          = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
-  DAC_LSFR_BITA0_AMPLITUDE_2047          = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
-  DAC_LSFR_BITB0_AMPLITUDE_4095          = 0x0B  /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
-} dac_mask_amplitude_type;
-
-/**
-  * @brief  dac1 aligned data type
-  */
-typedef enum
-{
-  DAC1_12BIT_RIGHT                       = 0x40007408, /*!< dac1 12-bit data right-aligned */
-  DAC1_12BIT_LEFT                        = 0x4000740C, /*!< dac1 12-bit data left-aligned */
-  DAC1_8BIT_RIGHT                        = 0x40007410  /*!< dac1 8-bit data right-aligned */
-} dac1_aligned_data_type;
-
-/**
-  * @brief  dac2 aligned data type
-  */
-typedef enum
-{
-  DAC2_12BIT_RIGHT                       = 0x40007414, /*!< dac2 12-bit data right-aligned */
-  DAC2_12BIT_LEFT                        = 0x40007418, /*!< dac2 12-bit data left-aligned */
-  DAC2_8BIT_RIGHT                        = 0x4000741C  /*!< dac2 8-bit data right-aligned */
-} dac2_aligned_data_type;
-
-/**
-  * @brief  dac dual data type
-  */
-typedef enum
-{
-  DAC_DUAL_12BIT_RIGHT                   = 0x40007420, /*!<double dac 12-bit data right-aligned */
-  DAC_DUAL_12BIT_LEFT                    = 0x40007424, /*!<double dac 12-bit data left-aligned */
-  DAC_DUAL_8BIT_RIGHT                    = 0x40007428  /*!<double dac 8-bit data right-aligned */
-} dac_dual_data_type;
-
-/**
-  * @brief type define dac register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief dac ctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t d1en                 : 1; /* [0] */
-      __IO uint32_t d1obdis              : 1; /* [1] */
-      __IO uint32_t d1trgen              : 1; /* [2] */
-      __IO uint32_t d1trgsel             : 3; /* [5:3] */
-      __IO uint32_t d1nm                 : 2; /* [7:6] */
-      __IO uint32_t d1nbsel              : 4; /* [11:8] */
-      __IO uint32_t d1dmaen              : 1; /* [12] */
-      __IO uint32_t reserved1            : 3; /* [15:13] */
-      __IO uint32_t d2en                 : 1; /* [16] */
-      __IO uint32_t d2obdis              : 1; /* [17] */
-      __IO uint32_t d2trgen              : 1; /* [18] */
-      __IO uint32_t d2trgsel             : 3; /* [21:19] */
-      __IO uint32_t d2nm                 : 2; /* [23:22] */
-      __IO uint32_t d2nbsel              : 4; /* [27:24] */
-      __IO uint32_t d2dmaen              : 1; /* [28] */
-      __IO uint32_t reserved2            : 3; /* [31:29] */
-    } ctrl_bit;
-  };
-
- /**
-    * @brief dac swtrg register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t swtrg;
-    struct
-    {
-      __IO uint32_t d1swtrg              : 1; /* [0] */
-      __IO uint32_t d2swtrg              : 1; /* [1] */
-      __IO uint32_t reserved1            : 30;/* [31:2] */
-    } swtrg_bit;
-  };
-
- /**
-    * @brief dac d1dth12r register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t d1dth12r;
-    struct
-    {
-      __IO uint32_t d1dt12r              : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:2] */
-    } d1dth12r_bit;
-  };
-
- /**
-    * @brief dac d1dth12l register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t d1dth12l;
-    struct
-    {
-      __IO uint32_t d1dt12l              : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:2] */
-    } d1dth12l_bit;
-  };
-
- /**
-    * @brief dac d1dth8r register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t d1dth8r;
-    struct
-    {
-      __IO uint32_t d1dt8r               : 8; /* [7:0] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } d1dth8r_bit;
-  };
-
- /**
-    * @brief dac d2dth12r register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t d2dth12r;
-    struct
-    {
-      __IO uint32_t d2dt12r              : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:2] */
-    } d2dth12r_bit;
-  };
-
- /**
-    * @brief dac d2dth12l register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t d2dth12l;
-    struct
-    {
-      __IO uint32_t d2dt12l              : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:2] */
-    } d2dth12l_bit;
-  };
-
- /**
-    * @brief dac d2dth8r register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t d2dth8r;
-    struct
-    {
-      __IO uint32_t d2dt8r               : 8; /* [7:0] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } d2dth8r_bit;
-  };
-
- /**
-    * @brief dac ddth12r register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t ddth12r;
-    struct
-    {
-      __IO uint32_t dd1dt12r             : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 4; /* [15:12] */
-      __IO uint32_t dd2dt12r             : 12;/* [27:16] */
-      __IO uint32_t reserved2            : 4; /* [31:28] */
-    } ddth12r_bit;
-  };
-
- /**
-    * @brief dac ddth12l register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t ddth12l;
-    struct
-    {
-      __IO uint32_t reserved1            : 4; /* [3:0] */
-      __IO uint32_t dd1dt12l             : 12;/* [15:4] */
-      __IO uint32_t reserved2            : 4; /* [19:16] */
-      __IO uint32_t dd2dt12l             : 12;/* [31:20] */
-    } ddth12l_bit;
-  };
-
- /**
-    * @brief dac ddth8r register, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t ddth8r;
-    struct
-    {
-      __IO uint32_t dd1dt8r              : 8; /* [7:0] */
-      __IO uint32_t dd2dt8r              : 8; /* [15:8] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } ddth8r_bit;
-  };
-
- /**
-    * @brief dac d1odt register, offset:0x2c
-    */
-  union
-  {
-    __IO uint32_t d1odt;
-    struct
-    {
-      __IO uint32_t d1odt                : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } d1odt_bit;
-  };
-
- /**
-    * @brief dac d2odt register, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t d2odt;
-    struct
-    {
-      __IO uint32_t d2odt                : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } d2odt_bit;
-  };
-} dac_type;
-
-/**
-  * @}
-  */
-
-#define DAC                              ((dac_type *) DAC_BASE)
-
-/** @defgroup DAC_exported_functions
-  * @{
-  */
-
-void dac_reset(void);
-void dac_enable(dac_select_type dac_select, confirm_state new_state);
-void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
-void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
-void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
-void dac_software_trigger_generate(dac_select_type dac_select);
-void dac_dual_software_trigger_generate(void);
-void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
-void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
-void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
-uint16_t dac_data_output_get(dac_select_type dac_select);
-void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
-void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
-void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_debug.h

@@ -1,171 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_debug.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 debug header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_DEBUG_H
-#define __AT32F403A_407_DEBUG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup DEBUG
-  * @{
-  */
-
-/** @defgroup DEBUG_mode_definition
-  * @{
-  */
-
-#define DEBUG_SLEEP                      0x00000001 /*!< debug sleep mode */
-#define DEBUG_DEEPSLEEP                  0x00000002 /*!< debug deepsleep mode */
-#define DEBUG_STANDBY                    0x00000004 /*!< debug standby mode */
-#define DEBUG_WDT_PAUSE                  0x00000100 /*!< debug watchdog timer pause */
-#define DEBUG_WWDT_PAUSE                 0x00000200 /*!< debug window watchdog timer pause */
-#define DEBUG_TMR1_PAUSE                 0x00000400 /*!< debug timer1 pause */
-#define DEBUG_TMR3_PAUSE                 0x00001000 /*!< debug timer3 pause */
-#define DEBUG_I2C1_SMBUS_TIMEOUT         0x00008000 /*!< debug i2c1 smbus timeout */
-#define DEBUG_I2C2_SMBUS_TIMEOUT         0x00010000 /*!< debug i2c2 smbus timeout */
-#define DEBUG_I2C3_SMBUS_TIMEOUT         0x80000000 /*!< debug i2c3 smbus timeout */
-#define DEBUG_TMR2_PAUSE                 0x00000800 /*!< debug timer2 pause */
-#define DEBUG_TMR4_PAUSE                 0x00002000 /*!< debug timer4 pause */
-#define DEBUG_CAN1_PAUSE                 0x00004000 /*!< debug can1 pause */
-#define DEBUG_TMR8_PAUSE                 0x00020000 /*!< debug timer8 pause */
-#define DEBUG_TMR5_PAUSE                 0x00040000 /*!< debug timer5 pause */
-#define DEBUG_TMR6_PAUSE                 0x00080000 /*!< debug timer6 pause */
-#define DEBUG_TMR7_PAUSE                 0x00100000 /*!< debug timer7 pause */
-#define DEBUG_CAN2_PAUSE                 0x00200000 /*!< debug can2 pause */
-#define DEBUG_TMR12_PAUSE                0x02000000 /*!< debug timer12 pause */
-#define DEBUG_TMR13_PAUSE                0x04000000 /*!< debug timer13 pause */
-#define DEBUG_TMR14_PAUSE                0x08000000 /*!< debug timer14 pause */
-#define DEBUG_TMR9_PAUSE                 0x10000000 /*!< debug timer9 pause */
-#define DEBUG_TMR10_PAUSE                0x20000000 /*!< debug timer10 pause */
-#define DEBUG_TMR11_PAUSE                0x40000000 /*!< debug timer11 pause */
-
-/**
-  * @}
-  */
-
-/** @defgroup DEBUG_exported_types
-  * @{
-  */
-
-/**
-  * @brief type define debug register all
-  */
-typedef struct
-{
-  /**
-    * @brief debug idcode register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t pid;
-    struct
-    {
-      __IO uint32_t pid                  : 32;/* [31:0] */
-    } idcode_bit;
-  };
-
-  /**
-    * @brief debug ctrl register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t sleep_debug          : 1;/* [0] */
-      __IO uint32_t deepsleep_debug      : 1;/* [1] */
-      __IO uint32_t standby_debug        : 1;/* [2] */
-      __IO uint32_t reserved1            : 2;/* [4:3] */
-      __IO uint32_t trace_ioen           : 1;/* [5] */
-      __IO uint32_t trace_mode           : 2;/* [7:6] */
-      __IO uint32_t wdt_pause            : 1;/* [8] */
-      __IO uint32_t wwdt_pause           : 1;/* [9] */
-      __IO uint32_t tmr1_pause           : 1;/* [10] */
-      __IO uint32_t tmr2_pause           : 1;/* [11] */
-      __IO uint32_t tmr3_pause           : 1;/* [12] */
-      __IO uint32_t tmr4_pause           : 1;/* [13] */
-      __IO uint32_t can1_pause           : 1;/* [14] */
-      __IO uint32_t i2c1_smbus_timeout   : 1;/* [15] */
-      __IO uint32_t i2c2_smbus_timeout   : 1;/* [16] */
-      __IO uint32_t tmr8_pause           : 1;/* [17] */
-      __IO uint32_t tmr5_pause           : 1;/* [18] */
-      __IO uint32_t tmr6_pause           : 1;/* [19] */
-      __IO uint32_t tmr7_pause           : 1;/* [20] */
-      __IO uint32_t can2_pause           : 1;/* [21] */
-      __IO uint32_t reserved2            : 3;/* [24:22] */
-      __IO uint32_t tmr12_pause          : 1;/* [25] */
-      __IO uint32_t tmr13_pause          : 1;/* [26] */
-      __IO uint32_t tmr14_pause          : 1;/* [27] */
-      __IO uint32_t tmr9_pause           : 1;/* [28] */
-      __IO uint32_t tmr10_pause          : 1;/* [29] */
-      __IO uint32_t tmr11_pause          : 1;/* [30] */
-      __IO uint32_t i2c3_smbus_timeout   : 1;/* [31] */
-    } ctrl_bit;
-  };
-
-} debug_type;
-
-/**
-  * @}
-  */
-
-#define DEBUGMCU                         ((debug_type *) DEBUG_BASE)
-
-/** @defgroup DEBUG_exported_functions
-  * @{
-  */
-
-uint32_t debug_device_id_get(void);
-void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_def.h

@@ -1,69 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_def.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 macros header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_DEF_H
-#define __AT32F403A_407_DEF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* gnu compiler */
-#if defined (__GNUC__)
-  #ifndef ALIGNED_HEAD
-    #define ALIGNED_HEAD
-  #endif
-  #ifndef ALIGNED_TAIL
-    #define ALIGNED_TAIL                 __attribute__ ((aligned (4)))
-  #endif
-#endif
-
-/* arm compiler */
-#if defined (__CC_ARM)
-  #ifndef ALIGNED_HEAD
-    #define ALIGNED_HEAD                 __align(4)
-  #endif
-  #ifndef ALIGNED_TAIL
-    #define ALIGNED_TAIL
-  #endif
-#endif
-
-/* iar compiler */
-#if defined (__ICCARM__)
-  #ifndef ALIGNED_HEAD
-    #define ALIGNED_HEAD
-  #endif
-  #ifndef ALIGNED_TAIL
-    #define ALIGNED_TAIL
-  #endif
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_dma.h

@@ -1,550 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_dma.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 dma header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_DMA_H
-#define __AT32F403A_407_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/** @defgroup DMA_interrupts_definition
-  * @brief dma interrupt
-  * @{
-  */
-
-#define DMA_FDT_INT                      ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
-#define DMA_HDT_INT                      ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
-#define DMA_DTERR_INT                    ((uint32_t)0x00000008) /*!< dma errorr interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flexible_channel
-  * @{
-  */
-
-#define FLEX_CHANNEL1                    ((uint8_t)0x01) /*!< dma flexible channel1 */
-#define FLEX_CHANNEL2                    ((uint8_t)0x02) /*!< dma flexible channel2 */
-#define FLEX_CHANNEL3                    ((uint8_t)0x03) /*!< dma flexible channel3 */
-#define FLEX_CHANNEL4                    ((uint8_t)0x04) /*!< dma flexible channel4 */
-#define FLEX_CHANNEL5                    ((uint8_t)0x05) /*!< dma flexible channel5 */
-#define FLEX_CHANNEL6                    ((uint8_t)0x06) /*!< dma flexible channel6 */
-#define FLEX_CHANNEL7                    ((uint8_t)0x07) /*!< dma flexible channel7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flags_definition
-  * @brief dma flag
-  * @{
-  */
-
-#define DMA1_GL1_FLAG                    ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
-#define DMA1_FDT1_FLAG                   ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
-#define DMA1_HDT1_FLAG                   ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
-#define DMA1_DTERR1_FLAG                 ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
-#define DMA1_GL2_FLAG                    ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
-#define DMA1_FDT2_FLAG                   ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
-#define DMA1_HDT2_FLAG                   ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
-#define DMA1_DTERR2_FLAG                 ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
-#define DMA1_GL3_FLAG                    ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
-#define DMA1_FDT3_FLAG                   ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
-#define DMA1_HDT3_FLAG                   ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
-#define DMA1_DTERR3_FLAG                 ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
-#define DMA1_GL4_FLAG                    ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
-#define DMA1_FDT4_FLAG                   ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
-#define DMA1_HDT4_FLAG                   ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
-#define DMA1_DTERR4_FLAG                 ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
-#define DMA1_GL5_FLAG                    ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
-#define DMA1_FDT5_FLAG                   ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
-#define DMA1_HDT5_FLAG                   ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
-#define DMA1_DTERR5_FLAG                 ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
-#define DMA1_GL6_FLAG                    ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
-#define DMA1_FDT6_FLAG                   ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
-#define DMA1_HDT6_FLAG                   ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
-#define DMA1_DTERR6_FLAG                 ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
-#define DMA1_GL7_FLAG                    ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
-#define DMA1_FDT7_FLAG                   ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
-#define DMA1_HDT7_FLAG                   ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
-#define DMA1_DTERR7_FLAG                 ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
-
-#define DMA2_GL1_FLAG                    ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
-#define DMA2_FDT1_FLAG                   ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
-#define DMA2_HDT1_FLAG                   ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
-#define DMA2_DTERR1_FLAG                 ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
-#define DMA2_GL2_FLAG                    ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
-#define DMA2_FDT2_FLAG                   ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
-#define DMA2_HDT2_FLAG                   ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
-#define DMA2_DTERR2_FLAG                 ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
-#define DMA2_GL3_FLAG                    ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
-#define DMA2_FDT3_FLAG                   ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
-#define DMA2_HDT3_FLAG                   ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
-#define DMA2_DTERR3_FLAG                 ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
-#define DMA2_GL4_FLAG                    ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
-#define DMA2_FDT4_FLAG                   ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
-#define DMA2_HDT4_FLAG                   ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
-#define DMA2_DTERR4_FLAG                 ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
-#define DMA2_GL5_FLAG                    ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
-#define DMA2_FDT5_FLAG                   ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
-#define DMA2_HDT5_FLAG                   ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
-#define DMA2_DTERR5_FLAG                 ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
-#define DMA2_GL6_FLAG                    ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
-#define DMA2_FDT6_FLAG                   ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
-#define DMA2_HDT6_FLAG                   ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
-#define DMA2_DTERR6_FLAG                 ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
-#define DMA2_GL7_FLAG                    ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
-#define DMA2_FDT7_FLAG                   ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
-#define DMA2_HDT7_FLAG                   ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
-#define DMA2_DTERR7_FLAG                 ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_exported_types
-  * @{
-  */
-
-/**
-  * @brief dma flexible request type
-  */
-typedef enum
-{
-  DMA_FLEXIBLE_ADC1                      = 0x01, /*!< adc1 flexible request id */
-  DMA_FLEXIBLE_ADC3                      = 0x03, /*!< adc3 flexible request id */
-  DMA_FLEXIBLE_DAC1                      = 0x05, /*!< dac1 flexible request id */
-  DMA_FLEXIBLE_DAC2                      = 0x06, /*!< dac2 flexible request id */
-  DMA_FLEXIBLE_SPI1_RX                   = 0x09, /*!< spi1_rx flexible request id */
-  DMA_FLEXIBLE_SPI1_TX                   = 0x0A, /*!< spi1_tx flexible request id */
-  DMA_FLEXIBLE_SPI2_RX                   = 0x0B, /*!< spi2_rx flexible request id */
-  DMA_FLEXIBLE_SPI2_TX                   = 0x0C, /*!< spi2_tx flexible request id */
-  DMA_FLEXIBLE_SPI3_RX                   = 0x0D, /*!< spi3_rx flexible request id */
-  DMA_FLEXIBLE_SPI3_TX                   = 0x0E, /*!< spi3_tx flexible request id */
-  DMA_FLEXIBLE_SPI4_RX                   = 0x0F, /*!< spi4_rx flexible request id */
-  DMA_FLEXIBLE_SPI4_TX                   = 0x10, /*!< spi4_tx flexible request id */
-  DMA_FLEXIBLE_I2S2EXT_RX                = 0x11, /*!< i2s2ext_rx flexible request id */
-  DMA_FLEXIBLE_I2S2EXT_TX                = 0x12, /*!< i2s2ext_tx flexible request id */
-  DMA_FLEXIBLE_I2S3EXT_RX                = 0x13, /*!< i2s3ext_rx flexible request id */
-  DMA_FLEXIBLE_I2S3EXT_TX                = 0x14, /*!< i2s3ext_tx flexible request id */
-  DMA_FLEXIBLE_UART1_RX                  = 0x19, /*!< uart1_rx flexible request id */
-  DMA_FLEXIBLE_UART1_TX                  = 0x1A, /*!< uart1_tx flexible request id */
-  DMA_FLEXIBLE_UART2_RX                  = 0x1B, /*!< uart2_rx flexible request id */
-  DMA_FLEXIBLE_UART2_TX                  = 0x1C, /*!< uart2_tx flexible request id */
-  DMA_FLEXIBLE_UART3_RX                  = 0x1D, /*!< uart3_rx flexible request id */
-  DMA_FLEXIBLE_UART3_TX                  = 0x1E, /*!< uart3_tx flexible request id */
-  DMA_FLEXIBLE_UART4_RX                  = 0x1F, /*!< uart4_rx flexible request id */
-  DMA_FLEXIBLE_UART4_TX                  = 0x20, /*!< uart4_tx flexible request id */
-  DMA_FLEXIBLE_UART5_RX                  = 0x21, /*!< uart5_rx flexible request id */
-  DMA_FLEXIBLE_UART5_TX                  = 0x22, /*!< uart5_tx flexible request id */
-  DMA_FLEXIBLE_UART6_RX                  = 0x23, /*!< uart6_rx flexible request id */
-  DMA_FLEXIBLE_UART6_TX                  = 0x24, /*!< uart6_tx flexible request id */
-  DMA_FLEXIBLE_UART7_RX                  = 0x25, /*!< uart7_rx flexible request id */
-  DMA_FLEXIBLE_UART7_TX                  = 0x26, /*!< uart7_tx flexible request id */
-  DMA_FLEXIBLE_UART8_RX                  = 0x27, /*!< uart8_rx flexible request id */
-  DMA_FLEXIBLE_UART8_TX                  = 0x28, /*!< uart8_tx flexible request id */
-  DMA_FLEXIBLE_I2C1_RX                   = 0x29, /*!< i2c1_rx flexible request id */
-  DMA_FLEXIBLE_I2C1_TX                   = 0x2A, /*!< i2c1_tx flexible request id */
-  DMA_FLEXIBLE_I2C2_RX                   = 0x2B, /*!< i2c2_rx flexible request id */
-  DMA_FLEXIBLE_I2C2_TX                   = 0x2C, /*!< i2c2_tx flexible request id */
-  DMA_FLEXIBLE_I2C3_RX                   = 0x2D, /*!< i2c3_rx flexible request id */
-  DMA_FLEXIBLE_I2C3_TX                   = 0x2E, /*!< i2c3_tx flexible request id */
-  DMA_FLEXIBLE_SDIO1                     = 0x31, /*!< sdio1 flexible request id */
-  DMA_FLEXIBLE_SDIO2                     = 0x32, /*!< sdio2 flexible request id */
-  DMA_FLEXIBLE_TMR1_TRIG                 = 0x35, /*!< tmr1_trig flexible request id */
-  DMA_FLEXIBLE_TMR1_HALL                 = 0x36, /*!< tmr1_hall flexible request id */
-  DMA_FLEXIBLE_TMR1_OVERFLOW             = 0x37, /*!< tmr1_overflow flexible request id */
-  DMA_FLEXIBLE_TMR1_CH1                  = 0x38, /*!< tmr1_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR1_CH2                  = 0x39, /*!< tmr1_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR1_CH3                  = 0x3A, /*!< tmr1_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR1_CH4                  = 0x3B, /*!< tmr1_ch4 flexible request id */
-  DMA_FLEXIBLE_TMR2_TRIG                 = 0x3D, /*!< tmr2_trig flexible request id */
-  DMA_FLEXIBLE_TMR2_OVERFLOW             = 0x3F, /*!< tmr2_overflow flexible request id */
-  DMA_FLEXIBLE_TMR2_CH1                  = 0x40, /*!< tmr2_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR2_CH2                  = 0x41, /*!< tmr2_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR2_CH3                  = 0x42, /*!< tmr2_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR2_CH4                  = 0x43, /*!< tmr2_ch4 flexible request id */
-  DMA_FLEXIBLE_TMR3_TRIG                 = 0x45, /*!< tmr3_trig flexible request id */
-  DMA_FLEXIBLE_TMR3_OVERFLOW             = 0x47, /*!< tmr3_overflow flexible request id */
-  DMA_FLEXIBLE_TMR3_CH1                  = 0x48, /*!< tmr3_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR3_CH2                  = 0x49, /*!< tmr3_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR3_CH3                  = 0x4A, /*!< tmr3_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR3_CH4                  = 0x4B, /*!< tmr3_ch4 flexible request id */
-  DMA_FLEXIBLE_TMR4_TRIG                 = 0x4D, /*!< tmr4_trig flexible request id */
-  DMA_FLEXIBLE_TMR4_OVERFLOW             = 0x4F, /*!< tmr4_overflow flexible request id */
-  DMA_FLEXIBLE_TMR4_CH1                  = 0x50, /*!< tmr4_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR4_CH2                  = 0x51, /*!< tmr4_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR4_CH3                  = 0x52, /*!< tmr4_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR4_CH4                  = 0x53, /*!< tmr4_ch4 flexible request id */
-  DMA_FLEXIBLE_TMR5_TRIG                 = 0x55, /*!< tmr5_trig flexible request id */
-  DMA_FLEXIBLE_TMR5_OVERFLOW             = 0x57, /*!< tmr5_overflow flexible request id */
-  DMA_FLEXIBLE_TMR5_CH1                  = 0x58, /*!< tmr5_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR5_CH2                  = 0x59, /*!< tmr5_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR5_CH3                  = 0x5A, /*!< tmr5_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR5_CH4                  = 0x5B, /*!< tmr5_ch4 flexible request id */
-  DMA_FLEXIBLE_TMR6_OVERFLOW             = 0x5F, /*!< tmr6_overflow flexible request id */
-  DMA_FLEXIBLE_TMR7_OVERFLOW             = 0x67, /*!< tmr7_overflow flexible request id */
-  DMA_FLEXIBLE_TMR8_TRIG                 = 0x6D, /*!< tmr8_trig flexible request id */
-  DMA_FLEXIBLE_TMR8_HALL                 = 0x6E, /*!< tmr8_hall flexible request id */
-  DMA_FLEXIBLE_TMR8_OVERFLOW             = 0x6F, /*!< tmr8_overflow flexible request id */
-  DMA_FLEXIBLE_TMR8_CH1                  = 0x70, /*!< tmr8_ch1 flexible request id */
-  DMA_FLEXIBLE_TMR8_CH2                  = 0x71, /*!< tmr8_ch2 flexible request id */
-  DMA_FLEXIBLE_TMR8_CH3                  = 0x72, /*!< tmr8_ch3 flexible request id */
-  DMA_FLEXIBLE_TMR8_CH4                  = 0x73  /*!< tmr8_ch4 flexible request id */
-} dma_flexible_request_type;
-
-/**
-  * @brief dma direction type
-  */
-typedef enum
-{
-  DMA_DIR_PERIPHERAL_TO_MEMORY           = 0x0000, /*!< dma data transfer direction:peripheral to memory */
-  DMA_DIR_MEMORY_TO_PERIPHERAL           = 0x0010, /*!< dma data transfer direction:memory to peripheral */
-  DMA_DIR_MEMORY_TO_MEMORY               = 0x4000  /*!< dma data transfer direction:memory to memory */
-} dma_dir_type;
-
-/**
-  * @brief dma peripheral incremented type
-  */
-typedef enum
-{
-  DMA_PERIPHERAL_INC_DISABLE             = 0x00, /*!< dma peripheral increment mode disable */
-  DMA_PERIPHERAL_INC_ENABLE              = 0x01  /*!< dma peripheral increment mode enable */
-} dma_peripheral_inc_type;
-
-/**
-  * @brief dma memory incremented type
-  */
-typedef enum
-{
-  DMA_MEMORY_INC_DISABLE                 = 0x00, /*!< dma memory increment mode disable */
-  DMA_MEMORY_INC_ENABLE                  = 0x01  /*!< dma memory increment mode enable */
-} dma_memory_inc_type;
-
-/**
-  * @brief dma peripheral data size type
-  */
-typedef enum
-{
-  DMA_PERIPHERAL_DATA_WIDTH_BYTE         = 0x00, /*!< dma peripheral databus width 8bit */
-  DMA_PERIPHERAL_DATA_WIDTH_HALFWORD     = 0x01, /*!< dma peripheral databus width 16bit */
-  DMA_PERIPHERAL_DATA_WIDTH_WORD         = 0x02  /*!< dma peripheral databus width 32bit */
-} dma_peripheral_data_size_type;
-
-/**
-  * @brief dma memory data size type
-  */
-typedef enum
-{
-  DMA_MEMORY_DATA_WIDTH_BYTE             = 0x00, /*!< dma memory databus width 8bit */
-  DMA_MEMORY_DATA_WIDTH_HALFWORD         = 0x01, /*!< dma memory databus width 16bit */
-  DMA_MEMORY_DATA_WIDTH_WORD             = 0x02  /*!< dma memory databus width 32bit */
-} dma_memory_data_size_type;
-
-/**
-  * @brief dma priority level type
-  */
-typedef enum
-{
-  DMA_PRIORITY_LOW                       = 0x00, /*!< dma channel priority: low */
-  DMA_PRIORITY_MEDIUM                    = 0x01, /*!< dma channel priority: mediue */
-  DMA_PRIORITY_HIGH                      = 0x02, /*!< dma channel priority: high */
-  DMA_PRIORITY_VERY_HIGH                 = 0x03  /*!< dma channel priority: very high */
-} dma_priority_level_type;
-
-/**
-  * @brief dma init type
-  */
-typedef struct
-{
-  uint32_t                               peripheral_base_addr;    /*!< base addrress for peripheral */
-  uint32_t                               memory_base_addr;        /*!< base addrress for memory */
-  dma_dir_type                           direction;               /*!< dma transmit direction, peripheral as source or as destnation  */
-  uint16_t                               buffer_size;             /*!< counter to transfer */
-  confirm_state                          peripheral_inc_enable;   /*!< periphera address increment after one transmit */
-  confirm_state                          memory_inc_enable;       /*!< memory address increment after one transmit */
-  dma_peripheral_data_size_type          peripheral_data_width;   /*!< peripheral data width for transmit */
-  dma_memory_data_size_type              memory_data_width;       /*!< memory data width for transmit */
-  confirm_state                          loop_mode_enable;        /*!< when circular mode enable, buffer size will reload if count to 0 */
-  dma_priority_level_type                priority;                /*!< dma priority can choose from very high, high, dedium or low */
-} dma_init_type;
-
-/**
-  * @brief type define dma register
-  */
-typedef struct
-{
-  /**
-    * @brief dma sts register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t gf1                  : 1; /* [0] */
-      __IO uint32_t fdtf1                : 1; /* [1] */
-      __IO uint32_t hdtf1                : 1; /* [2] */
-      __IO uint32_t dterrf1              : 1; /* [3] */
-      __IO uint32_t gf2                  : 1; /* [4] */
-      __IO uint32_t fdtf2                : 1; /* [5] */
-      __IO uint32_t hdtf2                : 1; /* [6] */
-      __IO uint32_t dterrf2              : 1; /* [7] */
-      __IO uint32_t gf3                  : 1; /* [8] */
-      __IO uint32_t fdtf3                : 1; /* [9] */
-      __IO uint32_t hdtf3                : 1; /* [10] */
-      __IO uint32_t dterrf3              : 1; /* [11] */
-      __IO uint32_t gf4                  : 1; /* [12] */
-      __IO uint32_t fdtf4                : 1; /* [13] */
-      __IO uint32_t hdtf4                : 1; /* [14] */
-      __IO uint32_t dterrf4              : 1; /* [15] */
-      __IO uint32_t gf5                  : 1; /* [16] */
-      __IO uint32_t fdtf5                : 1; /* [17] */
-      __IO uint32_t hdtf5                : 1; /* [18] */
-      __IO uint32_t dterrf5              : 1; /* [19] */
-      __IO uint32_t gf6                  : 1; /* [20] */
-      __IO uint32_t fdtf6                : 1; /* [21] */
-      __IO uint32_t hdtf6                : 1; /* [22] */
-      __IO uint32_t dterrf6              : 1; /* [23] */
-      __IO uint32_t gf7                  : 1; /* [24] */
-      __IO uint32_t fdtf7                : 1; /* [25] */
-      __IO uint32_t hdtf7                : 1; /* [26] */
-      __IO uint32_t dterrf7              : 1; /* [27] */
-      __IO uint32_t reserved1            : 4; /* [31:28] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief dma clr register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t clr;
-    struct
-    {
-      __IO uint32_t gfc1                 : 1; /* [0] */
-      __IO uint32_t fdtfc1               : 1; /* [1] */
-      __IO uint32_t hdtfc1               : 1; /* [2] */
-      __IO uint32_t dterrfc1             : 1; /* [3] */
-      __IO uint32_t gfc2                 : 1; /* [4] */
-      __IO uint32_t fdtfc2               : 1; /* [5] */
-      __IO uint32_t hdtfc2               : 1; /* [6] */
-      __IO uint32_t dterrfc2             : 1; /* [7] */
-      __IO uint32_t gfc3                 : 1; /* [8] */
-      __IO uint32_t fdtfc3               : 1; /* [9] */
-      __IO uint32_t hdtfc3               : 1; /* [10] */
-      __IO uint32_t dterrfc3             : 1; /* [11] */
-      __IO uint32_t gfc4                 : 1; /* [12] */
-      __IO uint32_t fdtfc4               : 1; /* [13] */
-      __IO uint32_t hdtfc4               : 1; /* [14] */
-      __IO uint32_t dterrfc4             : 1; /* [15] */
-      __IO uint32_t gfc5                 : 1; /* [16] */
-      __IO uint32_t fdtfc5               : 1; /* [17] */
-      __IO uint32_t hdtfc5               : 1; /* [18] */
-      __IO uint32_t dterrfc5             : 1; /* [19] */
-      __IO uint32_t gfc6                 : 1; /* [20] */
-      __IO uint32_t fdtfc6               : 1; /* [21] */
-      __IO uint32_t hdtfc6               : 1; /* [22] */
-      __IO uint32_t dterrfc6             : 1; /* [23] */
-      __IO uint32_t gfc7                 : 1; /* [24] */
-      __IO uint32_t fdtfc7               : 1; /* [25] */
-      __IO uint32_t hdtfc7               : 1; /* [26] */
-      __IO uint32_t dterrfc7             : 1; /* [27] */
-      __IO uint32_t reserved1            : 4; /* [31:28] */
-    } clr_bit;
-  };
-  /**
-    * @brief reserved, offset:0x08~0x9C
-    */
-  __IO uint32_t reserved1[38];
-  /**
-    * @brief dma src_sel0 register, offset:0xA0
-    */
-  union
-  {
-    __IO uint32_t src_sel0;
-    struct
-    {
-      __IO uint32_t ch1_src              : 8; /* [7:0] */
-      __IO uint32_t ch2_src              : 8; /* [15:8] */
-      __IO uint32_t ch3_src              : 8; /* [23:16] */
-      __IO uint32_t ch4_src              : 8; /* [31:24] */
-    } src_sel0_bit;
-  };
-
-  /**
-    * @brief dma src_sel1 register, offset:0xA4
-    */
-  union
-  {
-    __IO uint32_t src_sel1;
-    struct
-    {
-      __IO uint32_t ch5_src              : 8; /* [7:0] */
-      __IO uint32_t ch6_src              : 8; /* [15:8] */
-      __IO uint32_t ch7_src              : 8; /* [23:16] */
-      __IO uint32_t dma_flex_en          : 1; /* [24] */
-      __IO uint32_t reserved1            : 7; /* [31:25] */
-    } src_sel1_bit;
-  };
-} dma_type;
-
-/**
-  * @brief type define dma channel register all
-  */
-typedef struct
-{
-  /**
-    * @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t chen                 : 1; /* [0] */
-      __IO uint32_t fdtien               : 1; /* [1] */
-      __IO uint32_t hdtien               : 1; /* [2] */
-      __IO uint32_t dterrien             : 1; /* [3] */
-      __IO uint32_t dtd                  : 1; /* [4] */
-      __IO uint32_t lm                   : 1; /* [5] */
-      __IO uint32_t pincm                : 1; /* [6] */
-      __IO uint32_t mincm                : 1; /* [7] */
-      __IO uint32_t pwidth               : 2; /* [9:8] */
-      __IO uint32_t mwidth               : 2; /* [11:10] */
-      __IO uint32_t chpl                 : 2; /* [13:12] */
-      __IO uint32_t m2m                  : 1; /* [14] */
-      __IO uint32_t reserved1            : 17;/* [31:15] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
-    */
-  union
-  {
-    __IO uint32_t dtcnt;
-    struct
-    {
-      __IO uint32_t cnt                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } dtcnt_bit;
-  };
-
-  /**
-    * @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
-    */
-  union
-  {
-    __IO uint32_t paddr;
-    struct
-    {
-      __IO uint32_t paddr                : 32;/* [31:0] */
-    } paddr_bit;
-  };
-
-  /**
-    * @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
-    */
-  union
-  {
-    __IO uint32_t maddr;
-    struct
-    {
-      __IO uint32_t maddr                : 32;/* [31:0] */
-    } maddr_bit;
-  };
-} dma_channel_type;
-
-/**
-  * @}
-  */
-
-#define DMA1                             ((dma_type *) DMA1_BASE)
-#define DMA1_CHANNEL1                    ((dma_channel_type *) DMA1_CHANNEL1_BASE)
-#define DMA1_CHANNEL2                    ((dma_channel_type *) DMA1_CHANNEL2_BASE)
-#define DMA1_CHANNEL3                    ((dma_channel_type *) DMA1_CHANNEL3_BASE)
-#define DMA1_CHANNEL4                    ((dma_channel_type *) DMA1_CHANNEL4_BASE)
-#define DMA1_CHANNEL5                    ((dma_channel_type *) DMA1_CHANNEL5_BASE)
-#define DMA1_CHANNEL6                    ((dma_channel_type *) DMA1_CHANNEL6_BASE)
-#define DMA1_CHANNEL7                    ((dma_channel_type *) DMA1_CHANNEL7_BASE)
-
-#define DMA2                             ((dma_type *) DMA2_BASE)
-#define DMA2_CHANNEL1                    ((dma_channel_type *) DMA2_CHANNEL1_BASE)
-#define DMA2_CHANNEL2                    ((dma_channel_type *) DMA2_CHANNEL2_BASE)
-#define DMA2_CHANNEL3                    ((dma_channel_type *) DMA2_CHANNEL3_BASE)
-#define DMA2_CHANNEL4                    ((dma_channel_type *) DMA2_CHANNEL4_BASE)
-#define DMA2_CHANNEL5                    ((dma_channel_type *) DMA2_CHANNEL5_BASE)
-#define DMA2_CHANNEL6                    ((dma_channel_type *) DMA2_CHANNEL6_BASE)
-#define DMA2_CHANNEL7                    ((dma_channel_type *) DMA2_CHANNEL7_BASE)
-
-/** @defgroup DMA_exported_functions
-  * @{
-  */
-
-void dma_reset(dma_channel_type* dmax_channely);
-void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
-uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
-void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
-void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
-void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
-flag_status dma_flag_get(uint32_t dmax_flag);
-void dma_flag_clear(uint32_t dmax_flag);
-void dma_default_para_init(dma_init_type* dma_init_struct);
-void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_emac.h

@@ -1,1711 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_emac.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 emac header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_EMAC_H
-#define __AT32F403A_407_EMAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup EMAC
-  * @{
-  */
-
-#define PHY_TIMEOUT                      (0x0FFFFFFF) /*!< timeout for phy response */
-
-/** @defgroup EMAC_smi_clock_border_definition
-  * @brief emac smi clock border
-  * @{
-  */
-
-#define EMAC_HCLK_BORDER_20MHZ           (20000000)   /*!< hclk boarder of 20 mhz */
-#define EMAC_HCLK_BORDER_35MHZ           (35000000)   /*!< hclk boarder of 35 mhz */
-#define EMAC_HCLK_BORDER_60MHZ           (60000000)   /*!< hclk boarder of 60 mhz */
-#define EMAC_HCLK_BORDER_100MHZ          (100000000)  /*!< hclk boarder of 100 mhz */
-#define EMAC_HCLK_BORDER_150MHZ          (150000000)  /*!< hclk boarder of 150 mhz */
-#define EMAC_HCLK_BORDER_240MHZ          (240000000)  /*!< hclk boarder of 240 mhz */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_interrupts_definition
-  * @brief emac interrupts
-  * @{
-  */
-
-#define EMAC_PMT_FLAG                    ((uint32_t)0x00000008) /*!< interrupt bit of pmt */
-#define EMAC_MMC_FLAG                    ((uint32_t)0x00000010) /*!< interrupt bit of mmc */
-#define EMAC_MMCR_FLAG                   ((uint32_t)0x00000020) /*!< interrupt bit of mmcr */
-#define EMAC_MMCT_FLAG                   ((uint32_t)0x00000040) /*!< interrupt bit of mmct */
-#define EMAC_TST_FLAG                    ((uint32_t)0x00000200) /*!< interrupt bit of tst */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_mmc_flags_definition
-  * @brief emac mmc flags
-  * @{
-  */
-
-#define MMC_RX_CRC_ERROR                 ((uint32_t)0x00000020) /*!< mmc error flag of rx crc */
-#define MMC_RX_ALIGN_ERROR               ((uint32_t)0x00000040) /*!< mmc error flag of rx alignment */
-#define MMC_RX_GOOD_UNICAST              ((uint32_t)0x00020000) /*!< mmc error flag of rx unicast good frames */
-#define MMC_TX_SINGLE_COL                ((uint32_t)0x00004000) /*!< mmc error flag of tx single collision */
-#define MMC_TX_MULTIPLE_COL              ((uint32_t)0x00008000) /*!< mmc error flag of tx multiple collision */
-#define MMC_TX_GOOD_FRAMES               ((uint32_t)0x00200000) /*!< mmc error flag of tx good frames */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_packet_definition
-  * @brief emac packet
-  * @{
-  */
-
-#define EMAC_MAX_PACKET_LENGTH           1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
-#define EMAC_HEADER                      14   /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */
-#define EMAC_CRC                         4    /*!< ethernet crc */
-#define EMAC_EXTRA                       2    /*!< extra bytes in some cases */
-#define VLAN_TAG                         4    /*!< optional 802.1q vlan tag */
-#define EMAC_MIN_PAYLOAD                 46   /*!< minimum ethernet payload size */
-#define EMAC_MAX_PAYLOAD                 1500 /*!< maximum ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD              9000 /*!< jumbo frame payload size */
-#define EMAC_DMARXDESC_FRAME_LENGTHSHIFT 16
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_tdes0_definition
-  * @brief tdes0 definition
-  * @{
-  */
-
-#define EMAC_DMATXDESC_OWN               ((uint32_t)0x80000000) /*!< own bit: descriptor is owned by dma engine */
-#define EMAC_DMATXDESC_IC                ((uint32_t)0x40000000) /*!< interrupt on completion */
-#define EMAC_DMATXDESC_LS                ((uint32_t)0x20000000) /*!< last segment */
-#define EMAC_DMATXDESC_FS                ((uint32_t)0x10000000) /*!< first segment */
-#define EMAC_DMATXDESC_DC                ((uint32_t)0x08000000) /*!< disable crc */
-#define EMAC_DMATXDESC_DP                ((uint32_t)0x04000000) /*!< disable padding */
-#define EMAC_DMATXDESC_TTSE              ((uint32_t)0x02000000) /*!< transmit time stamp enable */
-#define EMAC_DMATXDESC_CIC               ((uint32_t)0x00C00000) /*!< checksum insertion control: 4 cases */
-#define EMAC_DMATXDESC_CIC_BYPASS        ((uint32_t)0x00000000) /*!< do nothing: checksum engine is bypassed */
-#define EMAC_DMATXDESC_CIC_IPV4HEADER    ((uint32_t)0x00400000) /*!< ipv4 header checksum insertion */
-#define EMAC_DMATXDESC_CIC_TUI_SEG       ((uint32_t)0x00800000) /*!< tcp/udp/icmp checksum insertion calculated over segment only */
-#define EMAC_DMATXDESC_CIC_TUI_FULL      ((uint32_t)0x00C00000) /*!< tcp/udp/icmp checksum insertion fully calculated */
-#define EMAC_DMATXDESC_TER               ((uint32_t)0x00200000) /*!< transmit end of ring */
-#define EMAC_DMATXDESC_TCH               ((uint32_t)0x00100000) /*!< second address chained */
-#define EMAC_DMATXDESC_TTSS              ((uint32_t)0x00020000) /*!< tx time stamp status */
-#define EMAC_DMATXDESC_IHE               ((uint32_t)0x00010000) /*!< ip header error */
-#define EMAC_DMATXDESC_ES                ((uint32_t)0x00008000) /*!< error summary: or of the following bits: ue || ED || EC || LCO || NC || LCA || FF || JT */
-#define EMAC_DMATXDESC_JT                ((uint32_t)0x00004000) /*!< jabber timeout */
-#define EMAC_DMATXDESC_FF                ((uint32_t)0x00002000) /*!< frame flushed: dma/mtl flushed the frame due to SW flush */
-#define EMAC_DMATXDESC_PCE               ((uint32_t)0x00001000) /*!< payload checksum error */
-#define EMAC_DMATXDESC_LCA               ((uint32_t)0x00000800) /*!< loss of carrier: carrier lost during tramsmission */
-#define EMAC_DMATXDESC_NC                ((uint32_t)0x00000400) /*!< no carrier: no carrier signal from the tranceiver */
-#define EMAC_DMATXDESC_LCO               ((uint32_t)0x00000200) /*!< late collision: transmission aborted due to collision */
-#define EMAC_DMATXDESC_EC                ((uint32_t)0x00000100) /*!< excessive collision: transmission aborted after 16 collisions */
-#define EMAC_DMATXDESC_VF                ((uint32_t)0x00000080) /*!< vlan frame */
-#define EMAC_DMATXDESC_CC                ((uint32_t)0x00000078) /*!< collision count */
-#define EMAC_DMATXDESC_ED                ((uint32_t)0x00000004) /*!< excessive deferral */
-#define EMAC_DMATXDESC_UF                ((uint32_t)0x00000002) /*!< underflow error: late data arrival from the memory */
-#define EMAC_DMATXDESC_DB                ((uint32_t)0x00000001) /*!< deferred bit */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_tdes1_definition
-  * @brief  tdes1 descriptor
-  * @{
-  */
-
-#define EMAC_DMATXDESC_TBS2              ((uint32_t)0x1FFF0000) /*!< transmit buffer2 size */
-#define EMAC_DMATXDESC_TBS1              ((uint32_t)0x00001FFF) /*!< transmit buffer1 size */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_tdes2_definition
-  * @brief  tdes2 descriptor
-  * @{
-  */
-
-#define EMAC_DMATXDESC_B1AP              ((uint32_t)0xFFFFFFFF) /*!< buffer1 address pointer */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_tdes3_definition
-  * @brief  tdes3 descriptor
-  * @{
-  */
-
-#define EMAC_DMATxDesc_B2AP              ((uint32_t)0xFFFFFFFF) /*!< buffer2 address pointer */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_rdes0_definition
-  * @brief  rdes0 descriptor
-  * @{
-  */
-
-#define EMAC_DMARXDESC_OWN               ((uint32_t)0x80000000) /*!< own bit: descriptor is owned by dma engine  */
-#define EMAC_DMARXDESC_AFM               ((uint32_t)0x40000000) /*!< da filter fail for the rx frame  */
-#define EMAC_DMARXDESC_FL                ((uint32_t)0x3FFF0000) /*!< receive descriptor frame length  */
-#define EMAC_DMARXDESC_ES                ((uint32_t)0x00008000) /*!< error summary: or of the following bits: de || OE || IPC || LC || RWT || RE || CE */
-#define EMAC_DMARXDESC_DE                ((uint32_t)0x00004000) /*!< desciptor error: no more descriptors for receive frame  */
-#define EMAC_DMARXDESC_SAF               ((uint32_t)0x00002000) /*!< sa filter fail for the received frame */
-#define EMAC_DMARXDESC_LE                ((uint32_t)0x00001000) /*!< frame size not matching with length field */
-#define EMAC_DMARXDESC_OE                ((uint32_t)0x00000800) /*!< overflow error: frame was damaged due to buffer overflow */
-#define EMAC_DMARXDESC_VLAN              ((uint32_t)0x00000400) /*!< vlan tag: received frame is a vlan frame */
-#define EMAC_DMARXDESC_FS                ((uint32_t)0x00000200) /*!< first descriptor of the frame  */
-#define EMAC_DMARXDESC_LS                ((uint32_t)0x00000100) /*!< last descriptor of the frame  */
-#define EMAC_DMARXDESC_IPV4HCE           ((uint32_t)0x00000080) /*!< ipc checksum error: rx ipv4 header checksum error   */
-#define EMAC_DMARXDESC_LC                ((uint32_t)0x00000040) /*!< late collision occurred during reception   */
-#define EMAC_DMARXDESC_FT                ((uint32_t)0x00000020) /*!< frame ept_type - ethernet, otherwise 802.3    */
-#define EMAC_DMARXDESC_RWT               ((uint32_t)0x00000010) /*!< receive watchdog timeout: watchdog timer expired during reception    */
-#define EMAC_DMARXDESC_RE                ((uint32_t)0x00000008) /*!< receive error: error reported by mii interface  */
-#define EMAC_DMARXDESC_DBE               ((uint32_t)0x00000004) /*!< dribble bit error: frame contains non int multiple of 8 bits  */
-#define EMAC_DMARXDESC_CE                ((uint32_t)0x00000002) /*!< crc error */
-#define EMAC_DMARXDESC_MAMPCE            ((uint32_t)0x00000001) /*!< rx mac address/payload checksum error: rx mac address matched/ Rx Payload Checksum Error */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_rdes1_definition
-  * @brief  rdes1 descriptor
-  * @{
-  */
-
-#define EMAC_DMARXDESC_DIC               ((uint32_t)0x80000000) /*!< disable interrupt on completion */
-#define EMAC_DMARXDESC_RBS2              ((uint32_t)0x1FFF0000) /*!< receive buffer2 size */
-#define EMAC_DMARXDESC_RER               ((uint32_t)0x00008000) /*!< receive end of ring */
-#define EMAC_DMARXDESC_RCH               ((uint32_t)0x00004000) /*!< second address chained */
-#define EMAC_DMARXDESC_RBS1              ((uint32_t)0x00001FFF) /*!< receive buffer1 size */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_rdes2_definition
-  * @brief  rdes2 descriptor
-  * @{
-  */
-
-#define EMAC_DMARXDESC_B1AP              ((uint32_t)0xFFFFFFFF) /*!< buffer1 address pointer */
-
-/**
-  * @}
-  */
-
-/** @defgroup EMAC_dma_descriptor_rdes3_definition
-  * @brief  rdes3 descriptor
-  * @{
-  */
-
-#define EMAC_DMARXDESC_B2AP              ((uint32_t)0xFFFFFFFF) /*!< buffer2 address pointer */
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  emac dma flag
-  */
-#define EMAC_DMA_TI_FLAG                 ((uint32_t)0x00000001) /*!< emac dma transmit interrupt */
-#define EMAC_DMA_TPS_FLAG                ((uint32_t)0x00000002) /*!< emac dma transmit process stopped */
-#define EMAC_DMA_TBU_FLAG                ((uint32_t)0x00000004) /*!< emac dma transmit buffer unavailable */
-#define EMAC_DMA_TJT_FLAG                ((uint32_t)0x00000008) /*!< emac dma transmit jabber timeout */
-#define EMAC_DMA_OVF_FLAG                ((uint32_t)0x00000010) /*!< emac dma receive overflow */
-#define EMAC_DMA_UNF_FLAG                ((uint32_t)0x00000020) /*!< emac dma transmit underflow */
-#define EMAC_DMA_RI_FLAG                 ((uint32_t)0x00000040) /*!< emac dma receive interrupt */
-#define EMAC_DMA_RBU_FLAG                ((uint32_t)0x00000080) /*!< emac dma receive buffer unavailable */
-#define EMAC_DMA_RPS_FLAG                ((uint32_t)0x00000100) /*!< emac dma receive process stopped */
-#define EMAC_DMA_RWT_FLAG                ((uint32_t)0x00000200) /*!< emac dma receive watchdog timeout */
-#define EMAC_DMA_ETI_FLAG                ((uint32_t)0x00000400) /*!< emac dma early transmit interrupt */
-#define EMAC_DMA_FBEI_FLAG               ((uint32_t)0x00002000) /*!< emac dma fatal bus error interrupt */
-#define EMAC_DMA_ERI_FLAG                ((uint32_t)0x00004000) /*!< emac dma early receive interrupt */
-#define EMAC_DMA_AIS_FLAG                ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */
-#define EMAC_DMA_NIS_FLAG                ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */
-
-/** @defgroup EMAC_exported_types
-  * @{
-  */
-
-/**
-  * @brief  emac auto negotiation type
-  */
-typedef enum
-{
-  EMAC_AUTO_NEGOTIATION_OFF              = 0x00, /*!< disable auto negotiation */
-  EMAC_AUTO_NEGOTIATION_ON               = 0x01  /*!< enable auto negotiation */
-} emac_auto_negotiation_type;
-
-/**
-  * @brief  emac back_off limit type
-  */
-typedef enum
-{
-  EMAC_BACKOFF_LIMIT_0                   = 0x00, /*!< retransmission clock gap numbers betwenn n and 10 */
-  EMAC_BACKOFF_LIMIT_1                   = 0x01, /*!< retransmission clock gap numbers betwenn n and 8 */
-  EMAC_BACKOFF_LIMIT_2                   = 0x02, /*!< retransmission clock gap numbers betwenn n and 4 */
-  EMAC_BACKOFF_LIMIT_3                   = 0x03  /*!< retransmission clock gap numbers betwenn n and 1 */
-} emac_bol_type;
-
-/**
-  * @brief  emac duplex type
-  */
-typedef enum
-{
-  EMAC_HALF_DUPLEX                       = 0x00, /*!< half duplex */
-  EMAC_FULL_DUPLEX                       = 0x01  /*!< full duplex */
-} emac_duplex_type;
-
-/**
-  * @brief  emac speed type
-  */
-typedef enum
-{
-  EMAC_SPEED_10MBPS                      = 0x00, /*!< 10 mbps */
-  EMAC_SPEED_100MBPS                     = 0x01  /*!< 100 mbps */
-} emac_speed_type;
-
-/**
-  * @brief  emac interframe gap type
-  */
-typedef enum
-{
-  EMAC_INTERFRAME_GAP_96BIT              = 0x00, /*!< 96-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_88BIT              = 0x01, /*!< 88-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_80BIT              = 0x02, /*!< 80-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_72BIT              = 0x03, /*!< 72-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_64BIT              = 0x04, /*!< 64-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_56BIT              = 0x05, /*!< 56-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_48BIT              = 0x06, /*!< 48-bit numbers between two frames */
-  EMAC_INTERFRAME_GAP_40BIT              = 0x07  /*!< 40-bit numbers between two frames */
-} emac_intergrame_gap_type;
-
-/**
-  * @brief  mdc clock range type
-  */
-typedef enum
-{
-  EMAC_CLOCK_RANGE_60_TO_100             = 0x00, /*!< mdc is hclk/42 */
-  EMAC_CLOCK_RANGE_100_TO_150            = 0x01, /*!< mdc is hclk/62 */
-  EMAC_CLOCK_RANGE_20_TO_35              = 0x02, /*!< mdc is hclk/16 */
-  EMAC_CLOCK_RANGE_35_TO_60              = 0x03, /*!< mdc is hclk/26 */
-  EMAC_CLOCK_RANGE_150_TO_240            = 0x04  /*!< mdc is hclk/102 */
-} emac_clock_range_type;
-
-/**
-  * @brief  emac control frames filter type
-  */
-typedef enum
-{
-  EMAC_CONTROL_FRAME_PASSING_NO          = 0x00, /*!< don't pass any control frame to application */
-  EMAC_CONTROL_FRAME_PASSING_ALL         = 0x02, /*!< pass all control frames to application */
-  EMAC_CONTROL_FRAME_PASSING_MATCH       = 0x03  /*!< only pass filtered control frames to application */
-} emac_control_frames_filter_type;
-
-/**
-  * @brief  pause threshold type
-  */
-typedef enum
-{
-  EMAC_PAUSE_4_SLOT_TIME                 = 0x00, /*!< pause time is 4 slot time */
-  EMAC_PAUSE_28_SLOT_TIME                = 0x01, /*!< pause time is 28 slot time */
-  EMAC_PAUSE_144_SLOT_TIME               = 0x02, /*!< pause time is 144 slot time */
-  EMAC_PAUSE_256_SLOT_TIME               = 0x03  /*!< pause time is 256 slot time */
-} emac_pause_slot_threshold_type;
-
-/**
-  * @brief  interrupt mask type
-  */
-typedef enum
-{
-  EMAC_INTERRUPT_PMT_MASK                = 0x00, /*!< mask pmt interrupt */
-  EMAC_INTERRUPT_TST_MASK                = 0x01  /*!< mask tst interrupt */
-} emac_interrupt_mask_type;
-
-/**
-  * @brief  mac address type
-  */
-typedef enum
-{
-  EMAC_ADDRESS_FILTER_1                  = 0x01, /*!< mac address 1 filter */
-  EMAC_ADDRESS_FILTER_2                  = 0x02, /*!< mac address 2 filter */
-  EMAC_ADDRESS_FILTER_3                  = 0x03  /*!< mac address 3 filter */
-} emac_address_type;
-
-/**
-  * @brief  address filter type
-  */
-typedef enum
-{
-  EMAC_DESTINATION_FILTER                = 0x00, /*!< destination mac address filter */
-  EMAC_SOURCE_FILTER                     = 0x01  /*!< source mac address filter */
-} emac_address_filter_type;
-
-/**
-  * @brief  address mask type
-  */
-typedef enum
-{
-  EMAC_ADDRESS_MASK_8L0                  = 0x01, /*!< byte 0 of mac address low register */
-  EMAC_ADDRESS_MASK_15L8                 = 0x02, /*!< byte 1 of mac address low register */
-  EMAC_ADDRESS_MASK_23L16                = 0x04, /*!< byte 2 of mac address low register */
-  EMAC_ADDRESS_MASK_31L24                = 0x08, /*!< byte 3 of mac address low register */
-  EMAC_ADDRESS_MASK_7H0                  = 0x10, /*!< byte 0 of mac address high register */
-  EMAC_ADDRESS_MASK_15H8                 = 0x20  /*!< byte 1 of mac address high register */
-} emac_address_mask_type;
-
-/**
-  * @brief  rx tx priority ratio type
-  */
-typedef enum
-{
-  EMAC_DMA_1_RX_1_TX                     = 0x00, /*!< rx/tx ratio is 1:1 */
-  EMAC_DMA_2_RX_1_TX                     = 0x01, /*!< rx/tx ratio is 2:1 */
-  EMAC_DMA_3_RX_1_TX                     = 0x02, /*!< rx/tx ratio is 3:1 */
-  EMAC_DMA_4_RX_1_TX                     = 0x03  /*!< rx/tx ratio is 4:1 */
-} emac_dma_rx_tx_ratio_type;
-
-/**
-  * @brief  programmable burst length
-  */
-typedef enum
-{
-  EMAC_DMA_PBL_1                         = 0x01, /*!< maximum 1 time of beats to be transferred in one dma transaction */
-  EMAC_DMA_PBL_2                         = 0x02, /*!< maximum 2 times of beats to be transferred in one dma transaction */
-  EMAC_DMA_PBL_4                         = 0x04, /*!< maximum 4 times of beats to be transferred in one dma transaction */
-  EMAC_DMA_PBL_8                         = 0x08, /*!< maximum 8 times of beats to be transferred in one dma transaction */
-  EMAC_DMA_PBL_16                        = 0x10, /*!< maximum 16 times of beats to be transferred in one dma transaction */
-  EMAC_DMA_PBL_32                        = 0x20  /*!< maximum 32 times of beats to be transferred in one dma transaction */
-} emac_dma_pbl_type;
-
-/**
-  * @brief  dma tx rx type
-  */
-typedef enum
-{
-  EMAC_DMA_TRANSMIT                      = 0x00, /*!< transmit dma */
-  EMAC_DMA_RECEIVE                       = 0x01  /*!< receive dma */
-} emac_dma_tx_rx_type;
-
-/**
-  * @brief  dma receive process status type
-  */
-typedef enum
-{
-  EMAC_DMA_RX_RESET_STOP_COMMAND         = 0x00, /*!< receive reset or stop command */
-  EMAC_DMA_RX_FETCH_DESCRIPTOR           = 0x01, /*!< rx dma is fetching descriptor */
-  EMAC_DMA_RX_WAITING_PACKET             = 0x03, /*!< rx dma is waiting for packets */
-  EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE     = 0x04, /*!< rx dma descriptor is unavailable */
-  EMAC_DMA_RX_CLOSE_DESCRIPTOR           = 0x05, /*!< rx dma is closing descriptor */
-  EMAC_DMA_RX_FIFO_TO_HOST               = 0x07  /*!< rx dma is transferring data from fifo to host */
-} emac_dma_receive_process_status_type;
-
-/**
-  * @brief  dma transmit process status type
-  */
-typedef enum
-{
-  EMAC_DMA_TX_RESET_STOP_COMMAND         = 0x00, /*!< receive reset or stop command */
-  EMAC_DMA_TX_FETCH_DESCRIPTOR           = 0x01, /*!< tx dma is fetching descriptor */
-  EMAC_DMA_TX_WAITING_FOR_STATUS         = 0x02, /*!< tx dma is waiting for status message */
-  EMAC_DMA_TX_HOST_TO_FIFO               = 0x03, /*!< tx dma is reading data from host and forward data to fifo */
-  EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE     = 0x06, /*!< tx dma is unavailable or fifo underflow */
-  EMAC_DMA_TX_CLOSE_DESCRIPTOR           = 0x07  /*!< tx dma is closing descriptor */
-} emac_dma_transmit_process_status_type;
-
-/**
-  * @brief  dma operations type
-  */
-typedef enum
-{
-  EMAC_DMA_OPS_START_STOP_RECEIVE        = 0x00, /*!< start/stop receive */
-  EMAC_DMA_OPS_SECOND_FRAME              = 0x01, /*!< operate on second frame */
-  EMAC_DMA_OPS_FORWARD_UNDERSIZED        = 0x02, /*!< forward undersized good frames*/
-  EMAC_DMA_OPS_FORWARD_ERROR             = 0x03, /*!< forward error frames */
-  EMAC_DMA_OPS_START_STOP_TRANSMIT       = 0x04, /*!< start/stop transmission */
-  EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO       = 0x05, /*!< flush transmit fifo */
-  EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD    = 0x06, /*!< transmit store and forward */
-  EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE     = 0x07, /*!< disable flushing of received frames */
-  EMAC_DMA_OPS_RECEIVE_STORE_FORWARD     = 0x08, /*!< receive store and forward */
-  EMAC_DMA_OPS_DROP_ERROR_DISABLE        = 0x09  /*!< disbale dropping of tcp/ip checksum error frames */
-} emac_dma_operations_type;
-
-/**
-  * @brief  receive threshold control type
-  */
-typedef enum
-{
-  EMAC_DMA_RX_THRESHOLD_64_BYTES         = 0x00, /*!< receive starts when the frame size within the receiv fifo is larger than 64 bytes */
-  EMAC_DMA_RX_THRESHOLD_32_BYTES         = 0x01, /*!< receive starts when the frame size within the receiv fifo is larger than 32 bytes */
-  EMAC_DMA_RX_THRESHOLD_96_BYTES         = 0x02, /*!< receive starts when the frame size within the receiv fifo is larger than 96 bytes */
-  EMAC_DMA_RX_THRESHOLD_128_BYTES        = 0x03  /*!< receive starts when the frame size within the receiv fifo is larger than 128 bytes */
-} emac_dma_receive_threshold_type;
-
-/**
-  * @brief  transmit threshold control type
-  */
-typedef enum
-{
-  EMAC_DMA_TX_THRESHOLD_64_BYTES         = 0x00, /*!< transmission starts when the frame size within the transmit FIFO is larger than 64 bytes */
-  EMAC_DMA_TX_THRESHOLD_128_BYTES        = 0x01, /*!< transmission starts when the frame size within the transmit FIFO is larger than 128 bytes */
-  EMAC_DMA_TX_THRESHOLD_192_BYTES        = 0x02, /*!< transmission starts when the frame size within the transmit FIFO is larger than 192 bytes */
-  EMAC_DMA_TX_THRESHOLD_256_BYTES        = 0x03, /*!< transmission starts when the frame size within the transmit FIFO is larger than 256 bytes */
-  EMAC_DMA_TX_THRESHOLD_40_BYTES         = 0x04, /*!< transmission starts when the frame size within the transmit FIFO is larger than 40 bytes */
-  EMAC_DMA_TX_THRESHOLD_32_BYTES         = 0x05, /*!< transmission starts when the frame size within the transmit FIFO is larger than 32 bytes */
-  EMAC_DMA_TX_THRESHOLD_24_BYTES         = 0x06, /*!< transmission starts when the frame size within the transmit FIFO is larger than 24 bytes */
-  EMAC_DMA_TX_THRESHOLD_16_BYTES         = 0x07  /*!< transmission starts when the frame size within the transmit FIFO is larger than 16 bytes */
-} emac_dma_transmit_threshold_type;
-
-/**
-  * @brief  dma interrupt type
-  */
-typedef enum
-{
-  EMAC_DMA_INTERRUPT_TX                  = 0x00, /*!< transmit interrupt */
-  EMAC_DMA_INTERRUPT_TX_STOP             = 0x01, /*!< transmit process stopped interrupt */
-  EMAC_DMA_INTERRUPT_TX_UNAVAILABLE      = 0x02, /*!< transmit buffer unavailable interrupt */
-  EMAC_DMA_INTERRUPT_TX_JABBER           = 0x03, /*!< transmit jabber timeout interrupt */
-  EMAC_DMA_INTERRUPT_RX_OVERFLOW         = 0x04, /*!< receive overflow interrupt */
-  EMAC_DMA_INTERRUPT_TX_UNDERFLOW        = 0x05, /*!< transmit underflow interrupt */
-  EMAC_DMA_INTERRUPT_RX                  = 0x06, /*!< receive interrupt */
-  EMAC_DMA_INTERRUPT_RX_UNAVAILABLE      = 0x07, /*!< receive buffer unavailable interrupt */
-  EMAC_DMA_INTERRUPT_RX_STOP             = 0x08, /*!< receive process stopped interrupt */
-  EMAC_DMA_INTERRUPT_RX_TIMEOUT          = 0x09, /*!< receive watchdog timeout interrupt */
-  EMAC_DMA_INTERRUPT_TX_EARLY            = 0x0A, /*!< early transmit interrupt */
-  EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR     = 0x0B, /*!< fatal bus error interrupt */
-  EMAC_DMA_INTERRUPT_RX_EARLY            = 0x0C, /*!< early receive interrupt */
-  EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY    = 0x0D, /*!< abnormal interrupt summary */
-  EMAC_DMA_INTERRUPT_NORMAL_SUMMARY      = 0x0E  /*!< normal interrupt summary */
-} emac_dma_interrupt_type;
-
-/**
-  * @brief  dma tansfer address type
-  */
-typedef enum
-{
-  EMAC_DMA_TX_DESCRIPTOR                 = 0x00, /*!< transmit descriptor address */
-  EMAC_DMA_RX_DESCRIPTOR                 = 0x01, /*!< receive descriptor address */
-  EMAC_DMA_TX_BUFFER                     = 0x02, /*!< transmit buffer address */
-  EMAC_DMA_RX_BUFFER                     = 0x03  /*!< receive buffer address */
-} emac_dma_transfer_address_type;
-
-/**
-  * @brief  clock node type
-  */
-typedef enum
-{
-  EMAC_PTP_NORMAL_CLOCK                  = 0x00, /*!< normal clock node */
-  EMAC_PTP_BOUNDARY_CLOCK                = 0x01, /*!< boundary clock node */
-  EMAC_PTP_END_TO_END_CLOCK              = 0x02, /*!< end to end transparent clock node */
-  EMAC_PTP_PEER_TO_PEER_CLOCK            = 0x03  /*!< peer to peer transparent clock node */
-} emac_ptp_clock_node_type;
-
-/**
-  * @brief  time stamp status type
-  */
-typedef enum
-{
-  EMAC_PTP_SECOND_OVERFLOW               = 0x00, /*!< time stamp second overflow */
-  EMAC_PTP_TARGET_TIME_REACH             = 0x01  /*!< time stamp target time reached */
-} emac_ptp_timestamp_status_type;
-
-/**
-  * @brief  pps control type
-  */
-typedef enum
-{
-  EMAC_PTP_PPS_1HZ                       = 0x00, /*!< pps frequency is 1 hz */
-  EMAC_PTP_PPS_2HZ                       = 0x01, /*!< pps frequency is 2 hz */
-  EMAC_PTP_PPS_4HZ                       = 0x02, /*!< pps frequency is 4 hz */
-  EMAC_PTP_PPS_8HZ                       = 0x03, /*!< pps frequency is 8 hz */
-  EMAC_PTP_PPS_16HZ                      = 0x04, /*!< pps frequency is 16 hz */
-  EMAC_PTP_PPS_32HZ                      = 0x05, /*!< pps frequency is 32 hz */
-  EMAC_PTP_PPS_64HZ                      = 0x06, /*!< pps frequency is 64 hz */
-  EMAC_PTP_PPS_128HZ                     = 0x07, /*!< pps frequency is 128 hz */
-  EMAC_PTP_PPS_256HZ                     = 0x08, /*!< pps frequency is 256 hz */
-  EMAC_PTP_PPS_512HZ                     = 0x09, /*!< pps frequency is 512 hz */
-  EMAC_PTP_PPS_1024HZ                    = 0x0A, /*!< pps frequency is 1024 hz */
-  EMAC_PTP_PPS_2048HZ                    = 0x0B, /*!< pps frequency is 2048 hz */
-  EMAC_PTP_PPS_4096HZ                    = 0x0C, /*!< pps frequency is 4096 hz */
-  EMAC_PTP_PPS_8192HZ                    = 0x0D, /*!< pps frequency is 8192 hz */
-  EMAC_PTP_PPS_16384HZ                   = 0x0E, /*!< pps frequency is 16384 hz */
-  EMAC_PTP_PPS_32768HZ                   = 0x0F  /*!< pps frequency is 32768 hz */
-} emac_ptp_pps_control_type;
-
-/**
-  * @brief  ethernet mac control config type
-  */
-typedef struct
-{
-  emac_auto_negotiation_type             auto_nego;             /*!< auto negotiatin enable */
-  confirm_state                          deferral_check;        /*!< deferral check enable */
-  emac_bol_type                          back_off_limit;        /*!< back-off limit setting */
-  confirm_state                          auto_pad_crc_strip;    /*!< automtic pad/crc stripping enable */
-  confirm_state                          retry_disable;         /*!< retry disable*/
-  confirm_state                          ipv4_checksum_offload; /*!< ipv4 checksum offload enable */
-  emac_duplex_type                       duplex_mode;           /*!< duplex mode enable */
-  confirm_state                          loopback_mode;         /*!< loopback mode enable */
-  confirm_state                          receive_own_disable;   /*!< receive own disbale */
-  emac_speed_type                        fast_ethernet_speed;   /*!< fast ethernet speed enable */
-  confirm_state                          carrier_sense_disable; /*!< carrier sense disable*/
-  emac_intergrame_gap_type               interframe_gap;        /*!< set interframe gap */
-  confirm_state                          jabber_disable;        /*!< jabber disbale */
-  confirm_state                          watchdog_disable;      /*!< watchdog disable */
-} emac_control_config_type;
-
-/**
-  * @brief  ethernet mac dma config type
-  */
-typedef struct
-{
-  confirm_state                          aab_enable;        /*!< address-aligned beats enable */
-  confirm_state                          usp_enable;        /*!< separate PBL enable */
-  emac_dma_pbl_type                      rx_dma_pal;        /*!< rx dma pbl */
-  confirm_state                          fb_enable;         /*!< separate PBL enable */
-  emac_dma_pbl_type                      tx_dma_pal;        /*!< tx dma pbl */
-  uint8_t                                desc_skip_length;  /*!< descriptor skip length */
-  confirm_state                          da_enable;         /*!< dma arbitration enable */
-  emac_dma_rx_tx_ratio_type              priority_ratio;    /*!< priority ratio */
-  confirm_state                          dt_disable;        /*!< disable dropping of tcp/ip checksum error frames */
-  confirm_state                          rsf_enable;        /*!< enable receiving store or forward */
-  confirm_state                          flush_rx_disable;  /*!< disable flushing of received frames */
-  confirm_state                          tsf_enable;        /*!< enable transmitting store or forward */
-  emac_dma_transmit_threshold_type       tx_threshold;      /*!< transmit threshold control */
-  confirm_state                          fef_enable;        /*!< enable forward error frames */
-  confirm_state                          fugf_enable;       /*!< enable forward undersized good frames */
-  emac_dma_receive_threshold_type        rx_threshold;      /*!< receive threshold control */
-  confirm_state                          osf_enable;        /*!< enable operating on second frames */
-} emac_dma_config_type;
-
-/**
-  * @brief  dma desciptors data structure definition
-  */
-typedef struct  {
-  uint32_t   status;                /*!< status */
-  uint32_t   controlsize;           /*!< control and buffer1, buffer2 lengths */
-  uint32_t   buf1addr;              /*!< buffer1 address pointer */
-  uint32_t   buf2nextdescaddr;      /*!< buffer2 or next descriptor address pointer */
-} emac_dma_desc_type;
-
-/**
-  * @brief type define emac mac register all
-  */
-typedef struct
-{
-  /**
-    * @brief emac mac ctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t reserved1            : 2; /* [0:1] */
-      __IO uint32_t re                   : 1; /* [2] */
-      __IO uint32_t te                   : 1; /* [3] */
-      __IO uint32_t dc                   : 1; /* [4] */
-      __IO uint32_t bl                   : 2; /* [5:6] */
-      __IO uint32_t acs                  : 1; /* [7] */
-      __IO uint32_t reserved2            : 1; /* [8] */
-      __IO uint32_t dr                   : 1; /* [9] */
-      __IO uint32_t ipc                  : 1; /* [10] */
-      __IO uint32_t dm                   : 1; /* [11] */
-      __IO uint32_t lm                   : 1; /* [12] */
-      __IO uint32_t dro                  : 1; /* [13] */
-      __IO uint32_t fes                  : 1; /* [14] */
-      __IO uint32_t reserved3            : 1; /* [15] */
-      __IO uint32_t dcs                  : 1; /* [16] */
-      __IO uint32_t ifg                  : 3; /* [17:19] */
-      __IO uint32_t reserved4            : 2; /* [20:21] */
-      __IO uint32_t jd                   : 1; /* [22] */
-      __IO uint32_t wd                   : 1; /* [23] */
-      __IO uint32_t reserved5            : 8; /* [24:31] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief emac mac frmf register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t frmf;
-    struct
-    {
-      __IO uint32_t pr                   : 1; /* [0] */
-      __IO uint32_t huc                  : 1; /* [1] */
-      __IO uint32_t hmc                  : 1; /* [2] */
-      __IO uint32_t daif                 : 1; /* [3] */
-      __IO uint32_t pmc                  : 1; /* [4] */
-      __IO uint32_t dbf                  : 1; /* [5] */
-      __IO uint32_t pcf                  : 2; /* [6:7] */
-      __IO uint32_t saif                 : 1; /* [8] */
-      __IO uint32_t saf                  : 1; /* [9] */
-      __IO uint32_t hpf                  : 1; /* [10] */
-      __IO uint32_t reserved1            : 20;/* [11:30] */
-      __IO uint32_t ra                   : 1; /* [31] */
-    } frmf_bit;
-  };
-
-  /**
-    * @brief emac mac hth register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t hth;
-    struct
-    {
-      __IO uint32_t hth                  : 32; /* [0:31] */
-    } hth_bit;
-  };
-
-  /**
-    * @brief emac mac htl register, offset:0x0c
-    */
-  union
-  {
-    __IO uint32_t htl;
-    struct
-    {
-      __IO uint32_t htl                  : 32; /* [0:31] */
-    } htl_bit;
-  };
-
-  /**
-    * @brief emac mac miiaddr register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t miiaddr;
-    struct
-    {
-      __IO uint32_t mb                   : 1; /* [0] */
-      __IO uint32_t mw                   : 1; /* [1] */
-      __IO uint32_t cr                   : 4; /* [2:5] */
-      __IO uint32_t mii                  : 5; /* [6:10] */
-      __IO uint32_t pa                   : 5; /* [11:15] */
-      __IO uint32_t reserved1            : 16;/* [16:31] */
-    } miiaddr_bit;
-  };
-
-  /**
-    * @brief emac mac miidt register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t miidt;
-    struct
-    {
-      __IO uint32_t md                   : 16;/* [0:15] */
-      __IO uint32_t reserved1            : 16;/* [16:31] */
-    } miidt_bit;
-  };
-
-  /**
-    * @brief emac mac fctrl register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t fctrl;
-    struct
-    {
-      __IO uint32_t fcbbpa               : 1; /* [0] */
-      __IO uint32_t etf                  : 1; /* [1] */
-      __IO uint32_t erf                  : 1; /* [2] */
-      __IO uint32_t dup                  : 1; /* [3] */
-      __IO uint32_t plt                  : 2; /* [4:5] */
-      __IO uint32_t reserved1            : 1; /* [6] */
-      __IO uint32_t dzqp                 : 1; /* [7] */
-      __IO uint32_t reserved2            : 8; /* [8:15] */
-      __IO uint32_t pt                   : 16;/* [16:31] */
-    } fctrl_bit;
-  };
-
-  /**
-    * @brief emac mac vlt register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t vlt;
-    struct
-    {
-      __IO uint32_t vti                  : 16;/* [0:15] */
-      __IO uint32_t etv                  : 1; /* [16] */
-      __IO uint32_t reserved1            : 15;/* [17:31] */
-    } vlt_bit;
-  };
-
-  /**
-    * @brief emac mac reserved1 register, offset:0x20~0x24
-    */
-  __IO uint32_t reserved1[2];
-
-  /**
-    * @brief emac mac rwff register, offset:0x28
-    */
-  __IO uint32_t rwff;
-
-  /**
-    * @brief emac mac pmtctrlsts register, offset:0x2C
-    */
-  union
-  {
-    __IO uint32_t pmtctrlsts;
-    struct
-    {
-      __IO uint32_t pd                   : 1; /* [0] */
-      __IO uint32_t emp                  : 1; /* [1] */
-      __IO uint32_t erwf                 : 1; /* [2] */
-      __IO uint32_t reserved1            : 2; /* [3:4] */
-      __IO uint32_t rmp                  : 1; /* [5] */
-      __IO uint32_t rrwf                 : 1; /* [6] */
-      __IO uint32_t reserved2            : 2; /* [7:8] */
-      __IO uint32_t guc                  : 1; /* [9] */
-      __IO uint32_t reserved3            : 21;/* [10:30] */
-      __IO uint32_t rwffpr               : 1; /* [31] */
-    } pmtctrlsts_bit;
-  };
-
-  /**
-    * @brief emac mac reserved2 register, offset:0x30~0x34
-    */
-  __IO uint32_t reserved2[2];
-
-  /**
-    * @brief emac mac ists register, offset:0x38
-    */
-  union
-  {
-    __IO uint32_t ists;
-    struct
-    {
-      __IO uint32_t reserved1            : 3; /* [0:2] */
-      __IO uint32_t pis                  : 1; /* [3] */
-      __IO uint32_t mis                  : 1; /* [4] */
-      __IO uint32_t mris                 : 1; /* [5] */
-      __IO uint32_t mtis                 : 1; /* [6] */
-      __IO uint32_t reserved2            : 2; /* [7:8] */
-      __IO uint32_t tis                  : 1; /* [9] */
-      __IO uint32_t reserved3            : 22;/* [10:31] */
-    } ists_bit;
-  };
-
-  /**
-    * @brief emac mac imr register, offset:0x3C
-    */
-  union
-  {
-    __IO uint32_t imr;
-    struct
-    {
-      __IO uint32_t reserved1            : 3; /* [0:2] */
-      __IO uint32_t pim                  : 1; /* [3] */
-      __IO uint32_t reserved2            : 5; /* [4:8] */
-      __IO uint32_t tim                  : 1; /* [9] */
-      __IO uint32_t reserved3            : 22;/* [10:31] */
-    } imr_bit;
-  };
-
-  /**
-    * @brief emac mac a0h register, offset:0x40
-    */
-  union
-  {
-    __IO uint32_t a0h;
-    struct
-    {
-      __IO uint32_t ma0h                 : 16;/* [0:15] */
-      __IO uint32_t reserved1            : 15;/* [16:30] */
-      __IO uint32_t ae                   : 1; /* [31] */
-    } a0h_bit;
-  };
-
-   /**
-    * @brief emac mac a0l register, offset:0x44
-    */
-  union
-  {
-    __IO uint32_t a0l;
-    struct
-    {
-      __IO uint32_t ma0l                 : 32;/* [0:31] */
-    } a0l_bit;
-  };
-
-  /**
-    * @brief emac mac a1h register, offset:0x48
-    */
-  union
-  {
-    __IO uint32_t a1h;
-    struct
-    {
-      __IO uint32_t ma1h                 : 16;/* [0:15] */
-      __IO uint32_t reserved1            : 8; /* [16:23] */
-      __IO uint32_t mbc                  : 6; /* [24:29] */
-      __IO uint32_t sa                   : 1; /* [30] */
-      __IO uint32_t ae                  : 1; /* [31] */
-    } a1h_bit;
-  };
-
-  /**
-    * @brief emac mac a1l register, offset:0x4C
-    */
-  union
-  {
-    __IO uint32_t a1l;
-    struct
-    {
-      __IO uint32_t ma1l                 : 32;/* [0:31] */
-    } a1l_bit;
-  };
-
-  /**
-    * @brief emac mac a2h register, offset:0x50
-    */
-  union
-  {
-    __IO uint32_t a2h;
-    struct
-    {
-      __IO uint32_t ma2h                 : 16;/* [0:15] */
-      __IO uint32_t reserved1            : 8; /* [16:23] */
-      __IO uint32_t mbc                  : 6; /* [24:29] */
-      __IO uint32_t sa                   : 1; /* [30] */
-      __IO uint32_t ae                   : 1; /* [31] */
-    } a2h_bit;
-  };
-
-  /**
-    * @brief emac mac a2l register, offset:0x54
-    */
-  union
-  {
-    __IO uint32_t a2l;
-    struct
-    {
-      __IO uint32_t ma2l                 : 32;/* [0:31] */
-    } a2l_bit;
-  };
-
-  /**
-    * @brief emac mac a3h register, offset:0x58
-    */
-  union
-  {
-    __IO uint32_t a3h;
-    struct
-    {
-      __IO uint32_t ma3h                 : 16;/* [0:15] */
-      __IO uint32_t reserved1            : 8; /* [16:23] */
-      __IO uint32_t mbc                  : 6; /* [24:29] */
-      __IO uint32_t sa                   : 1; /* [30] */
-      __IO uint32_t ae                   : 1; /* [31] */
-    } a3h_bit;
-  };
-
-  /**
-    * @brief emac mac a3l register, offset:0x5C
-    */
-  union
-  {
-    __IO uint32_t a3l;
-    struct
-    {
-      __IO uint32_t ma3l                 : 32;/* [0:31] */
-    } a3l_bit;
-  };
-} emac_type;
-
-/**
-  * @brief type define emac mmc register all
-  */
-typedef struct
-{
-  /**
-    * @brief emac mmc ctrl register, offset:0x0100
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t rc                   : 1; /* [0] */
-      __IO uint32_t scr                  : 1; /* [1] */
-      __IO uint32_t rr                   : 1; /* [2] */
-      __IO uint32_t fmc                  : 1; /* [3] */
-      __IO uint32_t reserved1            : 28;/* [4:31] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief emac mmc ri register, offset:0x0104
-    */
-  union
-  {
-    __IO uint32_t ri;
-    struct
-    {
-      __IO uint32_t reserved1            : 5; /* [0:4] */
-      __IO uint32_t rfce                 : 1; /* [5] */
-      __IO uint32_t rfae                 : 1; /* [6] */
-      __IO uint32_t reserved2            : 10;/* [7:16] */
-      __IO uint32_t rguf                 : 1; /* [17] */
-      __IO uint32_t reserved3            : 14;/* [18:31] */
-    } ri_bit;
-  };
-
-  /**
-    * @brief emac mmc ti register, offset:0x0108
-    */
-  union
-  {
-    __IO uint32_t ti;
-    struct
-    {
-      __IO uint32_t reserved1            : 14;/* [0:13] */
-      __IO uint32_t tscgfci              : 1; /* [14] */
-      __IO uint32_t tgfmsc               : 1; /* [15] */
-      __IO uint32_t reserved2            : 5; /* [16:20] */
-      __IO uint32_t tgf                  : 1; /* [21] */
-      __IO uint32_t reserved3            : 10;/* [22:31] */
-    } ti_bit;
-  };
-
-  /**
-    * @brief emac mmc rim register, offset:0x010C
-    */
-  union
-  {
-    __IO uint32_t rim;
-    struct
-    {
-      __IO uint32_t reserved1            : 5; /* [0:4] */
-      __IO uint32_t rcefcim              : 1; /* [5] */
-      __IO uint32_t raefacim             : 1; /* [6] */
-      __IO uint32_t reserved2            : 10;/* [7:16] */
-      __IO uint32_t rugfcim              : 1; /* [17] */
-      __IO uint32_t reserved3            : 14;/* [18:31] */
-    } rim_bit;
-  };
-
-  /**
-    * @brief emac mmc tim register, offset:0x0110
-    */
-  union
-  {
-    __IO uint32_t tim;
-    struct
-    {
-      __IO uint32_t reserved1            : 14;/* [0:13] */
-      __IO uint32_t tscgfcim             : 1; /* [14] */
-      __IO uint32_t tmcgfcim             : 1; /* [15] */
-      __IO uint32_t reserved2            : 5; /* [16:20] */
-      __IO uint32_t tgfcim               : 1; /* [21] */
-      __IO uint32_t reserved3            : 10;/* [22:31] */
-    } tim_bit;
-  };
-
-  /**
-    * @brief emac mmc reserved1 register, offset:0x0114~0x0148
-    */
-  __IO uint32_t reserved1[14];
-
-  /**
-    * @brief emac mmc tfscc register, offset:0x014C
-    */
-  union
-  {
-    __IO uint32_t tfscc;
-    struct
-    {
-      __IO uint32_t tgfscc               : 32;/* [0:31] */
-    } tfscc_bit;
-  };
-
-  /**
-    * @brief emac mmc tfmscc register, offset:0x0150
-    */
-  union
-  {
-    __IO uint32_t tfmscc;
-    struct
-    {
-      __IO uint32_t tgfmscc              : 32;/* [0:31] */
-    } tfmscc_bit;
-  };
-
-  /**
-    * @brief emac mmc reserved2 register, offset:0x0154~0x0164
-    */
-  __IO uint32_t reserved2[5];
-
-  /**
-    * @brief emac mmc tfcnt register, offset:0x0168
-    */
-  union
-  {
-    __IO uint32_t tfcnt;
-    struct
-    {
-      __IO uint32_t tgfc                 : 32;/* [0:31] */
-    } tfcnt_bit;
-  };
-
-  /**
-    * @brief emac mmc reserved3 register, offset:0x016C~0x0190
-    */
-  __IO uint32_t reserved3[10];
-
-  /**
-    * @brief emac mmc rfcecnt register, offset:0x0194
-    */
-  union
-  {
-    __IO uint32_t rfcecnt;
-    struct
-    {
-      __IO uint32_t rfcec                : 32;/* [0:31] */
-    } rfcecnt_bit;
-  };
-
-  /**
-    * @brief emac mmc rfaecnt register, offset:0x0198
-    */
-  union
-  {
-    __IO uint32_t rfaecnt;
-    struct
-    {
-      __IO uint32_t rfaec                : 32;/* [0:31] */
-    } rfaecnt_bit;
-  };
-
-  /**
-    * @brief emac mmc reserved4 register, offset:0x019C~0x01C0
-    */
-  __IO uint32_t reserved4[10];
-
-  /**
-    * @brief emac mmc rgufcnt register, offset:0x01C4
-    */
-  union
-  {
-    __IO uint32_t rgufcnt;
-    struct
-    {
-      __IO uint32_t rgufc                : 32;/* [0:31] */
-    } rgufcnt_bit;
-  };
-} emac_mmc_type;
-
-/**
-  * @brief type define emac ptp register all
-  */
-typedef struct
-{
-  /**
-    * @brief emac ptp tsctrl register, offset:0x0700
-    */
-  union
-  {
-    __IO uint32_t tsctrl;
-    struct
-    {
-      __IO uint32_t te                   : 1; /* [0] */
-      __IO uint32_t tfcu                 : 1; /* [1] */
-      __IO uint32_t ti                   : 1; /* [2] */
-      __IO uint32_t tu                   : 1; /* [3] */
-      __IO uint32_t tite                 : 1; /* [4] */
-      __IO uint32_t aru                  : 1; /* [5] */
-      __IO uint32_t reserved1            : 2; /* [6:7] */
-      __IO uint32_t etaf                 : 1; /* [8] */
-      __IO uint32_t tdbrc                : 1; /* [9] */
-      __IO uint32_t eppv2f               : 1; /* [10] */
-      __IO uint32_t eppef                : 1; /* [11] */
-      __IO uint32_t eppfsip6u            : 1; /* [12] */
-      __IO uint32_t eppfsip4u            : 1; /* [13] */
-      __IO uint32_t etsfem               : 1; /* [14] */
-      __IO uint32_t esfmrtm              : 1; /* [15] */
-      __IO uint32_t sppfts               : 2; /* [16:17] */
-      __IO uint32_t emafpff              : 1; /* [18] */
-      __IO uint32_t reserved2            : 13;/* [19:31] */
-    } tsctrl_bit;
-  };
-
-  /**
-    * @brief emac ptp ssinc register, offset:0x0704
-    */
-  union
-  {
-    __IO uint32_t ssinc;
-    struct
-    {
-      __IO uint32_t ssiv                 : 8; /* [0] */
-      __IO uint32_t reserved1            : 24;/* [8:31] */
-    } ssinc_bit;
-  };
-
-  /**
-    * @brief emac ptp tsh register, offset:0x0708
-    */
-  union
-  {
-    __IO uint32_t tsh;
-    struct
-    {
-      __IO uint32_t ts                   : 32;/* [0:31] */
-    } tsh_bit;
-  };
-
-  /**
-    * @brief emac ptp tsl register, offset:0x070C
-    */
-  union
-  {
-    __IO uint32_t tsl;
-    struct
-    {
-      __IO uint32_t tss                  : 31;/* [0:30] */
-      __IO uint32_t ast                  : 1; /* [31] */
-    } tsl_bit;
-  };
-
-  /**
-    * @brief emac ptp tshud register, offset:0x0710
-    */
-  union
-  {
-    __IO uint32_t tshud;
-    struct
-    {
-      __IO uint32_t ts                   : 32;/* [0:31] */
-    } tshud_bit;
-  };
-
-  /**
-    * @brief emac ptp tslud register, offset:0x0714
-    */
-  union
-  {
-    __IO uint32_t tslud;
-    struct
-    {
-      __IO uint32_t tss                  : 31;/* [0:30] */
-      __IO uint32_t ast                  : 1; /* [31] */
-    } tslud_bit;
-  };
-
-  /**
-    * @brief emac ptp tsad register, offset:0x0718
-    */
-  union
-  {
-    __IO uint32_t tsad;
-    struct
-    {
-      __IO uint32_t tar                  : 32;/* [0:31] */
-    } tsad_bit;
-  };
-
-  /**
-    * @brief emac ptp tth register, offset:0x071C
-    */
-  union
-  {
-    __IO uint32_t tth;
-    struct
-    {
-      __IO uint32_t ttsr                 : 32;/* [0:31] */
-    } tth_bit;
-  };
-
-  /**
-    * @brief emac ptp ttl register, offset:0x0720
-    */
-  union
-  {
-    __IO uint32_t ttl;
-    struct
-    {
-      __IO uint32_t ttlr                 : 32;/* [0:31] */
-    } ttl_bit;
-  };
-
-  /**
-    * @brief emac ptp reserved register, offset:0x0724
-    */
-  __IO uint32_t reserved1;
-
-   /**
-    * @brief emac ptp tssr register, offset:0x0728
-    */
-  union
-  {
-    __IO uint32_t tssr;
-    struct
-    {
-      __IO uint32_t tso                  : 1; /* [0] */
-      __IO uint32_t tttr                 : 1; /* [1] */
-      __IO uint32_t reserved1            : 30;/* [2:31] */
-    } tssr_bit;
-  };
-
-  /**
-    * @brief emac ptp ppscr register, offset:0x072C
-    */
-  union
-  {
-    __IO uint32_t ppscr;
-    struct
-    {
-      __IO uint32_t pofc                 : 4; /* [0:3] */
-      __IO uint32_t reserved1            : 28;/* [4:31] */
-    } ppscr_bit;
-  };
-} emac_ptp_type;
-
-/**
-  * @brief type define emac ptp register all
-  */
-typedef struct
-{
-  /**
-    * @brief emac dma bm register, offset:0x1000
-    */
-  union
-  {
-    __IO uint32_t bm;
-    struct
-    {
-      __IO uint32_t swr                  : 1; /* [0] */
-      __IO uint32_t da                   : 1; /* [1] */
-      __IO uint32_t dsl                  : 5; /* [2:6] */
-      __IO uint32_t reserved1            : 1; /* [7] */
-      __IO uint32_t pbl                  : 6; /* [8:13] */
-      __IO uint32_t pr                   : 2; /* [14:15] */
-      __IO uint32_t fb                   : 1; /* [16] */
-      __IO uint32_t rdp                  : 6; /* [17:22] */
-      __IO uint32_t usp                  : 1; /* [23] */
-      __IO uint32_t pblx8                : 1; /* [24] */
-      __IO uint32_t aab                  : 1; /* [25] */
-      __IO uint32_t reserved2            : 6; /* [26:31] */
-    } bm_bit;
-  };
-
-  /**
-    * @brief emac dma tpd register, offset:0x1004
-    */
-  union
-  {
-    __IO uint32_t tpd;
-    struct
-    {
-      __IO uint32_t tpd                  : 32; /* [0:31] */
-    } tpd_bit;
-  };
-
-  /**
-    * @brief emac dma rpd register, offset:0x1008
-    */
-  union
-  {
-    __IO uint32_t rpd;
-    struct
-    {
-      __IO uint32_t rpd                  : 32; /* [0:31] */
-    } rpd_bit;
-  };
-
-  /**
-    * @brief emac dma rdladdr register, offset:0x100c
-    */
-  union
-  {
-    __IO uint32_t rdladdr;
-    struct
-    {
-      __IO uint32_t srl                  : 32; /* [0:31] */
-    } rdladdr_bit;
-  };
-
-  /**
-    * @brief emac dma tdladdr register, offset:0x1010
-    */
-  union
-  {
-    __IO uint32_t tdladdr;
-    struct
-    {
-      __IO uint32_t stl                  : 32; /* [0:31] */
-    } tdladdr_bit;
-  };
-
-  /**
-    * @brief emac dma sts register, offset:0x1014
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t ti                   : 1; /* [0] */
-      __IO uint32_t tps                  : 1; /* [1] */
-      __IO uint32_t tbu                  : 1; /* [2] */
-      __IO uint32_t tjt                  : 1; /* [3] */
-      __IO uint32_t ovf                  : 1; /* [4] */
-      __IO uint32_t unf                  : 1; /* [5] */
-      __IO uint32_t ri                   : 1; /* [6] */
-      __IO uint32_t rbu                  : 1; /* [7] */
-      __IO uint32_t rps                  : 1; /* [8] */
-      __IO uint32_t rwt                  : 1; /* [9] */
-      __IO uint32_t eti                  : 1; /* [10] */
-      __IO uint32_t reserved1            : 2; /* [11:12] */
-      __IO uint32_t fbei                 : 1; /* [13] */
-      __IO uint32_t eri                  : 1; /* [14] */
-      __IO uint32_t ais                  : 1; /* [15] */
-      __IO uint32_t nis                  : 1; /* [16] */
-      __IO uint32_t rs                   : 3; /* [17:19] */
-      __IO uint32_t ts                   : 3; /* [20:22] */
-      __IO uint32_t eb                   : 3; /* [23:25] */
-      __IO uint32_t reserved2            : 1; /* [26] */
-      __IO uint32_t mmi                  : 1; /* [27] */
-      __IO uint32_t mpi                  : 1; /* [28] */
-      __IO uint32_t tti                  : 1; /* [29] */
-      __IO uint32_t reserved3            : 2; /* [30:31] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief emac dma opm register, offset:0x1018
-    */
-  union
-  {
-    __IO uint32_t opm;
-    struct
-    {
-      __IO uint32_t reserved1            : 1; /* [0] */
-      __IO uint32_t ssr                  : 1; /* [1] */
-      __IO uint32_t osf                  : 1; /* [2] */
-      __IO uint32_t rtc                  : 2; /* [3:4] */
-      __IO uint32_t reserved2            : 1; /* [5] */
-      __IO uint32_t fugf                 : 1; /* [6] */
-      __IO uint32_t fef                  : 1; /* [7] */
-      __IO uint32_t reserved3            : 5; /* [8:12] */
-      __IO uint32_t sstc                 : 1; /* [13] */
-      __IO uint32_t ttc                  : 3; /* [14:16] */
-      __IO uint32_t reserved4            : 3; /* [17:19] */
-      __IO uint32_t ftf                  : 1; /* [20] */
-      __IO uint32_t tsf                  : 1; /* [21] */
-      __IO uint32_t reserved5            : 2; /* [22:23] */
-      __IO uint32_t dfrf                 : 1; /* [24] */
-      __IO uint32_t rsf                  : 1; /* [25] */
-      __IO uint32_t dt                   : 1; /* [26] */
-      __IO uint32_t reserved6            : 5; /* [27:31] */
-    } opm_bit;
-  };
-
-  /**
-    * @brief emac dma ie register, offset:0x101C
-    */
-  union
-  {
-    __IO uint32_t ie;
-    struct
-    {
-      __IO uint32_t tie                  : 1; /* [0] */
-      __IO uint32_t tse                  : 1; /* [1] */
-      __IO uint32_t tue                  : 1; /* [2] */
-      __IO uint32_t tje                  : 1; /* [3] */
-      __IO uint32_t ove                  : 1; /* [4] */
-      __IO uint32_t une                  : 1; /* [5] */
-      __IO uint32_t rie                  : 1; /* [6] */
-      __IO uint32_t rbue                 : 1; /* [7] */
-      __IO uint32_t rse                  : 1; /* [8] */
-      __IO uint32_t rwte                 : 1; /* [9] */
-      __IO uint32_t eie                  : 1; /* [10] */
-      __IO uint32_t reserved1            : 2; /* [11:12] */
-      __IO uint32_t fbee                 : 1; /* [13] */
-      __IO uint32_t ere                  : 1; /* [14] */
-      __IO uint32_t aie                  : 1; /* [15] */
-      __IO uint32_t nie                  : 1; /* [16] */
-      __IO uint32_t reserved2            : 15;/* [17:31] */
-    } ie_bit;
-  };
-
-  /**
-    * @brief emac dma mfbocnt register, offset:0x1020
-    */
-  union
-  {
-    __IO uint32_t mfbocnt;
-    struct
-    {
-      __IO uint32_t mfc                  : 16;/* [0:15] */
-      __IO uint32_t obmfc                : 1; /* [16] */
-      __IO uint32_t ofc                  : 11;/* [17:27] */
-      __IO uint32_t obfoc                : 1; /* [28] */
-      __IO uint32_t reserved1            : 3; /* [29:31] */
-    } mfbocnt_bit;
-  };
-
-  /**
-    * @brief emac dma reserved1 register, offset:0x1024~0x1044
-    */
-  __IO uint32_t reserved1[9];
-
-  /**
-    * @brief emac ctd register, offset:0x1048
-    */
-  union
-  {
-    __IO uint32_t ctd;
-    struct
-    {
-      __IO uint32_t htdap                : 32;/* [0:31] */
-    } ctd_bit;
-  };
-
-  /**
-    * @brief emac crd register, offset:0x104C
-    */
-  union
-  {
-    __IO uint32_t crd;
-    struct
-    {
-      __IO uint32_t hrdap                : 32;/* [0:31] */
-    } crd_bit;
-  };
-
-  /**
-    * @brief emac ctbaddr register, offset:0x1050
-    */
-  union
-  {
-    __IO uint32_t ctbaddr;
-    struct
-    {
-      __IO uint32_t htbap                : 32;/* [0:31] */
-    } ctbaddr_bit;
-  };
-
-  /**
-    * @brief emac crbaddr register, offset:0x1054
-    */
-  union
-  {
-    __IO uint32_t crbaddr;
-    struct
-    {
-      __IO uint32_t hrbap                : 32;/* [0:31] */
-    } crbaddr_bit;
-  };
-} emac_dma_type;
-
-/**
-  * @}
-  */
-
-#define EMAC                             ((emac_type *) EMAC_BASE)
-#define EMAC_MMC                         ((emac_mmc_type *) EMAC_MMC_BASE)
-#define EMAC_PTP                         ((emac_ptp_type *) EMAC_PTP_BASE)
-#define EMAC_DMA                         ((emac_dma_type *) EMAC_DMA_BASE)
-
-/** @defgroup EMAC_exported_functions
-  * @{
-  */
-
-void emac_reset(void);
-void emac_clock_range_set(void);
-void emac_dma_software_reset_set(void);
-flag_status emac_dma_software_reset_get(void);
-void emac_start(void);
-void emac_stop(void);
-error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data);
-error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data);
-void emac_control_para_init(emac_control_config_type *control_para);
-void emac_control_config(emac_control_config_type *control_struct);
-void emac_receiver_enable(confirm_state new_state);
-void emac_trasmitter_enable(confirm_state new_state);
-void emac_deferral_check_set(confirm_state new_state);
-void emac_backoff_limit_set(emac_bol_type slot_time);
-void emac_auto_pad_crc_stripping_set(confirm_state new_state);
-void emac_retry_disable(confirm_state new_state);
-void emac_ipv4_checksum_offload_set(confirm_state new_state);
-void emac_loopback_mode_enable(confirm_state new_state);
-void emac_receive_own_disable(confirm_state new_state);
-void emac_carrier_sense_disable(confirm_state new_state);
-void emac_interframe_gap_set(emac_intergrame_gap_type number);
-void emac_jabber_disable(confirm_state new_state);
-void emac_watchdog_disable(confirm_state new_state);
-void emac_fast_speed_set(emac_speed_type speed);
-void emac_duplex_mode_set(emac_duplex_type duplex_mode);
-void emac_promiscuous_mode_set(confirm_state new_state);
-void emac_hash_unicast_set(confirm_state new_state);
-void emac_hash_multicast_set(confirm_state new_state);
-void emac_dstaddr_inverse_filter_set(confirm_state new_state);
-void emac_pass_all_multicasting_set(confirm_state new_state);
-void emac_broadcast_frames_disable(confirm_state new_state);
-void emac_pass_control_frames_set(emac_control_frames_filter_type condition);
-void emac_srcaddr_inverse_filter_set(confirm_state new_state);
-void emac_srcaddr_filter_set(confirm_state new_state);
-void emac_hash_perfect_filter_set(confirm_state new_state);
-void emac_receive_all_set(confirm_state new_state);
-void emac_hash_table_high32bits_set(uint32_t high32bits);
-void emac_hash_table_low32bits_set(uint32_t low32bits);
-flag_status emac_mii_busy_get(void);
-void emac_mii_write(confirm_state new_state);
-void emac_fcb_bpa_set(confirm_state new_state);
-void emac_transmit_flow_control_enable(confirm_state new_state);
-void emac_receive_flow_control_enable(confirm_state new_state);
-void emac_unicast_pause_frame_detect(confirm_state new_state);
-void emac_pause_low_threshold_set(emac_pause_slot_threshold_type pasue_threshold);
-void emac_zero_quanta_pause_disable(confirm_state new_state);
-void emac_pause_time_set(uint16_t pause_time);
-void emac_vlan_tag_identifier_set(uint16_t identifier);
-void emac_vlan_tag_comparison_set(confirm_state new_state);
-void emac_wakeup_frame_set(uint32_t value);
-uint32_t emac_wakeup_frame_get(void);
-void emac_power_down_set(confirm_state new_state);
-void emac_magic_packet_enable(confirm_state new_state);
-void emac_wakeup_frame_enable(confirm_state new_state);
-flag_status emac_received_magic_packet_get(void);
-flag_status emac_received_wakeup_frame_get(void);
-void emac_global_unicast_set(confirm_state new_state);
-void emac_wakeup_frame_filter_reset(confirm_state new_state);
-flag_status emac_interrupt_status_read(uint32_t flag);
-void emac_interrupt_mask_set(emac_interrupt_mask_type mask_type, confirm_state new_state);
-void emac_local_address_set(uint8_t *address);
-void emac_address_filter_set(emac_address_type mac, emac_address_filter_type filter, emac_address_mask_type mask_bit, confirm_state new_state);
-uint32_t emac_received_packet_size_get(void);
-uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
-void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
-uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
-void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
-void emac_dma_para_init(emac_dma_config_type *control_para);
-void emac_dma_config(emac_dma_config_type *control_para);
-void emac_dma_arbitation_set(emac_dma_rx_tx_ratio_type ratio, confirm_state new_state);
-void emac_dma_descriptor_skip_length_set(uint8_t length);
-void emac_dma_separate_pbl_set(emac_dma_pbl_type tx_length, emac_dma_pbl_type rx_length, confirm_state new_state);
-void emac_dma_eight_pbl_mode_set(confirm_state new_state);
-void emac_dma_address_aligned_beats_set(confirm_state new_state);
-void emac_dma_poll_demand_set(emac_dma_tx_rx_type transfer_type, uint32_t value);
-uint32_t emac_dma_poll_demand_get(emac_dma_tx_rx_type transfer_type);
-flag_status emac_dma_status_get(uint32_t flag);
-emac_dma_receive_process_status_type emac_dma_receive_status_get(void);
-emac_dma_transmit_process_status_type emac_dma_transmit_status_get(void);
-void emac_dma_operations_set(emac_dma_operations_type ops, confirm_state new_state);
-void emac_dma_receive_threshold_set(emac_dma_receive_threshold_type value);
-void emac_dma_transmit_threshold_set(emac_dma_transmit_threshold_type value);
-void emac_dma_interrupt_enable(emac_dma_interrupt_type it, confirm_state new_state);
-uint16_t emac_dma_controller_missing_frame_get(void);
-uint8_t emac_dma_missing_overflow_bit_get(void);
-uint16_t emac_dma_application_missing_frame_get(void);
-uint8_t emac_dma_fifo_overflow_bit_get(void);
-uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
-void emac_mmc_counter_reset(void);
-void emac_mmc_rollover_stop(confirm_state new_state);
-void emac_mmc_reset_on_read_enable(confirm_state new_state);
-void emac_mmc_counter_freeze(confirm_state new_state);
-flag_status emac_mmc_received_status_get(uint32_t flag);
-flag_status emac_mmc_transmit_status_get(uint32_t flag);
-void emac_mmc_received_interrupt_mask_set(uint32_t flag, confirm_state new_state);
-void emac_mmc_transmit_interrupt_mask_set(uint32_t flag, confirm_state new_state);
-uint32_t emac_mmc_transmit_good_frames_get(uint32_t flag);
-uint32_t emac_mmc_received_error_frames_get(uint32_t flag);
-void emac_ptp_timestamp_enable(confirm_state new_state);
-void emac_ptp_timestamp_fine_update_enable(confirm_state new_state);
-void emac_ptp_timestamp_system_time_init(confirm_state new_state);
-void emac_ptp_timestamp_system_time_update(confirm_state new_state);
-void emac_ptp_interrupt_trigger_enable(confirm_state new_state);
-void emac_ptp_addend_register_update(confirm_state new_state);
-void emac_ptp_snapshot_received_frames_enable(confirm_state new_state);
-void emac_ptp_subsecond_rollover_enable(confirm_state new_state);
-void emac_ptp_psv2_enable(confirm_state new_state);
-void emac_ptp_snapshot_emac_frames_enable(confirm_state new_state);
-void emac_ptp_snapshot_ipv6_frames_enable(confirm_state new_state);
-void emac_ptp_snapshot_ipv4_frames_enable(confirm_state new_state);
-void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
-void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
-void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
-void emac_ptp_mac_address_filter_enable(confirm_state new_state);
-void emac_ptp_subsecond_increment_set(uint8_t value);
-uint32_t emac_ptp_system_second_get(void);
-uint32_t emac_ptp_system_subsecond_get(void);
-confirm_state emac_ptp_system_time_sign_get(void);
-void emac_ptp_system_second_set(uint32_t second);
-void emac_ptp_system_subsecond_set(uint32_t subsecond);
-void emac_ptp_system_time_sign_set(confirm_state sign);
-void emac_ptp_timestamp_addend_set(uint32_t value);
-void emac_ptp_target_second_set(uint32_t value);
-void emac_ptp_target_nanosecond_set(uint32_t value);
-confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status);
-void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq);
-flag_status emac_dma_flag_get(uint32_t dma_flag);
-void emac_dma_flag_clear(uint32_t dma_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_exint.h

@@ -1,231 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_exint.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 exint header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_EXINT_H
-#define __AT32F403A_407_EXINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup EXINT
-  * @{
-  */
-
-/** @defgroup EXINT_lines
-  * @{
-  */
-
-#define EXINT_LINE_NONE                  ((uint32_t)0x000000)
-#define EXINT_LINE_0                     ((uint32_t)0x000001) /*!< external interrupt line 0 */
-#define EXINT_LINE_1                     ((uint32_t)0x000002) /*!< external interrupt line 1 */
-#define EXINT_LINE_2                     ((uint32_t)0x000004) /*!< external interrupt line 2 */
-#define EXINT_LINE_3                     ((uint32_t)0x000008) /*!< external interrupt line 3 */
-#define EXINT_LINE_4                     ((uint32_t)0x000010) /*!< external interrupt line 4 */
-#define EXINT_LINE_5                     ((uint32_t)0x000020) /*!< external interrupt line 5 */
-#define EXINT_LINE_6                     ((uint32_t)0x000040) /*!< external interrupt line 6 */
-#define EXINT_LINE_7                     ((uint32_t)0x000080) /*!< external interrupt line 7 */
-#define EXINT_LINE_8                     ((uint32_t)0x000100) /*!< external interrupt line 8 */
-#define EXINT_LINE_9                     ((uint32_t)0x000200) /*!< external interrupt line 9 */
-#define EXINT_LINE_10                    ((uint32_t)0x000400) /*!< external interrupt line 10 */
-#define EXINT_LINE_11                    ((uint32_t)0x000800) /*!< external interrupt line 11 */
-#define EXINT_LINE_12                    ((uint32_t)0x001000) /*!< external interrupt line 12 */
-#define EXINT_LINE_13                    ((uint32_t)0x002000) /*!< external interrupt line 13 */
-#define EXINT_LINE_14                    ((uint32_t)0x004000) /*!< external interrupt line 14 */
-#define EXINT_LINE_15                    ((uint32_t)0x008000) /*!< external interrupt line 15 */
-#define EXINT_LINE_16                    ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
-#define EXINT_LINE_17                    ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
-#define EXINT_LINE_18                    ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb device fs wakeup from suspend event */
-#define EXINT_LINE_19                    ((uint32_t)0x080000) /*!< external interrupt line 19 connected to the comp1*/
-
-/**
-  * @}
-  */
-
-/** @defgroup EXINT_exported_types
-  * @{
-  */
-
-/**
-  * @brief exint line mode type
-  */
-typedef enum
-{
-  EXINT_LINE_INTERRUPUT                  = 0x00, /*!< external interrupt line interrupt mode */
-  EXINT_LINE_EVENT                       = 0x01  /*!< external interrupt line event mode */
-} exint_line_mode_type;
-
-/**
-  * @brief exint polarity configuration type
-  */
-typedef enum
-{
-  EXINT_TRIGGER_RISING_EDGE              = 0x00, /*!< external interrupt line rising trigger mode */
-  EXINT_TRIGGER_FALLING_EDGE             = 0x01, /*!< external interrupt line falling trigger mode */
-  EXINT_TRIGGER_BOTH_EDGE                = 0x02  /*!< external interrupt line both rising and falling trigger mode */
-} exint_polarity_config_type;
-
-/**
-  * @brief exint init type
-  */
-typedef struct
-{
-  exint_line_mode_type                   line_mode;     /*!< choose mode event or interrupt mode */
-  uint32_t                               line_select;   /*!< select the exint line, availiable for single line or multiple lines */
-  exint_polarity_config_type             line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
-  confirm_state                          line_enable;   /*!< enable or disable exint */
-} exint_init_type;
-
-/**
-  * @brief type define exint register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief exint inten register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t inten;
-    struct
-    {
-      __IO uint32_t intenx               : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } inten_bit;
-  };
-
-  /**
-    * @brief exint evten register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t evten;
-    struct
-    {
-      __IO uint32_t evtenx               : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } evten_bit;
-  };
-
-  /**
-    * @brief exint polcfg1 register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t polcfg1;
-    struct
-    {
-      __IO uint32_t rpx                  : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } polcfg1_bit;
-  };
-
-  /**
-    * @brief exint polcfg2 register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t polcfg2;
-    struct
-    {
-      __IO uint32_t fpx                  : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } polcfg2_bit;
-  };
-
-  /**
-    * @brief exint swtrg register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t swtrg;
-    struct
-    {
-      __IO uint32_t swtx                 : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } swtrg_bit;
-  };
-
-  /**
-    * @brief exint intsts register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t intsts;
-    struct
-    {
-      __IO uint32_t linex                : 20;/* [19:0] */
-      __IO uint32_t reserved1            : 12;/* [31:20] */
-    } intsts_bit;
-  };
-} exint_type;
-
-/**
-  * @}
-  */
-
-#define EXINT                             ((exint_type *) EXINT_BASE)
-
-/** @defgroup EXINT_exported_functions
-  * @{
-  */
-
-void exint_reset(void);
-void exint_default_para_init(exint_init_type *exint_struct);
-void exint_init(exint_init_type *exint_struct);
-void exint_flag_clear(uint32_t exint_line);
-flag_status exint_flag_get(uint32_t exint_line);
-void exint_software_interrupt_event_generate(uint32_t exint_line);
-void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
-void exint_event_enable(uint32_t exint_line, confirm_state new_state);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_flash.h

@@ -1,728 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_flash.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 flash header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_FLASH_H
-#define __AT32F403A_407_FLASH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/** @defgroup FLASH_unlock_keys
-  * @brief flash unlock keys
-  * @{
-  */
-
-#define FLASH_UNLOCK_KEY1                ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
-#define FLASH_UNLOCK_KEY2                ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
-#define FAP_RELIEVE_KEY                  ((uint16_t)0x00A5)     /*!< flash fap relieve key val */
-#define SLIB_UNLOCK_KEY                  ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_bank_address
-  * @brief flash bank address
-  * @{
-  */
-
-#define FLASH_BANK1_START_ADDR           ((uint32_t)0x08000000) /*!< flash start address of bank1 */
-#define FLASH_BANK1_END_ADDR             ((uint32_t)0x0807FFFF) /*!< flash end address of bank1 */
-#define FLASH_BANK2_START_ADDR           ((uint32_t)0x08080000) /*!< flash start address of bank2 */
-#define FLASH_BANK2_END_ADDR             ((uint32_t)0x080FFFFF) /*!< flash end address of bank2 */
-#define FLASH_SPIM_START_ADDR            ((uint32_t)0x08400000) /*!< flash start address of spim */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_flags
-  * @brief flash flag
-  * @{
-  */
-
-#define FLASH_OBF_FLAG                   FLASH_BANK1_OBF_FLAG     /*!< flash operate busy flag */
-#define FLASH_ODF_FLAG                   FLASH_BANK1_ODF_FLAG     /*!< flash operate done flag */
-#define FLASH_PRGMERR_FLAG               FLASH_BANK1_PRGMERR_FLAG /*!< flash program error flag */
-#define FLASH_EPPERR_FLAG                FLASH_BANK1_EPPERR_FLAG  /*!< flash erase/program protection error flag */
-#define FLASH_BANK1_OBF_FLAG             ((uint32_t)0x00000001)   /*!< flash bank1 operate busy flag */
-#define FLASH_BANK1_ODF_FLAG             ((uint32_t)0x00000020)   /*!< flash bank1 operate done flag */
-#define FLASH_BANK1_PRGMERR_FLAG         ((uint32_t)0x00000004)   /*!< flash bank1 program error flag */
-#define FLASH_BANK1_EPPERR_FLAG          ((uint32_t)0x00000010)   /*!< flash bank1 erase/program protection error flag */
-#define FLASH_BANK2_OBF_FLAG             ((uint32_t)0x10000001)   /*!< flash bank2 operate busy flag */
-#define FLASH_BANK2_ODF_FLAG             ((uint32_t)0x10000020)   /*!< flash bank2 operate done flag */
-#define FLASH_BANK2_PRGMERR_FLAG         ((uint32_t)0x10000004)   /*!< flash bank2 program error flag */
-#define FLASH_BANK2_EPPERR_FLAG          ((uint32_t)0x10000010)   /*!< flash bank2 erase/program protection error flag */
-#define FLASH_SPIM_OBF_FLAG              ((uint32_t)0x20000001)   /*!< flash spim operate busy flag */
-#define FLASH_SPIM_ODF_FLAG              ((uint32_t)0x20000020)   /*!< flash spim operate done flag */
-#define FLASH_SPIM_PRGMERR_FLAG          ((uint32_t)0x20000004)   /*!< flash spim program error flag */
-#define FLASH_SPIM_EPPERR_FLAG           ((uint32_t)0x20000010)   /*!< flash spim erase/program protection error flag */
-#define FLASH_USDERR_FLAG                ((uint32_t)0x40000001)   /*!< flash user system data error flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_interrupts
-  * @brief flash interrupts
-  * @{
-  */
-
-#define FLASH_ERR_INT                    FLASH_BANK1_ERR_INT    /*!< flash error interrupt */
-#define FLASH_ODF_INT                    FLASH_BANK1_ODF_INT    /*!< flash operate done interrupt */
-#define FLASH_BANK1_ERR_INT              ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
-#define FLASH_BANK1_ODF_INT              ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
-#define FLASH_BANK2_ERR_INT              ((uint32_t)0x00000004) /*!< flash bank2 error interrupt */
-#define FLASH_BANK2_ODF_INT              ((uint32_t)0x00000008) /*!< flash bank2 operate done interrupt */
-#define FLASH_SPIM_ERR_INT               ((uint32_t)0x00000010) /*!< flash spim error interrupt */
-#define FLASH_SPIM_ODF_INT               ((uint32_t)0x00000020) /*!< flash spim operate done interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_slib_mask
-  * @brief flash slib mask
-  * @{
-  */
-
-#define FLASH_SLIB_START_SECTOR          ((uint32_t)0x000007FF) /*!< flash slib start sector */
-#define FLASH_SLIB_DATA_START_SECTOR     ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
-#define FLASH_SLIB_END_SECTOR            ((uint32_t)0xFFC00000) /*!< flash slib end sector */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_user_system_data
-  * @brief flash user system data
-  * @{
-  */
-
-#define USD_WDT_ATO_DISABLE              ((uint16_t)0x0001) /*!< wdt auto start disabled  */
-#define USD_WDT_ATO_ENABLE               ((uint16_t)0x0000) /*!< wdt auto start enabled */
-
-#define USD_DEPSLP_NO_RST                ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
-#define USD_DEPSLP_RST                   ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
-
-#define USD_STDBY_NO_RST                 ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
-#define USD_STDBY_RST                    ((uint16_t)0x0000) /*!< reset generated when entering in standby */
-
-#define FLASH_BOOT_FROM_BANK1            ((uint16_t)0x0008) /*!< boot from bank1 */
-#define FLASH_BOOT_FROM_BANK2            ((uint16_t)0x0000) /*!< boot from bank 2 or bank 1,depending on the activation of the bank */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_timeout_definition
-  * @brief flash timeout definition
-  * @{
-  */
-
-#define ERASE_TIMEOUT                    ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
-#define PROGRAMMING_TIMEOUT              ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
-#define SPIM_ERASE_TIMEOUT               ((uint32_t)0xFFFFFFFF) /*!< spim erase operation timeout */
-#define SPIM_PROGRAMMING_TIMEOUT         ((uint32_t)0x00100000) /*!< spim program operation timeout */
-#define OPERATION_TIMEOUT                ((uint32_t)0x10000000) /*!< flash common operation timeout */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_exported_types
-  * @{
-  */
-
-/**
-  * @brief  flash status type
-  */
-typedef enum
-{
-  FLASH_OPERATE_BUSY                     = 0x00, /*!< flash status is operate busy */
-  FLASH_PROGRAM_ERROR                    = 0x01, /*!< flash status is program error */
-  FLASH_EPP_ERROR                        = 0x02, /*!< flash status is epp error */
-  FLASH_OPERATE_DONE                     = 0x03, /*!< flash status is operate done */
-  FLASH_OPERATE_TIMEOUT                  = 0x04  /*!< flash status is operate timeout */
-} flash_status_type;
-
-/**
-  * @brief  flash spim model type
-  */
-typedef enum
-{
-  FLASH_SPIM_MODEL1                      = 0x01, /*!< spim model 1 */
-  FLASH_SPIM_MODEL2                      = 0x02, /*!< spim model 2 */
-} flash_spim_model_type;
-
-/**
-  * @brief type define flash register all
-  */
-typedef struct
-{
-  /**
-    * @brief flash psr register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t psr;
-    struct
-    {
-      __IO uint32_t reserved1            : 32; /* [31:0] */
-    } psr_bit;
-  };
-
-  /**
-    * @brief flash unlock register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t unlock;
-    struct
-    {
-      __IO uint32_t ukval                : 32;/* [31:0] */
-    } unlock_bit;
-  };
-
-  /**
-    * @brief flash usd unlock register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t usd_unlock;
-    struct
-    {
-      __IO uint32_t usd_ukval            : 32;/* [31:0] */
-    } usd_unlock_bit;
-  };
-
-  /**
-    * @brief flash sts register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t obf                  : 1; /* [0] */
-      __IO uint32_t reserved1            : 1; /* [1] */
-      __IO uint32_t prgmerr              : 1; /* [2] */
-      __IO uint32_t reserved2            : 1; /* [3] */
-      __IO uint32_t epperr               : 1; /* [4] */
-      __IO uint32_t odf                  : 1; /* [5] */
-      __IO uint32_t reserved3            : 26;/* [31:6] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief flash ctrl register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t fprgm                : 1; /* [0] */
-      __IO uint32_t secers               : 1; /* [1] */
-      __IO uint32_t bankers              : 1; /* [2] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t usdprgm              : 1; /* [4] */
-      __IO uint32_t usders               : 1; /* [5] */
-      __IO uint32_t erstr                : 1; /* [6] */
-      __IO uint32_t oplk                 : 1; /* [7] */
-      __IO uint32_t reserved2            : 1; /* [8] */
-      __IO uint32_t usdulks              : 1; /* [9] */
-      __IO uint32_t errie                : 1; /* [10] */
-      __IO uint32_t reserved3            : 1; /* [11] */
-      __IO uint32_t odfie                : 1; /* [12] */
-      __IO uint32_t reserved4            : 19;/* [31:13] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief flash addr register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t addr;
-    struct
-    {
-      __IO uint32_t fa                   : 32;/* [31:0] */
-    } addr_bit;
-  };
-
-  /**
-    * @brief flash reserved1 register, offset:0x18
-    */
-  __IO uint32_t reserved1;
-
-  /**
-    * @brief flash usd register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t usd;
-    struct
-    {
-      __IO uint32_t usderr               : 1; /* [0] */
-      __IO uint32_t fap                  : 1; /* [1] */
-      __IO uint32_t wdt_ato_en           : 1; /* [2] */
-      __IO uint32_t depslp_rst           : 1; /* [3] */
-      __IO uint32_t stdby_rst            : 1; /* [4] */
-      __IO uint32_t btopt                : 1; /* [5] */
-      __IO uint32_t reserved1            : 4; /* [9:6] */
-      __IO uint32_t user_d0              : 8; /* [17:10] */
-      __IO uint32_t user_d1              : 8; /* [25:18] */
-      __IO uint32_t reserved2            : 6; /* [31:26] */
-    } usd_bit;
-  };
-
-  /**
-    * @brief flash epps register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t epps;
-    struct
-    {
-      __IO uint32_t epps                 : 32;/* [31:0] */
-    } epps_bit;
-  };
-
-  /**
-    * @brief flash reserved2 register, offset:0x40~0x24
-    */
-  __IO uint32_t reserved2[8];
-
-  /**
-    * @brief flash unlock2 register, offset:0x44
-    */
-  union
-  {
-    __IO uint32_t unlock2;
-    struct
-    {
-      __IO uint32_t ukval                : 32;/* [31:0] */
-    } unlock2_bit;
-  };
-
-  /**
-    * @brief flash reserved3 register, offset:0x48
-    */
-  __IO uint32_t reserved3;
-
-  /**
-    * @brief flash sts2 register, offset:0x4C
-    */
-  union
-  {
-    __IO uint32_t sts2;
-    struct
-    {
-      __IO uint32_t obf                  : 1; /* [0] */
-      __IO uint32_t reserved1            : 1; /* [1] */
-      __IO uint32_t prgmerr              : 1; /* [2] */
-      __IO uint32_t reserved2            : 1; /* [3] */
-      __IO uint32_t epperr               : 1; /* [4] */
-      __IO uint32_t odf                  : 1; /* [5] */
-      __IO uint32_t reserved3            : 26;/* [31:6] */
-    } sts2_bit;
-  };
-
-  /**
-    * @brief flash ctrl2 register, offset:0x50
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t fprgm                : 1; /* [0] */
-      __IO uint32_t secers               : 1; /* [1] */
-      __IO uint32_t bankers              : 1; /* [2] */
-      __IO uint32_t reserved1            : 3; /* [5:3] */
-      __IO uint32_t erstr                : 1; /* [6] */
-      __IO uint32_t oplk                 : 1; /* [7] */
-      __IO uint32_t reserved2            : 2; /* [9:8] */
-      __IO uint32_t errie                : 1; /* [10] */
-      __IO uint32_t reserved3            : 1; /* [11] */
-      __IO uint32_t odfie                : 1; /* [12] */
-      __IO uint32_t reserved4            : 19;/* [31:13] */
-    } ctrl2_bit;
-  };
-
-  /**
-    * @brief flash addr2 register, offset:0x54
-    */
-  union
-  {
-    __IO uint32_t addr2;
-    struct
-    {
-      __IO uint32_t fa                   : 32;/* [31:0] */
-    } addr2_bit;
-  };
-
-  /**
-    * @brief flash reserved4 register, offset:0x80~0x58
-    */
-  __IO uint32_t reserved4[11];
-
-  /**
-    * @brief flash unlock3 register, offset:0x84
-    */
-  union
-  {
-    __IO uint32_t unlock3;
-    struct
-    {
-      __IO uint32_t ukval                : 32;/* [31:0] */
-    } unlock3_bit;
-  };
-
-  /**
-    * @brief flash select register, offset:0x88
-    */
-  union
-  {
-    __IO uint32_t select;
-    struct
-    {
-      __IO uint32_t select               : 32;/* [31:0] */
-    } select_bit;
-  };
-
-  /**
-    * @brief flash sts3 register, offset:0x8C
-    */
-  union
-  {
-    __IO uint32_t sts3;
-    struct
-    {
-      __IO uint32_t obf                  : 1; /* [0] */
-      __IO uint32_t reserved1            : 1; /* [1] */
-      __IO uint32_t prgmerr              : 1; /* [2] */
-      __IO uint32_t reserved2            : 1; /* [3] */
-      __IO uint32_t epperr               : 1; /* [4] */
-      __IO uint32_t odf                  : 1; /* [5] */
-      __IO uint32_t reserved3            : 26;/* [31:6] */
-    } sts3_bit;
-  };
-
-  /**
-    * @brief flash ctrl3 register, offset:0x90
-    */
-  union
-  {
-    __IO uint32_t ctrl3;
-    struct
-    {
-      __IO uint32_t fprgm                : 1; /* [0] */
-      __IO uint32_t secers               : 1; /* [1] */
-      __IO uint32_t chpers               : 1; /* [2] */
-      __IO uint32_t reserved1            : 3; /* [5:3] */
-      __IO uint32_t erstr                : 1; /* [6] */
-      __IO uint32_t oplk                 : 1; /* [7] */
-      __IO uint32_t reserved2            : 2; /* [9:8] */
-      __IO uint32_t errie                : 1; /* [10] */
-      __IO uint32_t reserved3            : 1; /* [11] */
-      __IO uint32_t odfie                : 1; /* [12] */
-      __IO uint32_t reserved4            : 19;/* [31:13] */
-    } ctrl3_bit;
-  };
-
-  /**
-    * @brief flash addr3 register, offset:0x94
-    */
-  union
-  {
-    __IO uint32_t addr3;
-    struct
-    {
-      __IO uint32_t fa                   : 32;/* [31:0] */
-    } addr3_bit;
-  };
-
-  /**
-    * @brief flash da register, offset:0x98
-    */
-  union
-  {
-    __IO uint32_t da;
-    struct
-    {
-      __IO uint32_t fda                  : 32;/* [31:0] */
-    } da_bit;
-  };
-
-  /**
-    * @brief flash reserved5 register, offset:0xC8~0x9C
-    */
-  __IO uint32_t reserved5[12];
-
-  /**
-    * @brief flash slib_sts0 register, offset:0xCC
-    */
-  union
-  {
-    __IO uint32_t slib_sts0;
-    struct
-    {
-      __IO uint32_t reserved1            : 3; /* [2:0] */
-      __IO uint32_t slib_enf             : 1; /* [3] */
-      __IO uint32_t reserved2            : 28;/* [31:4] */
-    } slib_sts0_bit;
-  };
-
-  /**
-    * @brief flash slib_sts1 register, offset:0xD0
-    */
-  union
-  {
-    __IO uint32_t slib_sts1;
-    struct
-    {
-      __IO uint32_t slib_ss              : 11;/* [10:0] */
-      __IO uint32_t slib_dat_ss          : 11;/* [21:11] */
-      __IO uint32_t slib_es              : 10;/* [31:22] */
-    } slib_sts1_bit;
-  };
-
-  /**
-    * @brief flash slib_pwd_clr register, offset:0xD4
-    */
-  union
-  {
-    __IO uint32_t slib_pwd_clr;
-    struct
-    {
-      __IO uint32_t slib_pclr_val        : 32;/* [31:0] */
-    } slib_pwd_clr_bit;
-  };
-
-  /**
-    * @brief flash slib_misc_sts register, offset:0xD8
-    */
-  union
-  {
-    __IO uint32_t slib_misc_sts;
-    struct
-    {
-      __IO uint32_t slib_pwd_err         : 1; /* [0] */
-      __IO uint32_t slib_pwd_ok          : 1; /* [1] */
-      __IO uint32_t slib_ulkf            : 1; /* [2] */
-      __IO uint32_t reserved1            : 13;/* [15:3] */
-      __IO uint32_t slib_rcnt            : 9; /* [24:16] */
-      __IO uint32_t reserved2            : 7; /* [31:25] */
-    } slib_misc_sts_bit;
-  };
-
-  /**
-    * @brief flash slib_set_pwd register, offset:0xDC
-    */
-  union
-  {
-    __IO uint32_t slib_set_pwd;
-    struct
-    {
-      __IO uint32_t slib_pset_val        : 32;/* [31:0] */
-    } slib_set_pwd_bit;
-  };
-
-  /**
-    * @brief flash slib_set_range register, offset:0xE0
-    */
-  union
-  {
-    __IO uint32_t slib_set_range;
-    struct
-    {
-      __IO uint32_t slib_ss_set          : 11;/* [10:0] */
-      __IO uint32_t slib_dss_set         : 11;/* [21:11] */
-      __IO uint32_t slib_es_set          : 10;/* [31:22] */
-    } slib_set_range_bit;
-  };
-
-  /**
-    * @brief flash reserved6 register, offset:0xEC~0xE4
-    */
-  __IO uint32_t reserved6[3];
-
-  /**
-    * @brief flash slib_unlock register, offset:0xF0
-    */
-  union
-  {
-    __IO uint32_t slib_unlock;
-    struct
-    {
-      __IO uint32_t slib_ukval           : 32;/* [31:0] */
-    } slib_unlock_bit;
-  };
-
-  /**
-    * @brief flash crc_ctrl register, offset:0xF4
-    */
-  union
-  {
-    __IO uint32_t crc_ctrl;
-    struct
-    {
-      __IO uint32_t crc_ss               : 12;/* [11:0] */
-      __IO uint32_t crc_sn               : 12;/* [23:12] */
-      __IO uint32_t reserved1            : 7; /* [30:24] */
-      __IO uint32_t crc_strt             : 1; /* [31] */
-    } crc_ctrl_bit;
-  };
-
-  /**
-    * @brief flash crc_chkr register, offset:0xF8
-    */
-  union
-  {
-    __IO uint32_t crc_chkr;
-    struct
-    {
-      __IO uint32_t crc_chkr             : 32;/* [31:0] */
-    } crc_chkr_bit;
-  };
-
-} flash_type;
-
-/**
-  * @brief user system data
-  */
-typedef struct
-{
-  __IO uint16_t fap;
-  __IO uint16_t ssb;
-  __IO uint16_t data0;
-  __IO uint16_t data1;
-  __IO uint16_t epp0;
-  __IO uint16_t epp1;
-  __IO uint16_t epp2;
-  __IO uint16_t epp3;
-  __IO uint16_t eopb0;
-  __IO uint16_t reserved;
-  __IO uint16_t data2;
-  __IO uint16_t data3;
-  __IO uint16_t data4;
-  __IO uint16_t data5;
-  __IO uint16_t data6;
-  __IO uint16_t data7;
-  __IO uint16_t ext_flash_key[8];
-} usd_type;
-
-/**
-  * @}
-  */
-
-#define FLASH                            ((flash_type *) FLASH_REG_BASE)
-#define USD                              ((usd_type *) USD_BASE)
-
-/** @defgroup FLASH_exported_functions
-  * @{
-  */
-
-flag_status flash_flag_get(uint32_t flash_flag);
-void flash_flag_clear(uint32_t flash_flag);
-flash_status_type flash_operation_status_get(void);
-flash_status_type flash_bank1_operation_status_get(void);
-flash_status_type flash_bank2_operation_status_get(void);
-flash_status_type flash_spim_operation_status_get(void);
-flash_status_type flash_operation_wait_for(uint32_t time_out);
-flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
-flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
-flash_status_type flash_spim_operation_wait_for(uint32_t time_out);
-void flash_unlock(void);
-void flash_bank1_unlock(void);
-void flash_bank2_unlock(void);
-void flash_spim_unlock(void);
-void flash_lock(void);
-void flash_bank1_lock(void);
-void flash_bank2_lock(void);
-void flash_spim_lock(void);
-flash_status_type flash_sector_erase(uint32_t sector_address);
-flash_status_type flash_internal_all_erase(void);
-flash_status_type flash_bank1_erase(void);
-flash_status_type flash_bank2_erase(void);
-flash_status_type flash_spim_all_erase(void);
-flash_status_type flash_user_system_data_erase(void);
-flash_status_type flash_word_program(uint32_t address, uint32_t data);
-flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
-flash_status_type flash_byte_program(uint32_t address, uint8_t data);
-flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
-flash_status_type flash_epp_set(uint32_t *sector_bits);
-void flash_epp_status_get(uint32_t *sector_bits);
-flash_status_type flash_fap_enable(confirm_state new_state);
-flag_status flash_fap_status_get(void);
-flash_status_type flash_ssb_set(uint8_t usd_ssb);
-uint8_t flash_ssb_status_get(void);
-void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
-void flash_spim_model_select(flash_spim_model_type mode);
-void flash_spim_encryption_range_set(uint32_t decode_address);
-flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
-error_status flash_slib_disable(uint32_t pwd);
-uint32_t flash_slib_remaining_count_get(void);
-flag_status flash_slib_state_get(void);
-uint16_t flash_slib_start_sector_get(void);
-uint16_t flash_slib_datstart_sector_get(void);
-uint16_t flash_slib_end_sector_get(void);
-uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_gpio.h

@@ -1,941 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_gpio.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 gpio header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_GPIO_H
-#define __AT32F403A_407_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/** @defgroup GPIO_pins_number_definition
-  * @{
-  */
-
-#define GPIO_PINS_0                      0x0001 /*!< gpio pins number 0 */
-#define GPIO_PINS_1                      0x0002 /*!< gpio pins number 1 */
-#define GPIO_PINS_2                      0x0004 /*!< gpio pins number 2 */
-#define GPIO_PINS_3                      0x0008 /*!< gpio pins number 3 */
-#define GPIO_PINS_4                      0x0010 /*!< gpio pins number 4 */
-#define GPIO_PINS_5                      0x0020 /*!< gpio pins number 5 */
-#define GPIO_PINS_6                      0x0040 /*!< gpio pins number 6 */
-#define GPIO_PINS_7                      0x0080 /*!< gpio pins number 7 */
-#define GPIO_PINS_8                      0x0100 /*!< gpio pins number 8 */
-#define GPIO_PINS_9                      0x0200 /*!< gpio pins number 9 */
-#define GPIO_PINS_10                     0x0400 /*!< gpio pins number 10 */
-#define GPIO_PINS_11                     0x0800 /*!< gpio pins number 11 */
-#define GPIO_PINS_12                     0x1000 /*!< gpio pins number 12 */
-#define GPIO_PINS_13                     0x2000 /*!< gpio pins number 13 */
-#define GPIO_PINS_14                     0x4000 /*!< gpio pins number 14 */
-#define GPIO_PINS_15                     0x8000 /*!< gpio pins number 15 */
-#define GPIO_PINS_ALL                    0xFFFF /*!< gpio all pins */
-
-/**
-  * @}
-  */
-
-#define IOMUX_MAKE_VALUE(reg_offset, bit_addr ,bit_num, bit_val) \
-        (uint32_t)(((reg_offset) << 24) | ((bit_addr) << 16) | ((bit_num) << 8) | (bit_val))
-
-/** @defgroup IOMUX_map_definition
-  * @brief iomux map definitions
-  * @{
-  */
-
-#if defined (AT32F403Axx)
-#define SPI1_MUX_01                      SPI1_GMUX_0001    /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
-#define SPI1_MUX_10                      SPI1_GMUX_0010    /*!< spi1_cs/i2s1_ws(pa4),  spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
-#define SPI1_MUX_11                      SPI1_GMUX_0011    /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
-#define I2C1_MUX                         I2C1_GMUX_0001    /*!< i2c1_scl(pb8),      i2c1_sda(pb9) */
-#define USART1_MUX                       USART1_GMUX_0001  /*!< usart1_tx(pb6),     usart1_rx(pb7) */
-#define USART2_MUX                       USART2_GMUX_0001  /*!< usart2_tx(pd5),     usart2_rx(pd6),  usart2_ck(pd7),  usart2_cts(pd3),  usart2_rts(pd4) */
-#define USART3_MUX_01                    USART3_GMUX_0001  /*!< usart3_tx(pc10),    usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
-#define USART3_MUX_11                    USART3_GMUX_0011  /*!< usart3_tx(pd8),     usart3_rx(pd9),  usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
-#define TMR1_MUX_01                      TMR1_GMUX_0001    /*!< tmr1_ext(pa12),     tmr1_ch1(pa8),   tmr1_ch2(pa9),   tmr1_ch3(pa10),   tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
-#define TMR1_MUX_11                      TMR1_GMUX_0011    /*!< tmr1_ext(pe7),      tmr1_ch1(pe9),   tmr1_ch2(pe11),  tmr1_ch3(pe13),   tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
-#define TMR2_MUX_01                      TMR2_GMUX_01      /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pa2),   tmr2_ch4(pa3) */
-#define TMR2_MUX_10                      TMR2_GMUX_10      /*!< tmr2_ch1_ext(pa0),  tmr2_ch2(pa1),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
-#define TMR2_MUX_11                      TMR2_GMUX_11      /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
-#define TMR3_MUX_10                      TMR3_GMUX_0010    /*!< tmr3_ch1(pb4),      tmr3_ch2(pb5),   tmr3_ch3(pb0),   tmr3_ch4(pb1) */
-#define TMR3_MUX_11                      TMR3_GMUX_0011    /*!< tmr3_ch1(pc6),      tmr3_ch2(pc7),   tmr3_ch3(pc8),   tmr3_ch4(pc9) */
-#define TMR4_MUX                         TMR4_GMUX_0001    /*!< tmr4_ch1(pd12),     tmr4_ch2(pd13),  tmr4_ch3(pd14),  tmr4_ch4(pd15) */
-#define CAN_MUX_10                       CAN1_GMUX_0010    /*!< can_rx(pb8),        can_tx(pb9) */
-#define CAN_MUX_11                       CAN1_GMUX_0011    /*!< can_rx(pd0),        can_tx(pd1) */
-#define PD01_MUX                         PD01_GMUX         /*!< pd0/pd1 mapping on osc_in/osc_out */
-#define TMR5CH4_MUX                      TMR5CH4_GMUX      /*!< lick connected to tmr5_ch4 input capture for calibration */
-#define ADC1_ETP_MUX                     ADC1_ETP_GMUX     /*!< adc1 external trigger preempted conversion muxing */
-#define ADC1_ETO_MUX                     ADC1_ETO_GMUX     /*!< adc1 external trigger ordinary conversion muxing */
-#define ADC2_ETP_MUX                     ADC2_ETP_GMUX     /*!< adc2 external trigger preempted conversion muxing */
-#define ADC2_ETO_MUX                     ADC2_ETO_GMUX     /*!< adc2 external trigger ordinary conversion muxing */
-#define SWJTAG_MUX_001                   SWJTAG_GMUX_001   /*!< full swj enabled  (jtag-dp  +  sw-dp)  but without jtrst */
-#define SWJTAG_MUX_010                   SWJTAG_GMUX_010   /*!< jtag-dp disabled and sw-dp enabled */
-#define SWJTAG_MUX_100                   SWJTAG_GMUX_100   /*!< full swj disabled  (jtag-dp  +  sw-dp) */
-#endif
-#if defined (AT32F407xx)
-#define SPI1_MUX_01                      SPI1_GMUX_0001    /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
-#define SPI1_MUX_10                      SPI1_GMUX_0010    /*!< spi1_cs/i2s1_ws(pa4),  spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
-#define SPI1_MUX_11                      SPI1_GMUX_0011    /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
-#define I2C1_MUX                         I2C1_GMUX_0001    /*!< i2c1_scl(pb8),      i2c1_sda(pb9) */
-#define USART1_MUX                       USART1_GMUX_0001  /*!< usart1_tx(pb6),     usart1_rx(pb7) */
-#define USART2_MUX                       USART2_GMUX_0001  /*!< usart2_tx(pd5),     usart2_rx(pd6),  usart2_ck(pd7),  usart2_cts(pd3),  usart2_rts(pd4) */
-#define USART3_MUX_01                    USART3_GMUX_0001  /*!< usart3_tx(pc10),    usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
-#define USART3_MUX_11                    USART3_GMUX_0011  /*!< usart3_tx(pd8),     usart3_rx(pd9),  usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
-#define TMR1_MUX_01                      TMR1_GMUX_0001    /*!< tmr1_ext(pa12),     tmr1_ch1(pa8),   tmr1_ch2(pa9),   tmr1_ch3(pa10),   tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
-#define TMR1_MUX_11                      TMR1_GMUX_0011    /*!< tmr1_ext(pe7),      tmr1_ch1(pe9),   tmr1_ch2(pe11),  tmr1_ch3(pe13),   tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
-#define TMR2_MUX_01                      TMR2_GMUX_01      /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pa2),   tmr2_ch4(pa3) */
-#define TMR2_MUX_10                      TMR2_GMUX_10      /*!< tmr2_ch1_ext(pa0),  tmr2_ch2(pa1),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
-#define TMR2_MUX_11                      TMR2_GMUX_11      /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3),   tmr2_ch3(pb10),  tmr2_ch4(pb11) */
-#define TMR3_MUX_10                      TMR3_GMUX_0010    /*!< tmr3_ch1(pb4),      tmr3_ch2(pb5),   tmr3_ch3(pb0),   tmr3_ch4(pb1) */
-#define TMR3_MUX_11                      TMR3_GMUX_0011    /*!< tmr3_ch1(pc6),      tmr3_ch2(pc7),   tmr3_ch3(pc8),   tmr3_ch4(pc9) */
-#define TMR4_MUX                         TMR4_GMUX_0001    /*!< tmr4_ch1(pd12),     tmr4_ch2(pd13),  tmr4_ch3(pd14),  tmr4_ch4(pd15) */
-#define CAN_MUX_00                       CAN1_GMUX_0000    /*!< can_rx(pa11),       can_tx(pa12) */
-#define CAN_MUX_10                       CAN1_GMUX_0010    /*!< can_rx(pb8),        can_tx(pb9) */
-#define CAN_MUX_11                       CAN1_GMUX_0011    /*!< can_rx(pd0),        can_tx(pd1) */
-#define PD01_MUX                         PD01_GMUX         /*!< pd0/pd1 mapping on osc_in/osc_out */
-#define TMR5CH4_MUX                      TMR5CH4_GMUX      /*!< lick connected to tmr5_ch4 input capture for calibration */
-#define ADC1_ETP_MUX                     ADC1_ETP_GMUX     /*!< adc1 external trigger preempted conversion muxing */
-#define ADC1_ETO_MUX                     ADC1_ETO_GMUX     /*!< adc1 external trigger ordinary conversion muxing */
-#define ADC2_ETP_MUX                     ADC2_ETP_GMUX     /*!< adc2 external trigger preempted conversion muxing */
-#define ADC2_ETO_MUX                     ADC2_ETO_GMUX     /*!< adc2 external trigger ordinary conversion muxing */
-#define EMAC_MUX                         EMAC_GMUX_01      /*!< rx_dv/crs_dv(pd8), rxd0(pd9), rxd1(pd10), rxd2(pd11), rxd3(pd12) */
-#define CAN2_MUX                         CAN2_GMUX_0001    /*!< can2_rx(pb5), can2_tx(pb6) */
-#define MII_RMII_SEL_MUX                 MII_RMII_SEL_GMUX /*!< mii or rmii selection */
-#define SWJTAG_MUX_001                   SWJTAG_GMUX_001   /*!< full swj enabled  (jtag-dp  +  sw-dp)  but without jtrst */
-#define SWJTAG_MUX_010                   SWJTAG_GMUX_010   /*!< jtag-dp disabled and sw-dp enabled */
-#define SWJTAG_MUX_100                   SWJTAG_GMUX_100   /*!< full swj disabled  (jtag-dp  +  sw-dp) */
-#define SPI3_MUX                         SPI3_GMUX_0001    /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pc7) */
-#define TMR2ITR1_MUX                     TMR2ITR1_GMAP_10  /*!< tmr2 internal trigger 1 mux remapping */
-#define PTP_PPS_MUX                      PTP_PPS_GMUX      /*!< ethernet ptp pps mux function remapping */
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map2_definition
-  * @brief iomux map2 definitions
-  * @{
-  */
-
-#define TMR9_MUX                         TMR9_GMUX          /*!< tmr9_ch1(pe5),   tmr9_ch2(pe6) */
-#define XMC_NADV_MUX                     XMC_NADV_GMUX      /*!< xmc_nadv not used */
-#define SPI4_MUX                         SPI4_GMUX_0001     /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
-#define I2C3_MUX                         I2C3_GMUX_0001     /*!< i2c3_scl(pa8), i2c3_sda(pb4) */
-#define SDIO2_MUX01                      SDIO2_GMUX_0001    /*!< sdio2_ck(pc4), sdio2_cmd(pc5), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
-#define SDIO2_MUX10                      SDIO2_GMUX_0010    /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pc0), sdio2_d1(pc1), sdio2_d2(pc2), sdio2_d3(pc3), sdio2_d4(pa4), sdio2_d5(pa5), sdio2_d6(pa6), sdio2_d7(pa7) */
-#define SDIO2_MUX11                      SDIO2_GMUX_0011    /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
-#define EXT_SPIM_EN_MUX                  EXT_SPIM_GMUX_1000 /*!< enable external spi-flash interface */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map3_definition
-  * @brief iomux map3 definitions
-  * @{
-  */
-
-#define TMR9_GMUX                        IOMUX_MAKE_VALUE(0x20, 0, 4, 0x01) /*!< tmr9_ch1(pe5),  tmr9_ch2(pe6) */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map4_definition
-  * @brief iomux map4 definitions
-  * @{
-  */
-
-#define TMR1_GMUX_0001                   IOMUX_MAKE_VALUE(0x24, 0, 4, 0x01)  /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
-#define TMR1_GMUX_0011                   IOMUX_MAKE_VALUE(0x24, 0, 4, 0x03)  /*!< tmr1_ext(pe7),  tmr1_ch1(pe9), tmr1_ch2(pe11), tmr1_ch3(pe13), tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
-#define TMR2_GMUX_01                     IOMUX_MAKE_VALUE(0x24, 4, 2, 0x01)  /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2),  tmr2_ch4(pa3) */
-#define TMR2_GMUX_10                     IOMUX_MAKE_VALUE(0x24, 4, 2, 0x02)  /*!< tmr2_ch1_ext(pa0),  tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
-#define TMR2_GMUX_11                     IOMUX_MAKE_VALUE(0x24, 4, 2, 0x03)  /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
-#define TMR2ITR1_GMUX_10                 IOMUX_MAKE_VALUE(0x24, 6, 2, 0x02)  /*!< ethernet ptp as input to tmr2_int.1 */
-#define TMR2ITR1_GMUX_11                 IOMUX_MAKE_VALUE(0x24, 6, 2, 0x03)  /*!< usbdev sof as input to tmr2_int.1 */
-#define TMR3_GMUX_0010                   IOMUX_MAKE_VALUE(0x24, 8, 4, 0x02)  /*!< tmr3_ch1(pb4),  tmr3_ch2(pb5),  tmr3_ch3(pb0),  tmr3_ch4(pb1) */
-#define TMR3_GMUX_0011                   IOMUX_MAKE_VALUE(0x24, 8, 4, 0x03)  /*!< tmr3_ch1(pc6),  tmr3_ch2(pc7),  tmr3_ch3(pc8),  tmr3_ch4(pc9) */
-#define TMR4_GMUX_0001                   IOMUX_MAKE_VALUE(0x24, 12, 4, 0x01) /*!< tmr4_ch1(pd12), tmr4_ch2(pd13), tmr4_ch3(pd14), tmr4_ch4(pd15) */
-#define TMR5CH4_GMUX                     IOMUX_MAKE_VALUE(0x24, 19, 1, 0x01) /*!< lick connected to tmr5_ch4 input capture for calibration */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map5_definition
-  * @brief iomux map5 definitions
-  * @{
-  */
-
-#define UART5_GMUX_0001                  IOMUX_MAKE_VALUE(0x28, 0, 4, 0x01)  /*!< uart5_tx(pb9), uart5_rx(pb8) */
-#define I2C1_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 4, 4, 0x01)  /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
-#define I2C3_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 12, 4, 0x01) /*!< i2c3_scl(pa8), i2c3_sda(pb4) */
-#define SPI1_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 16, 4, 0x01) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
-#define SPI1_GMUX_0010                   IOMUX_MAKE_VALUE(0x28, 16, 4, 0x02) /*!< spi1_cs/i2s1_ws(pa4),  spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
-#define SPI1_GMUX_0011                   IOMUX_MAKE_VALUE(0x28, 16, 4, 0x03) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
-#define SPI2_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 20, 4, 0x01) /*!< i2s2_mck(pa3) */
-#define SPI2_GMUX_0010                   IOMUX_MAKE_VALUE(0x28, 20, 4, 0x02) /*!< i2s2_mck(pa6) */
-#define SPI3_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 24, 4, 0x01) /*!< spi3_cs/i2s3_ws(pa4),  spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pc7) */
-#define SPI3_GMUX_0010                   IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3),  spi3_miso(pb4),  spi3_mosi/i2s3_sd(pb5),  i2s3_mck(pb10) */
-#define SPI3_GMUX_0011                   IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4),  spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */
-#define SPI4_GMUX_0001                   IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
-#define SPI4_GMUX_0010                   IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6),  spi4_sck/i2s4_ck(pb7),  spi4_miso(pb8),  spi4_mosi/i2s4_sd(pb8),  i2s4_mck(pc8) */
-#define SPI4_GMUX_0011                   IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6),  spi4_sck/i2s4_ck(pb7),  spi4_miso(pb8),  spi4_mosi/i2s4_sd(pb8),  i2s4_mck(pa10) */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map6_definition
-  * @brief iomux map6 definitions
-  * @{
-  */
-
-#define CAN1_GMUX_0010                   IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x02)  /*!< can_rx(pb8),   can_tx(pb9) */
-#define CAN1_GMUX_0011                   IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x03)  /*!< can_rx(pd0),   can_tx(pd1) */
-#define CAN2_GMUX_0001                   IOMUX_MAKE_VALUE(0x2C, 4, 4, 0x01)  /*!< can2_rx(pb5),  can2_tx(pb6) */
-#define SDIO2_GMUX_0001                  IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x01) /*!< sdio2_ck(pc4), sdio2_cmd(pc5), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
-#define SDIO2_GMUX_0010                  IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x02) /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pc0), sdio2_d1(pc1), sdio2_d2(pc2), sdio2_d3(pc3), sdio2_d4(pa4), sdio2_d5(pa5), sdio2_d6(pa6), sdio2_d7(pa7) */
-#define SDIO2_GMUX_0011                  IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x03) /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
-#define USART1_GMUX_0001                 IOMUX_MAKE_VALUE(0x2C, 16, 4, 0x01) /*!< usart1_tx(pb6),  usart1_rx(pb7) */
-#define USART2_GMUX_0001                 IOMUX_MAKE_VALUE(0x2C, 20, 4, 0x01) /*!< usart2_tx(pd5),  usart2_rx(pd6),  usart2_ck(pd7),  usart2_cts(pd3),  usart2_rts(pd4) */
-#define USART3_GMUX_0001                 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x01) /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
-#define USART3_GMUX_0011                 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x03) /*!< usart3_tx(pd8),  usart3_rx(pd9),  usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
-#define UART4_GMUX_0010                  IOMUX_MAKE_VALUE(0x2C, 28, 4, 0x02) /*!< uart4_tx(pa0),   uart4_rx(pa1) */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map7_definition
-  * @brief iomux map7 definitions
-  * @{
-  */
-
-#define EXT_SPIM_GMUX_1000               IOMUX_MAKE_VALUE(0x30, 0, 4, 0x08)  /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pa11), spim_io1(pa12), spim_io2(pb7), spim_sio3(pb6) */
-#define EXT_SPIM_GMUX_1001               IOMUX_MAKE_VALUE(0x30, 0, 4, 0x09)  /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pb10), spim_io1(pb11), spim_io2(pb7), spim_sio3(pb6) */
-#define ADC1_ETP_GMUX                    IOMUX_MAKE_VALUE(0x30, 4, 1, 0x01)  /*!< adc1 external trigger preempted conversion muxing */
-#define ADC1_ETO_GMUX                    IOMUX_MAKE_VALUE(0x30, 5, 1, 0x01)  /*!< adc1 external trigger ordinary conversion muxing */
-#define ADC2_ETP_GMUX                    IOMUX_MAKE_VALUE(0x30, 8, 1, 0x01)  /*!< adc2 external trigger preempted conversion muxing */
-#define ADC2_ETO_GMUX                    IOMUX_MAKE_VALUE(0x30, 9, 1, 0x01)  /*!< adc2 external trigger ordinary conversion muxing */
-#define SWJTAG_GMUX_001                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x01) /*!< full swj enabled  (jtag-dp  +  sw-dp)  but without jtrst */
-#define SWJTAG_GMUX_010                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x02) /*!< jtag-dp disabled and sw-dp enabled */
-#define SWJTAG_GMUX_100                  IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled  (jtag-dp  +  sw-dp) */
-#define PD01_GMUX                        IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
-#define XMC_GMUX_001                     IOMUX_MAKE_VALUE(0x30, 24, 3, 0x01) /*!< xmc_nwe(pd2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
-#define XMC_GMUX_010                     IOMUX_MAKE_VALUE(0x30, 24, 3, 0x02) /*!< xmc_nwe(pc2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
-#define XMC_NADV_GMUX                    IOMUX_MAKE_VALUE(0x30, 27, 1, 0x01) /*!< xmc_nadv not used */
-
-/**
-  * @}
-  */
-
-/** @defgroup IOMUX_map8_definition
-  * @brief iomux map8 definitions
-  * @{
-  */
-
-#if defined (AT32F407xx)
-#define EMAC_GMUX_01                     IOMUX_MAKE_VALUE(0x34, 16, 2, 0x01) /*!< rx_dv/crs_dv(pd8), rxd0(pd9), rxd1(pd10), rxd2(pd11), rxd3(pd12) */
-#define MII_RMII_SEL_GMUX                IOMUX_MAKE_VALUE(0x34, 18, 1, 0x01) /*!< mii or rmii selection */
-#define PTP_PPS_GMUX                     IOMUX_MAKE_VALUE(0x34, 19, 1, 0x01) /*!< ethernet ptp pps mux function remapping */
-#endif
-#define USART6_GMUX                      IOMUX_MAKE_VALUE(0x34, 20, 4, 0x01) /*!< usart6_tx(pa4), usart6_rx(pa5) */
-#define UART7_GMUX                       IOMUX_MAKE_VALUE(0x34, 24, 4, 0x01) /*!< uart7_tx(pb4),  uart7_rx(pb3) */
-#define UART8_GMUX                       IOMUX_MAKE_VALUE(0x34, 28, 4, 0x01) /*!< uart8_tx(pc2),  uart8_rx(pc3) */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_exported_types
-  * @{
-  */
-
-/**
-  * @brief gpio mode select
-  */
-typedef enum
-{
-  GPIO_MODE_INPUT                        = 0x00, /*!< gpio input mode */
-  GPIO_MODE_OUTPUT                       = 0x10, /*!< gpio output mode */
-  GPIO_MODE_MUX                          = 0x08, /*!< gpio mux function mode */
-  GPIO_MODE_ANALOG                       = 0x03  /*!< gpio analog in/out mode */
-} gpio_mode_type;
-
-/**
-  * @brief gpio output drive strength select
-  */
-typedef enum
-{
-  GPIO_DRIVE_STRENGTH_STRONGER           = 0x01, /*!< stronger sourcing/sinking strength */
-  GPIO_DRIVE_STRENGTH_MODERATE           = 0x02  /*!< moderate sourcing/sinking strength */
-} gpio_drive_type;
-
-/**
-  * @brief gpio output type
-  */
-typedef enum
-{
-  GPIO_OUTPUT_PUSH_PULL                  = 0x00, /*!< output push-pull */
-  GPIO_OUTPUT_OPEN_DRAIN                 = 0x04  /*!< output open-drain */
-} gpio_output_type;
-
-/**
-  * @brief gpio pull type
-  */
-typedef enum
-{
-  GPIO_PULL_NONE                         = 0x0004, /*!< floating for input, no pull for output */
-  GPIO_PULL_UP                           = 0x0018, /*!< pull-up */
-  GPIO_PULL_DOWN                         = 0x0028  /*!< pull-down */
-} gpio_pull_type;
-
-/**
-  * @brief gpio pins source type
-  */
-typedef enum
-{
-  GPIO_PINS_SOURCE0                      = 0x00, /*!< gpio pins source number 0 */
-  GPIO_PINS_SOURCE1                      = 0x01, /*!< gpio pins source number 1 */
-  GPIO_PINS_SOURCE2                      = 0x02, /*!< gpio pins source number 2 */
-  GPIO_PINS_SOURCE3                      = 0x03, /*!< gpio pins source number 3 */
-  GPIO_PINS_SOURCE4                      = 0x04, /*!< gpio pins source number 4 */
-  GPIO_PINS_SOURCE5                      = 0x05, /*!< gpio pins source number 5 */
-  GPIO_PINS_SOURCE6                      = 0x06, /*!< gpio pins source number 6 */
-  GPIO_PINS_SOURCE7                      = 0x07, /*!< gpio pins source number 7 */
-  GPIO_PINS_SOURCE8                      = 0x08, /*!< gpio pins source number 8 */
-  GPIO_PINS_SOURCE9                      = 0x09, /*!< gpio pins source number 9 */
-  GPIO_PINS_SOURCE10                     = 0x0A, /*!< gpio pins source number 10 */
-  GPIO_PINS_SOURCE11                     = 0x0B, /*!< gpio pins source number 11 */
-  GPIO_PINS_SOURCE12                     = 0x0C, /*!< gpio pins source number 12 */
-  GPIO_PINS_SOURCE13                     = 0x0D, /*!< gpio pins source number 13 */
-  GPIO_PINS_SOURCE14                     = 0x0E, /*!< gpio pins source number 14 */
-  GPIO_PINS_SOURCE15                     = 0x0F  /*!< gpio pins source number 15 */
-} gpio_pins_source_type;
-
-/**
-  * @brief gpio port source type
-  */
-typedef enum
-{
-  GPIO_PORT_SOURCE_GPIOA                 = 0x00, /*!< gpio port source gpioa */
-  GPIO_PORT_SOURCE_GPIOB                 = 0x01, /*!< gpio port source gpiob */
-  GPIO_PORT_SOURCE_GPIOC                 = 0x02, /*!< gpio port source gpioc */
-  GPIO_PORT_SOURCE_GPIOD                 = 0x03, /*!< gpio port source gpiod */
-  GPIO_PORT_SOURCE_GPIOE                 = 0x04, /*!< gpio port source gpioe */
-} gpio_port_source_type;
-
-/**
-  * @brief gpio init type
-  */
-typedef struct
-{
-  uint32_t                               gpio_pins;           /*!< pins number selection */
-  gpio_output_type                       gpio_out_type;       /*!< output type selection */
-  gpio_pull_type                         gpio_pull;           /*!< pull type selection */
-  gpio_mode_type                         gpio_mode;           /*!< mode selection */
-  gpio_drive_type                        gpio_drive_strength; /*!< drive strength selection */
-} gpio_init_type;
-
-/**
-  * @brief type define gpio register all
-  */
-typedef struct
-{
-  /**
-    * @brief gpio cfglr register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t cfglr;
-    struct
-    {
-      __IO uint32_t iomc0                : 2; /* [1:0] */
-      __IO uint32_t iofc0                : 2; /* [3:2] */
-      __IO uint32_t iomc1                : 2; /* [5:4] */
-      __IO uint32_t iofc1                : 2; /* [7:6] */
-      __IO uint32_t iomc2                : 2; /* [9:8] */
-      __IO uint32_t iofc2                : 2; /* [11:10] */
-      __IO uint32_t iomc3                : 2; /* [13:12] */
-      __IO uint32_t iofc3                : 2; /* [15:14] */
-      __IO uint32_t iomc4                : 2; /* [17:16] */
-      __IO uint32_t iofc4                : 2; /* [19:18] */
-      __IO uint32_t iomc5                : 2; /* [21:20] */
-      __IO uint32_t iofc5                : 2; /* [23:22] */
-      __IO uint32_t iomc6                : 2; /* [25:24] */
-      __IO uint32_t iofc6                : 2; /* [27:26] */
-      __IO uint32_t iomc7                : 2; /* [29:28] */
-      __IO uint32_t iofc7                : 2; /* [31:30] */
-    } cfglr_bit;
-  };
-
-  /**
-    * @brief gpio cfghr register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t cfghr;
-    struct
-    {
-      __IO uint32_t iomc8                : 2; /* [1:0] */
-      __IO uint32_t iofc8                : 2; /* [3:2] */
-      __IO uint32_t iomc9                : 2; /* [5:4] */
-      __IO uint32_t iofc9                : 2; /* [7:6] */
-      __IO uint32_t iomc10               : 2; /* [9:8] */
-      __IO uint32_t iofc10               : 2; /* [11:10] */
-      __IO uint32_t iomc11               : 2; /* [13:12] */
-      __IO uint32_t iofc11               : 2; /* [15:14] */
-      __IO uint32_t iomc12               : 2; /* [17:16] */
-      __IO uint32_t iofc12               : 2; /* [19:18] */
-      __IO uint32_t iomc13               : 2; /* [21:20] */
-      __IO uint32_t iofc13               : 2; /* [23:22] */
-      __IO uint32_t iomc14               : 2; /* [25:24] */
-      __IO uint32_t iofc14               : 2; /* [27:26] */
-      __IO uint32_t iomc15               : 2; /* [29:28] */
-      __IO uint32_t iofc15               : 2; /* [31:30] */
-    } cfghr_bit;
-  };
-
-  /**
-    * @brief gpio idt register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t idt;
-    struct
-    {
-      __IO uint32_t idt0                 : 1; /* [0] */
-      __IO uint32_t idt1                 : 1; /* [1] */
-      __IO uint32_t idt2                 : 1; /* [2] */
-      __IO uint32_t idt3                 : 1; /* [3] */
-      __IO uint32_t idt4                 : 1; /* [4] */
-      __IO uint32_t idt5                 : 1; /* [5] */
-      __IO uint32_t idt6                 : 1; /* [6] */
-      __IO uint32_t idt7                 : 1; /* [7] */
-      __IO uint32_t idt8                 : 1; /* [8] */
-      __IO uint32_t idt9                 : 1; /* [9] */
-      __IO uint32_t idt10                : 1; /* [10] */
-      __IO uint32_t idt11                : 1; /* [11] */
-      __IO uint32_t idt12                : 1; /* [12] */
-      __IO uint32_t idt13                : 1; /* [13] */
-      __IO uint32_t idt14                : 1; /* [14] */
-      __IO uint32_t idt15                : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } idt_bit;
-  };
-
-  /**
-    * @brief gpio odt register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t odt;
-    struct
-    {
-      __IO uint32_t odt0                 : 1; /* [0] */
-      __IO uint32_t odt1                 : 1; /* [1] */
-      __IO uint32_t odt2                 : 1; /* [2] */
-      __IO uint32_t odt3                 : 1; /* [3] */
-      __IO uint32_t odt4                 : 1; /* [4] */
-      __IO uint32_t odt5                 : 1; /* [5] */
-      __IO uint32_t odt6                 : 1; /* [6] */
-      __IO uint32_t odt7                 : 1; /* [7] */
-      __IO uint32_t odt8                 : 1; /* [8] */
-      __IO uint32_t odt9                 : 1; /* [9] */
-      __IO uint32_t odt10                : 1; /* [10] */
-      __IO uint32_t odt11                : 1; /* [11] */
-      __IO uint32_t odt12                : 1; /* [12] */
-      __IO uint32_t odt13                : 1; /* [13] */
-      __IO uint32_t odt14                : 1; /* [14] */
-      __IO uint32_t odt15                : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } odt_bit;
-  };
-
-  /**
-    * @brief gpio scr register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t scr;
-    struct
-    {
-      __IO uint32_t iosb0                : 1; /* [0] */
-      __IO uint32_t iosb1                : 1; /* [1] */
-      __IO uint32_t iosb2                : 1; /* [2] */
-      __IO uint32_t iosb3                : 1; /* [3] */
-      __IO uint32_t iosb4                : 1; /* [4] */
-      __IO uint32_t iosb5                : 1; /* [5] */
-      __IO uint32_t iosb6                : 1; /* [6] */
-      __IO uint32_t iosb7                : 1; /* [7] */
-      __IO uint32_t iosb8                : 1; /* [8] */
-      __IO uint32_t iosb9                : 1; /* [9] */
-      __IO uint32_t iosb10               : 1; /* [10] */
-      __IO uint32_t iosb11               : 1; /* [11] */
-      __IO uint32_t iosb12               : 1; /* [12] */
-      __IO uint32_t iosb13               : 1; /* [13] */
-      __IO uint32_t iosb14               : 1; /* [14] */
-      __IO uint32_t iosb15               : 1; /* [15] */
-      __IO uint32_t iocb0                : 1; /* [16] */
-      __IO uint32_t iocb1                : 1; /* [17] */
-      __IO uint32_t iocb2                : 1; /* [18] */
-      __IO uint32_t iocb3                : 1; /* [19] */
-      __IO uint32_t iocb4                : 1; /* [20] */
-      __IO uint32_t iocb5                : 1; /* [21] */
-      __IO uint32_t iocb6                : 1; /* [22] */
-      __IO uint32_t iocb7                : 1; /* [23] */
-      __IO uint32_t iocb8                : 1; /* [24] */
-      __IO uint32_t iocb9                : 1; /* [25] */
-      __IO uint32_t iocb10               : 1; /* [26] */
-      __IO uint32_t iocb11               : 1; /* [27] */
-      __IO uint32_t iocb12               : 1; /* [28] */
-      __IO uint32_t iocb13               : 1; /* [29] */
-      __IO uint32_t iocb14               : 1; /* [30] */
-      __IO uint32_t iocb15               : 1; /* [31] */
-    } scr_bit;
-  };
-
-  /**
-    * @brief gpio clr register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t clr;
-    struct
-    {
-      __IO uint32_t iocb0                : 1; /* [0] */
-      __IO uint32_t iocb1                : 1; /* [1] */
-      __IO uint32_t iocb2                : 1; /* [2] */
-      __IO uint32_t iocb3                : 1; /* [3] */
-      __IO uint32_t iocb4                : 1; /* [4] */
-      __IO uint32_t iocb5                : 1; /* [5] */
-      __IO uint32_t iocb6                : 1; /* [6] */
-      __IO uint32_t iocb7                : 1; /* [7] */
-      __IO uint32_t iocb8                : 1; /* [8] */
-      __IO uint32_t iocb9                : 1; /* [9] */
-      __IO uint32_t iocb10               : 1; /* [10] */
-      __IO uint32_t iocb11               : 1; /* [11] */
-      __IO uint32_t iocb12               : 1; /* [12] */
-      __IO uint32_t iocb13               : 1; /* [13] */
-      __IO uint32_t iocb14               : 1; /* [14] */
-      __IO uint32_t iocb15               : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } clr_bit;
-  };
-
-  /**
-    * @brief gpio wpr register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t wpr;
-    struct
-    {
-      __IO uint32_t wpen0                : 1; /* [0] */
-      __IO uint32_t wpen1                : 1; /* [1] */
-      __IO uint32_t wpen2                : 1; /* [2] */
-      __IO uint32_t wpen3                : 1; /* [3] */
-      __IO uint32_t wpen4                : 1; /* [4] */
-      __IO uint32_t wpen5                : 1; /* [5] */
-      __IO uint32_t wpen6                : 1; /* [6] */
-      __IO uint32_t wpen7                : 1; /* [7] */
-      __IO uint32_t wpen8                : 1; /* [8] */
-      __IO uint32_t wpen9                : 1; /* [9] */
-      __IO uint32_t wpen10               : 1; /* [10] */
-      __IO uint32_t wpen11               : 1; /* [11] */
-      __IO uint32_t wpen12               : 1; /* [12] */
-      __IO uint32_t wpen13               : 1; /* [13] */
-      __IO uint32_t wpen14               : 1; /* [14] */
-      __IO uint32_t wpen15               : 1; /* [15] */
-      __IO uint32_t wpseq                : 1; /* [16] */
-      __IO uint32_t reserved1            : 15;/* [31:17] */
-    } wpr_bit;
-  };
-
-  /**
-    * @brief gpio reserved1 register, offset:0x1C~0x38
-    */
-    __IO uint32_t reserved1[8];
-
-  /**
-    * @brief gpio hdrv register, offset:0x3C
-    */
-  union
-  {
-    __IO uint32_t hdrv;
-    struct
-    {
-      __IO uint32_t hdrv0                : 1; /* [0] */
-      __IO uint32_t hdrv1                : 1; /* [1] */
-      __IO uint32_t hdrv2                : 1; /* [2] */
-      __IO uint32_t hdrv3                : 1; /* [3] */
-      __IO uint32_t hdrv4                : 1; /* [4] */
-      __IO uint32_t hdrv5                : 1; /* [5] */
-      __IO uint32_t hdrv6                : 1; /* [6] */
-      __IO uint32_t hdrv7                : 1; /* [7] */
-      __IO uint32_t hdrv8                : 1; /* [8] */
-      __IO uint32_t hdrv9                : 1; /* [9] */
-      __IO uint32_t hdrv10               : 1; /* [10] */
-      __IO uint32_t hdrv11               : 1; /* [11] */
-      __IO uint32_t hdrv12               : 1; /* [12] */
-      __IO uint32_t hdrv13               : 1; /* [13] */
-      __IO uint32_t hdrv14               : 1; /* [14] */
-      __IO uint32_t hdrv15               : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } hdrv_bit;
-  };
-} gpio_type;
-
-/**
-  * @brief type define iomux register all
-  */
-typedef struct
-{
-  /**
-    * @brief mux event control register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t evtout;
-    struct
-    {
-      __IO uint32_t selpin               : 4; /* [3:0] */
-      __IO uint32_t selport              : 3; /* [6:4] */
-      __IO uint32_t evoen                : 1; /* [7]   */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } evtout_bit;
-  };
-
-  /**
-    * @brief iomux remap register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t remap;
-    struct
-    {
-      __IO uint32_t spi1_mux_l           : 1; /* [0] */
-      __IO uint32_t i2c1_mux             : 1; /* [1] */
-      __IO uint32_t usart1_mux           : 1; /* [2] */
-      __IO uint32_t usart2_mux           : 1; /* [3] */
-      __IO uint32_t usart3_mux           : 2; /* [5:4] */
-      __IO uint32_t tmr1_mux             : 2; /* [7:6] */
-      __IO uint32_t tmr2_mux             : 2; /* [9:8] */
-      __IO uint32_t tmr3_mux             : 2; /* [11:10] */
-      __IO uint32_t tmr4_mux             : 1; /* [12] */
-      __IO uint32_t can_mux              : 2; /* [14:13] */
-      __IO uint32_t pd01_mux             : 1; /* [15] */
-      __IO uint32_t tmr5ch4_mux          : 1; /* [16] */
-      __IO uint32_t adc1_extrgpre_mux    : 1; /* [17] */
-      __IO uint32_t adc1_extrgord_mux    : 1; /* [18] */
-      __IO uint32_t adc2_extrgpre_mux    : 1; /* [19] */
-      __IO uint32_t adc2_extrgord_mux    : 1; /* [20] */
-      __IO uint32_t emac_mux             : 1; /* [21] */
-      __IO uint32_t can2_mux             : 1; /* [22] */
-      __IO uint32_t mii_rmii_sel_mux     : 1; /* [23] */
-      __IO uint32_t swjtag_mux           : 3; /* [26:24] */
-      __IO uint32_t reserved1            : 1; /* [27] */
-      __IO uint32_t spi3_mux             : 1; /* [28] */
-      __IO uint32_t tim2itr1_mux         : 1; /* [29] */
-      __IO uint32_t ptp_pps_mux          : 1; /* [30] */
-      __IO uint32_t spi1_mux_h           : 1; /* [31] */
-    } remap_bit;
-  };
-
-  /**
-    * @brief mux external interrupt configuration register 1, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t exintc1;
-    struct
-    {
-      __IO uint32_t exint0              : 4; /* [3:0] */
-      __IO uint32_t exint1              : 4; /* [7:4] */
-      __IO uint32_t exint2              : 4; /* [11:8] */
-      __IO uint32_t exint3              : 4; /* [15:12] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } exintc1_bit;
-  };
-
-  /**
-    * @brief mux external interrupt configuration register 2, offset:0x0c
-    */
-  union
-  {
-    __IO uint32_t exintc2;
-    struct
-    {
-      __IO uint32_t exint4              : 4; /* [3:0] */
-      __IO uint32_t exint5              : 4; /* [7:4] */
-      __IO uint32_t exint6              : 4; /* [11:8] */
-      __IO uint32_t exint7              : 4; /* [15:12] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } exintc2_bit;
-  };
-
-  /**
-    * @brief mux external interrupt configuration register 3, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t exintc3;
-    struct
-    {
-      __IO uint32_t exint8              : 4; /* [3:0] */
-      __IO uint32_t exint9              : 4; /* [7:4] */
-      __IO uint32_t exint10             : 4; /* [11:8] */
-      __IO uint32_t exint11             : 4; /* [15:12] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } exintc3_bit;
-  };
-
-  /**
-    * @brief mux external interrupt configuration register 4, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t exintc4;
-    struct
-    {
-      __IO uint32_t exint12             : 4; /* [3:0] */
-      __IO uint32_t exint13             : 4; /* [7:4] */
-      __IO uint32_t exint14             : 4; /* [11:8] */
-      __IO uint32_t exint15             : 4; /* [15:12] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } exintc4_bit;
-  };
-
-  /**
-    * @brief iomux reserved1 register, offset:0x18
-    */
-  __IO uint32_t reserved1;
-
-  /**
-    * @brief iomux remap register 2, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t remap2;
-    struct
-    {
-      __IO uint32_t tmr15_mux            : 1; /* [0] */
-      __IO uint32_t reserved1            : 4; /* [4:1] */
-      __IO uint32_t tmr9_mux             : 1; /* [5] */
-      __IO uint32_t tmr10_mux            : 1; /* [6] */
-      __IO uint32_t tmr11_mux            : 1; /* [7] */
-      __IO uint32_t tmr13_mux            : 1; /* [8] */
-      __IO uint32_t tmr14_mux            : 1; /* [9] */
-      __IO uint32_t xmc_nadv_mux         : 1; /* [10] */
-      __IO uint32_t reserved2            : 6; /* [16:11] */
-      __IO uint32_t spi4_mux             : 1; /* [17] */
-      __IO uint32_t i2c3_mux             : 1; /* [18] */
-      __IO uint32_t sdio2_mux            : 2; /* [20:19] */
-      __IO uint32_t ext_spim_en_mux      : 1; /* [21] */
-      __IO uint32_t reserved3            : 10;/* [31:22] */
-    } remap2_bit;
-  };
-
-  /**
-    * @brief iomux remap register 3, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t remap3;
-    struct
-    {
-      __IO uint32_t tmr9_gmux            : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 28;/* [31:4] */
-    } remap3_bit;
-  };
-
-  /**
-    * @brief iomux remap register 4, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t remap4;
-    struct
-    {
-      __IO uint32_t tmr1_gmux            : 4; /* [3:0] */
-      __IO uint32_t tmr2_gmux            : 2; /* [5:4] */
-      __IO uint32_t tmr2itr1_gmux        : 2; /* [7:6] */
-      __IO uint32_t tmr3_gmux            : 4; /* [11:8] */
-      __IO uint32_t tmr4_gmux            : 4; /* [15:12] */
-      __IO uint32_t reserved1            : 3; /* [18:16] */
-      __IO uint32_t tmr5ch4_gmux         : 1; /* [19] */
-      __IO uint32_t reserved2            : 12; /* [31:20] */
-    } remap4_bit;
-  };
-
-  /**
-    * @brief iomux remap register 5, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t remap5;
-    struct
-    {
-      __IO uint32_t usart5_gmux          : 4; /* [3:0] */
-      __IO uint32_t i2c1_gmux            : 4; /* [7:4] */
-      __IO uint32_t reserved1            : 4; /* [11:8] */
-      __IO uint32_t i2c3_gmux            : 4; /* [15:12] */
-      __IO uint32_t spi1_gmux            : 4; /* [19:16] */
-      __IO uint32_t spi2_gmux            : 4; /* [23:20] */
-      __IO uint32_t spi3_gmux            : 4; /* [27:24] */
-      __IO uint32_t spi4_gmux            : 4; /* [31:28] */
-    } remap5_bit;
-  };
-
-  /**
-    * @brief iomux remap register 6, offset:0x2C
-    */
-  union
-  {
-    __IO uint32_t remap6;
-    struct
-    {
-      __IO uint32_t can1_gmux            : 4; /* [3:0] */
-      __IO uint32_t can2_gmux            : 4; /* [7:4] */
-      __IO uint32_t reserved1            : 4; /* [11:8] */
-      __IO uint32_t sdio2_gmux           : 4; /* [15:12] */
-      __IO uint32_t usart1_gmux          : 4; /* [19:16] */
-      __IO uint32_t usart2_gmux          : 4; /* [23:20] */
-      __IO uint32_t usart3_gmux          : 4; /* [27:24] */
-      __IO uint32_t uart4_gmux           : 4; /* [31:28] */
-    } remap6_bit;
-  };
-
-  /**
-    * @brief iomux remap register 7, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t remap7;
-    struct
-    {
-      __IO uint32_t ext_spim_gmux        : 3; /* [2:0] */
-      __IO uint32_t ext_spim_gen         : 1; /* [3] */
-      __IO uint32_t adc1_etp_gmux        : 1; /* [4] */
-      __IO uint32_t adc1_eto_gmux        : 1; /* [5] */
-      __IO uint32_t reserved1            : 2; /* [7:6] */
-      __IO uint32_t adc2_etp_gmux        : 1; /* [8] */
-      __IO uint32_t adc2_eto_gmux        : 1; /* [9] */
-      __IO uint32_t reserved2            : 6; /* [15:10] */
-      __IO uint32_t swjtag_gmux          : 3; /* [18:16] */
-      __IO uint32_t reserved3            : 1; /* [19] */
-      __IO uint32_t pd01_gmux            : 1; /* [20] */
-      __IO uint32_t reserved4            : 3; /* [23:21] */
-      __IO uint32_t xmc_gmux             : 3; /* [26:24] */
-      __IO uint32_t xmc_nadv_gmux        : 1; /* [27] */
-      __IO uint32_t reserved5            : 4; /* [31:28] */
-    } remap7_bit;
-  };
-
-  /**
-    * @brief iomux remap register 8, offset:0x34
-    */
-  union
-  {
-    __IO uint32_t remap8;
-    struct
-    {
-      __IO uint32_t reserved1            : 16; /* [15:0] */
-      __IO uint32_t emac_gmux            : 2; /* [17:16] */
-      __IO uint32_t mii_rmii_sel_gmux    : 1; /* [18] */
-      __IO uint32_t ptp_pps_gmux         : 1; /* [19] */
-      __IO uint32_t usart6_gmux          : 4; /* [23:20] */
-      __IO uint32_t uart7_gmux           : 4; /* [27:24] */
-      __IO uint32_t uart8_gmux           : 4; /* [31:28] */
-    } remap8_bit;
-  };
-} iomux_type;
-
-/**
-  * @}
-  */
-
-#define GPIOA                            ((gpio_type *) GPIOA_BASE)
-#define GPIOB                            ((gpio_type *) GPIOB_BASE)
-#define GPIOC                            ((gpio_type *) GPIOC_BASE)
-#define GPIOD                            ((gpio_type *) GPIOD_BASE)
-#define GPIOE                            ((gpio_type *) GPIOE_BASE)
-#define IOMUX                            ((iomux_type *) IOMUX_BASE)
-
-/** @defgroup GPIO_exported_functions
-  * @{
-  */
-
-void gpio_reset(gpio_type *gpio_x);
-void gpio_iomux_reset(void);
-void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
-void gpio_default_para_init(gpio_init_type *gpio_init_struct);
-flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
-uint16_t gpio_input_data_read(gpio_type *gpio_x);
-flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
-uint16_t gpio_output_data_read(gpio_type *gpio_x);
-void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
-void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
-void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
-void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
-void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
-void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
-void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
-void gpio_event_output_enable(confirm_state new_state);
-void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state);
-void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_i2c.h

@@ -1,402 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_i2c.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 i2c header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_I2C_H
-#define __AT32F403A_407_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/** @defgroup I2C_sts1_flags_definition
-  * @brief  i2c sts1 flag
-  * @{
-  */
-
-#define I2C_STARTF_FLAG                  ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
-#define I2C_ADDR7F_FLAG                  ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
-#define I2C_TDC_FLAG                     ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
-#define I2C_ADDRHF_FLAG                  ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
-#define I2C_STOPF_FLAG                   ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
-#define I2C_RDBF_FLAG                    ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
-#define I2C_TDBE_FLAG                    ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
-#define I2C_BUSERR_FLAG                  ((uint32_t)0x00000100) /*!< i2c bus error flag */
-#define I2C_ARLOST_FLAG                  ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
-#define I2C_ACKFAIL_FLAG                 ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
-#define I2C_OUF_FLAG                     ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
-#define I2C_PECERR_FLAG                  ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
-#define I2C_TMOUT_FLAG                   ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
-#define I2C_ALERTF_FLAG                  ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_sts2_flags_definition
-  * @brief  i2c sts2 flag
-  * @{
-  */
-
-#define I2C_TRMODE_FLAG                  ((uint32_t)0x10010000) /*!< i2c transmission mode */
-#define I2C_BUSYF_FLAG                   ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
-#define I2C_DIRF_FLAG                    ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
-#define I2C_GCADDRF_FLAG                 ((uint32_t)0x10100000) /*!< i2c general call address received flag */
-#define I2C_DEVADDRF_FLAG                ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
-#define I2C_HOSTADDRF_FLAG               ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
-#define I2C_ADDR2_FLAG                   ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_interrupts_definition
-  * @brief i2c interrupt
-  * @{
-  */
-
-#define I2C_DATA_INT                     ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
-#define I2C_EVT_INT                      ((uint16_t)0x0200) /*!< i2c event interrupt */
-#define I2C_ERR_INT                      ((uint16_t)0x0100) /*!< i2c error interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_exported_types
-  * @{
-  */
-
-/**
-  * @brief i2c master receiving mode acknowledge control
-  */
-typedef enum
-{
-  I2C_MASTER_ACK_CURRENT                 = 0x00, /*!< acken bit acts on the current byte */
-  I2C_MASTER_ACK_NEXT                    = 0x01  /*!< acken bit acts on the next byte */
-} i2c_master_ack_type;
-
-/**
-  * @brief i2c pec position set
-  */
-typedef enum
-{
-  I2C_PEC_POSITION_CURRENT               = 0x00, /*!< the current byte is pec */
-  I2C_PEC_POSITION_NEXT                  = 0x01  /*!< the next byte is pec */
-} i2c_pec_position_type;
-
-
-/**
-  * @brief i2c smbus alert pin set
-  */
-typedef enum
-{
-  I2C_SMBUS_ALERT_HIGH                   = 0x00, /*!< smbus alert pin set high */
-  I2C_SMBUS_ALERT_LOW                    = 0x01  /*!< smbus alert pin set low */
-} i2c_smbus_alert_set_type;
-
-/**
-  * @brief i2c smbus mode set
-  */
-typedef enum
-{
-  I2C_SMBUS_MODE_DEVICE                  = 0x00, /*!< smbus device mode */
-  I2C_SMBUS_MODE_HOST                    = 0x01  /*!< smbus host mode */
-} i2c_smbus_mode_set_type;
-
-
-/**
-  * @brief i2c fast mode duty cycle
-  */
-typedef enum
-{
-  I2C_FSMODE_DUTY_2_1                    = 0x00, /*!< duty cycle is 2:1 in fast mode */
-  I2C_FSMODE_DUTY_16_9                   = 0x01  /*!< duty cycle is 16:9 in fast mode */
-} i2c_fsmode_duty_cycle_type;
-
-/**
-  * @brief i2c address mode
-  */
-typedef enum
-{
-  I2C_ADDRESS_MODE_7BIT                  = 0x00, /*!< 7bit address mode */
-  I2C_ADDRESS_MODE_10BIT                 = 0x01  /*!< 10bit address mode */
-} i2c_address_mode_type;
-
-/**
-  * @brief i2c address direction
-  */
-typedef enum
-{
-  I2C_DIRECTION_TRANSMIT                 = 0x00, /*!< transmit mode */
-  I2C_DIRECTION_RECEIVE                  = 0x01  /*!< receive mode */
-} i2c_direction_type;
-
-/**
-  * @brief type define i2c register all
-  */
-typedef struct
-{
-  /**
-    * @brief i2c ctrl1 register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t i2cen                : 1; /* [0] */
-      __IO uint32_t permode              : 1; /* [1] */
-      __IO uint32_t reserved1            : 1; /* [2] */
-      __IO uint32_t smbmode              : 1; /* [3] */
-      __IO uint32_t arpen                : 1; /* [4] */
-      __IO uint32_t pecen                : 1; /* [5] */
-      __IO uint32_t gcaen                : 1; /* [6] */
-      __IO uint32_t stretch              : 1; /* [7] */
-      __IO uint32_t genstart             : 1; /* [8] */
-      __IO uint32_t genstop              : 1; /* [9] */
-      __IO uint32_t acken                : 1; /* [10] */
-      __IO uint32_t mackctrl             : 1; /* [11] */
-      __IO uint32_t pecten               : 1; /* [12] */
-      __IO uint32_t smbalert             : 1; /* [13] */
-      __IO uint32_t reserved2            : 1; /* [14] */
-      __IO uint32_t reset                : 1; /* [15] */
-      __IO uint32_t reserved3            : 16;/* [31:16] */
-    } ctrl1_bit;
-  };
-
-  /**
-    * @brief i2c ctrl2 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t clkfreq              : 8; /* [7:0] */
-      __IO uint32_t errien               : 1; /* [8] */
-      __IO uint32_t evtien               : 1; /* [9] */
-      __IO uint32_t dataien              : 1; /* [10] */
-      __IO uint32_t dmaen                : 1; /* [11] */
-      __IO uint32_t dmaend               : 1; /* [12] */
-      __IO uint32_t reserved1            : 19;/* [31:13] */
-    } ctrl2_bit;
-  };
-
-  /**
-    * @brief i2c oaddr1 register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t oaddr1;
-    struct
-    {
-      __IO uint32_t addr1                : 10;/* [9:0] */
-      __IO uint32_t reserved1            : 5; /* [14:10] */
-      __IO uint32_t addr1mode            : 1; /* [15] */
-      __IO uint32_t reserved2            : 16;/* [31:16] */
-    } oaddr1_bit;
-  };
-
-  /**
-    * @brief i2c oaddr2 register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t oaddr2;
-    struct
-    {
-      __IO uint32_t addr2en              : 1; /* [0] */
-      __IO uint32_t addr2                : 7; /* [7:1] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } oaddr2_bit;
-  };
-
-  /**
-    * @brief i2c dt register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t dt;
-    struct
-    {
-      __IO uint32_t dt                   : 8; /* [7:0] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } dt_bit;
-  };
-
-  /**
-    * @brief i2c sts1 register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t sts1;
-    struct
-    {
-      __IO uint32_t startf               : 1; /* [0] */
-      __IO uint32_t addr7f               : 1; /* [1] */
-      __IO uint32_t tdc                  : 1; /* [2] */
-      __IO uint32_t addrhf               : 1; /* [3] */
-      __IO uint32_t stopf                : 1; /* [4] */
-      __IO uint32_t reserved1            : 1; /* [5] */
-      __IO uint32_t rdbf                 : 1; /* [6] */
-      __IO uint32_t tdbe                 : 1; /* [7] */
-      __IO uint32_t buserr               : 1; /* [8] */
-      __IO uint32_t arlost               : 1; /* [9] */
-      __IO uint32_t ackfail              : 1; /* [10] */
-      __IO uint32_t ouf                  : 1; /* [11] */
-      __IO uint32_t pecerr               : 1; /* [12] */
-      __IO uint32_t reserved2            : 1; /* [13] */
-      __IO uint32_t tmout                : 1; /* [14] */
-      __IO uint32_t alertf               : 1; /* [15] */
-      __IO uint32_t reserved3            : 16; /* [31:16] */
-    } sts1_bit;
-  };
-
-  /**
-    * @brief i2c sts2 register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t sts2;
-    struct
-    {
-      __IO uint32_t trmode               : 1; /* [0] */
-      __IO uint32_t busyf                : 1; /* [1] */
-      __IO uint32_t dirf                 : 1; /* [2] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t gcaddrf              : 1; /* [4] */
-      __IO uint32_t devaddrf             : 1; /* [5] */
-      __IO uint32_t hostaddrf            : 1; /* [6] */
-      __IO uint32_t addr2                : 1; /* [7] */
-      __IO uint32_t pecval               : 8; /* [15:8] */
-      __IO uint32_t reserved2            : 16;/* [31:16] */
-    } sts2_bit;
-  };
-
-  /**
-    * @brief i2c clkctrl register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t clkctrl;
-    struct
-    {
-      __IO uint32_t speed                : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 2; /* [13:12] */
-      __IO uint32_t dutymode             : 1; /* [14] */
-      __IO uint32_t speedmode            : 1; /* [15] */
-      __IO uint32_t reserved2            : 16;/* [31:16] */
-    } clkctrl_bit;
-  };
-
-  /**
-    * @brief i2c tmrise register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t tmrise;
-    struct
-    {
-      __IO uint32_t risetime             : 6; /* [5:0] */
-      __IO uint32_t reserved1            : 26;/* [31:6] */
-    } tmrise_bit;
-  };
-
-} i2c_type;
-
-/**
-  * @}
-  */
-
-#define I2C1                             ((i2c_type *) I2C1_BASE)
-#define I2C2                             ((i2c_type *) I2C2_BASE)
-#define I2C3                             ((i2c_type *) I2C3_BASE)
-
-/** @defgroup I2C_exported_functions
-  * @{
-  */
-
-void i2c_reset(i2c_type *i2c_x);
-void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
-void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
-void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
-void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
-void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
-void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
-void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
-void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
-void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
-void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
-uint8_t i2c_pec_value_get(i2c_type *i2c_x);
-void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
-void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
-void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
-void i2c_start_generate(i2c_type *i2c_x);
-void i2c_stop_generate(i2c_type *i2c_x);
-void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
-void i2c_data_send(i2c_type *i2c_x, uint8_t data);
-uint8_t i2c_data_receive(i2c_type *i2c_x);
-flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
-void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_misc.h

@@ -1,125 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_misc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 misc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_MISC_H
-#define __AT32F403A_407_MISC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/** @defgroup MISC_vector_table_base_address
-  * @{
-  */
-
-#define NVIC_VECTTAB_RAM                 ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
-#define NVIC_VECTTAB_FLASH               ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_exported_types
-  * @{
-  */
-
-/**
-  * @brief nvic interrupt priority group
-  */
-typedef enum
-{
-  NVIC_PRIORITY_GROUP_0                  = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
-  NVIC_PRIORITY_GROUP_1                  = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
-  NVIC_PRIORITY_GROUP_2                  = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
-  NVIC_PRIORITY_GROUP_3                  = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
-  NVIC_PRIORITY_GROUP_4                  = ((uint32_t)0x3)  /*!< 4 bits for preemption priority, 0 bits for subpriority */
-} nvic_priority_group_type;
-
-/**
-  * @brief nvic low power mode
-  */
-typedef enum
-{
-  NVIC_LP_SLEEPONEXIT                    = 0x02, /*!< send event on pending */
-  NVIC_LP_SLEEPDEEP                      = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
-  NVIC_LP_SEVONPEND                      = 0x10  /*!< enable sleep-on-exit feature */
-} nvic_lowpower_mode_type;
-
-/**
-  * @brief systick clock source
-  */
-typedef enum
-{
-  SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8       = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
-  SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV      = ((uint32_t)0x00000004)  /*!< systick clock source from core clock */
-} systick_clock_source_type;
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_exported_functions
-  * @{
-  */
-
-void nvic_system_reset(void);
-void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
-void nvic_irq_disable(IRQn_Type irqn);
-void nvic_priority_group_config(nvic_priority_group_type priority_group);
-void nvic_vector_table_set(uint32_t base, uint32_t offset);
-void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
-void systick_clock_source_config(systick_clock_source_type source);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_pwc.h

@@ -1,191 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_pwc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 pwc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_PWC_H
-#define __AT32F403A_407_PWC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup PWC
-  * @{
-  */
-
-/** @defgroup PWC_flags_definition
-  * @brief pwc flag
-  * @{
-  */
-
-#define PWC_WAKEUP_FLAG                  ((uint32_t)0x00000001) /*!< wakeup flag */
-#define PWC_STANDBY_FLAG                 ((uint32_t)0x00000002) /*!< standby flag */
-#define PWC_PVM_OUTPUT_FLAG              ((uint32_t)0x00000004) /*!< pvm output flag */
-
-/**
-  * @}
-  */
-
-/**
-  * @brief pwc wakeup pin num definition
-  */
-#define PWC_WAKEUP_PIN_1                 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
-
-/** @defgroup PWC_exported_types
-  * @{
-  */
-
-/**
-  * @brief pwc pvm voltage type
-  */
-typedef enum
-{
-  PWC_PVM_VOLTAGE_2V3                    = 0x01, /*!< power voltage monitoring boundary 2.3v */
-  PWC_PVM_VOLTAGE_2V4                    = 0x02, /*!< power voltage monitoring boundary 2.4v */
-  PWC_PVM_VOLTAGE_2V5                    = 0x03, /*!< power voltage monitoring boundary 2.5v */
-  PWC_PVM_VOLTAGE_2V6                    = 0x04, /*!< power voltage monitoring boundary 2.6v */
-  PWC_PVM_VOLTAGE_2V7                    = 0x05, /*!< power voltage monitoring boundary 2.7v */
-  PWC_PVM_VOLTAGE_2V8                    = 0x06, /*!< power voltage monitoring boundary 2.8v */
-  PWC_PVM_VOLTAGE_2V9                    = 0x07  /*!< power voltage monitoring boundary 2.9v */
-} pwc_pvm_voltage_type;
-
-/**
-  * @brief pwc sleep enter type
-  */
-typedef enum
-{
-  PWC_SLEEP_ENTER_WFI                    = 0x00, /*!< use wfi enter sleep mode */
-  PWC_SLEEP_ENTER_WFE                    = 0x01  /*!< use wfe enter sleep mode */
-} pwc_sleep_enter_type;
-
-/**
-  * @brief pwc deep sleep enter type
-  */
-typedef enum
-{
-  PWC_DEEP_SLEEP_ENTER_WFI               = 0x00, /*!< use wfi enter deepsleep mode */
-  PWC_DEEP_SLEEP_ENTER_WFE               = 0x01  /*!< use wfe enter deepsleep mode */
-} pwc_deep_sleep_enter_type;
-
-/**
-  * @brief pwc regulator type
-  */
-typedef enum
-{
-  PWC_REGULATOR_ON                       = 0x00, /*!< voltage regulator state on when deepsleep mode */
-  PWC_REGULATOR_LOW_POWER                = 0x01  /*!< voltage regulator state low power when deepsleep mode */
-} pwc_regulator_type;
-
-/**
-  * @brief type define pwc register all
-  */
-typedef struct
-{
-  /**
-    * @brief pwc ctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t vrsel                : 1; /* [0] */
-      __IO uint32_t lpsel                : 1; /* [1] */
-      __IO uint32_t clswef               : 1; /* [2] */
-      __IO uint32_t clsef                : 1; /* [3] */
-      __IO uint32_t pvmen                : 1; /* [4] */
-      __IO uint32_t pvmsel               : 3; /* [7:5] */
-      __IO uint32_t bpwen                : 1; /* [8] */
-      __IO uint32_t reserved1            : 23;/* [31:9] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief pwc ctrlsts register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrlsts;
-    struct
-    {
-      __IO uint32_t swef                 : 1; /* [0] */
-      __IO uint32_t sef                  : 1; /* [1] */
-      __IO uint32_t pvmof                : 1; /* [2] */
-      __IO uint32_t reserved1            : 5; /* [7:3] */
-      __IO uint32_t swpen                : 1; /* [8] */
-      __IO uint32_t reserved2            : 23;/* [31:9] */
-    } ctrlsts_bit;
-  };
-
-} pwc_type;
-
-/**
-  * @}
-  */
-
-#define PWC                              ((pwc_type *) PWC_BASE)
-
-/** @defgroup PWC_exported_functions
-  * @{
-  */
-
-void pwc_reset(void);
-void pwc_battery_powered_domain_access(confirm_state new_state);
-void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
-void pwc_power_voltage_monitor_enable(confirm_state new_state);
-void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
-void pwc_flag_clear(uint32_t pwc_flag);
-flag_status pwc_flag_get(uint32_t pwc_flag);
-void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
-void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
-void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
-void pwc_standby_mode_enter(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_rtc.h

@@ -1,261 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_rtc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 rtc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_RTC_H
-#define __AT32F403A_407_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */
-
-/** @defgroup RTC_interrupts_definition
-  * @brief rtc interrupt
-  * @{
-  */
-
-#define RTC_TS_INT                       ((uint16_t)0x0001) /*!< rtc time second interrupt */
-#define RTC_TA_INT                       ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
-#define RTC_OVF_INT                      ((uint16_t)0x0004) /*!< rtc overflow interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_flags_definition
-  * @brief rtc flag
-  * @{
-  */
-
-#define RTC_TS_FLAG                      ((uint16_t)0x0001) /*!< rtc time second flag */
-#define RTC_TA_FLAG                      ((uint16_t)0x0002) /*!< rtc time alarm flag */
-#define RTC_OVF_FLAG                     ((uint16_t)0x0004) /*!< rtc overflow flag */
-#define RTC_UPDF_FLAG                    ((uint16_t)0x0008) /*!< rtc update finish flag */
-#define RTC_CFGF_FLAG                    ((uint16_t)0x0020) /*!< rtc configuration finish flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_exported_types
-  * @{
-  */
-
-/**
-  * @brief type define rtc register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief rtc ctrlh register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrlh;
-    struct
-    {
-      __IO uint32_t tsien                : 1; /* [0] */
-      __IO uint32_t taien                : 1; /* [1] */
-      __IO uint32_t ovfien               : 1; /* [2] */
-      __IO uint32_t reserved1            : 29;/* [31:3] */
-    } ctrlh_bit;
-  };
-
-  /**
-    * @brief rtc ctrll register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrll;
-    struct
-    {
-      __IO uint32_t tsf                  : 1; /* [0] */
-      __IO uint32_t taf                  : 1; /* [1] */
-      __IO uint32_t ovff                 : 1; /* [2] */
-      __IO uint32_t updf                 : 1; /* [3] */
-      __IO uint32_t cfgen                : 1; /* [4] */
-      __IO uint32_t cfgf                 : 1; /* [5] */
-      __IO uint32_t reserved1            : 26;/* [31:6] */
-    } ctrll_bit;
-  };
-
-  /**
-    * @brief rtc divh register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t divh;
-    struct
-    {
-      __IO uint32_t div                  : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 28;/* [31:4] */
-    } divh_bit;
-  };
-
-  /**
-    * @brief rtc divl register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t divl;
-    struct
-    {
-      __IO uint32_t div                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } divl_bit;
-  };
-
-  /**
-    * @brief rtc divcnth register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t divcnth;
-    struct
-    {
-      __IO uint32_t divcnt               : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 28;/* [31:15] */
-    } divcnth_bit;
-  };
-
-  /**
-    * @brief rtc divcntl register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t divcntl;
-    struct
-    {
-      __IO uint32_t divcnt               : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } divcntl_bit;
-  };
-
-  /**
-    * @brief rtc cnth register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t cnth;
-    struct
-    {
-      __IO uint32_t cnt                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } cnth_bit;
-  };
-
-  /**
-    * @brief rtc cntl register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t cntl;
-    struct
-    {
-      __IO uint32_t cnt                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } cntl_bit;
-  };
-
-  /**
-    * @brief rtc tah register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t tah;
-    struct
-    {
-      __IO uint32_t ta                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } tah_bit;
-  };
-
-  /**
-    * @brief rtc tal register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t tal;
-    struct
-    {
-      __IO uint32_t ta                   : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:15] */
-    } tal_bit;
-  };
-
-} rtc_type;
-
-/**
-  * @}
-  */
-
-#define RTC                              ((rtc_type *) RTC_BASE)
-
-/** @defgroup RTC_exported_functions
-  * @{
-  */
-
-void rtc_counter_set(uint32_t counter_value);
-uint32_t rtc_counter_get(void);
-void rtc_divider_set(uint32_t div_value);
-uint32_t rtc_divider_get(void);
-void rtc_alarm_set(uint32_t alarm_value);
-void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
-flag_status rtc_flag_get(uint16_t flag);
-void rtc_flag_clear(uint16_t flag);
-void rtc_wait_config_finish(void);
-void rtc_wait_update_finish(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_sdio.h

@@ -1,624 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_sdio.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 sdio header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_SDIO_H
-#define __AT32F403A_407_SDIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup SDIO
-  * @{
-  */
-
-/** @defgroup SDIO_interrupts_definition
-  * @brief sdio interrupt
-  * @{
-  */
-
-#define SDIO_CMDFAIL_INT                 ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
-#define SDIO_DTFAIL_INT                  ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
-#define SDIO_CMDTIMEOUT_INT              ((uint32_t)0x00000004) /*!< command response timerout interrupt */
-#define SDIO_DTTIMEOUT_INT               ((uint32_t)0x00000008) /*!< data timeout interrupt */
-#define SDIO_TXERRU_INT                  ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
-#define SDIO_RXERRO_INT                  ((uint32_t)0x00000020) /*!< received overrun error interrupt */
-#define SDIO_CMDRSPCMPL_INT              ((uint32_t)0x00000040) /*!< command response received interrupt */
-#define SDIO_CMDCMPL_INT                 ((uint32_t)0x00000080) /*!< command sent interrupt */
-#define SDIO_DTCMP_INT                   ((uint32_t)0x00000100) /*!< data sent interrupt */
-#define SDIO_SBITERR_INT                 ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
-#define SDIO_DTBLKCMPL_INT               ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
-#define SDIO_DOCMD_INT                   ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
-#define SDIO_DOTX_INT                    ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
-#define SDIO_DORX_INT                    ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
-#define SDIO_TXBUFH_INT                  ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
-#define SDIO_RXBUFH_INT                  ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
-#define SDIO_TXBUFF_INT                  ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
-#define SDIO_RXBUFF_INT                  ((uint32_t)0x00020000) /*!< receive buf full interrupt */
-#define SDIO_TXBUFE_INT                  ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
-#define SDIO_RXBUFE_INT                  ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
-#define SDIO_TXBUF_INT                   ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
-#define SDIO_RXBUF_INT                   ((uint32_t)0x00200000) /*!< data available in receive interrupt */
-#define SDIO_SDIOIF_INT                  ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_flags_definition
-  * @brief sdio flag
-  * @{
-  */
-
-#define SDIO_CMDFAIL_FLAG                ((uint32_t)0x00000001) /*!< command response received check failed flag */
-#define SDIO_DTFAIL_FLAG                 ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
-#define SDIO_CMDTIMEOUT_FLAG             ((uint32_t)0x00000004) /*!< command response timerout flag */
-#define SDIO_DTTIMEOUT_FLAG              ((uint32_t)0x00000008) /*!< data timeout flag */
-#define SDIO_TXERRU_FLAG                 ((uint32_t)0x00000010) /*!< transmit underrun error flag */
-#define SDIO_RXERRO_FLAG                 ((uint32_t)0x00000020) /*!< received overrun error flag */
-#define SDIO_CMDRSPCMPL_FLAG             ((uint32_t)0x00000040) /*!< command response received flag */
-#define SDIO_CMDCMPL_FLAG                ((uint32_t)0x00000080) /*!< command sent flag */
-#define SDIO_DTCMPL_FLAG                 ((uint32_t)0x00000100) /*!< data sent flag */
-#define SDIO_SBITERR_FLAG                ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
-#define SDIO_DTBLKCMPL_FLAG              ((uint32_t)0x00000400) /*!< data block sent/received flag */
-#define SDIO_DOCMD_FLAG                  ((uint32_t)0x00000800) /*!< command transfer in progress flag */
-#define SDIO_DOTX_FLAG                   ((uint32_t)0x00001000) /*!< data transmit in progress flag */
-#define SDIO_DORX_FLAG                   ((uint32_t)0x00002000) /*!< data receive in progress flag */
-#define SDIO_TXBUFH_FLAG                 ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
-#define SDIO_RXBUFH_FLAG                 ((uint32_t)0x00008000) /*!< receive buf half full flag */
-#define SDIO_TXBUFF_FLAG                 ((uint32_t)0x00010000) /*!< transmit buf full flag */
-#define SDIO_RXBUFF_FLAG                 ((uint32_t)0x00020000) /*!< receive buf full flag */
-#define SDIO_TXBUFE_FLAG                 ((uint32_t)0x00040000) /*!< transmit buf empty flag */
-#define SDIO_RXBUFE_FLAG                 ((uint32_t)0x00080000) /*!< receive buf empty flag */
-#define SDIO_TXBUF_FLAG                  ((uint32_t)0x00100000) /*!< data available in transmit flag */
-#define SDIO_RXBUF_FLAG                  ((uint32_t)0x00200000) /*!< data available in receive flag */
-#define SDIO_SDIOIF_FLAG                 ((uint32_t)0x00400000) /*!< sdio interface received flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_exported_types
-  * @{
-  */
-
-/**
-  * @brief sdio power state
-  */
-typedef enum
-{
-  SDIO_POWER_OFF                         = 0x00, /*!< power-off, clock to card is stopped */
-  SDIO_POWER_ON                          = 0x03  /*!< power-on, the card is clocked */
-} sdio_power_state_type;
-
-/**
-  * @brief sdio edge phase
-  */
-typedef enum
-{
-  SDIO_CLOCK_EDGE_RISING                 = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
-  SDIO_CLOCK_EDGE_FALLING                = 0x01  /*!< sdio bus clock generated on the falling edge of the master clock */
-} sdio_edge_phase_type;
-
-/**
-  * @brief sdio bus width
-  */
-typedef enum
-{
-  SDIO_BUS_WIDTH_D1                      = 0x00, /*!< sdio wide bus select 1-bit */
-  SDIO_BUS_WIDTH_D4                      = 0x01, /*!< sdio wide bus select 4-bit */
-  SDIO_BUS_WIDTH_D8                      = 0x02  /*!< sdio wide bus select 8-bit */
-} sdio_bus_width_type;
-
-/**
-  * @brief sdio response type
-  */
-typedef enum
-{
-  SDIO_RESPONSE_NO                       = 0x00, /*!< no response */
-  SDIO_RESPONSE_SHORT                    = 0x01, /*!< short response */
-  SDIO_RESPONSE_LONG                     = 0x03  /*!< long response */
-} sdio_reponse_type;
-
-/**
-  * @brief sdio wait type
-  */
-typedef enum
-{
-  SDIO_WAIT_FOR_NO                       = 0x00, /*!< no wait */
-  SDIO_WAIT_FOR_INT                      = 0x01, /*!< wait interrupt request */
-  SDIO_WAIT_FOR_PEND                     = 0x02  /*!< wait end of transfer */
-} sdio_wait_type;
-
-/**
-  * @brief sdio response register index
-  */
-typedef enum
-{
-  SDIO_RSP1_INDEX                        = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
-  SDIO_RSP2_INDEX                        = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
-  SDIO_RSP3_INDEX                        = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
-  SDIO_RSP4_INDEX                        = 0x03  /*!< response index 4, corresponding to sdio_rsp register 4 */
-} sdio_rsp_index_type;
-
-/**
-  * @brief sdio data block size
-  */
-typedef enum
-{
-  SDIO_DATA_BLOCK_SIZE_1B                = 0x00, /*!< data block size 1 byte */
-  SDIO_DATA_BLOCK_SIZE_2B                = 0x01, /*!< data block size 2 bytes */
-  SDIO_DATA_BLOCK_SIZE_4B                = 0x02, /*!< data block size 4 bytes */
-  SDIO_DATA_BLOCK_SIZE_8B                = 0x03, /*!< data block size 8 bytes */
-  SDIO_DATA_BLOCK_SIZE_16B               = 0x04, /*!< data block size 16 bytes */
-  SDIO_DATA_BLOCK_SIZE_32B               = 0x05, /*!< data block size 32 bytes */
-  SDIO_DATA_BLOCK_SIZE_64B               = 0x06, /*!< data block size 64 bytes */
-  SDIO_DATA_BLOCK_SIZE_128B              = 0x07, /*!< data block size 128 bytes */
-  SDIO_DATA_BLOCK_SIZE_256B              = 0x08, /*!< data block size 256 bytes */
-  SDIO_DATA_BLOCK_SIZE_512B              = 0x09, /*!< data block size 512 bytes */
-  SDIO_DATA_BLOCK_SIZE_1024B             = 0x0A, /*!< data block size 1024 bytes */
-  SDIO_DATA_BLOCK_SIZE_2048B             = 0x0B, /*!< data block size 2048 bytes */
-  SDIO_DATA_BLOCK_SIZE_4096B             = 0x0C, /*!< data block size 4096 bytes */
-  SDIO_DATA_BLOCK_SIZE_8192B             = 0x0D, /*!< data block size 8192 bytes */
-  SDIO_DATA_BLOCK_SIZE_16384B            = 0x0E  /*!< data block size 16384 bytes */
-} sdio_block_size_type;
-
-/**
-  * @brief sdio data transfer mode
-  */
-typedef enum
-{
-  SDIO_DATA_BLOCK_TRANSFER               = 0x00, /*!< the sdio block transfer mode */
-  SDIO_DATA_STREAM_TRANSFER              = 0x01  /*!< the sdio stream transfer mode */
-} sdio_transfer_mode_type;
-
-/**
-  * @brief sdio data transfer direction
-  */
-typedef enum
-{
-  SDIO_DATA_TRANSFER_TO_CARD             = 0x00, /*!< the sdio controller write */
-  SDIO_DATA_TRANSFER_TO_CONTROLLER       = 0x01  /*!< the sdio controller read */
-} sdio_transfer_direction_type;
-
-/**
-  * @brief sdio read wait mode
-  */
-typedef enum
-{
-  SDIO_READ_WAIT_CONTROLLED_BY_D2        = 0x00, /*!< the sdio read wait on data2 line */
-  SDIO_READ_WAIT_CONTROLLED_BY_CK        = 0x01  /*!< the sdio read wait on clock line */
-} sdio_read_wait_mode_type;
-
-/**
-  * @brief sdio command structure
-  */
-typedef struct
-{
-  uint32_t                               argument;  /*!< the sdio command argument is sent to a card as part of command message */
-  uint8_t                                cmd_index; /*!< the sdio command index */
-  sdio_reponse_type                      rsp_type;  /*!< the sdio response type */
-  sdio_wait_type                         wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
-} sdio_command_struct_type;
-
-/**
-  * @brief sdio data structure
-  */
-typedef struct
-{
-  uint32_t                               timeout;            /*!< the sdio data timeout period in car bus clock periods */
-  uint32_t                               data_length;        /*!< the sdio data length */
-  sdio_block_size_type                   block_size;         /*!< the sdio data block size of block transfer mode */
-  sdio_transfer_mode_type                transfer_mode;      /*!< the sdio transfer mode, block or stream */
-  sdio_transfer_direction_type           transfer_direction; /*!< the sdio data transfer direction */
-} sdio_data_struct_type;
-
-/**
-  * @brief type define sdio register all
-  */
-typedef struct
-{
-  /**
-    * @brief sdio pwrctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t pwrctrl;
-    struct
-    {
-      __IO uint32_t ps                   : 2; /* [1:0] */
-      __IO uint32_t reserved1            : 30;/* [31:2] */
-    } pwrctrl_bit;
-  };
-
-  /**
-    * @brief sdio clkctrl register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t clkctrl;
-    struct
-    {
-      __IO uint32_t clkdiv_l             : 8; /* [7:0] */
-      __IO uint32_t clkoen               : 1; /* [8] */
-      __IO uint32_t pwrsven              : 1; /* [9] */
-      __IO uint32_t bypsen               : 1; /* [10] */
-      __IO uint32_t busws                : 2; /* [12:11] */
-      __IO uint32_t clkegs               : 1; /* [13] */
-      __IO uint32_t hfcen                : 1; /* [14] */
-      __IO uint32_t clkdiv_h             : 2; /* [16:15] */
-      __IO uint32_t reserved1            : 15;/* [31:17] */
-    } clkctrl_bit;
-  };
-
-  /**
-    * @brief sdio argu register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t argu;
-    struct
-    {
-      __IO uint32_t argu                 : 32;/* [31:0] */
-    } argu_bit;
-  };
-
-  /**
-    * @brief sdio cmdctrl register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t cmdctrl;
-    struct
-    {
-      __IO uint32_t cmdidx               : 6; /* [5:0] */
-      __IO uint32_t rspwt                : 2; /* [7:6] */
-      __IO uint32_t intwt                : 1; /* [8] */
-      __IO uint32_t pndwt                : 1; /* [9] */
-      __IO uint32_t ccsmen               : 1; /* [10] */
-      __IO uint32_t iosusp               : 1; /* [11] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } cmdctrl_bit;
-  };
-
-  /**
-    * @brief sdio rspcmd register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t rspcmd;
-    struct
-    {
-      __IO uint32_t rspcmd               : 6; /* [5:0] */
-      __IO uint32_t reserved1            : 26;/* [31:6] */
-    } rspcmd_bit;
-  };
-
-  /**
-    * @brief sdio rsp1 register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t rsp1;
-    struct
-    {
-      __IO uint32_t cardsts1             : 32;/* [31:0] */
-    } rsp1_bit;
-  };
-
-  /**
-    * @brief sdio rsp2 register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t rsp2;
-    struct
-    {
-      __IO uint32_t cardsts2             : 32;/* [31:0] */
-    } rsp2_bit;
-  };
-
-  /**
-    * @brief sdio rsp3 register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t rsp3;
-    struct
-    {
-      __IO uint32_t cardsts3             : 32;/* [31:0] */
-    } rsp3_bit;
-  };
-
-  /**
-    * @brief sdio rsp4 register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t rsp4;
-    struct
-    {
-      __IO uint32_t cardsts4             : 32;/* [31:0] */
-    } rsp4_bit;
-  };
-
-  /**
-    * @brief sdio dttmr register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t dttmr;
-    struct
-    {
-      __IO uint32_t timeout              : 32;/* [31:0] */
-    } dttmr_bit;
-  };
-
-  /**
-    * @brief sdio dtlen register, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t dtlen;
-    struct
-    {
-      __IO uint32_t dtlen                : 25;/* [24:0] */
-      __IO uint32_t reserved1            : 7; /* [31:25] */
-    } dtlen_bit;
-  };
-
-  /**
-    * @brief sdio dtctrl register, offset:0x2C
-    */
-  union
-  {
-    __IO uint32_t dtctrl;
-    struct
-    {
-      __IO uint32_t tfren                : 1; /* [0] */
-      __IO uint32_t tfrdir               : 1; /* [1] */
-      __IO uint32_t tfrmode              : 1; /* [2] */
-      __IO uint32_t dmaen                : 1; /* [3] */
-      __IO uint32_t blksize              : 4; /* [7:4] */
-      __IO uint32_t rdwtstart            : 1; /* [8] */
-      __IO uint32_t rdwtstop             : 1; /* [9] */
-      __IO uint32_t rdwtmode             : 1; /* [10] */
-      __IO uint32_t ioen                 : 1; /* [11] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } dtctrl_bit;
-  };
-
-  /**
-    * @brief sdio dtcnt register, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t dtcnt;
-    struct
-    {
-      __IO uint32_t cnt                  : 25;/* [24:0] */
-      __IO uint32_t reserved1            : 7; /* [31:25] */
-    } dtcnt_bit;
-  };
-
-  /**
-    * @brief sdio sts register, offset:0x34
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t cmdfail              : 1; /* [0] */
-      __IO uint32_t dtfail               : 1; /* [1] */
-      __IO uint32_t cmdtimeout           : 1; /* [2] */
-      __IO uint32_t dttimeout            : 1; /* [3] */
-      __IO uint32_t txerru               : 1; /* [4] */
-      __IO uint32_t rxerro               : 1; /* [5] */
-      __IO uint32_t cmdrspcmpl           : 1; /* [6] */
-      __IO uint32_t cmdcmpl              : 1; /* [7] */
-      __IO uint32_t dtcmpl               : 1; /* [8] */
-      __IO uint32_t sbiterr              : 1; /* [9] */
-      __IO uint32_t dtblkcmpl            : 1; /* [10] */
-      __IO uint32_t docmd                : 1; /* [11] */
-      __IO uint32_t dotx                 : 1; /* [12] */
-      __IO uint32_t dorx                 : 1; /* [13] */
-      __IO uint32_t txbufh               : 1; /* [14] */
-      __IO uint32_t rxbufh               : 1; /* [15] */
-      __IO uint32_t txbuff               : 1; /* [16] */
-      __IO uint32_t rxbuff               : 1; /* [17] */
-      __IO uint32_t txbufe               : 1; /* [18] */
-      __IO uint32_t rxbufe               : 1; /* [19] */
-      __IO uint32_t txbuf                : 1; /* [20] */
-      __IO uint32_t rxbuf                : 1; /* [21] */
-      __IO uint32_t ioif                 : 1; /* [22] */
-      __IO uint32_t reserved1            : 9; /* [31:23] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief sdio intclr register, offset:0x38
-    */
-  union
-  {
-    __IO uint32_t intclr;
-    struct
-    {
-      __IO uint32_t cmdfail              : 1; /* [0] */
-      __IO uint32_t dtfail               : 1; /* [1] */
-      __IO uint32_t cmdtimeout           : 1; /* [2] */
-      __IO uint32_t dttimeout            : 1; /* [3] */
-      __IO uint32_t txerru               : 1; /* [4] */
-      __IO uint32_t rxerro               : 1; /* [5] */
-      __IO uint32_t cmdrspcmpl           : 1; /* [6] */
-      __IO uint32_t cmdcmpl              : 1; /* [7] */
-      __IO uint32_t dtcmpl               : 1; /* [8] */
-      __IO uint32_t sbiterr              : 1; /* [9] */
-      __IO uint32_t dtblkcmpl            : 1; /* [10] */
-      __IO uint32_t reserved1            : 11;/* [21:11] */
-      __IO uint32_t ioif                 : 1; /* [22] */
-      __IO uint32_t reserved2            : 9; /* [31:23] */
-    } intclr_bit;
-  };
-
-  /**
-    * @brief sdio inten register, offset:0x3C
-    */
-  union
-  {
-    __IO uint32_t inten;
-    struct
-    {
-      __IO uint32_t cmdfailien           : 1; /* [0] */
-      __IO uint32_t dtfailien            : 1; /* [1] */
-      __IO uint32_t cmdtimeoutien        : 1; /* [2] */
-      __IO uint32_t dttimeoutien         : 1; /* [3] */
-      __IO uint32_t txerruien            : 1; /* [4] */
-      __IO uint32_t rxerroien            : 1; /* [5] */
-      __IO uint32_t cmdrspcmplien        : 1; /* [6] */
-      __IO uint32_t cmdcmplien           : 1; /* [7] */
-      __IO uint32_t dtcmplien            : 1; /* [8] */
-      __IO uint32_t sbiterrien           : 1; /* [9] */
-      __IO uint32_t dtblkcmplien         : 1; /* [10] */
-      __IO uint32_t docmdien             : 1; /* [11] */
-      __IO uint32_t dotxien              : 1; /* [12] */
-      __IO uint32_t dorxien              : 1; /* [13] */
-      __IO uint32_t txbufhien            : 1; /* [14] */
-      __IO uint32_t rxbufhien            : 1; /* [15] */
-      __IO uint32_t txbuffien            : 1; /* [16] */
-      __IO uint32_t rxbuffien            : 1; /* [17] */
-      __IO uint32_t txbufeien            : 1; /* [18] */
-      __IO uint32_t rxbufeien            : 1; /* [19] */
-      __IO uint32_t txbufien             : 1; /* [20] */
-      __IO uint32_t rxbufien             : 1; /* [21] */
-      __IO uint32_t ioifien              : 1; /* [22] */
-      __IO uint32_t reserved1            : 9; /* [31:23] */
-    } inten_bit;
-  };
-
-  /**
-    * @brief sdio reserved1 register, offset:0x40~0x44
-    */
-  __IO uint32_t reserved1[2];
-
-  /**
-    * @brief sdio bufcnt register, offset:0x48
-    */
-  union
-  {
-    __IO uint32_t bufcnt;
-    struct
-    {
-      __IO uint32_t cnt                  : 24;/* [23:0] */
-      __IO uint32_t reserved1            : 8; /* [31:24] */
-    } bufcnt_bit;
-  };
-
-  /**
-    * @brief sdio reserved2 register, offset:0x4C~0x7C
-    */
-  __IO uint32_t reserved2[13];
-
-  /**
-    * @brief sdio buf register, offset:0x80
-    */
-  union
-  {
-    __IO uint32_t buf;
-    struct
-    {
-      __IO uint32_t dt                   : 32;/* [31:0] */
-    } buf_bit;
-  };
-
-} sdio_type;
-
-/**
-  * @}
-  */
-
-#define SDIO1                            ((sdio_type *) SDIO1_BASE)
-#define SDIO2                            ((sdio_type *) SDIO2_BASE)
-
-/** @defgroup SDIO_exported_functions
-  * @{
-  */
-
-void sdio_reset(sdio_type *sdio_x);
-void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
-flag_status sdio_power_status_get(sdio_type *sdio_x);
-void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
-void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
-void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
-void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
-void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
-void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
-void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
-void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt,  confirm_state new_state);
-flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
-void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
-void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
-void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
-uint8_t sdio_command_response_get(sdio_type *sdio_x);
-uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
-void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
-void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
-uint32_t sdio_data_counter_get(sdio_type *sdio_x);
-uint32_t sdio_data_read(sdio_type *sdio_x);
-uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
-void sdio_data_write(sdio_type *sdio_x, uint32_t data);
-void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
-void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
-void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
-void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
-void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_spi.h

@@ -1,499 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_spi.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 spi header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_SPI_H
-#define __AT32F403A_407_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/**
-  * @defgroup SPI_I2S_flags_definition
-  * @brief spi i2s flag
-  * @{
-  */
-
-#define SPI_I2S_RDBF_FLAG                0x0001 /*!< spi or i2s receive data buffer full flag */
-#define SPI_I2S_TDBE_FLAG                0x0002 /*!< spi or i2s transmit data buffer empty flag */
-#define I2S_ACS_FLAG                     0x0004 /*!< i2s audio channel state flag */
-#define I2S_TUERR_FLAG                   0x0008 /*!< i2s transmitter underload error flag */
-#define SPI_CCERR_FLAG                   0x0010 /*!< spi crc calculation error flag */
-#define SPI_MMERR_FLAG                   0x0020 /*!< spi master mode error flag */
-#define SPI_I2S_ROERR_FLAG               0x0040 /*!< spi or i2s receiver overflow error flag */
-#define SPI_I2S_BF_FLAG                  0x0080 /*!< spi or i2s busy flag */
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup SPI_I2S_interrupts_definition
-  * @brief spi i2s interrupt
-  * @{
-  */
-
-#define SPI_I2S_ERROR_INT                0x0020 /*!< error interrupt */
-#define SPI_I2S_RDBF_INT                 0x0040 /*!< receive data buffer full interrupt */
-#define SPI_I2S_TDBE_INT                 0x0080 /*!< transmit data buffer empty interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_exported_types
-  * @{
-  */
-
-/**
-  * @brief spi frame bit num type
-  */
-typedef enum
-{
-  SPI_FRAME_8BIT                         = 0x00, /*!< 8-bit data frame format */
-  SPI_FRAME_16BIT                        = 0x01  /*!< 16-bit data frame format */
-} spi_frame_bit_num_type;
-
-/**
-  * @brief spi master/slave mode type
-  */
-typedef enum
-{
-  SPI_MODE_SLAVE                         = 0x00, /*!< select as slave mode */
-  SPI_MODE_MASTER                        = 0x01  /*!< select as master mode */
-} spi_master_slave_mode_type;
-
-/**
-  * @brief spi clock polarity (clkpol) type
-  */
-typedef enum
-{
-  SPI_CLOCK_POLARITY_LOW                 = 0x00, /*!< sck keeps low at idle state */
-  SPI_CLOCK_POLARITY_HIGH                = 0x01  /*!< sck keeps high at idle state */
-} spi_clock_polarity_type;
-
-/**
-  * @brief spi clock phase (clkpha) type
-  */
-typedef enum
-{
-  SPI_CLOCK_PHASE_1EDGE                  = 0x00, /*!< data capture start from the first clock edge */
-  SPI_CLOCK_PHASE_2EDGE                  = 0x01  /*!< data capture start from the second clock edge */
-} spi_clock_phase_type;
-
-/**
-  * @brief spi cs mode type
-  */
-typedef enum
-{
-  SPI_CS_HARDWARE_MODE                   = 0x00, /*!< cs is hardware mode */
-  SPI_CS_SOFTWARE_MODE                   = 0x01  /*!< cs is software mode */
-} spi_cs_mode_type;
-
-/**
-  * @brief spi master clock frequency division type
-  */
-typedef enum
-{
-  SPI_MCLK_DIV_2                        = 0x00, /*!< master clock frequency division 2 */
-  SPI_MCLK_DIV_4                        = 0x01, /*!< master clock frequency division 4 */
-  SPI_MCLK_DIV_8                        = 0x02, /*!< master clock frequency division 8 */
-  SPI_MCLK_DIV_16                       = 0x03, /*!< master clock frequency division 16 */
-  SPI_MCLK_DIV_32                       = 0x04, /*!< master clock frequency division 32 */
-  SPI_MCLK_DIV_64                       = 0x05, /*!< master clock frequency division 64 */
-  SPI_MCLK_DIV_128                      = 0x06, /*!< master clock frequency division 128 */
-  SPI_MCLK_DIV_256                      = 0x07, /*!< master clock frequency division 256 */
-  SPI_MCLK_DIV_512                      = 0x08, /*!< master clock frequency division 512 */
-  SPI_MCLK_DIV_1024                     = 0x09  /*!< master clock frequency division 1024 */
-} spi_mclk_freq_div_type;
-
-/**
-  * @brief spi transmit first bit (lsb/msb) type
-  */
-typedef enum
-{
-  SPI_FIRST_BIT_MSB                      = 0x00, /*!< the frame format is msb first */
-  SPI_FIRST_BIT_LSB                      = 0x01  /*!< the frame format is lsb first */
-} spi_first_bit_type;
-
-/**
-  * @brief spi transmission mode type
-  */
-typedef enum
-{
-  SPI_TRANSMIT_FULL_DUPLEX               = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
-  SPI_TRANSMIT_SIMPLEX_RX                = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
-  SPI_TRANSMIT_HALF_DUPLEX_RX            = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
-  SPI_TRANSMIT_HALF_DUPLEX_TX            = 0x03  /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
-} spi_transmission_mode_type;
-
-/**
-  * @brief spi crc direction type
-  */
-typedef enum
-{
-  SPI_CRC_RX                             = 0x0014, /*!< crc direction is rx */
-  SPI_CRC_TX                             = 0x0018  /*!< crc direction is tx */
-} spi_crc_direction_type;
-
-/**
-  * @brief spi single line bidirectional direction type
-  */
-typedef enum
-{
-  SPI_HALF_DUPLEX_DIRECTION_RX           = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
-  SPI_HALF_DUPLEX_DIRECTION_TX           = 0x01  /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
-} spi_half_duplex_direction_type;
-
-/**
-  * @brief spi software cs internal level type
-  */
-typedef enum
-{
-  SPI_SWCS_INTERNAL_LEVEL_LOW            = 0x00, /*!< internal level low */
-  SPI_SWCS_INTERNAL_LEVEL_HIGHT          = 0x01  /*!< internal level high */
-} spi_software_cs_level_type;
-
-/**
-  * @brief i2s audio protocol type
-  */
-typedef enum
-{
-  I2S_AUDIO_PROTOCOL_PHILLIPS            = 0x00, /*!< i2s philip standard */
-  I2S_AUDIO_PROTOCOL_MSB                 = 0x01, /*!< msb-justified standard */
-  I2S_AUDIO_PROTOCOL_LSB                 = 0x02, /*!< lsb-justified standard */
-  I2S_AUDIO_PROTOCOL_PCM_SHORT           = 0x03, /*!< pcm standard-short frame */
-  I2S_AUDIO_PROTOCOL_PCM_LONG            = 0x04  /*!< pcm standard-long frame */
-} i2s_audio_protocol_type;
-
-/**
-  * @brief i2s audio frequency type
-  */
-typedef enum
-{
-  I2S_AUDIO_FREQUENCY_DEFAULT            = 2,     /*!< i2s audio sampling frequency default */
-  I2S_AUDIO_FREQUENCY_8K                 = 8000,  /*!< i2s audio sampling frequency 8k */
-  I2S_AUDIO_FREQUENCY_11_025K            = 11025, /*!< i2s audio sampling frequency 11.025k */
-  I2S_AUDIO_FREQUENCY_16K                = 16000, /*!< i2s audio sampling frequency 16k */
-  I2S_AUDIO_FREQUENCY_22_05K             = 22050, /*!< i2s audio sampling frequency 22.05k */
-  I2S_AUDIO_FREQUENCY_32K                = 32000, /*!< i2s audio sampling frequency 32k */
-  I2S_AUDIO_FREQUENCY_44_1K              = 44100, /*!< i2s audio sampling frequency 44.1k */
-  I2S_AUDIO_FREQUENCY_48K                = 48000, /*!< i2s audio sampling frequency 48k */
-  I2S_AUDIO_FREQUENCY_96K                = 96000, /*!< i2s audio sampling frequency 96k */
-  I2S_AUDIO_FREQUENCY_192K               = 192000 /*!< i2s audio sampling frequency 192k */
-} i2s_audio_sampling_freq_type;
-
-/**
-  * @brief i2s data bit num and channel bit num type
-  */
-typedef enum
-{
-  I2S_DATA_16BIT_CHANNEL_16BIT           = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
-  I2S_DATA_16BIT_CHANNEL_32BIT           = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
-  I2S_DATA_24BIT_CHANNEL_32BIT           = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
-  I2S_DATA_32BIT_CHANNEL_32BIT           = 0x04  /*!< 32-bit data packed in 32-bit channel frame */
-} i2s_data_channel_format_type;
-
-/**
-  * @brief i2s operation mode type
-  */
-typedef enum
-{
-  I2S_MODE_SLAVE_TX                      = 0x00, /*!< slave transmission mode */
-  I2S_MODE_SLAVE_RX                      = 0x01, /*!< slave reception mode */
-  I2S_MODE_MASTER_TX                     = 0x02, /*!< master transmission mode */
-  I2S_MODE_MASTER_RX                     = 0x03  /*!< master reception mode */
-} i2s_operation_mode_type;
-
-/**
-  * @brief i2s clock polarity type
-  */
-typedef enum
-{
-  I2S_CLOCK_POLARITY_LOW                 = 0x00, /*!< i2s clock steady state is low level */
-  I2S_CLOCK_POLARITY_HIGH                = 0x01  /*!< i2s clock steady state is high level */
-} i2s_clock_polarity_type;
-
-/**
-  * @brief spi init type
-  */
-typedef struct
-{
-  spi_transmission_mode_type             transmission_mode;     /*!< transmission mode selection */
-  spi_master_slave_mode_type             master_slave_mode;     /*!< master or slave mode selection */
-  spi_mclk_freq_div_type                 mclk_freq_division;    /*!< master clock frequency division selection */
-  spi_first_bit_type                     first_bit_transmission;/*!< transmit lsb or msb selection */
-  spi_frame_bit_num_type                 frame_bit_num;         /*!< frame bit num 8 or 16 bit selection */
-  spi_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
-  spi_clock_phase_type                   clock_phase;           /*!< clock phase selection */
-  spi_cs_mode_type                       cs_mode_selection;     /*!< hardware or software cs mode selection */
-} spi_init_type;
-
-/**
-  * @brief i2s init type
-  */
-typedef struct
-{
-  i2s_operation_mode_type                operation_mode;        /*!< operation mode selection */
-  i2s_audio_protocol_type                audio_protocol;        /*!< audio protocol selection */
-  i2s_audio_sampling_freq_type           audio_sampling_freq;   /*!< audio frequency selection */
-  i2s_data_channel_format_type           data_channel_format;   /*!< data bit num and channel bit num selection */
-  i2s_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
-  confirm_state                          mclk_output_enable;    /*!< mclk_output selection */
-} i2s_init_type;
-
-/**
-  * @brief type define spi register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief spi ctrl1 register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t clkpha               : 1; /* [0] */
-      __IO uint32_t clkpol               : 1; /* [1] */
-      __IO uint32_t msten                : 1; /* [2] */
-      __IO uint32_t mdiv_l               : 3; /* [5:3] */
-      __IO uint32_t spien                : 1; /* [6] */
-      __IO uint32_t ltf                  : 1; /* [7] */
-      __IO uint32_t swcsil               : 1; /* [8] */
-      __IO uint32_t swcsen               : 1; /* [9] */
-      __IO uint32_t ora                  : 1; /* [10] */
-      __IO uint32_t fbn                  : 1; /* [11] */
-      __IO uint32_t ntc                  : 1; /* [12] */
-      __IO uint32_t ccen                 : 1; /* [13] */
-      __IO uint32_t slbtd                : 1; /* [14] */
-      __IO uint32_t slben                : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } ctrl1_bit;
-  };
-
-  /**
-    * @brief spi ctrl2 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t dmaren               : 1; /* [0] */
-      __IO uint32_t dmaten               : 1; /* [1] */
-      __IO uint32_t hwcsoe               : 1; /* [2] */
-      __IO uint32_t reserved1            : 2; /* [4:3] */
-      __IO uint32_t errie                : 1; /* [5] */
-      __IO uint32_t rdbfie               : 1; /* [6] */
-      __IO uint32_t tdbeie               : 1; /* [7] */
-      __IO uint32_t mdiv_h               : 1; /* [8] */
-      __IO uint32_t reserved2            : 23;/* [31:9] */
-    } ctrl2_bit;
-  };
-
-  /**
-    * @brief spi sts register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t rdbf                 : 1; /* [0] */
-      __IO uint32_t tdbe                 : 1; /* [1] */
-      __IO uint32_t acs                  : 1; /* [2] */
-      __IO uint32_t tuerr                : 1; /* [3] */
-      __IO uint32_t ccerr                : 1; /* [4] */
-      __IO uint32_t mmerr                : 1; /* [5] */
-      __IO uint32_t roerr                : 1; /* [6] */
-      __IO uint32_t bf                   : 1; /* [7] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief spi dt register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t dt;
-    struct
-    {
-      __IO uint32_t dt                  : 16;/* [15:0] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } dt_bit;
-  };
-
-  /**
-    * @brief spi cpoly register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t cpoly;
-    struct
-    {
-      __IO uint32_t cpoly               : 16;/* [15:0] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } cpoly_bit;
-  };
-
-  /**
-    * @brief spi rcrc register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t rcrc;
-    struct
-    {
-      __IO uint32_t rcrc                : 16;/* [15:0] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } rcrc_bit;
-  };
-
-  /**
-    * @brief spi tcrc register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t tcrc;
-    struct
-    {
-      __IO uint32_t tcrc                : 16;/* [15:0] */
-      __IO uint32_t reserved1           : 16;/* [31:16] */
-    } tcrc_bit;
-  };
-
-  /**
-    * @brief spi i2sctrl register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t i2sctrl;
-    struct
-    {
-      __IO uint32_t i2scbn              : 1; /* [0] */
-      __IO uint32_t i2sdbn              : 2; /* [2:1] */
-      __IO uint32_t i2sclkpol           : 1; /* [3] */
-      __IO uint32_t stdsel              : 2; /* [5:4] */
-      __IO uint32_t reserved1           : 1; /* [6] */
-      __IO uint32_t pcmfssel            : 1; /* [7] */
-      __IO uint32_t opersel             : 2; /* [9:8] */
-      __IO uint32_t i2sen               : 1; /* [10] */
-      __IO uint32_t i2smsel             : 1; /* [11] */
-      __IO uint32_t reserved2           : 20;/* [31:12] */
-    } i2sctrl_bit;
-  };
-
-  /**
-    * @brief spi i2sclk register, offset:0x20
-    */
-  union
-  {
-    __IO uint32_t i2sclk;
-    struct
-    {
-      __IO uint32_t i2sdiv_l            : 8; /* [7:0] */
-      __IO uint32_t i2sodd              : 1; /* [8] */
-      __IO uint32_t i2smclkoe           : 1; /* [9] */
-      __IO uint32_t i2sdiv_h            : 2; /* [11:10] */
-      __IO uint32_t reserved1           : 20;/* [31:12] */
-    } i2sclk_bit;
-  };
-
-} spi_type;
-
-/**
-  * @}
-  */
-
-#define SPI1                            ((spi_type *) SPI1_BASE)
-#define SPI2                            ((spi_type *) SPI2_BASE)
-#define SPI3                            ((spi_type *) SPI3_BASE)
-#define SPI4                            ((spi_type *) SPI4_BASE)
-#define I2S2EXT                         ((spi_type *) I2S2EXT_BASE)
-#define I2S3EXT                         ((spi_type *) I2S3EXT_BASE)
-
-/** @defgroup SPI_exported_functions
-  * @{
-  */
-
-void spi_i2s_reset(spi_type *spi_x);
-void spi_default_para_init(spi_init_type* spi_init_struct);
-void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
-void spi_crc_next_transmit(spi_type* spi_x);
-void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
-uint16_t spi_crc_polynomial_get(spi_type* spi_x);
-void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
-uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
-void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
-void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
-void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
-void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
-void spi_enable(spi_type* spi_x, confirm_state new_state);
-void i2s_default_para_init(i2s_init_type* i2s_init_struct);
-void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
-void i2s_enable(spi_type* spi_x, confirm_state new_state);
-void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
-void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
-void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
-void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
-uint16_t spi_i2s_data_receive(spi_type* spi_x);
-flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
-void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_tmr.h

@@ -1,941 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_tmr.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 tmr header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_TMR_H
-#define __AT32F403A_407_TMR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup TMR
-  * @{
-  */
-
-/** @defgroup TMR_flags_definition
-  * @brief tmr flag
-  * @{
-  */
-
-#define TMR_OVF_FLAG                     ((uint32_t)0x000001) /*!< tmr flag overflow */
-#define TMR_C1_FLAG                      ((uint32_t)0x000002) /*!< tmr flag channel 1 */
-#define TMR_C2_FLAG                      ((uint32_t)0x000004) /*!< tmr flag channel 2 */
-#define TMR_C3_FLAG                      ((uint32_t)0x000008) /*!< tmr flag channel 3 */
-#define TMR_C4_FLAG                      ((uint32_t)0x000010) /*!< tmr flag channel 4 */
-#define TMR_HALL_FLAG                    ((uint32_t)0x000020) /*!< tmr flag hall */
-#define TMR_TRIGGER_FLAG                 ((uint32_t)0x000040) /*!< tmr flag trigger */
-#define TMR_BRK_FLAG                     ((uint32_t)0x000080) /*!< tmr flag brake */
-#define TMR_C1_RECAPTURE_FLAG            ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
-#define TMR_C2_RECAPTURE_FLAG            ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
-#define TMR_C3_RECAPTURE_FLAG            ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
-#define TMR_C4_RECAPTURE_FLAG            ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
-
-/**
-  * @}
-  */
-
-/** @defgroup TMR_interrupt_select_type_definition
-  * @brief tmr interrupt select type
-  * @{
-  */
-
-#define TMR_OVF_INT                      ((uint32_t)0x000001) /*!< tmr interrupt overflow */
-#define TMR_C1_INT                       ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
-#define TMR_C2_INT                       ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
-#define TMR_C3_INT                       ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
-#define TMR_C4_INT                       ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
-#define TMR_HALL_INT                     ((uint32_t)0x000020) /*!< tmr interrupt hall */
-#define TMR_TRIGGER_INT                  ((uint32_t)0x000040) /*!< tmr interrupt trigger */
-#define TMR_BRK_INT                      ((uint32_t)0x000080) /*!< tmr interrupt brake */
-
-/**
-  * @}
-  */
-
-/** @defgroup TMR_exported_types
-  * @{
-  */
-
-/**
-  * @brief tmr clock division type
-  */
-typedef enum
-{
-  TMR_CLOCK_DIV1                         = 0x00, /*!< tmr clock division 1 */
-  TMR_CLOCK_DIV2                         = 0x01, /*!< tmr clock division 2 */
-  TMR_CLOCK_DIV4                         = 0x02  /*!< tmr clock division 4 */
-} tmr_clock_division_type;
-
-/**
-  * @brief tmr counter mode type
-  */
-typedef enum
-{
-  TMR_COUNT_UP                           = 0x00, /*!< tmr counter mode up */
-  TMR_COUNT_DOWN                         = 0x01, /*!< tmr counter mode down */
-  TMR_COUNT_TWO_WAY_1                    = 0x02, /*!< tmr counter mode two way 1 */
-  TMR_COUNT_TWO_WAY_2                    = 0x04, /*!< tmr counter mode two way 2 */
-  TMR_COUNT_TWO_WAY_3                    = 0x06  /*!< tmr counter mode two way 3 */
-} tmr_count_mode_type;
-
-/**
-  * @brief tmr primary mode select type
-  */
-typedef enum
-{
-  TMR_PRIMARY_SEL_RESET                  = 0x00, /*!< tmr primary mode select reset */
-  TMR_PRIMARY_SEL_ENABLE                 = 0x01, /*!< tmr primary mode select enable */
-  TMR_PRIMARY_SEL_OVERFLOW               = 0x02, /*!< tmr primary mode select overflow */
-  TMR_PRIMARY_SEL_COMPARE                = 0x03, /*!< tmr primary mode select compare */
-  TMR_PRIMARY_SEL_C1ORAW                 = 0x04, /*!< tmr primary mode select c1oraw */
-  TMR_PRIMARY_SEL_C2ORAW                 = 0x05, /*!< tmr primary mode select c2oraw */
-  TMR_PRIMARY_SEL_C3ORAW                 = 0x06, /*!< tmr primary mode select c3oraw */
-  TMR_PRIMARY_SEL_C4ORAW                 = 0x07  /*!< tmr primary mode select c4oraw */
-} tmr_primary_select_type;
-
-/**
-  * @brief tmr subordinate mode input select type
-  */
-typedef enum
-{
-  TMR_SUB_INPUT_SEL_IS0                  = 0x00, /*!< subordinate mode input select is0 */
-  TMR_SUB_INPUT_SEL_IS1                  = 0x01, /*!< subordinate mode input select is1 */
-  TMR_SUB_INPUT_SEL_IS2                  = 0x02, /*!< subordinate mode input select is2 */
-  TMR_SUB_INPUT_SEL_IS3                  = 0x03, /*!< subordinate mode input select is3 */
-  TMR_SUB_INPUT_SEL_C1INC                = 0x04, /*!< subordinate mode input select c1inc */
-  TMR_SUB_INPUT_SEL_C1DF1                = 0x05, /*!< subordinate mode input select c1df1 */
-  TMR_SUB_INPUT_SEL_C2DF2                = 0x06, /*!< subordinate mode input select c2df2 */
-  TMR_SUB_INPUT_SEL_EXTIN                = 0x07  /*!< subordinate mode input select extin */
-} sub_tmr_input_sel_type;
-
-/**
-  * @brief tmr subordinate mode select type
-  */
-typedef enum
-{
-  TMR_SUB_MODE_DIABLE                    = 0x00, /*!< subordinate mode disable */
-  TMR_SUB_ENCODER_MODE_A                 = 0x01, /*!< subordinate mode select encoder mode a */
-  TMR_SUB_ENCODER_MODE_B                 = 0x02, /*!< subordinate mode select encoder mode b */
-  TMR_SUB_ENCODER_MODE_C                 = 0x03, /*!< subordinate mode select encoder mode c */
-  TMR_SUB_RESET_MODE                     = 0x04, /*!< subordinate mode select reset */
-  TMR_SUB_HANG_MODE                      = 0x05, /*!< subordinate mode select hang */
-  TMR_SUB_TRIGGER_MODE                   = 0x06, /*!< subordinate mode select trigger */
-  TMR_SUB_EXTERNAL_CLOCK_MODE_A          = 0x07  /*!< subordinate mode external clock mode a */
-} tmr_sub_mode_select_type;
-
-/**
-  * @brief tmr encoder mode type
-  */
-typedef enum
-{
-  TMR_ENCODER_MODE_A                     = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
-  TMR_ENCODER_MODE_B                     = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
-  TMR_ENCODER_MODE_C                     = TMR_SUB_ENCODER_MODE_C  /*!< tmr encoder mode c */
-} tmr_encoder_mode_type;
-
-/**
-  * @brief tmr output control mode type
-  */
-typedef enum
-{
-  TMR_OUTPUT_CONTROL_OFF                 = 0x00, /*!< tmr output control mode off */
-  TMR_OUTPUT_CONTROL_HIGH                = 0x01, /*!< tmr output control mode high */
-  TMR_OUTPUT_CONTROL_LOW                 = 0x02, /*!< tmr output control mode low */
-  TMR_OUTPUT_CONTROL_SWITCH              = 0x03, /*!< tmr output control mode switch */
-  TMR_OUTPUT_CONTROL_FORCE_LOW           = 0x04, /*!< tmr output control mode force low */
-  TMR_OUTPUT_CONTROL_FORCE_HIGH          = 0x05, /*!< tmr output control mode force high */
-  TMR_OUTPUT_CONTROL_PWM_MODE_A          = 0x06, /*!< tmr output control mode pwm a */
-  TMR_OUTPUT_CONTROL_PWM_MODE_B          = 0x07  /*!< tmr output control mode pwm b */
-} tmr_output_control_mode_type;
-
-/**
-  * @brief tmr force output type
-  */
-typedef enum
-{
-  TMR_FORCE_OUTPUT_HIGH                  = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
-  TMR_FORCE_OUTPUT_LOW                   = TMR_OUTPUT_CONTROL_FORCE_LOW   /*!< tmr force output low */
-} tmr_force_output_type;
-
-/**
-  * @brief tmr output channel polarity type
-  */
-typedef enum
-{
-  TMR_OUTPUT_ACTIVE_HIGH                 = 0x00, /*!< tmr output channel polarity high */
-  TMR_OUTPUT_ACTIVE_LOW                  = 0x01  /*!< tmr output channel polarity low */
-} tmr_output_polarity_type;
-
-/**
-  * @brief tmr input channel polarity type
-  */
-typedef enum
-{
-  TMR_INPUT_RISING_EDGE                  = 0x00, /*!< tmr input channel polarity rising */
-  TMR_INPUT_FALLING_EDGE                 = 0x01, /*!< tmr input channel polarity falling */
-  TMR_INPUT_BOTH_EDGE                    = 0x03  /*!< tmr input channel polarity both edge */
-} tmr_input_polarity_type;
-
-/**
-  * @brief tmr channel select type
-  */
-typedef enum
-{
-  TMR_SELECT_CHANNEL_1                   = 0x00, /*!< tmr channel select channel 1 */
-  TMR_SELECT_CHANNEL_1C                  = 0x01, /*!< tmr channel select channel 1 complementary */
-  TMR_SELECT_CHANNEL_2                   = 0x02, /*!< tmr channel select channel 2 */
-  TMR_SELECT_CHANNEL_2C                  = 0x03, /*!< tmr channel select channel 2 complementary */
-  TMR_SELECT_CHANNEL_3                   = 0x04, /*!< tmr channel select channel 3 */
-  TMR_SELECT_CHANNEL_3C                  = 0x05, /*!< tmr channel select channel 3 complementary */
-  TMR_SELECT_CHANNEL_4                   = 0x06  /*!< tmr channel select channel 4 */
-} tmr_channel_select_type;
-
-/**
-  * @brief tmr channel1 input connected type
-  */
-typedef enum
-{
-  TMR_CHANEL1_CONNECTED_C1IRAW           = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
-  TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR   = 0x01  /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
-} tmr_channel1_input_connected_type;
-
-/**
-  * @brief tmr input channel mapped type channel direction
-  */
-typedef enum
-{
-  TMR_CC_CHANNEL_MAPPED_DIRECT           = 0x01, /*!< channel is configured as input, mapped direct */
-  TMR_CC_CHANNEL_MAPPED_INDIRECT         = 0x02, /*!< channel is configured as input, mapped indirect */
-  TMR_CC_CHANNEL_MAPPED_STI              = 0x03  /*!< channel is configured as input, mapped trc */
-} tmr_input_direction_mapped_type;
-
-/**
-  * @brief tmr input divider type
-  */
-typedef enum
-{
-  TMR_CHANNEL_INPUT_DIV_1                = 0x00, /*!< tmr channel input divider 1 */
-  TMR_CHANNEL_INPUT_DIV_2                = 0x01, /*!< tmr channel input divider 2 */
-  TMR_CHANNEL_INPUT_DIV_4                = 0x02, /*!< tmr channel input divider 4 */
-  TMR_CHANNEL_INPUT_DIV_8                = 0x03  /*!< tmr channel input divider 8 */
-} tmr_channel_input_divider_type;
-
-/**
-  * @brief tmr dma request source select type
-  */
-typedef enum
-{
-  TMR_DMA_REQUEST_BY_CHANNEL             = 0x00, /*!< tmr dma request source select channel */
-  TMR_DMA_REQUEST_BY_OVERFLOW            = 0x01  /*!< tmr dma request source select overflow */
-} tmr_dma_request_source_type;
-
-/**
-  * @brief tmr dma request type
-  */
-typedef enum
-{
-  TMR_OVERFLOW_DMA_REQUEST               = 0x00000100, /*!< tmr dma request select overflow */
-  TMR_C1_DMA_REQUEST                     = 0x00000200, /*!< tmr dma request select channel 1 */
-  TMR_C2_DMA_REQUEST                     = 0x00000400, /*!< tmr dma request select channel 2 */
-  TMR_C3_DMA_REQUEST                     = 0x00000800, /*!< tmr dma request select channel 3 */
-  TMR_C4_DMA_REQUEST                     = 0x00001000, /*!< tmr dma request select channel 4 */
-  TMR_HALL_DMA_REQUEST                   = 0x00002000, /*!< tmr dma request select hall */
-  TMR_TRIGGER_DMA_REQUEST                = 0x00004000  /*!< tmr dma request select trigger */
-} tmr_dma_request_type;
-
-/**
-  * @brief tmr event triggered by software type
-  */
-typedef enum
-{
-  TMR_OVERFLOW_SWTRIG                    = 0x00000001, /*!< tmr event triggered by software of overflow */
-  TMR_C1_SWTRIG                          = 0x00000002, /*!< tmr event triggered by software of channel 1 */
-  TMR_C2_SWTRIG                          = 0x00000004, /*!< tmr event triggered by software of channel 2 */
-  TMR_C3_SWTRIG                          = 0x00000008, /*!< tmr event triggered by software of channel 3 */
-  TMR_C4_SWTRIG                          = 0x00000010, /*!< tmr event triggered by software of channel 4 */
-  TMR_HALL_SWTRIG                        = 0x00000020, /*!< tmr event triggered by software of hall */
-  TMR_TRIGGER_SWTRIG                     = 0x00000040, /*!< tmr event triggered by software of trigger */
-  TMR_BRK_SWTRIG                         = 0x00000080  /*!< tmr event triggered by software of brake */
-}tmr_event_trigger_type;
-
-/**
-  * @brief tmr polarity active type
-  */
-typedef enum
-{
-  TMR_POLARITY_ACTIVE_HIGH               = 0x00, /*!< tmr polarity active high */
-  TMR_POLARITY_ACTIVE_LOW                = 0x01, /*!< tmr polarity active low */
-  TMR_POLARITY_ACTIVE_BOTH               = 0x02  /*!< tmr polarity active both high ande low */
-}tmr_polarity_active_type;
-
-/**
-  * @brief tmr external signal divider type
-  */
-typedef enum
-{
-  TMR_ES_FREQUENCY_DIV_1                 = 0x00, /*!< tmr external signal frequency divider 1 */
-  TMR_ES_FREQUENCY_DIV_2                 = 0x01, /*!< tmr external signal frequency divider 2 */
-  TMR_ES_FREQUENCY_DIV_4                 = 0x02, /*!< tmr external signal frequency divider 4 */
-  TMR_ES_FREQUENCY_DIV_8                 = 0x03  /*!< tmr external signal frequency divider 8 */
-}tmr_external_signal_divider_type;
-
-/**
-  * @brief tmr external signal polarity type
-  */
-typedef enum
-{
-  TMR_ES_POLARITY_NON_INVERTED           = 0x00, /*!< tmr external signal polarity non-inerted */
-  TMR_ES_POLARITY_INVERTED               = 0x01  /*!< tmr external signal polarity inerted */
-}tmr_external_signal_polarity_type;
-
-/**
-  * @brief tmr dma transfer length type
-  */
-typedef enum
-{
-  TMR_DMA_TRANSFER_1BYTE                 = 0x00, /*!< tmr dma transfer length 1 byte */
-  TMR_DMA_TRANSFER_2BYTES                = 0x01, /*!< tmr dma transfer length 2 bytes */
-  TMR_DMA_TRANSFER_3BYTES                = 0x02, /*!< tmr dma transfer length 3 bytes */
-  TMR_DMA_TRANSFER_4BYTES                = 0x03, /*!< tmr dma transfer length 4 bytes */
-  TMR_DMA_TRANSFER_5BYTES                = 0x04, /*!< tmr dma transfer length 5 bytes */
-  TMR_DMA_TRANSFER_6BYTES                = 0x05, /*!< tmr dma transfer length 6 bytes */
-  TMR_DMA_TRANSFER_7BYTES                = 0x06, /*!< tmr dma transfer length 7 bytes */
-  TMR_DMA_TRANSFER_8BYTES                = 0x07, /*!< tmr dma transfer length 8 bytes */
-  TMR_DMA_TRANSFER_9BYTES                = 0x08, /*!< tmr dma transfer length 9 bytes */
-  TMR_DMA_TRANSFER_10BYTES               = 0x09, /*!< tmr dma transfer length 10 bytes */
-  TMR_DMA_TRANSFER_11BYTES               = 0x0A, /*!< tmr dma transfer length 11 bytes */
-  TMR_DMA_TRANSFER_12BYTES               = 0x0B, /*!< tmr dma transfer length 12 bytes */
-  TMR_DMA_TRANSFER_13BYTES               = 0x0C, /*!< tmr dma transfer length 13 bytes */
-  TMR_DMA_TRANSFER_14BYTES               = 0x0D, /*!< tmr dma transfer length 14 bytes */
-  TMR_DMA_TRANSFER_15BYTES               = 0x0E, /*!< tmr dma transfer length 15 bytes */
-  TMR_DMA_TRANSFER_16BYTES               = 0x0F, /*!< tmr dma transfer length 16 bytes */
-  TMR_DMA_TRANSFER_17BYTES               = 0x10, /*!< tmr dma transfer length 17 bytes */
-  TMR_DMA_TRANSFER_18BYTES               = 0x11  /*!< tmr dma transfer length 18 bytes */
-}tmr_dma_transfer_length_type;
-
-/**
-  * @brief tmr dma base address type
-  */
-typedef enum
-{
-  TMR_CTRL1_ADDRESS                      = 0x0000, /*!< tmr dma base address ctrl1 */
-  TMR_CTRL2_ADDRESS                      = 0x0001, /*!< tmr dma base address ctrl2 */
-  TMR_STCTRL_ADDRESS                     = 0x0002, /*!< tmr dma base address stctrl */
-  TMR_IDEN_ADDRESS                       = 0x0003, /*!< tmr dma base address iden */
-  TMR_ISTS_ADDRESS                       = 0x0004, /*!< tmr dma base address ists */
-  TMR_SWEVT_ADDRESS                      = 0x0005, /*!< tmr dma base address swevt */
-  TMR_CM1_ADDRESS                        = 0x0006, /*!< tmr dma base address cm1 */
-  TMR_CM2_ADDRESS                        = 0x0007, /*!< tmr dma base address cm2 */
-  TMR_CCTRL_ADDRESS                      = 0x0008, /*!< tmr dma base address cctrl */
-  TMR_CVAL_ADDRESS                       = 0x0009, /*!< tmr dma base address cval */
-  TMR_DIV_ADDRESS                        = 0x000A, /*!< tmr dma base address div */
-  TMR_PR_ADDRESS                         = 0x000B, /*!< tmr dma base address pr */
-  TMR_RPR_ADDRESS                        = 0x000C, /*!< tmr dma base address rpr */
-  TMR_C1DT_ADDRESS                       = 0x000D, /*!< tmr dma base address c1dt */
-  TMR_C2DT_ADDRESS                       = 0x000E, /*!< tmr dma base address c2dt */
-  TMR_C3DT_ADDRESS                       = 0x000F, /*!< tmr dma base address c3dt */
-  TMR_C4DT_ADDRESS                       = 0x0010, /*!< tmr dma base address c4dt */
-  TMR_BRK_ADDRESS                        = 0x0011, /*!< tmr dma base address brake */
-  TMR_DMACTRL_ADDRESS                    = 0x0012  /*!< tmr dma base address dmactrl */
-}tmr_dma_address_type;
-
-/**
-  * @brief tmr brk polarity type
-  */
-typedef enum
-{
-  TMR_BRK_INPUT_ACTIVE_LOW               = 0x00, /*!< tmr brk input channel active low */
-  TMR_BRK_INPUT_ACTIVE_HIGH              = 0x01  /*!< tmr brk input channel active high */
-}tmr_brk_polarity_type;
-
-/**
-  * @brief tmr write protect level type
-  */
-typedef enum
-{
-  TMR_WP_OFF                             = 0x00, /*!< tmr write protect off */
-  TMR_WP_LEVEL_3                         = 0x01, /*!< tmr write protect level 3 */
-  TMR_WP_LEVEL_2                         = 0x02, /*!< tmr write protect level 2 */
-  TMR_WP_LEVEL_1                         = 0x03  /*!< tmr write protect level 1 */
-}tmr_wp_level_type;
-
-/**
-  * @brief tmr output config type
-  */
-typedef struct
-{
-  tmr_output_control_mode_type           oc_mode;             /*!< output channel mode */
-  confirm_state                          oc_idle_state;       /*!< output channel idle state */
-  confirm_state                          occ_idle_state;      /*!< output channel complementary idle state */
-  tmr_output_polarity_type               oc_polarity;         /*!< output channel polarity */
-  tmr_output_polarity_type               occ_polarity;        /*!< output channel complementary polarity */
-  confirm_state                          oc_output_state;     /*!< output channel enable */
-  confirm_state                          occ_output_state;    /*!< output channel complementary enable */
-} tmr_output_config_type;
-
-/**
-  * @brief tmr input capture config type
-  */
-typedef struct
-{
-  tmr_channel_select_type                input_channel_select;   /*!< tmr input channel select */
-  tmr_input_polarity_type                input_polarity_select;  /*!< tmr input polarity select */
-  tmr_input_direction_mapped_type        input_mapped_select;    /*!< tmr channel mapped direct or indirect */
-  uint8_t                                input_filter_value;     /*!< tmr channel filter value */
-} tmr_input_config_type;
-
-/**
-  * @brief tmr brkdt config type
-  */
-typedef struct
-{
-  uint8_t                                deadtime;            /*!< dead-time generator setup */
-  tmr_brk_polarity_type                  brk_polarity;        /*!< tmr brake polarity */
-  tmr_wp_level_type                      wp_level;            /*!< write protect configuration */
-  confirm_state                          auto_output_enable;  /*!< automatic output enable */
-  confirm_state                          fcsoen_state;        /*!< frozen channel status when output enable */
-  confirm_state                          fcsodis_state;       /*!< frozen channel status when output disable */
-  confirm_state                          brk_enable;          /*!< tmr brk enale */
-} tmr_brkdt_config_type;
-
-/**
-  * @brief type define tmr register all
-  */
-typedef struct
-{
-  /**
-    * @brief tmr ctrl1 register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t tmren                : 1; /* [0] */
-      __IO uint32_t ovfen                : 1; /* [1] */
-      __IO uint32_t ovfs                 : 1; /* [2] */
-      __IO uint32_t ocmen                : 1; /* [3] */
-      __IO uint32_t cnt_dir              : 3; /* [6:4] */
-      __IO uint32_t prben                : 1; /* [7] */
-      __IO uint32_t clkdiv               : 2; /* [9:8] */
-      __IO uint32_t pmen                 : 1; /* [10] */
-      __IO uint32_t reserved1            : 21;/* [31:11] */
-    } ctrl1_bit;
-  };
-
-  /**
-    * @brief tmr ctrl2 register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t cbctrl               : 1; /* [0] */
-      __IO uint32_t reserved1            : 1; /* [1] */
-      __IO uint32_t ccfs                 : 1; /* [2] */
-      __IO uint32_t drs                  : 1; /* [3] */
-      __IO uint32_t ptos                 : 3; /* [6:4] */
-      __IO uint32_t c1insel              : 1; /* [7] */
-      __IO uint32_t c1ios                : 1; /* [8] */
-      __IO uint32_t c1cios               : 1; /* [9] */
-      __IO uint32_t c2ios                : 1; /* [10] */
-      __IO uint32_t c2cios               : 1; /* [11] */
-      __IO uint32_t c3ios                : 1; /* [12] */
-      __IO uint32_t c3cios               : 1; /* [13] */
-      __IO uint32_t c4ios                : 1; /* [14] */
-      __IO uint32_t reserved2            : 17;/* [31:15] */
-    } ctrl2_bit;
-  };
-
-  /**
-    * @brief tmr smc register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t stctrl;
-    struct
-    {
-      __IO uint32_t smsel                : 3; /* [2:0] */
-      __IO uint32_t reserved1            : 1; /* [3] */
-      __IO uint32_t stis                 : 3; /* [6:4] */
-      __IO uint32_t sts                  : 1; /* [7] */
-      __IO uint32_t esf                  : 4; /* [11:8] */
-      __IO uint32_t esdiv                : 2; /* [13:12] */
-      __IO uint32_t ecmben               : 1; /* [14] */
-      __IO uint32_t esp                  : 1; /* [15] */
-      __IO uint32_t reserved2            : 16;/* [31:16] */
-    } stctrl_bit;
-  };
-
-  /**
-    * @brief tmr die register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t iden;
-    struct
-    {
-      __IO uint32_t ovfien               : 1; /* [0] */
-      __IO uint32_t c1ien                : 1; /* [1] */
-      __IO uint32_t c2ien                : 1; /* [2] */
-      __IO uint32_t c3ien                : 1; /* [3] */
-      __IO uint32_t c4ien                : 1; /* [4] */
-      __IO uint32_t hallien              : 1; /* [5] */
-      __IO uint32_t tien                 : 1; /* [6] */
-      __IO uint32_t brkie                : 1; /* [7] */
-      __IO uint32_t ovfden               : 1; /* [8] */
-      __IO uint32_t c1den                : 1; /* [9] */
-      __IO uint32_t c2den                : 1; /* [10] */
-      __IO uint32_t c3den                : 1; /* [11] */
-      __IO uint32_t c4den                : 1; /* [12] */
-      __IO uint32_t hallde               : 1; /* [13] */
-      __IO uint32_t tden                 : 1; /* [14] */
-      __IO uint32_t reserved1            : 17;/* [31:15] */
-    } iden_bit;
-  };
-
-  /**
-    * @brief tmr ists register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t ists;
-    struct
-    {
-      __IO uint32_t ovfif                : 1; /* [0] */
-      __IO uint32_t c1if                 : 1; /* [1] */
-      __IO uint32_t c2if                 : 1; /* [2] */
-      __IO uint32_t c3if                 : 1; /* [3] */
-      __IO uint32_t c4if                 : 1; /* [4] */
-      __IO uint32_t hallif               : 1; /* [5] */
-      __IO uint32_t trgif                : 1; /* [6] */
-      __IO uint32_t brkif                : 1; /* [7] */
-      __IO uint32_t reserved1            : 1; /* [8] */
-      __IO uint32_t c1rf                 : 1; /* [9] */
-      __IO uint32_t c2rf                 : 1; /* [10] */
-      __IO uint32_t c3rf                 : 1; /* [11] */
-      __IO uint32_t c4rf                 : 1; /* [12] */
-      __IO uint32_t reserved2            : 19;/* [31:13] */
-    } ists_bit;
-  };
-
-  /**
-    * @brief tmr eveg register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t swevt;
-    struct
-    {
-      __IO uint32_t  ovfswtr             : 1; /* [0] */
-      __IO uint32_t  c1swtr              : 1; /* [1] */
-      __IO uint32_t  c2swtr              : 1; /* [2] */
-      __IO uint32_t  c3swtr              : 1; /* [3] */
-      __IO uint32_t  c4swtr              : 1; /* [4] */
-      __IO uint32_t  hallswtr            : 1; /* [5] */
-      __IO uint32_t  trgswtr             : 1; /* [6] */
-      __IO uint32_t  brkswtr             : 1; /* [7] */
-      __IO uint32_t  reserved            : 24;/* [31:8] */
-    } swevt_bit;
-  };
-
-  /**
-    * @brief tmr ccm1 register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t cm1;
-
-    /**
-     * @brief channel mode
-     */
-    struct
-    {
-      __IO uint32_t c1c                  : 2; /* [1:0] */
-      __IO uint32_t c1oien               : 1; /* [2] */
-      __IO uint32_t c1oben               : 1; /* [3] */
-      __IO uint32_t c1octrl              : 3; /* [6:4] */
-      __IO uint32_t c1osen               : 1; /* [7] */
-      __IO uint32_t c2c                  : 2; /* [9:8] */
-      __IO uint32_t c2oien               : 1; /* [10] */
-      __IO uint32_t c2oben               : 1; /* [11] */
-      __IO uint32_t c2octrl              : 3; /* [14:12] */
-      __IO uint32_t c2osen               : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } cm1_output_bit;
-
-    /**
-      * @brief input capture mode
-      */
-    struct
-    {
-      __IO uint32_t c1c                  : 2; /* [1:0] */
-      __IO uint32_t c1idiv               : 2; /* [3:2] */
-      __IO uint32_t c1df                 : 4; /* [7:4] */
-      __IO uint32_t c2c                  : 2; /* [9:8] */
-      __IO uint32_t c2idiv               : 2; /* [11:10] */
-      __IO uint32_t c2df                 : 4; /* [15:12] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } cm1_input_bit;
-  };
-
-  /**
-    * @brief tmr ccm2 register, offset:0x1C
-    */
-  union
-  {
-    __IO uint32_t cm2;
-
-    /**
-      * @brief channel mode
-      */
-    struct
-    {
-      __IO uint32_t c3c                  : 2; /* [1:0] */
-      __IO uint32_t c3oien               : 1; /* [2] */
-      __IO uint32_t c3oben               : 1; /* [3] */
-      __IO uint32_t c3octrl              : 3; /* [6:4] */
-      __IO uint32_t c3osen               : 1; /* [7] */
-      __IO uint32_t c4c                  : 2; /* [9:8] */
-      __IO uint32_t c4oien               : 1; /* [10] */
-      __IO uint32_t c4oben               : 1; /* [11] */
-      __IO uint32_t c4octrl              : 3; /* [14:12] */
-      __IO uint32_t c4osen               : 1; /* [15] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } cm2_output_bit;
-
-    /**
-      * @brief input capture mode
-      */
-    struct
-    {
-      __IO uint32_t c3c                  : 2; /* [1:0] */
-      __IO uint32_t c3idiv               : 2; /* [3:2] */
-      __IO uint32_t c3df                 : 4; /* [7:4] */
-      __IO uint32_t c4c                  : 2; /* [9:8] */
-      __IO uint32_t c4idiv               : 2; /* [11:10] */
-      __IO uint32_t c4df                 : 4; /* [15:12] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } cm2_input_bit;
-  };
-
-  /**
-    * @brief tmr cce register, offset:0x20
-    */
-  union
-  {
-    uint32_t cctrl;
-    struct
-    {
-      __IO uint32_t c1en                 : 1; /* [0] */
-      __IO uint32_t c1p                  : 1; /* [1] */
-      __IO uint32_t c1cen                : 1; /* [2] */
-      __IO uint32_t c1cp                 : 1; /* [3] */
-      __IO uint32_t c2en                 : 1; /* [4] */
-      __IO uint32_t c2p                  : 1; /* [5] */
-      __IO uint32_t c2cen                : 1; /* [6] */
-      __IO uint32_t c2cp                 : 1; /* [7] */
-      __IO uint32_t c3en                 : 1; /* [8] */
-      __IO uint32_t c3p                  : 1; /* [9] */
-      __IO uint32_t c3cen                : 1; /* [10] */
-      __IO uint32_t c3cp                 : 1; /* [11] */
-      __IO uint32_t c4en                 : 1; /* [12] */
-      __IO uint32_t c4p                  : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } cctrl_bit;
-  };
-
-  /**
-    * @brief tmr cnt register, offset:0x24
-    */
-  union
-  {
-    __IO uint32_t cval;
-    struct
-    {
-      __IO uint32_t cval                 : 32;/* [31:0] */
-    } cval_bit;
-  };
-
-  /**
-    * @brief tmr div, offset:0x28
-    */
-  union
-  {
-    __IO uint32_t div;
-    struct
-    {
-      __IO uint32_t div                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } div_bit;
-  };
-
-  /**
-    * @brief tmr pr register, offset:0x2C
-    */
-  union
-  {
-    __IO  uint32_t pr;
-    struct
-    {
-      __IO uint32_t pr                   : 32;/* [31:0] */
-    } pr_bit;
-  };
-
-  /**
-    * @brief tmr rpr register, offset:0x30
-    */
-  union
-  {
-    __IO uint32_t rpr;
-    struct
-    {
-      __IO uint32_t rpr                  : 8; /* [7:0] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } rpr_bit;
-  };
-
-  /**
-    * @brief tmr c1dt register, offset:0x34
-    */
-  union
-  {
-    uint32_t c1dt;
-    struct
-    {
-      __IO uint32_t c1dt                 : 32;/* [31:0] */
-    } c1dt_bit;
-  };
-
-  /**
-    * @brief tmr c2dt register, offset:0x38
-    */
-  union
-  {
-    uint32_t c2dt;
-    struct
-    {
-      __IO uint32_t c2dt                 : 32;/* [31:0] */
-    } c2dt_bit;
-  };
-
-  /**
-    * @brief tmr c3dt register, offset:0x3C
-    */
-  union
-  {
-    __IO uint32_t c3dt;
-    struct
-    {
-      __IO uint32_t c3dt                 : 32;/* [31:0] */
-    } c3dt_bit;
-  };
-
-  /**
-    * @brief tmr c4dt register, offset:0x40
-    */
-  union
-  {
-    __IO uint32_t c4dt;
-    struct
-    {
-      __IO uint32_t c4dt                 : 32;/* [31:0] */
-    } c4dt_bit;
-  };
-
-  /**
-    * @brief tmr brk register, offset:0x44
-    */
-  union
-  {
-    __IO uint32_t brk;
-    struct
-    {
-      __IO uint32_t dtc                  : 8; /* [7:0] */
-      __IO uint32_t wpc                  : 2; /* [9:8] */
-      __IO uint32_t fcsodis              : 1; /* [10] */
-      __IO uint32_t fcsoen               : 1; /* [11] */
-      __IO uint32_t brken                : 1; /* [12] */
-      __IO uint32_t brkv                 : 1; /* [13] */
-      __IO uint32_t aoen                 : 1; /* [14] */
-      __IO uint32_t oen                  : 1; /* [15] */
-      __IO uint32_t reserved1            : 16; /* [31:16] */
-    } brk_bit;
-  };
-  /**
-    * @brief tmr dmactrl register, offset:0x48
-    */
-  union
-  {
-    __IO uint32_t dmactrl;
-    struct
-    {
-      __IO uint32_t addr                 : 5; /* [4:0] */
-      __IO uint32_t reserved1            : 3; /* [7:5] */
-      __IO uint32_t dtb                  : 5; /* [12:8] */
-      __IO uint32_t reserved2            : 19;/* [31:13] */
-    } dmactrl_bit;
-  };
-
-  /**
-    * @brief tmr dmadt register, offset:0x4C
-    */
-  union
-  {
-    __IO uint32_t dmadt;
-    struct
-    {
-      __IO uint32_t dmadt                : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } dmadt_bit;
-  };
-
-} tmr_type;
-
-/**
-  * @}
-  */
-
-#define TMR1                             ((tmr_type *) TMR1_BASE)
-#define TMR2                             ((tmr_type *) TMR2_BASE)
-#define TMR3                             ((tmr_type *) TMR3_BASE)
-#define TMR4                             ((tmr_type *) TMR4_BASE)
-#define TMR5                             ((tmr_type *) TMR5_BASE)
-#define TMR6                             ((tmr_type *) TMR6_BASE)
-#define TMR7                             ((tmr_type *) TMR7_BASE)
-#define TMR8                             ((tmr_type *) TMR8_BASE)
-#define TMR9                             ((tmr_type *) TMR9_BASE)
-#define TMR10                            ((tmr_type *) TMR10_BASE)
-#define TMR11                            ((tmr_type *) TMR11_BASE)
-#define TMR12                            ((tmr_type *) TMR12_BASE)
-#define TMR13                            ((tmr_type *) TMR13_BASE)
-#define TMR14                            ((tmr_type *) TMR14_BASE)
-
-/** @defgroup TMR_exported_functions
-  * @{
-  */
-
-void tmr_reset(tmr_type *tmr_x);
-void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
-void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
-void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
-void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
-void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
-void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
-void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
-void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
-uint32_t tmr_counter_value_get(tmr_type *tmr_x);
-void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
-uint32_t tmr_div_value_get(tmr_type *tmr_x);
-void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                               tmr_output_config_type *tmr_output_struct);
-void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                    tmr_output_control_mode_type oc_mode);
-void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
-uint32_t tmr_period_value_get(tmr_type *tmr_x);
-void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                           uint32_t tmr_channel_value);
-uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
-void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                   confirm_state new_state);
-void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                        confirm_state new_state);
-void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                   confirm_state new_state);
-void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
-void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
-void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
-                            tmr_channel_input_divider_type divider_factor);
-void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
-void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                  uint16_t filter_value);
-void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
-                          tmr_channel_input_divider_type divider_factor);
-void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect);
-void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                   tmr_channel_input_divider_type divider_factor);
-void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
-void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
-void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
-void tmr_hall_select(tmr_type *tmr_x,  confirm_state new_state);
-void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
-void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
-void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
-void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
-flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
-void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
-void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
-void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
-void tmr_internal_clock_set(tmr_type *tmr_x);
-
-void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
-                                     tmr_polarity_active_type oc_polarity);
-void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
-                               tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
-void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
-                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
-void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
-                                     tmr_external_signal_polarity_type  es_polarity, uint16_t es_filter);
-void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
-                             ic1_polarity, tmr_input_polarity_type ic2_polarity);
-void tmr_force_output_set(tmr_type *tmr_x,  tmr_channel_select_type tmr_channel, \
-                          tmr_force_output_type force_output);
-void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
-                            tmr_dma_address_type dma_base_address);
-void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_usart.h

@@ -1,378 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_usart.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 usart header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_USART_H
-#define __AT32F403A_407_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */
-
-/** @defgroup USART_flags_definition
-  * @brief usart flag
-  * @{
-  */
-
-#define USART_PERR_FLAG                  ((uint32_t)0x00000001) /*!< usart parity error flag */
-#define USART_FERR_FLAG                  ((uint32_t)0x00000002) /*!< usart framing error flag */
-#define USART_NERR_FLAG                  ((uint32_t)0x00000004) /*!< usart noise error flag */
-#define USART_ROERR_FLAG                 ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
-#define USART_IDLEF_FLAG                 ((uint32_t)0x00000010) /*!< usart idle flag */
-#define USART_RDBF_FLAG                  ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
-#define USART_TDC_FLAG                   ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
-#define USART_TDBE_FLAG                  ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
-#define USART_BFF_FLAG                   ((uint32_t)0x00000100) /*!< usart break frame flag */
-#define USART_CTSCF_FLAG                 ((uint32_t)0x00000200) /*!< usart cts change flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_interrupts_definition
-  * @brief usart interrupt
-  * @{
-  */
-
-#define USART_IDLE_INT                   MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
-#define USART_RDBF_INT                   MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
-#define USART_TDC_INT                    MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
-#define USART_TDBE_INT                   MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
-#define USART_PERR_INT                   MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
-#define USART_BF_INT                     MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
-#define USART_ERR_INT                    MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
-#define USART_CTSCF_INT                  MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_exported_types
-  * @{
-  */
-
-/**
-  * @brief  usart parity selection type
-  */
-typedef enum
-{
-  USART_PARITY_NONE                      = 0x00, /*!< usart no parity */
-  USART_PARITY_EVEN                      = 0x01, /*!< usart even parity */
-  USART_PARITY_ODD                       = 0x02  /*!< usart odd parity */
-} usart_parity_selection_type;
-
-/**
-  * @brief  usart wakeup mode type
-  */
-typedef enum
-{
-  USART_WAKEUP_BY_IDLE_FRAME             = 0x00, /*!< usart wakeup by idle frame */
-  USART_WAKEUP_BY_MATCHING_ID            = 0x01  /*!< usart wakeup by matching id */
-} usart_wakeup_mode_type;
-
-/**
-  * @brief  usart data bit num type
-  */
-typedef enum
-{
-  USART_DATA_8BITS                       = 0x00, /*!< usart data size is 8 bits */
-  USART_DATA_9BITS                       = 0x01  /*!< usart data size is 9 bits */
-} usart_data_bit_num_type;
-
-/**
-  * @brief  usart break frame bit num type
-  */
-typedef enum
-{
-  USART_BREAK_10BITS                     = 0x00, /*!< usart lin mode berak frame detection 10 bits */
-  USART_BREAK_11BITS                     = 0x01  /*!< usart lin mode berak frame detection 11 bits */
-} usart_break_bit_num_type;
-
-/**
-  * @brief  usart phase of the clock type
-  */
-typedef enum
-{
-  USART_CLOCK_PHASE_1EDGE                = 0x00, /*!< usart data capture is done on the clock leading edge */
-  USART_CLOCK_PHASE_2EDGE                = 0x01  /*!< usart data capture is done on the clock trailing edge */
-} usart_clock_phase_type;
-
-/**
-  * @brief  usart polarity of the clock type
-  */
-typedef enum
-{
-  USART_CLOCK_POLARITY_LOW               = 0x00, /*!< usart clock stay low level outside transmission window */
-  USART_CLOCK_POLARITY_HIGH              = 0x01  /*!< usart clock stay high level outside transmission window */
-} usart_clock_polarity_type;
-
-/**
-  * @brief  usart last bit clock pulse type
-  */
-typedef enum
-{
-  USART_CLOCK_LAST_BIT_NONE              = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
-  USART_CLOCK_LAST_BIT_OUTPUT            = 0x01  /*!< usart clock pulse of the last data bit is outputted */
-} usart_lbcp_type;
-
-/**
-  * @brief  usart stop bit num type
-  */
-typedef enum
-{
-  USART_STOP_1_BIT                       = 0x00, /*!< usart stop bits num is 1 */
-  USART_STOP_0_5_BIT                     = 0x01, /*!< usart stop bits num is 0.5 */
-  USART_STOP_2_BIT                       = 0x02, /*!< usart stop bits num is 2 */
-  USART_STOP_1_5_BIT                     = 0x03  /*!< usart stop bits num is 1.5 */
-} usart_stop_bit_num_type;
-
-/**
-  * @brief  usart hardware flow control type
-  */
-typedef enum
-{
-  USART_HARDWARE_FLOW_NONE               = 0x00, /*!< usart without hardware flow */
-  USART_HARDWARE_FLOW_RTS                = 0x01, /*!< usart hardware flow only rts */
-  USART_HARDWARE_FLOW_CTS                = 0x02, /*!< usart hardware flow only cts */
-  USART_HARDWARE_FLOW_RTS_CTS            = 0x03  /*!< usart hardware flow both rts and cts */
-} usart_hardware_flow_control_type;
-
-/**
-  * @brief type define usart register all
-  */
-typedef struct
-{
-  /**
-    * @brief usart sts register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t perr                 : 1; /* [0] */
-      __IO uint32_t ferr                 : 1; /* [1] */
-      __IO uint32_t nerr                 : 1; /* [2] */
-      __IO uint32_t roerr                : 1; /* [3] */
-      __IO uint32_t idlef                : 1; /* [4] */
-      __IO uint32_t rdbf                 : 1; /* [5] */
-      __IO uint32_t tdc                  : 1; /* [6] */
-      __IO uint32_t tdbe                 : 1; /* [7] */
-      __IO uint32_t bff                  : 1; /* [8] */
-      __IO uint32_t ctscf                : 1; /* [9] */
-      __IO uint32_t reserved1            : 22;/* [31:10] */
-    } sts_bit;
-  };
-
-  /**
-    * @brief usart dt register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t dt;
-    struct
-    {
-      __IO uint32_t dt                   : 9; /* [8:0] */
-      __IO uint32_t reserved1            : 23;/* [31:9] */
-    } dt_bit;
-  };
-
-  /**
-    * @brief usart baudr register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t baudr;
-    struct
-    {
-      __IO uint32_t div                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } baudr_bit;
-  };
-
-  /**
-    * @brief usart ctrl1 register, offset:0x0C
-    */
-  union
-  {
-    __IO uint32_t ctrl1;
-    struct
-    {
-      __IO uint32_t sbf                  : 1; /* [0] */
-      __IO uint32_t rm                   : 1; /* [1] */
-      __IO uint32_t ren                  : 1; /* [2] */
-      __IO uint32_t ten                  : 1; /* [3] */
-      __IO uint32_t idleien              : 1; /* [4] */
-      __IO uint32_t rdbfien              : 1; /* [5] */
-      __IO uint32_t tdcien               : 1; /* [6] */
-      __IO uint32_t tdbeien              : 1; /* [7] */
-      __IO uint32_t perrien              : 1; /* [8] */
-      __IO uint32_t psel                 : 1; /* [9] */
-      __IO uint32_t pen                  : 1; /* [10] */
-      __IO uint32_t wum                  : 1; /* [11] */
-      __IO uint32_t dbn                  : 1; /* [12] */
-      __IO uint32_t uen                  : 1; /* [13] */
-      __IO uint32_t reserved1            : 18;/* [31:14] */
-    } ctrl1_bit;
-  };
-
-  /**
-    * @brief usart ctrl2 register, offset:0x10
-    */
-  union
-  {
-    __IO uint32_t ctrl2;
-    struct
-    {
-      __IO uint32_t id                   : 4; /* [3:0] */
-      __IO uint32_t reserved1            : 1; /* [4] */
-      __IO uint32_t bfbn                 : 1; /* [5] */
-      __IO uint32_t bfien                : 1; /* [6] */
-      __IO uint32_t reserved2            : 1; /* [7] */
-      __IO uint32_t lbcp                 : 1; /* [8] */
-      __IO uint32_t clkpha               : 1; /* [9] */
-      __IO uint32_t clkpol               : 1; /* [10] */
-      __IO uint32_t clken                : 1; /* [11] */
-      __IO uint32_t stopbn               : 2; /* [13:12] */
-      __IO uint32_t linen                : 1; /* [14] */
-      __IO uint32_t reserved3            : 17;/* [31:15] */
-    } ctrl2_bit;
-  };
-
-  /**
-    * @brief usart ctrl3 register, offset:0x14
-    */
-  union
-  {
-    __IO uint32_t ctrl3;
-    struct
-    {
-      __IO uint32_t errien               : 1; /* [0] */
-      __IO uint32_t irdaen               : 1; /* [1] */
-      __IO uint32_t irdalp               : 1; /* [2] */
-      __IO uint32_t slben                : 1; /* [3] */
-      __IO uint32_t scnacken             : 1; /* [4] */
-      __IO uint32_t scmen                : 1; /* [5] */
-      __IO uint32_t dmaren               : 1; /* [6] */
-      __IO uint32_t dmaten               : 1; /* [7] */
-      __IO uint32_t rtsen                : 1; /* [8] */
-      __IO uint32_t ctsen                : 1; /* [9] */
-      __IO uint32_t ctscfien             : 1; /* [10] */
-      __IO uint32_t reserved1            : 21;/* [31:11] */
-    } ctrl3_bit;
-  };
-
-  /**
-    * @brief usart gdiv register, offset:0x18
-    */
-  union
-  {
-    __IO uint32_t gdiv;
-    struct
-    {
-      __IO uint32_t isdiv                : 8; /* [7:0] */
-      __IO uint32_t scgt                 : 8; /* [15:8] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } gdiv_bit;
-  };
-} usart_type;
-
-/**
-  * @}
-  */
-
-#define USART1                           ((usart_type *) USART1_BASE)
-#define USART2                           ((usart_type *) USART2_BASE)
-#define USART3                           ((usart_type *) USART3_BASE)
-#define UART4                            ((usart_type *) UART4_BASE)
-#define UART5                            ((usart_type *) UART5_BASE)
-#define USART6                           ((usart_type *) USART6_BASE)
-#define UART7                            ((usart_type *) UART7_BASE)
-#define UART8                            ((usart_type *) UART8_BASE)
-
-/** @defgroup USART_exported_functions
-  * @{
-  */
-
-void usart_reset(usart_type* usart_x);
-void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
-void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
-void usart_enable(usart_type* usart_x, confirm_state new_state);
-void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
-void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
-void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
-void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
-void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
-void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
-void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
-void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
-void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
-void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
-void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
-void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
-void usart_data_transmit(usart_type* usart_x, uint16_t data);
-uint16_t usart_data_receive(usart_type* usart_x);
-void usart_break_send(usart_type* usart_x);
-void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
-void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
-void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
-void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
-void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
-void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
-void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
-void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
-flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
-void usart_flag_clear(usart_type* usart_x, uint32_t flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_usb.h

@@ -1,711 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_usb.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 usb header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup USB
-  * @{
-  */
-
-/* define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_USB_H
-#define __AT32F403A_407_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-
-
-/** @defgroup USB_interrupts_definition
-  * @brief usb interrupt mask
-  * @{
-  */
-
-#define USB_LSOF_INT                     ((uint32_t)0x00000100) /*!< usb lost sof interrupt */
-#define USB_SOF_INT                      ((uint32_t)0x00000200) /*!< usb sof interrupt */
-#define USB_RST_INT                      ((uint32_t)0x00000400) /*!< usb reset interrupt */
-#define USB_SP_INT                       ((uint32_t)0x00000800) /*!< usb suspend interrupt */
-#define USB_WK_INT                       ((uint32_t)0x00001000) /*!< usb wakeup interrupt */
-#define USB_BE_INT                       ((uint32_t)0x00002000) /*!< usb bus error interrupt */
-#define USB_UCFOR_INT                    ((uint32_t)0x00004000) /*!< usb core fifo overrun interrupt */
-#define USB_TC_INT                       ((uint32_t)0x00008000) /*!< usb transmission completed interrupt */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_interrupt_flags_definition
-  * @brief usb interrupt flag
-  * @{
-  */
-
-#define USB_EPT_NUM_FLAG                 ((uint32_t)0x0000000F) /*!< usb endpoint number */
-#define USB_INOUT_FLAG                   ((uint32_t)0x00000010) /*!< usb in/out transcation flag */
-#define USB_LSOF_FLAG                    ((uint32_t)0x00000100) /*!< usb lost sof flag */
-#define USB_SOF_FLAG                     ((uint32_t)0x00000200) /*!< usb sof flag */
-#define USB_RST_FLAG                     ((uint32_t)0x00000400) /*!< usb reset flag */
-#define USB_SP_FLAG                      ((uint32_t)0x00000800) /*!< usb suspend flag */
-#define USB_WK_FLAG                      ((uint32_t)0x00001000) /*!< usb wakeup flag */
-#define USB_BE_FLAG                      ((uint32_t)0x00002000) /*!< usb bus error flag */
-#define USB_UCFOR_FLAG                   ((uint32_t)0x00004000) /*!< usb core fifo overrun flag */
-#define USB_TC_FLAG                      ((uint32_t)0x00008000) /*!< usb transmission completed flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_endpoint_register_bit_definition
-  * @brief usb endpoint register bit define
-  * @{
-  */
-
-#define USB_EPTADDR                      ((uint32_t)0x0000000F) /*!< usb endpoint address */
-#define USB_TXSTS                        ((uint32_t)0x00000030) /*!< usb tx status */
-#define USB_TXDTS                        ((uint32_t)0x00000040) /*!< usb tx data toggle synchronization */
-#define USB_TXTC                         ((uint32_t)0x00000080) /*!< usb tx transcation completed */
-#define USB_EXF                          ((uint32_t)0x00000100) /*!< usb endpoint extend funtion */
-#define USB_TRANS_TYPE                   ((uint32_t)0x00000600) /*!< usb transfer type */
-#define USB_SETUPTC                      ((uint32_t)0x00000800) /*!< usb setup transcation completed */
-#define USB_RXSTS                        ((uint32_t)0x00003000) /*!< usb rx status */
-#define USB_RXDTS                        ((uint32_t)0x00004000) /*!< usb rx data toggle synchronization */
-#define USB_RXTC                         ((uint32_t)0x00008000) /*!< usb rx transcation completed */
-
-#define USB_EPT_BIT_MASK                 (uint32_t)(USB_TXTC | USB_SETUPTC | USB_EPTADDR | USB_EXF | USB_RXTC | USB_TRANS_TYPE) /*!< usb bit mask */
-#define USB_TX_MASK                      (USB_TXSTS | USB_EPT_BIT_MASK) /*!< usb tx mask */
-#define USB_RX_MASK                      (USB_RXSTS | USB_EPT_BIT_MASK) /*!< usb rx mask */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_endpoint_tx_and_rx_status_definition
-  * @brief usb endpoint tx and rx status
-  * @{
-  */
-
-#define USB_TX_DISABLE                   ((uint32_t)0x00000000) /*!< usb tx status disable */
-#define USB_TX_STALL                     ((uint32_t)0x00000010) /*!< usb tx status stall */
-#define USB_TX_NAK                       ((uint32_t)0x00000020) /*!< usb tx status nak */
-#define USB_TX_VALID                     ((uint32_t)0x00000030) /*!< usb tx status valid */
-
-#define USB_TXDTS0                       ((uint32_t)0x00000010) /*!< usb tx data toggle bit 0 */
-#define USB_TXDTS1                       ((uint32_t)0x00000020) /*!< usb tx data toggle bit 1 */
-
-#define USB_RX_DISABLE                   ((uint32_t)0x00000000) /*!< usb rx status disable */
-#define USB_RX_STALL                     ((uint32_t)0x00001000) /*!< usb rx status stall */
-#define USB_RX_NAK                       ((uint32_t)0x00002000) /*!< usb rx status nak */
-#define USB_RX_VALID                     ((uint32_t)0x00003000) /*!< usb rx status valid */
-
-#define USB_RXDTS0                       ((uint32_t)0x00001000) /*!< usb rx data toggle bit 0 */
-#define USB_RXDTS1                       ((uint32_t)0x00002000) /*!< usb rx data toggle bit 1 */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_device_endpoint_register_type_definition
-  * @brief usb device endpoint register type define
-  * @{
-  */
-
-#define USB_EPT_CONTROL                  ((uint32_t)0x00000200) /*!< usb endpoint transfer type control */
-#define USB_EPT_BULK                     ((uint32_t)0x00000000) /*!< usb endpoint transfer type bulk */
-#define USB_EPT_INT                      ((uint32_t)0x00000600) /*!< usb endpoint transfer type interrupt */
-#define USB_EPT_ISO                      ((uint32_t)0x00000400) /*!< usb endpoint transfer type iso */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_buffer_table_default_offset_address_definition
-  * @brief usb buffer table default offset address
-  * @{
-  */
-
-#define USB_BUFFER_TABLE_ADDRESS          0x0000 /*!< usb buffer table address */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_packet_buffer_start_address_definition
-  * @brief usb packet buffer start address
-  * @{
-  */
-
-#define USB_PACKET_BUFFER_ADDRESS         0x40006000 /*!< usb buffer address */
-#define USB_PACKET_BUFFER_ADDRESS_EX      0x40007800 /*!< usb buffer extend address */
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_exported_enum_types
-  * @{
-  */
-
-/**
-  * @brief usb endpoint number define
-  */
-typedef enum
-{
-  USB_EPT0                               = 0x00, /*!< usb endpoint 0 */
-  USB_EPT1                               = 0x01, /*!< usb endpoint 1 */
-  USB_EPT2                               = 0x02, /*!< usb endpoint 2 */
-  USB_EPT3                               = 0x03, /*!< usb endpoint 3 */
-  USB_EPT4                               = 0x04, /*!< usb endpoint 4 */
-  USB_EPT5                               = 0x05, /*!< usb endpoint 5 */
-  USB_EPT6                               = 0x06, /*!< usb endpoint 6 */
-  USB_EPT7                               = 0x07  /*!< usb endpoint 7 */
-} usb_ept_number_type;
-
-/**
-  * @brief usb endpoint max num define
-  */
-#ifndef USB_EPT_MAX_NUM
-#define USB_EPT_MAX_NUM                   8  /*!< usb device support endpoint number */
-#endif
-/**
-  * @brief endpoint transfer type define
-  */
-typedef enum
-{
-  EPT_CONTROL_TYPE                       = 0x00, /*!< usb transfer type control */
-  EPT_BULK_TYPE                          = 0x01, /*!< usb transfer type bulk */
-  EPT_INT_TYPE                           = 0x02, /*!< usb transfer type interrut */
-  EPT_ISO_TYPE                           = 0x03  /*!< usb transfer type iso */
-}ept_trans_type;
-
-/**
-  * @brief endpoint endpoint direction define
-  */
-typedef enum
-{
-  EPT_IN                                 = 0x00, /*!< usb endpoint direction in */
-  EPT_OUT                                = 0x01  /*!< usb endpoint direction out */
-}ept_inout_type;
-
-/**
-  * @brief data transfer direction
-  */
-typedef enum
-{
-  DATA_TRANS_OUT                         = 0x00, /*!< usb data transfer direction out */
-  DATA_TRANS_IN                          = 0x01  /*!< usb data transfer direction in */
-}data_trans_dir;
-
-/**
-  * @brief usb clock select
-  */
-typedef enum
-{
-  USB_CLK_HICK,
-  USB_CLK_HEXT
-}usb_clk48_s;
-/**
-  * @}
-  */
-
-/** @defgroup USB_macro_definition
-  * @{
-  */
-
-/**
-  * @brief  set usb endpoint tx status
-  * @param  ept_num: endpoint number
-  * @param  new_sts: the new tx status of this endpoint number
-  * @retval none
-  */
-#define USB_SET_TXSTS(ept_num, new_sts) { \
-  register uint16_t epsts = (USB->ept[ept_num]) & USB_TX_MASK; \
-  if((new_sts & USB_TXDTS0) != 0)                    \
-    epsts ^= USB_TXDTS0;                             \
-  if((new_sts & USB_TXDTS1) != 0)                    \
-    epsts ^= USB_TXDTS1;                             \
-  USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
-}
-
-/**
-  * @brief  set usb endpoint rx status
-  * @param  ept_num: endpoint number
-  * @param  new_sts: the new rx status of this endpoint number
-  * @retval none
-  */
-#define USB_SET_RXSTS(ept_num, new_sts) { \
-  register uint16_t epsts = (USB->ept[ept_num]) & USB_RX_MASK; \
-  if((new_sts & USB_RXDTS0) != 0) \
-    epsts ^= USB_RXDTS0; \
-  if((new_sts & USB_RXDTS1) != 0) \
-    epsts ^= USB_RXDTS1; \
-  USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
-}
-
-/**
-  * @brief  get usb endpoint tx/rx length address
-  * @param  eptn: endpoint number
-  * @retval the length address of tx/rx
-  */
-#define GET_TX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 2) * 2 + g_usb_packet_address)
-#define GET_RX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 6) * 2 + g_usb_packet_address)
-
-/**
-  * @brief  get usb endpoint tx/rx data length
-  * @param  eptn: endpoint number
-  * @retval the length of tx/rx
-  */
-#define USB_GET_TX_LEN(eptn)  ((uint16_t)(*GET_TX_LEN_ADDR(eptn)) & 0x3ff)
-#define USB_GET_RX_LEN(eptn)  ((uint16_t)(*GET_RX_LEN_ADDR(eptn)) & 0x3ff)
-
-/**
-  * @brief  double buffer mode get endpoint buf0/buf1 data length
-  * @param  eptn: endpoint number
-  * @retval the length of buf0/buf1
-  */
-#define USB_DBUF0_GET_LEN(eptn) USB_GET_TX_LEN(eptn)
-#define USB_DBUF1_GET_LEN(eptn) USB_GET_RX_LEN(eptn)
-
-/**
-  * @brief  set usb length of rx buffer
-  * @param  reg: usb rx length register
-  * @param  len: rx max length
-  * @param  blks: number of blocks
-  */
-#define BLK32(reg, len, blks) { \
-  blks = (len) >> 5; \
-  if(((len) & 0x1F) == 0) \
-    blks --; \
-  *reg = ((uint16_t)((blks) << 10) | 0x8000); \
-}
-
-#define BLK2(reg, len, blks) { \
-  blks = (len) >> 1; \
-  if(((len) & 0x1) == 0) \
-    blks ++; \
-  *reg = (uint16_t)((blks) << 10); \
-}
-
-#define USB_SET_RXLEN_REG(reg, len) { \
-  uint16_t blks;                         \
-  if(len > 62)                         \
-  {                                      \
-    BLK32(reg, len, blks);             \
-  }                                      \
-  else                                   \
-  {                                      \
-    BLK2(reg, len, blks);              \
-  }                                      \
-}
-
-/**
-  * @brief  set endpoint tx/rx transfer length
-  * @param  eptn: endpoint number
-  * @param  len: transfer length
-  * @retval none
-  */
-#define USB_SET_TXLEN(eptn, len) (*(GET_TX_LEN_ADDR(eptn)) = (len))
-#define USB_SET_RXLEN(eptn, len) { \
-  uint32_t *rx_reg = GET_RX_LEN_ADDR(eptn); \
-  USB_SET_RXLEN_REG(rx_reg, (len)); \
-}
-
-/**
-  * @brief  double buffer mode set endpoint rx buf0 length
-  * @param  eptn: endpoint number
-  * @param  len: transfer length
-  * @retval none
-  */
-#define USB_OUT_EPT_DOUBLE_BUF0(eptn, len) { \
-  uint32_t *rx_reg = GET_TX_LEN_ADDR(eptn); \
-  USB_SET_RXLEN_REG(rx_reg, (len)); \
-}
-
-/**
-  * @brief  double buffer mode set endpoint buf0 length
-  * @param  eptn: endpoint number
-  * @param  len: transfer length
-  * @param  dir: transfer direction(in/out)
-  * @retval none
-  */
-#define USB_SET_EPT_DOUBLE_BUF0_LEN(eptn, len, dir) { \
-  if(dir == DATA_TRANS_OUT) \
-  { \
-    USB_OUT_EPT_DOUBLE_BUF0(eptn, len); \
-  } \
-  else \
-  { \
-    *(GET_TX_LEN_ADDR(eptn)) = (len); \
-  } \
-}
-
-/**
-  * @brief  double buffer mode set endpoint buf1 length
-  * @param  eptn: endpoint number
-  * @param  len: transfer length
-  * @param  dir: transfer direction(in/out)
-  * @retval none
-  */
-#define USB_SET_EPT_DOUBLE_BUF1_LEN(eptn, len, dir) { \
-  if(dir == DATA_TRANS_OUT) \
-  { \
-    USB_SET_RXLEN(eptn, len); \
-  } \
-  else \
-  { \
-    *(GET_RX_LEN_ADDR(eptn)) = (len); \
-  } \
-}
-
-/**
-  * @brief  set usb endpoint tx/rx fifo address
-  * @param  eptn: endpoint number
-  * @param  address: offset of the fifo address
-  * @retval none
-  */
-#define USB_SET_TX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8) * 2 + g_usb_packet_address) = address)
-#define USB_SET_RX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8 + 4) * 2 + g_usb_packet_address) = address)
-
-/**
-  * @brief  set double buffer mode usb endpoint buf0/buf1 fifo address
-  * @param  eptn: endpoint number
-  * @param  address: offset of the fifo address
-  * @retval none
-  */
-#define USB_SET_DOUBLE_BUFF0_ADDRESS(eptn, address) (USB_SET_TX_ADDRESS(eptn, address))
-#define USB_SET_DOUBLE_BUFF1_ADDRESS(eptn, address) (USB_SET_RX_ADDRESS(eptn, address))
-
-/**
-  * @brief  set usb tx/rx toggle
-  * @param  eptn: endpoint number
-  * @retval none
-  */
-#define USB_TOGGLE_TXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_TXDTS | USB_RXTC | USB_TXTC))
-#define USB_TOGGLE_RXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_RXDTS | USB_RXTC | USB_TXTC))
-
-/**
-  * @brief  clear usb tx/rx toggle
-  * @param  eptn: endpoint number
-  * @retval none
-  */
-#define USB_CLEAR_TXDTS(eptn) { \
-  if(USB->ept_bit[eptn].txdts != 0) \
-    USB_TOGGLE_TXDTS(eptn); \
-}
-#define USB_CLEAR_RXDTS(eptn) { \
-  if(USB->ept_bit[eptn].rxdts != 0) \
-    USB_TOGGLE_RXDTS(eptn); \
-}
-
-/**
-  * @brief set usb endpoint type
-  */
-
-/**
-  * @brief  set usb transfer type
-  * @param  eptn: endpoint number
-  * @param  type: transfer type
-  * @retval none
-  */
-#define USB_SET_TRANS_TYPE(eptn, type) (USB->ept[eptn] = (USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_TRANS_TYPE)) | type)
-
-/**
-  * @brief  set/clear usb extend function
-  * @param  eptn: endpoint number
-  * @retval none
-  */
-#define USB_SET_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | ((USB->ept[eptn] | USB_EXF) & USB_EPT_BIT_MASK))
-#define USB_CLEAR_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | (USB->ept[eptn] & ((~USB_EXF) & USB_EPT_BIT_MASK)))
-
-/**
-  * @brief  set usb device address
-  * @param  eptn: endpoint number
-  * @param  address: device address
-  * @retval none
-  */
-#define USB_SET_EPT_ADDRESS(eptn, address) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_EPTADDR)) | address))
-
-/**
-  * @brief  free buffer used by application
-  * @param  eptn: endpoint number
-  * @param  inout: transfer direction
-  * @retval none
-  */
-#define USB_FREE_DB_USER_BUFFER(eptn, inout) { \
-  if(inout == DATA_TRANS_IN) \
-  { \
-    USB_TOGGLE_RXDTS(eptn); \
-  } \
-  else \
-  { \
-    USB_TOGGLE_TXDTS(eptn); \
-  } \
-}
-
-/**
-  * @brief  clear tx/rx transfer completed flag
-  * @param  eptn: endpoint number
-  * @retval none
-  */
-#define USB_CLEAR_TXTC(eptn)    (USB->ept[eptn] &= 0xFF7F & USB_EPT_BIT_MASK)
-#define USB_CLEAR_RXTC(eptn)    (USB->ept[eptn] &= 0x7FFF & USB_EPT_BIT_MASK)
-
-/**
-  * @brief  set/clear endpoint double buffer mode
-  * @param  eptn: endpoint number
-  * @retval none
-  */
-#define USB_SET_EPT_DOUBLE_BUFFER(eptn)   USB_SET_EXF(eptn)
-#define USB_CLEAR_EPT_DOUBLE_BUFFER(eptn) USB_CLEAR_EXF(eptn)
-
-/**
-  * @}
-  */
-
-/** @defgroup USB_exported_types
-  * @{
-  */
-
-/**
-  * @brief  usb endpoint infomation structure definition
-  */
-typedef struct
-{
-  uint8_t                                eptn;                        /*!< endpoint register number (0~7) */
-  uint8_t                                ept_address;                 /*!< endpoint address */
-  uint8_t                                inout;                       /*!< endpoint dir DATA_TRANS_IN or DATA_TRANS_OUT */
-  uint8_t                                trans_type;                  /*!< endpoint type:
-                                                                           EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
-  uint16_t                               tx_addr;                     /*!< endpoint tx buffer offset address */
-  uint16_t                               rx_addr;                     /*!< endpoint rx buffer offset address */
-  uint16_t                               maxpacket;                   /*!< endpoint max packet*/
-  uint8_t                                is_double_buffer;            /*!< endpoint double buffer flag */
-  uint8_t                                stall;                       /*!< endpoint is stall state */
-  uint16_t                               status;                      /*!< endpoint status */
-
-  /* transmission buffer and count */
-  uint16_t                               total_len;                   /*!< endpoint transmission total length */
-  uint16_t                               trans_len;                   /*!< endpoint transmission length*/
-  uint8_t                                *trans_buf;                  /*!< endpoint transmission buffer */
-
-  uint16_t                               last_len;                    /*!< last transfer length */
-  uint16_t                               ept0_slen;                   /*!< endpoint 0 transfer sum length */
-}usb_ept_info;
-
-/**
- * @brief type define usb register all
- */
-typedef struct
-{
-  /**
-  * @brief usb endpoint register, offset:0x00
-  */
-  union
-  {
-    __IO uint32_t ept[8];
-    struct
-    {
-      __IO uint32_t eptaddr                  : 4; /* [3:0] */
-      __IO uint32_t txsts                    : 2; /* [5:4] */
-      __IO uint32_t txdts                    : 1; /* [6] */
-      __IO uint32_t txtc                     : 1; /* [7] */
-      __IO uint32_t exf                      : 1; /* [8] */
-      __IO uint32_t trans_type               : 2; /* [10:9] */
-      __IO uint32_t setuptc                  : 1; /* [11] */
-      __IO uint32_t rxsts                    : 2; /* [13:12] */
-      __IO uint32_t rxdts                    : 1; /* [14] */
-      __IO uint32_t rxtc                     : 1; /* [15] */
-      __IO uint32_t reserved1                : 16; /* [31:16] */
-    } ept_bit[8];
-  };
-
-  __IO uint32_t reserved1[8];
-
-  /**
-  * @brief usb control register, offset:0x40
-  */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t csrst                    : 1; /* [0] */
-      __IO uint32_t disusb                   : 1; /* [1] */
-      __IO uint32_t lpm                      : 1; /* [2] */
-      __IO uint32_t ssp                      : 1; /* [3] */
-      __IO uint32_t gresume                  : 1; /* [4] */
-      __IO uint32_t reserved1                : 3; /* [7:5] */
-      __IO uint32_t lsofien                  : 1; /* [8] */
-      __IO uint32_t sofien                   : 1; /* [9] */
-      __IO uint32_t rstien                   : 1; /* [10] */
-      __IO uint32_t spien                    : 1; /* [11] */
-      __IO uint32_t wkien                    : 1; /* [12] */
-      __IO uint32_t beien                    : 1; /* [13] */
-      __IO uint32_t ucforien                 : 1; /* [14] */
-      __IO uint32_t tcien                    : 1; /* [15] */
-      __IO uint32_t reserved2                : 16; /* [31:16] */
-    } ctrl_bit;
-  };
-
-  /**
-  * @brief usb interrupt status register, offset:0x44
-  */
-  union
-  {
-    __IO uint32_t intsts;
-    struct
-    {
-      __IO uint32_t ept_num                  : 4; /* [3:0] */
-      __IO uint32_t inout                    : 1; /* [4] */
-      __IO uint32_t reserved1                : 3; /* [7:5] */
-      __IO uint32_t lsof                     : 1; /* [8] */
-      __IO uint32_t sof                      : 1; /* [9] */
-      __IO uint32_t rst                      : 1; /* [10] */
-      __IO uint32_t sp                       : 1; /* [11] */
-      __IO uint32_t wk                       : 1; /* [12] */
-      __IO uint32_t be                       : 1; /* [13] */
-      __IO uint32_t ucfor                    : 1; /* [14] */
-      __IO uint32_t tc                       : 1; /* [15] */
-      __IO uint32_t reserved2                : 16; /* [31:16] */
-    } intsts_bit;
-  };
-
-  /**
-  * @brief usb frame number register, offset:0x48
-  */
-  union
-  {
-    __IO uint32_t sofrnum;
-    struct
-    {
-      __IO uint32_t sofnum                   : 11; /* [10:0] */
-      __IO uint32_t lsofnum                  : 2; /* [12:11] */
-      __IO uint32_t clck                     : 1; /* [13] */
-      __IO uint32_t dmsts                    : 1; /* [14] */
-      __IO uint32_t dpsts                    : 1; /* [15] */
-      __IO uint32_t reserved1                : 16; /* [31:16] */
-    } sofrnum_bit;
-  };
-
-  /**
-  * @brief usb device address register, offset:0x4c
-  */
-  union
-  {
-    __IO uint32_t devaddr;
-    struct
-    {
-      __IO uint32_t addr                     : 7; /* [6:0] */
-      __IO uint32_t cen                      : 1; /* [7] */
-      __IO uint32_t reserved1                : 24; /* [31:8] */
-    } devaddr_bit;
-  };
-
-  /**
-  * @brief usb buffer address register, offset:0x50
-  */
-  union
-  {
-    __IO uint32_t buftbl;
-    struct
-    {
-      __IO uint32_t reserved1                : 3; /* [2:0] */
-      __IO uint32_t btaddr                   : 13; /* [15:3] */
-      __IO uint32_t reserved2                : 16; /* [31:16] */
-    } buftbl_bit;
-  };
-  __IO uint32_t reserved2[3];
-  /**
-  * @brief usb cfg control register, offset:0x60
-  */
-  union
-  {
-    __IO uint32_t cfg;
-    struct
-    {
-      __IO uint32_t sofouten                 : 1; /* [0] */
-      __IO uint32_t puo                      : 1; /* [1] */
-      __IO uint32_t reserved1                : 30; /* [31:2] */
-    } cfg_bit;
-  };
-
-} usbd_type;
-
-/**
-  * @}
-  */
-
-#define USB                              ((usbd_type *) USBFS_BASE)
-
-typedef usbd_type usb_reg_type;
-extern uint32_t g_usb_packet_address;
-
-/** @defgroup USB_exported_functions
-  * @{
-  */
-
-void usb_dev_init(usbd_type *usbx);
-void usb_connect(usbd_type *usbx);
-void usb_disconnect(usbd_type *usbx);
-void usb_usbbufs_enable(usbd_type *usbx, confirm_state state);
-void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info);
-void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info);
-void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
-void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
-void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state);
-void usb_set_address(usbd_type *usbx, uint8_t address);
-void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info);
-void usb_enter_suspend(usbd_type *usbx);
-void usb_exit_suspend(usbd_type *usbx);
-void usb_remote_wkup_set(usbd_type *usbx);
-void usb_remote_wkup_clear(usbd_type *usbx);
-uint16_t usb_buffer_malloc(uint16_t maxpacket);
-void usb_buffer_free(void);
-flag_status usb_flag_get(usbd_type *usbx, uint16_t flag);
-void usb_flag_clear(usbd_type *usbx, uint16_t flag);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_wdt.h

@@ -1,183 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_wdt.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 wdt header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_WDT_H
-#define __AT32F403A_407_WDT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup WDT
-  * @{
-  */
-
-
-/** @defgroup WDT_flags_definition
-  * @brief wdt flag
-  * @{
-  */
-
-#define WDT_DIVF_UPDATE_FLAG             ((uint16_t)0x0001) /*!< wdt division value update complete flag */
-#define WDT_RLDF_UPDATE_FLAG             ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup WDT_exported_types
-  * @{
-  */
-
-/**
-  * @brief wdt division value type
-  */
-typedef enum
-{
-  WDT_CLK_DIV_4                          = 0x00, /*!< wdt clock divider value is 4 */
-  WDT_CLK_DIV_8                          = 0x01, /*!< wdt clock divider value is 8 */
-  WDT_CLK_DIV_16                         = 0x02, /*!< wdt clock divider value is 16 */
-  WDT_CLK_DIV_32                         = 0x03, /*!< wdt clock divider value is 32 */
-  WDT_CLK_DIV_64                         = 0x04, /*!< wdt clock divider value is 64 */
-  WDT_CLK_DIV_128                        = 0x05, /*!< wdt clock divider value is 128 */
-  WDT_CLK_DIV_256                        = 0x06  /*!< wdt clock divider value is 256 */
-} wdt_division_type;
-
-/**
-  * @brief wdt cmd value type
-  */
-typedef enum
-{
-  WDT_CMD_LOCK                           = 0x0000, /*!< disable write protection command */
-  WDT_CMD_UNLOCK                         = 0x5555, /*!< enable write protection command */
-  WDT_CMD_ENABLE                         = 0xCCCC, /*!< enable wdt command */
-  WDT_CMD_RELOAD                         = 0xAAAA  /*!< reload command */
-} wdt_cmd_value_type;
-
-/**
-  * @brief type define wdt register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief wdt cmd register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t cmd;
-    struct
-    {
-      __IO uint32_t cmd                  : 16;/* [15:0] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } cmd_bit;
-  };
-
-  /**
-    * @brief wdt div register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t div;
-    struct
-    {
-      __IO uint32_t div                   : 3; /* [2:0] */
-      __IO uint32_t reserved1            : 29;/* [31:3] */
-    } div_bit;
-  };
-
-   /**
-    * @brief wdt rld register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t rld;
-    struct
-    {
-      __IO uint32_t rld                  : 12;/* [11:0] */
-      __IO uint32_t reserved1            : 20;/* [31:12] */
-    } rld_bit;
-  };
-
-  /**
-  * @brief wdt sts register, offset:0x0C
-  */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t divf                 : 1; /* [0] */
-      __IO uint32_t rldf                 : 1; /* [1] */
-      __IO uint32_t reserved1            : 30;/* [31:2] */
-    } sts_bit;
-  };
-
-} wdt_type;
-
-/**
-  * @}
-  */
-
-#define WDT                             ((wdt_type *) WDT_BASE)
-
-/** @defgroup WDT_exported_functions
-  * @{
-  */
-
-void wdt_enable(void);
-void wdt_counter_reload(void);
-void wdt_reload_value_set(uint16_t reload_value);
-void wdt_divider_set(wdt_division_type division);
-void wdt_register_write_enable( confirm_state new_state);
-flag_status wdt_flag_get(uint16_t wdt_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_wwdt.h

@@ -1,158 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_wwdt.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 wwdt header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_WWDT_H
-#define __AT32F403A_407_WWDT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup WWDT
-  * @{
-  */
-
-/** @defgroup WWDT_enable_bit_definition
-  * @brief wwdt enable bit
-  * @{
-  */
-
-#define WWDT_EN_BIT                      ((uint32_t)0x00000080) /*!< wwdt enable bit */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDT_exported_types
-  * @{
-  */
-
-/**
-  * @brief wwdt division type
-  */
-typedef enum
-{
-  WWDT_PCLK1_DIV_4096                    = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
-  WWDT_PCLK1_DIV_8192                    = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
-  WWDT_PCLK1_DIV_16384                   = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
-  WWDT_PCLK1_DIV_32768                   = 0x03  /*!< wwdt counter clock = (pclk1/4096)/8) */
-} wwdt_division_type;
-
-/**
-  * @brief type define wwdt register all
-  */
-typedef struct
-{
-
-  /**
-    * @brief wwdt ctrl register, offset:0x00
-    */
-  union
-  {
-    __IO uint32_t ctrl;
-    struct
-    {
-      __IO uint32_t cnt                  : 7; /* [6:0] */
-      __IO uint32_t wwdten               : 1; /* [7] */
-      __IO uint32_t reserved1            : 24;/* [31:8] */
-    } ctrl_bit;
-  };
-
-  /**
-    * @brief wwdt cfg register, offset:0x04
-    */
-  union
-  {
-    __IO uint32_t cfg;
-    struct
-    {
-      __IO uint32_t win                  : 7; /* [6:0] */
-      __IO uint32_t div                  : 2; /* [8:7] */
-      __IO uint32_t rldien               : 1; /* [9] */
-      __IO uint32_t reserved1            : 22;/* [31:10] */
-    } cfg_bit;
-  };
-
-  /**
-    * @brief wwdt cfg register, offset:0x08
-    */
-  union
-  {
-    __IO uint32_t sts;
-    struct
-    {
-      __IO uint32_t rldf                 : 1; /* [0] */
-      __IO uint32_t reserved1            : 31;/* [31:1] */
-    } sts_bit;
-  };
-
-} wwdt_type;
-
-/**
-  * @}
-  */
-
-#define WWDT                             ((wwdt_type *) WWDT_BASE)
-
-/** @defgroup WWDT_exported_functions
-  * @{
-  */
-
-void wwdt_reset(void);
-void wwdt_divider_set(wwdt_division_type division);
-void wwdt_flag_clear(void);
-void wwdt_enable(uint8_t wwdt_cnt);
-void wwdt_interrupt_enable(void);
-flag_status wwdt_flag_get(void);
-void wwdt_counter_set(uint8_t wwdt_cnt);
-void wwdt_window_counter_set(uint8_t window_cnt);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/inc/at32f403a_407_xmc.h

@@ -1,568 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_xmc.h
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    at32f403a_407 xmc header file
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __AT32F403A_407_XMC_H
-#define __AT32F403A_407_XMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "at32f403a_407.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @addtogroup XMC
-  * @{
-  */
-
-/** @defgroup XMC_exported_types
-  * @{
-  */
-
-/**
-  * @brief xmc data address bus multiplexing type
-  */
-typedef enum
-{
-  XMC_DATA_ADDR_MUX_DISABLE              = 0x00000000, /*!< xmc address/data multiplexing disable */
-  XMC_DATA_ADDR_MUX_ENABLE               = 0x00000002  /*!< xmc address/data multiplexing enable */
-} xmc_data_addr_mux_type;
-
-/**
-  * @brief xmc burst access mode type
-  */
-typedef enum
-{
-  XMC_BURST_MODE_DISABLE                 = 0x00000000, /*!< xmc burst mode disable */
-  XMC_BURST_MODE_ENABLE                  = 0x00000100  /*!< xmc burst mode enable */
-} xmc_burst_access_mode_type;
-
-/**
-  * @brief xmc asynchronous wait type
-  */
-typedef enum
-{
-  XMC_ASYN_WAIT_DISABLE                  = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
-  XMC_ASYN_WAIT_ENABLE                   = 0x00008000  /*!< xmc wait signal during asynchronous transfers enable */
-} xmc_asyn_wait_type;
-
-/**
-  * @brief xmc wrapped mode type
-  */
-typedef enum
-{
-  XMC_WRAPPED_MODE_DISABLE               = 0x00000000, /*!< xmc direct wrapped burst is disbale */
-  XMC_WRAPPED_MODE_ENABLE                = 0x00000400  /*!< xmc direct wrapped burst is enable */
-} xmc_wrap_mode_type;
-
-/**
-  * @brief xmc write operation type
-  */
-typedef enum
-{
-  XMC_WRITE_OPERATION_DISABLE            = 0x00000000, /*!< xmc write operations is disable */
-  XMC_WRITE_OPERATION_ENABLE             = 0x00001000  /*!< xmc write operations is enable */
-} xmc_write_operation_type;
-
-/**
-  * @brief xmc wait signal type
-  */
-typedef enum
-{
-  XMC_WAIT_SIGNAL_DISABLE                = 0x00000000, /*!< xmc nwait signal is disable */
-  XMC_WAIT_SIGNAL_ENABLE                 = 0x00002000  /*!< xmc nwait signal is enable */
-} xmc_wait_signal_type;
-
-/**
-  * @brief xmc write burst type
-  */
-typedef enum
-{
-  XMC_WRITE_BURST_SYN_DISABLE            = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
-  XMC_WRITE_BURST_SYN_ENABLE             = 0x00080000  /*!< xmc write operations are performed in synchronous mode */
-} xmc_write_burst_type;
-
-/**
-  * @brief xmc extended mode type
-  */
-typedef enum
-{
-  XMC_WRITE_TIMING_DISABLE               = 0x00000000, /*!< xmc write timing disable */
-  XMC_WRITE_TIMING_ENABLE                = 0x00004000  /*!< xmc write timing enable */
-} xmc_extended_mode_type;
-
-/**
-  * @brief xmc nand wait type
-  */
-typedef enum
-{
-  XMC_WAIT_OPERATION_DISABLE             = 0x00000000, /*!< xmc wait operation for the nand flash memory bank disable */
-  XMC_WAIT_OPERATION_ENABLE              = 0x00000002  /*!< xmc wait operation for the nand flash memory bank enable */
-} xmc_nand_wait_type;
-
-/**
-  * @brief xmc ecc enable type
-  */
-typedef enum
-{
-  XMC_ECC_OPERATION_DISABLE              = 0x00000000, /*!< xmc ecc module disable */
-  XMC_ECC_OPERATION_ENABLE               = 0x00000040  /*!< xmc ecc module enable */
-} xmc_ecc_enable_type;
-
-/**
-  * @brief xmc nor/sram bank type
-  */
-typedef enum
-{
-  XMC_BANK1_NOR_SRAM1                    = 0x00000000, /*!< xmc nor/sram subbank1 */
-  XMC_BANK1_NOR_SRAM4                    = 0x00000003  /*!< xmc nor/sram subbank4 */
-} xmc_nor_sram_subbank_type;
-
-/**
-  * @brief xmc class bank type
-  */
-typedef enum
-{
-  XMC_BANK2_NAND                         = 0x00000010, /*!< xmc nand flash bank2 */
-} xmc_class_bank_type;
-
-/**
-  * @brief xmc memory type
-  */
-typedef enum
-{
-  XMC_DEVICE_SRAM                        = 0x00000000, /*!< xmc device choice sram */
-  XMC_DEVICE_PSRAM                       = 0x00000004, /*!< xmc device choice psram */
-  XMC_DEVICE_NOR                         = 0x00000008  /*!< xmc device choice nor flash */
-} xmc_memory_type;
-
-/**
-  * @brief xmc data width type
-  */
-typedef enum
-{
-  XMC_BUSTYPE_8_BITS                     = 0x00000000, /*!< xmc databuss width 8bits */
-  XMC_BUSTYPE_16_BITS                    = 0x00000010  /*!< xmc databuss width 16bits */
-} xmc_data_width_type;
-
-/**
-  * @brief xmc wait signal polarity type
-  */
-typedef enum
-{
-  XMC_WAIT_SIGNAL_LEVEL_LOW              = 0x00000000, /*!< xmc nwait active low */
-  XMC_WAIT_SIGNAL_LEVEL_HIGH             = 0x00000200  /*!< xmc nwait active high */
-} xmc_wait_signal_polarity_type;
-
-/**
-  * @brief xmc wait timing type
-  */
-typedef enum
-{
-  XMC_WAIT_SIGNAL_SYN_BEFORE             = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
-  XMC_WAIT_SIGNAL_SYN_DURING             = 0x00000800  /*!< xmc nwait signal is active during wait state */
-} xmc_wait_timing_type;
-
-/**
-  * @brief xmc access mode type
-  */
-typedef enum
-{
-  XMC_ACCESS_MODE_A                      = 0x00000000, /*!< xmc access mode A */
-  XMC_ACCESS_MODE_B                      = 0x10000000, /*!< xmc access mode B */
-  XMC_ACCESS_MODE_C                      = 0x20000000, /*!< xmc access mode C */
-  XMC_ACCESS_MODE_D                      = 0x30000000  /*!< xmc access mode D */
-} xmc_access_mode_type;
-
-/**
-  * @brief xmc ecc page size type
-  */
-typedef enum
-{
-  XMC_ECC_PAGESIZE_256_BYTES             = 0x00000000, /*!< xmc ecc page size 256 bytes */
-  XMC_ECC_PAGESIZE_512_BYTES             = 0x00020000, /*!< xmc ecc page size 512 bytes */
-  XMC_ECC_PAGESIZE_1024_BYTES            = 0x00040000, /*!< xmc ecc page size 1024 bytes */
-  XMC_ECC_PAGESIZE_2048_BYTES            = 0x00060000, /*!< xmc ecc page size 2048 bytes */
-  XMC_ECC_PAGESIZE_4096_BYTES            = 0x00080000, /*!< xmc ecc page size 4096 bytes */
-  XMC_ECC_PAGESIZE_8192_BYTES            = 0x000A0000  /*!< xmc ecc page size 8192 bytes */
-} xmc_ecc_pagesize_type;
-
-/**
-  * @brief xmc interrupt sources type
-  */
-typedef enum
-{
-  XMC_INT_RISING_EDGE                    = 0x00000008, /*!< xmc rising edge detection interrupt enable */
-  XMC_INT_LEVEL                          = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
-  XMC_INT_FALLING_EDGE                   = 0x00000020  /*!< xmc falling edge detection interrupt enable */
-} xmc_interrupt_sources_type;
-
-/**
-  * @brief xmc interrupt flag type
-  */
-typedef enum
-{
-  XMC_RISINGEDGE_FLAG                    = 0x00000001, /*!< xmc interrupt rising edge detection flag */
-  XMC_LEVEL_FLAG                         = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
-  XMC_FALLINGEDGE_FLAG                   = 0x00000004, /*!< xmc interrupt falling edge detection flag */
-  XMC_FEMPT_FLAG                         = 0x00000040  /*!< xmc fifo empty flag */
-} xmc_interrupt_flag_type;
-
-/**
-  * @brief   nor/sram banks timing parameters
-  */
-typedef struct
-{
-  xmc_nor_sram_subbank_type              subbank;             /*!< xmc nor/sram subbank */
-  xmc_extended_mode_type                 write_timing_enable; /*!< xmc nor/sram write timing enable */
-  uint32_t                               addr_setup_time;     /*!< xmc nor/sram address setup time */
-  uint32_t                               addr_hold_time;      /*!< xmc nor/sram address hold time */
-  uint32_t                               data_setup_time;     /*!< xmc nor/sram data setup time */
-  uint32_t                               bus_latency_time;    /*!< xmc nor/sram bus latency time */
-  uint32_t                               clk_psc;             /*!< xmc nor/sram clock prescale */
-  uint32_t                               data_latency_time;   /*!< xmc nor/sram data latency time */
-  xmc_access_mode_type                   mode;                /*!< xmc nor/sram access mode */
-} xmc_norsram_timing_init_type;
-
-/**
-  * @brief  xmc nor/sram init structure definition
-  */
-typedef struct
-{
-  xmc_nor_sram_subbank_type              subbank;             /*!< xmc nor/sram subbank */
-  xmc_data_addr_mux_type                 data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
-  xmc_memory_type                        device;              /*!< xmc nor/sram memory device */
-  xmc_data_width_type                    bus_type;            /*!< xmc nor/sram data bus width */
-  xmc_burst_access_mode_type             burst_mode_enable;   /*!< xmc nor/sram burst mode enable */
-  xmc_asyn_wait_type                     asynwait_enable;     /*!< xmc nor/sram nwait in asynchronous transfer enable */
-  xmc_wait_signal_polarity_type          wait_signal_lv;      /*!< xmc nor/sram nwait polarity */
-  xmc_wrap_mode_type                     wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
-  xmc_wait_timing_type                   wait_signal_config;  /*!< xmc nor/sram nwait timing configuration */
-  xmc_write_operation_type               write_enable;        /*!< xmc nor/sram write enable */
-  xmc_wait_signal_type                   wait_signal_enable;  /*!< xmc nor/sram nwait in synchronous transfer enable */
-  xmc_extended_mode_type                 write_timing_enable; /*!< xmc nor/sram read-write timing different */
-  xmc_write_burst_type                   write_burst_syn;     /*!< xmc nor/sram memory write mode control */
-} xmc_norsram_init_type;
-
-/**
-  * @brief  nand timing parameters xmc
-  */
-
-typedef struct
-{
-  xmc_class_bank_type                    class_bank;     /*!< xmc nand bank */
-  uint32_t                               mem_setup_time; /*!< xmc nand memory setup time */
-  uint32_t                               mem_waite_time; /*!< xmc nand memory wait time */
-  uint32_t                               mem_hold_time;  /*!< xmc nand memory hold time */
-  uint32_t                               mem_hiz_time;   /*!< xmc nand memory databus high resistance time */
-} xmc_nand_timinginit_type;
-
-/**
-  * @brief  xmc nand init structure definition
-  */
-
-typedef struct
-{
-  xmc_class_bank_type                    nand_bank;        /*!< xmc nand bank */
-  xmc_nand_wait_type                     wait_enable;      /*!< xmc wait feature enable */
-  xmc_data_width_type                    bus_type;         /*!< xmc nand bus width */
-  xmc_ecc_enable_type                    ecc_enable;       /*!< xmc nand ecc enable */
-  xmc_ecc_pagesize_type                  ecc_pagesize;     /*!< xmc nand ecc page size */
-  uint32_t                               delay_time_cycle; /*!< xmc nand cle to re delay */
-  uint32_t                               delay_time_ar;    /*!< xmc nand ale to re delay */
-} xmc_nand_init_type;
-
-typedef struct
-{
-  /**
-    * @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1 or 4
-    */
-  union
-  {
-    __IO uint32_t bk1ctrl;
-    struct
-    {
-      __IO uint32_t en                   : 1; /* [0] */
-      __IO uint32_t admuxen              : 1; /* [1] */
-      __IO uint32_t dev                  : 2; /* [3:2] */
-      __IO uint32_t extmdbw              : 2; /* [5:4] */
-      __IO uint32_t noren                : 1; /* [6] */
-      __IO uint32_t reserved1            : 1; /* [7] */
-      __IO uint32_t syncben              : 1; /* [8] */
-      __IO uint32_t nwpol                : 1; /* [9] */
-      __IO uint32_t wrapen               : 1; /* [10] */
-      __IO uint32_t nwtcfg               : 1; /* [11] */
-      __IO uint32_t wen                  : 1; /* [12] */
-      __IO uint32_t nwsen                : 1; /* [13] */
-      __IO uint32_t rwtd                 : 1; /* [14] */
-      __IO uint32_t nwasen               : 1; /* [15] */
-      __IO uint32_t crpgs                : 3; /* [18:16] */
-      __IO uint32_t mwmc                 : 1; /* [19] */
-      __IO uint32_t reserved2            : 12;/* [31:20] */
-    } bk1ctrl_bit;
-  };
-
-  /**
-    * @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1 or 4
-    */
-  union
-  {
-    __IO uint32_t bk1tmg;
-    struct
-    {
-      __IO uint32_t addrst               : 4; /* [3:0] */
-      __IO uint32_t addrht               : 4; /* [7:4] */
-      __IO uint32_t dtst                 : 8; /* [15:8] */
-      __IO uint32_t buslat               : 4; /* [19:16] */
-      __IO uint32_t clkpsc               : 4; /* [23:20] */
-      __IO uint32_t dtlat                : 4; /* [27:24] */
-      __IO uint32_t asyncm               : 2; /* [29:28] */
-      __IO uint32_t reserved1            : 2; /* [31:30] */
-    } bk1tmg_bit;
-  };
-
-} xmc_bank1_ctrl_tmg_reg_type;
-
-typedef struct
-{
-  /**
-    * @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1 or 4
-    */
-  union
-  {
-    __IO uint32_t bk1tmgwr;
-    struct
-    {
-      __IO uint32_t addrst               : 4; /* [3:0] */
-      __IO uint32_t addrht               : 4; /* [7:4] */
-      __IO uint32_t dtst                 : 8; /* [15:8] */
-      __IO uint32_t buslat               : 4; /* [19:16] */
-      __IO uint32_t reserved1            : 8; /* [27:20] */
-      __IO uint32_t asyncm               : 2; /* [29:28] */
-      __IO uint32_t reserved2            : 2; /* [31:30] */
-    } bk1tmgwr_bit;
-  };
-
-  /**
-    * @brief xmc bank1 reserved register
-    */
-  __IO uint32_t reserved1;
-
-} xmc_bank1_tmgwr_reg_type;
-
-/**
-  * @brief xmc bank1 registers
-  */
-typedef struct
-{
-  /**
-    * @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
-    */
-  xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
-
-  /**
-    * @brief xmc bank1 reserved register, offset:0x20~0x100
-    */
-  __IO uint32_t reserved1[57];
-
- /**
-    * @brief xmc bank1 tmgwr register, offset:0x104~0x11C
-    */
-  xmc_bank1_tmgwr_reg_type tmgwr_group[4];
-
-  /**
-    * @brief xmc bank1 reserved register, offset:0x120~0x21C
-    */
-  __IO uint32_t reserved2[63];
-
-  /**
-    * @brief xmc bank1 ext register, offset:0x220~0x22C
-    */
-  union
-  {
-    __IO uint32_t ext[4];
-    struct
-    {
-      __IO uint32_t buslatw2w            : 8; /* [7:0] */
-      __IO uint32_t buslatr2r            : 8; /* [15:8] */
-      __IO uint32_t reserved1            : 16;/* [31:16] */
-    } ext_bit[4];
-  };
-
-} xmc_bank1_type;
-
-/**
-  * @brief xmc bank2 registers
-  */
-typedef struct
-{
-  /**
-    * @brief xmc bk2ctrl register, offset:0x60
-    */
-  union
-  {
-    __IO uint32_t bk2ctrl;
-    struct
-    {
-      __IO uint32_t reserved1            : 1; /* [0] */
-      __IO uint32_t nwen                 : 1; /* [1] */
-      __IO uint32_t en                   : 1; /* [2] */
-      __IO uint32_t dev                  : 1; /* [3] */
-      __IO uint32_t extmdbw              : 2; /* [5:4] */
-      __IO uint32_t eccen                : 1; /* [6] */
-      __IO uint32_t reserved2            : 2; /* [8:7] */
-      __IO uint32_t tcr                  : 4; /* [12:9] */
-      __IO uint32_t tar                  : 4; /* [16:13] */
-      __IO uint32_t eccpgs               : 3; /* [19:17] */
-      __IO uint32_t reserved3            : 12;/* [31:20] */
-    } bk2ctrl_bit;
-  };
-
-  /**
-    * @brief xmc bk2is register, offset:0x64
-    */
-  union
-  {
-    __IO uint32_t bk2is;
-    struct
-    {
-      __IO uint32_t res                  : 1; /* [0] */
-      __IO uint32_t hls                  : 1; /* [1] */
-      __IO uint32_t fes                  : 1; /* [2] */
-      __IO uint32_t reien                : 1; /* [3] */
-      __IO uint32_t hlien                : 1; /* [4] */
-      __IO uint32_t feien                : 1; /* [5] */
-      __IO uint32_t fifoe                : 1; /* [6] */
-      __IO uint32_t reserved1            : 25;/* [31:7] */
-    } bk2is_bit;
-  };
-
-  /**
-  * @brief xmc bk2tmgmem register, offset:0x68
-  */
-  union
-  {
-    __IO uint32_t bk2tmgmem;
-    struct
-    {
-      __IO uint32_t cmst                 : 8; /* [7:0] */
-      __IO uint32_t cmwt                 : 8; /* [15:8] */
-      __IO uint32_t cmht                 : 8; /* [23:16] */
-      __IO uint32_t cmdhizt              : 8; /* [31:24] */
-    } bk2tmgmem_bit;
-  };
-
-  /**
-  * @brief xmc bk2tmgatt register, offset:0x6C
-  */
-  union
-  {
-    __IO uint32_t bk2tmgatt;
-    struct
-    {
-      __IO uint32_t amst                 : 8; /* [7:0] */
-      __IO uint32_t amwt                 : 8; /* [15:8] */
-      __IO uint32_t amht                 : 8; /* [23:16] */
-      __IO uint32_t amdhizt              : 8; /* [31:24] */
-    } bk2tmgatt_bit;
-  };
-
-  /**
-  * @brief xmc reserved register, offset:0x70
-  */
-  __IO uint32_t reserved1;
-
-  /**
-  * @brief xmc bk2ecc register, offset:0x74
-  */
-  union
-  {
-    __IO uint32_t bk2ecc;
-    struct
-    {
-      __IO uint32_t ecc                  : 32; /* [31:0] */
-    } bk2ecc_bit;
-  };
-
-} xmc_bank2_type;
-
-/**
-  * @}
-  */
-
-#define XMC_BANK1                        ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
-#define XMC_BANK2                        ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
-
-/** @defgroup XMC_exported_functions
-  * @{
-  */
-
-void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
-void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
-void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
-                                xmc_norsram_timing_init_type* xmc_w_timing_struct);
-void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
-void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
-                                          xmc_norsram_timing_init_type* xmc_w_timing_struct);
-void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
-void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
-void xmc_nand_reset(xmc_class_bank_type xmc_bank);
-void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
-void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
-                            xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
-void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
-void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
-                                       xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
-void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
-void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
-uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
-void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
-flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
-void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/at32/libraries/f403a_407/firmware/drivers/src/at32f403a_407_acc.c

@@ -1,218 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_acc.c
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    contains all the functions for the acc firmware library
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-#include "at32f403a_407_conf.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @defgroup ACC
-  * @brief ACC driver modules
-  * @{
-  */
-
-#ifdef ACC_MODULE_ENABLED
-
-/** @defgroup ACC_private_functions
-  * @{
-  */
-
-/**
-  * @brief  enable or disable the acc calibration mode.
-  * @param  acc_trim: specifies the acc calibration type.
-  *         this parameter can be one of the following values:
-  *         - ACC_CAL_HICKCAL
-  *         - ACC_CAL_HICKTRIM
-  * @param  new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
-  * @retval none
-  */
-void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
-{
-  if(acc_trim == ACC_CAL_HICKCAL)
-  {
-    ACC->ctrl1_bit.entrim = FALSE;
-  }
-  else
-  {
-    ACC->ctrl1_bit.entrim = TRUE;
-  }
-  ACC->ctrl1_bit.calon = new_state;
-}
-
-/**
-  * @brief  store calibration step data in acc's ctrl1 register.
-  * @param  step_value:  value to be stored in the acc's ctrl1 register
-  * @retval none
-  */
-void acc_step_set(uint8_t step_value)
-{
-  ACC->ctrl1_bit.step = step_value;
-}
-
-/**
-  * @brief  enable or disable the specified acc interrupts.
-  * @param  acc_int: specifies the acc interrupt sources to be enabled or disabled.
-  *         this parameter can be one of the following values:
-  *         - ACC_CALRDYIEN_INT
-  *         - ACC_EIEN_INT
-  * @param  new_state (TRUE or FALSE)
-  * @retval none
-  */
-void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
-{
-  if(acc_int == ACC_CALRDYIEN_INT)
-  {
-    ACC->ctrl1_bit.calrdyien = new_state;
-  }
-  else
-  {
-    ACC->ctrl1_bit.eien = new_state;
-  }
-}
-
-/**
-  * @brief  return the current acc hicktrim value.
-  * @param  none
-  * @retval 8-bit hicktrim value.
-  */
-uint8_t acc_hicktrim_get(void)
-{
-  return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
-}
-
-/**
-  * @brief  return the current acc hickcal value.
-  * @param  none
-  * @retval 8-bit hicktrim value.
-  */
-uint8_t acc_hickcal_get(void)
-{
-  return ((uint8_t)(ACC->ctrl2_bit.hickcal));
-}
-
-/**
-  * @brief  wtire the value to  acc c1 register.
-  * @param  acc_c1_value
-  * @retval none.
-  */
-void acc_write_c1(uint16_t acc_c1_value)
-{
-  ACC->c1 = acc_c1_value;
-}
-
-/**
-  * @brief  wtire the value to  acc c2 register.
-  * @param  acc_c2_value
-  * @retval none.
-  */
-void acc_write_c2(uint16_t acc_c2_value)
-{
-  ACC->c2 = acc_c2_value;
-}
-
-/**
-  * @brief  wtire the value to  acc c3 register.
-  * @param  acc_c3_value
-  * @retval none.
-  */
-void acc_write_c3(uint16_t acc_c3_value)
-{
-  ACC->c3 = acc_c3_value;
-}
-
-/**
-  * @brief  return the current acc c1 value.
-  * @param  none
-  * @retval 16-bit c1 value.
-  */
-uint16_t acc_read_c1(void)
-{
-  return ((uint16_t)(ACC->c1));
-}
-
-/**
-  * @brief  return the current acc c2 value.
-  * @param  none
-  * @retval 16-bit c2 value.
-  */
-uint16_t acc_read_c2(void)
-{
-  return ((uint16_t)(ACC->c2));
-}
-
-/**
-  * @brief  return the current acc c3 value.
-  * @param  none
-  * @retval 16-bit c3 value.
-  */
-uint16_t acc_read_c3(void)
-{
-  return ((uint16_t)(ACC->c3));
-}
-
-/**
-  * @brief  check whether the specified acc flag is set or not.
-  * @param  acc_flag: specifies the flag to check.
-  *         this parameter can be one of the following values:
-  *         - ACC_RSLOST_FLAG
-  *         - ACC_CALRDY_FLAG
-  * @retval  flag_status (SET or RESET)
-  */
-flag_status acc_flag_get(uint16_t acc_flag)
-{
-  if(acc_flag == ACC_CALRDY_FLAG)
-    return (flag_status)(ACC->sts_bit.calrdy);
-  else
-    return (flag_status)(ACC->sts_bit.rslost);
-}
-
-/**
-  * @brief  clear the specified acc flag is set or not.
-  * @param  acc_flag: specifies the flag to check.
-  *         this parameter can be any combination of the following values:
-  *         - ACC_RSLOST_FLAG
-  *         - ACC_CALRDY_FLAG
-  * @retval  none
-  */
-void acc_flag_clear(uint16_t acc_flag)
-{
-  ACC->sts = ~acc_flag;
-}
-
-/**
-  * @}
-  */
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/at32/libraries/f403a_407/firmware/drivers/src/at32f403a_407_adc.c

@@ -1,949 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_adc.c
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    contains all the functions for the adc firmware library
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-#include "at32f403a_407_conf.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @defgroup ADC
-  * @brief ADC driver modules
-  * @{
-  */
-
-#ifdef ADC_MODULE_ENABLED
-
-/** @defgroup ADC_private_functions
-  * @{
-  */
-
-/**
-  * @brief  deinitialize the adc peripheral registers to their default reset values.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval none
-  */
-void adc_reset(adc_type *adc_x)
-{
-  if(adc_x == ADC1)
-  {
-    crm_periph_reset(CRM_ADC1_PERIPH_RESET, TRUE);
-    crm_periph_reset(CRM_ADC1_PERIPH_RESET, FALSE);
-  }
-  else if(adc_x == ADC2)
-  {
-    crm_periph_reset(CRM_ADC2_PERIPH_RESET, TRUE);
-    crm_periph_reset(CRM_ADC2_PERIPH_RESET, FALSE);
-  }
-  else if(adc_x == ADC3)
-  {
-    crm_periph_reset(CRM_ADC3_PERIPH_RESET, TRUE);
-    crm_periph_reset(CRM_ADC3_PERIPH_RESET, FALSE);
-  }
-}
-
-/**
-  * @brief  enable or disable the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of a/d converter.
-  *         this parameter can be: TRUE or FALSE.
-  *         note:after adc ready,user set adcen bit will cause ordinary conversion
-  * @retval none
-  */
-void adc_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl2_bit.adcen = new_state;
-}
-
-/**
-  * @brief  select combine mode of the specified adc peripheral.
-  * @param  combine_mode: select the adc combine mode.
-  *         this parameter can be one of the following values:
-  *         - ADC_INDEPENDENT_MODE
-  *         - ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE
-  *         - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE
-  *         - ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE
-  *         - ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE
-  *         - ADC_PREEMPT_SMLT_ONLY_MODE
-  *         - ADC_ORDINARY_SMLT_ONLY_MODE
-  *         - ADC_ORDINARY_SHORTSHIFT_ONLY_MODE
-  *         - ADC_ORDINARY_LONGSHIFT_ONLY_MODE
-  *         - ADC_PREEMPT_INTERLTRIG_ONLY_MODE
-  *         note:these bits are reserved in adc2 and adc3
-  * @retval none
-  */
-void adc_combine_mode_select(adc_combine_mode_type combine_mode)
-{
-    ADC1->ctrl1_bit.mssel = combine_mode;
-}
-
-/**
-  * @brief  adc base default para init.
-  * @param  sequence_mode: set the state of adc sequence mode.
-  *         this parameter can be:TRUE or FALSE
-  * @param  repeat_mode: set the state of adc repeat conversion mode.
-  *         this parameter can be:TRUE or FALSE
-  * @param  data_align: set the state of adc data alignment.
-  *         this parameter can be one of the following values:
-  *         - ADC_RIGHT_ALIGNMENT
-  *         - ADC_LEFT_ALIGNMENT
-  * @param  ordinary_channel_length: configure the adc ordinary channel sequence length.
-  *         this parameter can be:
-  *         - (0x1~0xf)
-  * @retval none
-  */
-void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
-{
-  adc_base_struct->sequence_mode = FALSE;
-  adc_base_struct->repeat_mode = FALSE;
-  adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
-  adc_base_struct->ordinary_channel_length = 1;
-}
-
-/**
-  * @brief  initialize the adc peripheral according to the specified parameters.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  sequence_mode: set the state of adc sequence mode.
-  *         this parameter can be:TRUE or FALSE
-  * @param  repeat_mode: set the state of adc repeat conversion mode.
-  *         this parameter can be:TRUE or FALSE
-  * @param  data_align: set the state of adc data alignment.
-  *         this parameter can be one of the following values:
-  *         - ADC_RIGHT_ALIGNMENT
-  *         - ADC_LEFT_ALIGNMENT
-  * @param  ordinary_channel_length: configure the adc ordinary channel sequence length.
-  *         this parameter can be:
-  *         - (0x1~0xf)
-  * @retval none
-  */
-void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
-{
-  adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
-  adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
-  adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
-  adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
-}
-
-/**
-  * @brief  enable or disable the adc dma transfer.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC3.
-  *         note:this bit is reserved in adc2
-  * @param  new_state: new state of the adc dma transfer.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl2_bit.ocdmaen = new_state;
-}
-
-/**
-  * @brief  enable or disable the specified adc interrupts.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_int: specifies the adc interrupt sources to be enabled or disabled.
-  *         this parameter can be one of the following values:
-  *         - ADC_VMOR_INT
-  *         - ADC_CCE_INT
-  *         - ADC_PCCE_INT
-  * @param  new_state: new state of the specified adc interrupts.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
-{
-  if(new_state == TRUE)
-  {
-    adc_x->ctrl1 |= adc_int;
-  }
-  else if(new_state == FALSE)
-  {
-    adc_x->ctrl1 &= ~adc_int;
-  }
-}
-
-/**
-  * @brief  initialize calibration register of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval none
-  */
-void adc_calibration_init(adc_type *adc_x)
-{
-  adc_x->ctrl2_bit.adcalinit = TRUE;
-}
-
-/**
-  * @brief  get calibration register's initialize status of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval the new state of reset calibration register status(SET or RESET).
-  */
-flag_status adc_calibration_init_status_get(adc_type *adc_x)
-{
-  if(adc_x->ctrl2_bit.adcalinit)
-  {
-    return SET;
-  }
-  else
-  {
-    return RESET;
-  }
-}
-
-/**
-  * @brief  start calibration process of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval none
-  */
-void adc_calibration_start(adc_type *adc_x)
-{
-  adc_x->ctrl2_bit.adcal = TRUE;
-}
-
-/**
-  * @brief  get calibration status of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval the new state of calibration status(SET or RESET).
-  */
-flag_status adc_calibration_status_get(adc_type *adc_x)
-{
-  if(adc_x->ctrl2_bit.adcal)
-  {
-    return SET;
-  }
-  else
-  {
-    return RESET;
-  }
-}
-
-/**
-  * @brief  enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_voltage_monitoring: choose the adc_voltage_monitoring config.
-  *         this parameter can be one of the following values:
-  *         - ADC_VMONITOR_SINGLE_ORDINARY
-  *         - ADC_VMONITOR_SINGLE_PREEMPT
-  *         - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
-  *         - ADC_VMONITOR_ALL_ORDINARY
-  *         - ADC_VMONITOR_ALL_PREEMPT
-  *         - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
-  *         - ADC_VMONITOR_NONE
-  * @retval none
-  */
-void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
-{
-  adc_x->ctrl1_bit.ocvmen = FALSE;
-  adc_x->ctrl1_bit.pcvmen = FALSE;
-  adc_x->ctrl1_bit.vmsgen = FALSE;
-  adc_x->ctrl1 |= adc_voltage_monitoring;
-}
-
-/**
-  * @brief  set voltage monitoring's high and low thresholds value of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_high_threshold: voltage monitoring's high thresholds value.
-  *         this parameter can be:
-  *         - (0x000~0xFFF)
-  * @param  adc_low_threshold: voltage monitoring's low thresholds value.
-  *         this parameter can be:
-  *         - (0x000~0xFFF)
-  * @retval none
-  */
-void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
-{
-  adc_x->vmhb_bit.vmhb = adc_high_threshold;
-  adc_x->vmlb_bit.vmlb = adc_low_threshold;
-}
-
-/**
-  * @brief  select the voltage monitoring's channel of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_channel: select the channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
-  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
-  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
-  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
-  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
-  * @retval none
-  */
-void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
-{
-  adc_x->ctrl1_bit.vmcsel = adc_channel;
-}
-
-/**
-  * @brief  set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_channel: select the channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
-  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
-  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
-  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
-  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
-  * @param  adc_sequence: set rank in the ordinary group sequencer.
-  *         this parameter must be:
-  *         - between 1 to 16
-  * @param  adc_sampletime: set the sampletime of adc channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_SAMPLETIME_1_5
-  *         - ADC_SAMPLETIME_7_5
-  *         - ADC_SAMPLETIME_13_5
-  *         - ADC_SAMPLETIME_28_5
-  *         - ADC_SAMPLETIME_41_5
-  *         - ADC_SAMPLETIME_55_5
-  *         - ADC_SAMPLETIME_71_5
-  *         - ADC_SAMPLETIME_239_5
-  * @retval none
-  */
-void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
-{
-  switch(adc_channel)
-  {
-    case ADC_CHANNEL_0:
-      adc_x->spt2_bit.cspt0 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_1:
-      adc_x->spt2_bit.cspt1 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_2:
-      adc_x->spt2_bit.cspt2 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_3:
-      adc_x->spt2_bit.cspt3 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_4:
-      adc_x->spt2_bit.cspt4 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_5:
-      adc_x->spt2_bit.cspt5 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_6:
-      adc_x->spt2_bit.cspt6 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_7:
-      adc_x->spt2_bit.cspt7 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_8:
-      adc_x->spt2_bit.cspt8 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_9:
-      adc_x->spt2_bit.cspt9 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_10:
-      adc_x->spt1_bit.cspt10 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_11:
-      adc_x->spt1_bit.cspt11 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_12:
-      adc_x->spt1_bit.cspt12 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_13:
-      adc_x->spt1_bit.cspt13 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_14:
-      adc_x->spt1_bit.cspt14 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_15:
-      adc_x->spt1_bit.cspt15 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_16:
-      adc_x->spt1_bit.cspt16 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_17:
-      adc_x->spt1_bit.cspt17 = adc_sampletime;
-      break;
-    default:
-      break;
-  }
-  switch(adc_sequence)
-  {
-    case 1:
-      adc_x->osq3_bit.osn1 = adc_channel;
-      break;
-    case 2:
-      adc_x->osq3_bit.osn2 = adc_channel;
-      break;
-    case 3:
-      adc_x->osq3_bit.osn3 = adc_channel;
-      break;
-    case 4:
-      adc_x->osq3_bit.osn4 = adc_channel;
-      break;
-    case 5:
-      adc_x->osq3_bit.osn5 = adc_channel;
-      break;
-    case 6:
-      adc_x->osq3_bit.osn6 = adc_channel;
-      break;
-    case 7:
-      adc_x->osq2_bit.osn7 = adc_channel;
-      break;
-    case 8:
-      adc_x->osq2_bit.osn8 = adc_channel;
-      break;
-    case 9:
-      adc_x->osq2_bit.osn9 = adc_channel;
-      break;
-    case 10:
-      adc_x->osq2_bit.osn10 = adc_channel;
-      break;
-    case 11:
-      adc_x->osq2_bit.osn11 = adc_channel;
-      break;
-    case 12:
-      adc_x->osq2_bit.osn12 = adc_channel;
-      break;
-    case 13:
-      adc_x->osq1_bit.osn13 = adc_channel;
-      break;
-    case 14:
-      adc_x->osq1_bit.osn14 = adc_channel;
-      break;
-    case 15:
-      adc_x->osq1_bit.osn15 = adc_channel;
-      break;
-    case 16:
-      adc_x->osq1_bit.osn16 = adc_channel;
-      break;
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  set preempt channel lenghth of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_channel_lenght: set the adc preempt channel lenghth.
-  *         this parameter can be:
-  *         - (0x1~0x4)
-  * @retval none
-  */
-void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
-{
-  adc_x->psq_bit.pclen =  adc_channel_lenght - 1;
-}
-
-/**
-  * @brief  configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_channel: select the channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_CHANNEL_0    - ADC_CHANNEL_1    - ADC_CHANNEL_2    - ADC_CHANNEL_3
-  *         - ADC_CHANNEL_4    - ADC_CHANNEL_5    - ADC_CHANNEL_6    - ADC_CHANNEL_7
-  *         - ADC_CHANNEL_8    - ADC_CHANNEL_9    - ADC_CHANNEL_10   - ADC_CHANNEL_11
-  *         - ADC_CHANNEL_12   - ADC_CHANNEL_13   - ADC_CHANNEL_14   - ADC_CHANNEL_15
-  *         - ADC_CHANNEL_16   - ADC_CHANNEL_17
-  * @param  adc_sequence: set rank in the preempt group sequencer.
-  *         this parameter must be:
-  *         - between 1 to 4
-  * @param  adc_sampletime: config the sampletime of adc channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_SAMPLETIME_1_5
-  *         - ADC_SAMPLETIME_7_5
-  *         - ADC_SAMPLETIME_13_5
-  *         - ADC_SAMPLETIME_28_5
-  *         - ADC_SAMPLETIME_41_5
-  *         - ADC_SAMPLETIME_55_5
-  *         - ADC_SAMPLETIME_71_5
-  *         - ADC_SAMPLETIME_239_5
-  * @retval none
-  */
-void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
-{
-  uint16_t sequence_index=0;
-  switch(adc_channel)
-  {
-    case ADC_CHANNEL_0:
-      adc_x->spt2_bit.cspt0 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_1:
-      adc_x->spt2_bit.cspt1 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_2:
-      adc_x->spt2_bit.cspt2 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_3:
-      adc_x->spt2_bit.cspt3 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_4:
-      adc_x->spt2_bit.cspt4 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_5:
-      adc_x->spt2_bit.cspt5 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_6:
-      adc_x->spt2_bit.cspt6 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_7:
-      adc_x->spt2_bit.cspt7 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_8:
-      adc_x->spt2_bit.cspt8 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_9:
-      adc_x->spt2_bit.cspt9 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_10:
-      adc_x->spt1_bit.cspt10 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_11:
-      adc_x->spt1_bit.cspt11 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_12:
-      adc_x->spt1_bit.cspt12 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_13:
-      adc_x->spt1_bit.cspt13 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_14:
-      adc_x->spt1_bit.cspt14 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_15:
-      adc_x->spt1_bit.cspt15 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_16:
-      adc_x->spt1_bit.cspt16 = adc_sampletime;
-      break;
-    case ADC_CHANNEL_17:
-      adc_x->spt1_bit.cspt17 = adc_sampletime;
-      break;
-    default:
-      break;
-  }
-  sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
-  switch(sequence_index)
-  {
-    case 1:
-      adc_x->psq_bit.psn1 = adc_channel;
-      break;
-    case 2:
-      adc_x->psq_bit.psn2 = adc_channel;
-      break;
-    case 3:
-      adc_x->psq_bit.psn3 = adc_channel;
-      break;
-    case 4:
-      adc_x->psq_bit.psn4 = adc_channel;
-      break;
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  enable or disable the ordinary channel's external trigger and
-  *         set external trigger event of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_ordinary_trig: select the external trigger event.
-  *         this parameter can be one of the following values:
-  *         adc1 & adc2
-  *         - ADC12_ORDINARY_TRIG_TMR1CH1     - ADC12_ORDINARY_TRIG_TMR1CH2  - ADC12_ORDINARY_TRIG_TMR1CH3             - ADC12_ORDINARY_TRIG_TMR2CH2
-  *         - ADC12_ORDINARY_TRIG_TMR3TRGOUT  - ADC12_ORDINARY_TRIG_TMR4CH4  - ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT  - ADC12_ORDINARY_TRIG_SOFTWARE
-  *         - ADC12_ORDINARY_TRIG_TMR1TRGOUT  - ADC12_ORDINARY_TRIG_TMR8CH1  - ADC12_ORDINARY_TRIG_TMR8CH2
-  *         adc3
-  *         - ADC3_ORDINARY_TRIG_TMR3CH1      - ADC3_ORDINARY_TRIG_TMR2CH3   - ADC3_ORDINARY_TRIG_TMR1CH3              - ADC3_ORDINARY_TRIG_TMR8CH1
-  *         - ADC3_ORDINARY_TRIG_TMR8TRGOUT   - ADC3_ORDINARY_TRIG_TMR5CH1   - ADC3_ORDINARY_TRIG_TMR5CH3              - ADC3_ORDINARY_TRIG_SOFTWARE
-  *         - ADC3_ORDINARY_TRIG_TMR1TRGOUT   - ADC3_ORDINARY_TRIG_TMR1CH1   - ADC3_ORDINARY_TRIG_TMR8CH3
-  * @param  new_state: new state of ordinary channel's external trigger.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state)
-{
-  if(adc_ordinary_trig > 7)
-  {
-    adc_x->ctrl2_bit.octesel_h = 1;
-    adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
-  }
-  else
-  {
-    adc_x->ctrl2_bit.octesel_h = 0;
-    adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
-  }
-  adc_x->ctrl2_bit.octen = new_state;
-}
-
-/**
-  * @brief  enable or disable the preempt channel's external trigger and
-  *         set external trigger event of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_preempt_trig: select the external trigger event.
-  *         this parameter can be one of the following values:
-  *         adc1 & adc2
-  *         - ADC12_PREEMPT_TRIG_TMR1TRGOUT  - ADC12_PREEMPT_TRIG_TMR1CH4     - ADC12_PREEMPT_TRIG_TMR2TRGOUT      - ADC12_PREEMPT_TRIG_TMR2CH1
-  *         - ADC12_PREEMPT_TRIG_TMR3CH4     - ADC12_PREEMPT_TRIG_TMR4TRGOUT  - ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4 - ADC12_PREEMPT_TRIG_SOFTWARE
-  *         - ADC12_PREEMPT_TRIG_TMR1CH1     - ADC12_PREEMPT_TRIG_TMR8CH1     - ADC12_PREEMPT_TRIG_TMR8TRGOUT
-  *         adc3
-  *         - ADC3_PREEMPT_TRIG_TMR1TRGOUT   - ADC3_PREEMPT_TRIG_TMR1CH4      - ADC3_PREEMPT_TRIG_TMR4CH3          - ADC3_PREEMPT_TRIG_TMR8CH2
-  *         - ADC3_PREEMPT_TRIG_TMR8CH4      - ADC3_PREEMPT_TRIG_TMR5TRGOUT   - ADC3_PREEMPT_TRIG_TMR5CH4          - ADC3_PREEMPT_TRIG_SOFTWARE
-  *         - ADC3_PREEMPT_TRIG_TMR1CH1      - ADC3_PREEMPT_TRIG_TMR1CH2      - ADC3_PREEMPT_TRIG_TMR8TRGOUT
-  * @param  new_state: new state of preempt channel's external trigger.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state)
-{
-  if(adc_preempt_trig > 7)
-  {
-    adc_x->ctrl2_bit.pctesel_h = 1;
-    adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
-  }
-  else
-  {
-    adc_x->ctrl2_bit.pctesel_h = 0;
-    adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
-  }
-  adc_x->ctrl2_bit.pcten = new_state;
-}
-
-
-/**
-  * @brief  set preempt channel's conversion value offset of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_preempt_channel: select the preempt channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_PREEMPT_CHANNEL_1
-  *         - ADC_PREEMPT_CHANNEL_2
-  *         - ADC_PREEMPT_CHANNEL_3
-  *         - ADC_PREEMPT_CHANNEL_4
-  * @param  adc_offset_value: set the adc preempt channel's conversion value offset.
-  *         this parameter can be:
-  *         - (0x000~0xFFF)
-  * @retval none
-  */
-void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
-{
-  switch(adc_preempt_channel)
-  {
-    case ADC_PREEMPT_CHANNEL_1:
-      adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
-      break;
-    case ADC_PREEMPT_CHANNEL_2:
-      adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
-      break;
-    case ADC_PREEMPT_CHANNEL_3:
-      adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
-      break;
-    case ADC_PREEMPT_CHANNEL_4:
-      adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
-      break;
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  set partitioned mode channel count of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_channel_count: configure the adc partitioned mode channel count.
-  *         this parameter can be:
-  *         - (0x1~0x8)
-  * @retval none
-  */
-void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
-{
-
-  adc_x->ctrl1_bit.ocpcnt =  adc_channel_count - 1;
-}
-
-/**
-  * @brief  enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of ordinary channel's partitioned mode.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl1_bit.ocpen = new_state;
-}
-
-/**
-  * @brief  enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of preempt channel's partitioned mode.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl1_bit.pcpen = new_state;
-}
-
-/**
-  * @brief  enable or disable automatic preempt group conversion of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of automatic preempt group conversion.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl1_bit.pcautoen = new_state;
-}
-
-/**
-  * @brief  enable or disable the temperature sensor and vintrv channel.
-  * @param  new_state: new state of Internal temperature sensor and vintrv.
-  *         this parameter can be: TRUE or FALSE.
-  *         note:this bit is present only in adc1
-  * @retval none
-  */
-void adc_tempersensor_vintrv_enable(confirm_state new_state)
-{
-  ADC1->ctrl2_bit.itsrven = new_state;
-}
-
-/**
-  * @brief  enable or disable ordinary software start conversion of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of ordinary software start conversion.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl2_bit.ocswtrg = new_state;
-}
-
-/**
-  * @brief  get ordinary software start conversion status of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval the new state of ordinary software start conversion status(SET or RESET).
-  */
-flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
-{
-  if(adc_x->ctrl2_bit.ocswtrg)
-  {
-    return SET;
-  }
-  else
-  {
-    return RESET;
-  }
-}
-
-/**
-  * @brief  enable or disable preempt software start conversion of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  new_state: new state of preempt software start conversion.
-  *         this parameter can be: TRUE or FALSE.
-  * @retval none
-  */
-void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
-{
-  adc_x->ctrl2_bit.pcswtrg = new_state;
-}
-
-/**
-  * @brief  get preempt software start conversion status of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval the new state of preempt software start conversion status(SET or RESET).
-  */
-flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
-{
-  if(adc_x->ctrl2_bit.pcswtrg)
-  {
-    return SET;
-  }
-  else
-  {
-    return RESET;
-  }
-}
-
-/**
-  * @brief  return the last conversion data for ordinary channel of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @retval the last conversion data for ordinary channel.
-  */
-uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
-{
-  return (uint16_t)(adc_x->odt_bit.odt);
-}
-
-/**
-  * @brief  return the last conversion data for ordinary channel of combine adc(adc1 and adc2).
-  * @retval the last conversion data for ordinary channel.
-  */
-uint32_t adc_combine_ordinary_conversion_data_get(void)
-{
-  return (uint32_t)(ADC1->odt);
-}
-
-/**
-  * @brief  return the conversion data for selection preempt channel of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_preempt_channel: select the preempt channel.
-  *         this parameter can be one of the following values:
-  *         - ADC_PREEMPTED_CHANNEL_1
-  *         - ADC_PREEMPTED_CHANNEL_2
-  *         - ADC_PREEMPTED_CHANNEL_3
-  *         - ADC_PREEMPTED_CHANNEL_4
-  * @retval the conversion data for selection preempt channel.
-  */
-uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
-{
-  uint16_t preempt_conv_data_index = 0;
-  switch(adc_preempt_channel)
-  {
-    case ADC_PREEMPT_CHANNEL_1:
-      preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
-      break;
-    case ADC_PREEMPT_CHANNEL_2:
-      preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
-      break;
-    case ADC_PREEMPT_CHANNEL_3:
-      preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
-      break;
-    case ADC_PREEMPT_CHANNEL_4:
-      preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
-      break;
-    default:
-      break;
-  }
-  return preempt_conv_data_index;
-}
-
-/**
-  * @brief  get flag of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_flag: select the adc flag.
-  *         this parameter can be one of the following values:
-  *         - ADC_VMOR_FLAG
-  *         - ADC_CCE_FLAG
-  *         - ADC_PCCE_FLAG
-  *         - ADC_PCCS_FLAG(no interrupt associated)
-  *         - ADC_OCCS_FLAG(no interrupt associated)
-  * @retval the new state of adc flag status(SET or RESET).
-  */
-flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
-{
-  flag_status status = RESET;
-
-  if((adc_x->sts & adc_flag) == RESET)
-  {
-    status = RESET;
-  }
-  else
-  {
-    status = SET;
-  }
-  return status;
-}
-
-/**
-  * @brief  clear flag of the specified adc peripheral.
-  * @param  adc_x: select the adc peripheral.
-  *         this parameter can be one of the following values:
-  *         ADC1, ADC2, ADC3.
-  * @param  adc_flag: select the adc flag.
-  *         this parameter can be any combination of the following values:
-  *         - ADC_VMOR_FLAG
-  *         - ADC_CCE_FLAG(also can clear by reading the adc_x->odt)
-  *         - ADC_PCCE_FLAG
-  *         - ADC_PCCS_FLAG
-  *         - ADC_OCCS_FLAG
-  * @retval none
-  */
-void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
-{
-  adc_x->sts = ~adc_flag;
-}
-
-/**
-  * @}
-  */
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/at32/libraries/f403a_407/firmware/drivers/src/at32f403a_407_bpr.c

@@ -1,206 +0,0 @@
-/**
-  **************************************************************************
-  * @file     at32f403a_407_bpr.c
-  * @version  v2.0.7
-  * @date     2022-02-11
-  * @brief    contains all the functions for the bpr firmware library
-  **************************************************************************
-  *                       Copyright notice & Disclaimer
-  *
-  * The software Board Support Package (BSP) that is made available to
-  * download from Artery official website is the copyrighted work of Artery.
-  * Artery authorizes customers to use, copy, and distribute the BSP
-  * software and its related documentation for the purpose of design and
-  * development in conjunction with Artery microcontrollers. Use of the
-  * software is governed by this copyright notice and the following disclaimer.
-  *
-  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
-  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
-  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
-  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
-  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
-  *
-  **************************************************************************
-  */
-
-#include "at32f403a_407_conf.h"
-
-/** @addtogroup AT32F403A_407_periph_driver
-  * @{
-  */
-
-/** @defgroup BPR
-  * @brief BPR driver modules
-  * @{
-  */
-
-#ifdef BPR_MODULE_ENABLED
-
-/** @defgroup BPR_private_functions
-  * @{
-  */
-
-/**
-  * @brief  bpr reset by crm reset register
-  * @param  none
-  * @retval none
-  */
-void bpr_reset(void)
-{
-  crm_battery_powered_domain_reset(TRUE);
-  crm_battery_powered_domain_reset(FALSE);
-}
-
-/**
-  * @brief  bpr event flag get, for tamper event flag
-  * @param  flag: specifies the flag to check.
-  *         this parameter can be one of the following values:
-  *         - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
-  *         - BPR_TAMPER_EVENT_FLAG:   tamper event flag
-  * @retval state of tamper event flag
-  */
-flag_status bpr_flag_get(uint32_t flag)
-{
-  if(flag == BPR_TAMPER_INTERRUPT_FLAG)
-  {
-    return (flag_status)(BPR->ctrlsts_bit.tpif);
-  }
-  else
-  {
-    return (flag_status)(BPR->ctrlsts_bit.tpef);
-  }
-}
-
-/**
-  * @brief  clear bpr tamper flag
-  * @param  flag: specifies the flag to clear.
-  *         this parameter can be one of the following values:
-  *         - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
-  *         - BPR_TAMPER_EVENT_FLAG:   tamper event flag
-  * @retval none
-  */
-void bpr_flag_clear(uint32_t flag)
-{
-  if(flag == BPR_TAMPER_INTERRUPT_FLAG)
-  {
-    BPR->ctrlsts_bit.tpifclr = TRUE;
-  }
-  else
-  {
-    BPR->ctrlsts_bit.tpefclr = TRUE;
-  }
-}
-
-/**
-  * @brief  enable or disable bpr tamper interrupt
-  * @param  new_state (TRUE or FALSE)
-  * @retval none
-  */
-void bpr_interrupt_enable(confirm_state new_state)
-{
-  BPR->ctrlsts_bit.tpien = new_state;
-}
-
-/**
-  * @brief  read bpr bpr data
-  * @param  bpr_data
-  *         this parameter can be one of the following values:
-  *         - BPR_DATA1
-  *         - BPR_DATA2
-  *         ...
-  *         - BPR_DATA41
-  *         - BPR_DATA42
-  * @retval none
-  */
-uint16_t bpr_data_read(bpr_data_type bpr_data)
-{
-  return (*(__IO uint16_t *)(BPR_BASE + bpr_data));
-}
-
-/**
-  * @brief  write bpr data
-  * @param  bpr_data
-  *         this parameter can be one of the following values:
-  *         - BPR_DATA1
-  *         - BPR_DATA2
-  *         ...
-  *         - BPR_DATA41
-  *         - BPR_DATA42
-  * @param  data_value (0x0000~0xFFFF)
-  * @retval none
-  */
-void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value)
-{
-  (*(__IO uint32_t *)(BPR_BASE + bpr_data)) = data_value;
-}
-
-/**
-  * @brief  select bpr rtc output
-  * @param  output_source
-  *         this parameter can be one of the following values:
-  *         - BPR_RTC_OUTPUT_NONE: output disable.
-  *         - BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE: output clock before calibration.
-  *         - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode.
-  *         - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode.
-  *         - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration.
-  *         - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode.
-  *         - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode.
-  * @retval none
-  */
-void bpr_rtc_output_select(bpr_rtc_output_type output_source)
-{
-  /* clear cco,asoe,asos,ccos,togen bits */
-  BPR->rtccal &= (uint32_t)~0x0F80;
-
-  /* set output_source value */
-  BPR->rtccal |= output_source;
-}
-
-/**
-  * @brief  set rtc clock calibration value
-  * @param  calibration_value (0x00~0x7f)
-  * @retval none
-  */
-void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value)
-{
-  /* set rtc clock calibration value */
-  BPR->rtccal_bit.calval= calibration_value;
-}
-
-/**
-  * @brief  enable or disable bpr tamper pin
-  * @param  new_state (TRUE or FALSE)
-  * @retval none
-  */
-void bpr_tamper_pin_enable(confirm_state new_state)
-{
-  BPR->ctrl_bit.tpen = new_state;
-}
-
-/**
-  * @brief  set bpr tamper pin active level
-  * @param  active_level
-  *         this parameter can be one of the following values:
-  *         - BPR_TAMPER_PIN_ACTIVE_HIGH: tamper pin input active level is high.
-  *         - BPR_TAMPER_PIN_ACTIVE_LOW: tamper pin input active level is low.
-  * @retval none
-  */
-void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level)
-{
-  BPR->ctrl_bit.tpp = active_level;
-}
-
-/**
-  * @}
-  */
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */