drv_sci_spi.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-23 Mr.Tiger first version
  9. * 2021-11-04 Sherman ADD complete_event
  10. * 2022-12-7 Vandoul ADD sci spi
  11. */
  12. /**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
  13. #include "drv_sci_spi.h"
  14. #ifdef RT_USING_SPI
  15. //#define DRV_DEBUG
  16. #define DBG_TAG "drv.scispi"
  17. #ifdef DRV_DEBUG
  18. #define DBG_LVL DBG_LOG
  19. #else
  20. #define DBG_LVL DBG_INFO
  21. #endif /* DRV_DEBUG */
  22. #include <rtdbg.h>
  23. #define RA_SCI_SPI0_EVENT 0x0001
  24. #define RA_SCI_SPI1_EVENT 0x0002
  25. #define RA_SCI_SPI2_EVENT 0x0004
  26. #define RA_SCI_SPI3_EVENT 0x0008
  27. #define RA_SCI_SPI4_EVENT 0x0010
  28. #define RA_SCI_SPI5_EVENT 0x0020
  29. #define RA_SCI_SPI6_EVENT 0x0040
  30. #define RA_SCI_SPI7_EVENT 0x0080
  31. #define RA_SCI_SPI8_EVENT 0x0100
  32. #define RA_SCI_SPI9_EVENT 0x0200
  33. static struct rt_event complete_event = {0};
  34. static struct ra_sci_spi_handle spi_handle[] =
  35. {
  36. #ifdef BSP_USING_SCI_SPI0
  37. {.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
  38. #endif
  39. #ifdef BSP_USING_SCI_SPI1
  40. {.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
  41. #endif
  42. #ifdef BSP_USING_SCI_SPI2
  43. {.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
  44. #endif
  45. #ifdef BSP_USING_SCI_SPI3
  46. {.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
  47. #endif
  48. #ifdef BSP_USING_SCI_SPI4
  49. {.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
  50. #endif
  51. #ifdef BSP_USING_SCI_SPI5
  52. {.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
  53. #endif
  54. #ifdef BSP_USING_SCI_SPI6
  55. {.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
  56. #endif
  57. #ifdef BSP_USING_SCI_SPI7
  58. {.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
  59. #endif
  60. #ifdef BSP_USING_SCI_SPI8
  61. {.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
  62. #endif
  63. #ifdef BSP_USING_SCI_SPI9
  64. {.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
  65. #endif
  66. };
  67. static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
  68. #define SCI_SPIx_CALLBACK(n) \
  69. void sci_spi##n##_callback(spi_callback_args_t *p_args) \
  70. { \
  71. rt_interrupt_enter(); \
  72. if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
  73. { \
  74. rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
  75. } \
  76. rt_interrupt_leave(); \
  77. }
  78. SCI_SPIx_CALLBACK(0);
  79. SCI_SPIx_CALLBACK(1);
  80. SCI_SPIx_CALLBACK(2);
  81. SCI_SPIx_CALLBACK(3);
  82. SCI_SPIx_CALLBACK(4);
  83. SCI_SPIx_CALLBACK(5);
  84. SCI_SPIx_CALLBACK(6);
  85. SCI_SPIx_CALLBACK(7);
  86. SCI_SPIx_CALLBACK(8);
  87. SCI_SPIx_CALLBACK(9);
  88. #define SCI_SPIx_EVENT_RECV(n) \
  89. rt_event_recv(event, \
  90. RA_SCI_SPI##n##_EVENT, \
  91. RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
  92. rt_tick_from_millisecond(1000), \
  93. &recved);
  94. static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
  95. {
  96. rt_uint32_t recved = 0x00;
  97. rt_err_t ret = RT_EOK;
  98. switch (bus_name[4])
  99. {
  100. case '0':
  101. ret = SCI_SPIx_EVENT_RECV(0);
  102. break;
  103. case '1':
  104. ret = SCI_SPIx_EVENT_RECV(1);
  105. break;
  106. case '2':
  107. ret = SCI_SPIx_EVENT_RECV(2);
  108. break;
  109. case '3':
  110. ret = SCI_SPIx_EVENT_RECV(3);
  111. break;
  112. case '4':
  113. ret = SCI_SPIx_EVENT_RECV(4);
  114. break;
  115. case '5':
  116. ret = SCI_SPIx_EVENT_RECV(5);
  117. break;
  118. case '6':
  119. ret = SCI_SPIx_EVENT_RECV(6);
  120. break;
  121. case '7':
  122. ret = SCI_SPIx_EVENT_RECV(7);
  123. break;
  124. case '8':
  125. ret = SCI_SPIx_EVENT_RECV(8);
  126. break;
  127. case '9':
  128. ret = SCI_SPIx_EVENT_RECV(9);
  129. break;
  130. default:
  131. break;
  132. }
  133. if (ret != RT_EOK)
  134. {
  135. LOG_D("%s ra_wait_complete failed!", bus_name);
  136. return ret;
  137. }
  138. return -RT_EINVAL;
  139. }
  140. static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
  141. {
  142. spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
  143. if(data_width == 1)
  144. bit_width = SPI_BIT_WIDTH_8_BITS;
  145. else if(data_width == 2)
  146. bit_width = SPI_BIT_WIDTH_16_BITS;
  147. else if(data_width == 4)
  148. bit_width = SPI_BIT_WIDTH_32_BITS;
  149. return bit_width;
  150. }
  151. static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
  152. {
  153. RT_ASSERT(device != NULL);
  154. RT_ASSERT(send_buf != NULL);
  155. RT_ASSERT(len > 0);
  156. rt_err_t err = RT_EOK;
  157. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  158. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  159. /**< send msessage */
  160. err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
  161. if (RT_EOK != err)
  162. {
  163. LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  164. return -RT_ERROR;
  165. }
  166. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  167. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  168. return len;
  169. }
  170. static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
  171. {
  172. RT_ASSERT(device != NULL);
  173. RT_ASSERT(recv_buf != NULL);
  174. RT_ASSERT(len > 0);
  175. rt_err_t err = RT_EOK;
  176. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  177. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  178. /**< receive message */
  179. err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
  180. if (RT_EOK != err)
  181. {
  182. LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  183. return -RT_ERROR;
  184. }
  185. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  186. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  187. return len;
  188. }
  189. static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
  190. {
  191. RT_ASSERT(device != NULL);
  192. RT_ASSERT(message != NULL);
  193. RT_ASSERT(message->length > 0);
  194. rt_err_t err = RT_EOK;
  195. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  196. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  197. /**< write and receive message */
  198. err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
  199. if (RT_EOK != err)
  200. {
  201. LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  202. return -RT_ERROR;
  203. }
  204. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  205. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  206. return message->length;
  207. }
  208. /**< init spi TODO : MSB does not support modification */
  209. static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
  210. struct rt_spi_configuration *configuration)
  211. {
  212. RT_ASSERT(device != NULL);
  213. RT_ASSERT(configuration != NULL);
  214. rt_err_t err = RT_EOK;
  215. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  216. /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
  217. rt_uint8_t data_width = configuration->data_width / 8;
  218. RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
  219. configuration->data_width = configuration->data_width / 8;
  220. spi_dev->rt_spi_cfg_t = configuration;
  221. sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
  222. /**< Configure Select Line */
  223. rt_pin_write(device->cs_pin, PIN_HIGH);
  224. /**< config bitrate */
  225. R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
  226. /**< init */
  227. err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
  228. /* handle error */
  229. if(err == FSP_ERR_IN_USE) {
  230. R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
  231. err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
  232. }
  233. if (RT_EOK != err)
  234. {
  235. LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  236. return -RT_ERROR;
  237. }
  238. return RT_EOK;
  239. }
  240. static rt_ssize_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  241. {
  242. RT_ASSERT(device != RT_NULL);
  243. RT_ASSERT(device->bus != RT_NULL);
  244. RT_ASSERT(message != RT_NULL);
  245. rt_err_t err = RT_EOK;
  246. if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  247. {
  248. if (device->config.mode & RT_SPI_CS_HIGH)
  249. rt_pin_write(device->cs_pin, PIN_HIGH);
  250. else
  251. rt_pin_write(device->cs_pin, PIN_LOW);
  252. }
  253. if (message->length > 0)
  254. {
  255. if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
  256. {
  257. /**< receive message */
  258. err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
  259. }
  260. else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
  261. {
  262. /**< send message */
  263. err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
  264. }
  265. else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
  266. {
  267. /**< send and receive message */
  268. err = ra_write_read_message(device, message);
  269. }
  270. }
  271. if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  272. {
  273. if (device->config.mode & RT_SPI_CS_HIGH)
  274. rt_pin_write(device->cs_pin, PIN_LOW);
  275. else
  276. rt_pin_write(device->cs_pin, PIN_HIGH);
  277. }
  278. return err;
  279. }
  280. static const struct rt_spi_ops ra_spi_ops =
  281. {
  282. .configure = ra_hw_spi_configure,
  283. .xfer = ra_spixfer,
  284. };
  285. int ra_hw_sci_spi_init(void)
  286. {
  287. for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
  288. {
  289. spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
  290. /**< register spi bus */
  291. rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
  292. if (RT_EOK != err)
  293. {
  294. LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
  295. return -RT_ERROR;
  296. }
  297. }
  298. if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
  299. {
  300. LOG_E("SPI transfer event init fail!");
  301. return -RT_ERROR;
  302. }
  303. return RT_EOK;
  304. }
  305. INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
  306. /**
  307. * Attach the spi device to SPI bus, this function must be used after initialization.
  308. */
  309. rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  310. {
  311. RT_ASSERT(bus_name != RT_NULL);
  312. RT_ASSERT(device_name != RT_NULL);
  313. rt_err_t result;
  314. struct rt_spi_device *spi_device;
  315. /* attach the device to spi bus*/
  316. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  317. RT_ASSERT(spi_device != RT_NULL);
  318. result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  319. if (result != RT_EOK)
  320. {
  321. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  322. }
  323. LOG_D("%s attach to %s done", device_name, bus_name);
  324. return result;
  325. }
  326. #endif /* RT_USING_SPI */