drv_i2c.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202
  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-02-22 airm2m first version
  9. */
  10. #include <rtdevice.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include <stdlib.h>
  14. #ifdef BSP_USING_HW_I2C
  15. #define DRV_DEBUG
  16. #define LOG_TAG "drv.hwi2c"
  17. #include <drv_log.h>
  18. #include <hal_data.h>
  19. #define RA_SCI_EVENT_ABORTED 1
  20. #define RA_SCI_EVENT_RX_COMPLETE 2
  21. #define RA_SCI_EVENT_TX_COMPLETE 4
  22. #define RA_SCI_EVENT_ERROR 8
  23. #define RA_SCI_EVENT_ALL 15
  24. struct ra_i2c_handle
  25. {
  26. struct rt_i2c_bus_device bus;
  27. char bus_name[RT_NAME_MAX];
  28. const i2c_master_cfg_t *i2c_cfg;
  29. void *i2c_ctrl;
  30. struct rt_event event;
  31. };
  32. static struct ra_i2c_handle ra_i2cs[] =
  33. {
  34. #ifdef BSP_USING_HW_I2C0
  35. {.bus_name = "i2c0", .i2c_cfg = &g_i2c_master0_cfg, .i2c_ctrl = &g_i2c_master0_ctrl,},
  36. #endif
  37. #ifdef BSP_USING_HW_I2C1
  38. {.bus_name = "i2c1", .i2c_cfg = &g_i2c_master1_cfg, .i2c_ctrl = &g_i2c_master1_ctrl,},
  39. #endif
  40. };
  41. void i2c_master_callback(i2c_master_callback_args_t *p_args)
  42. {
  43. rt_interrupt_enter();
  44. if (NULL != p_args)
  45. {
  46. /* capture callback event for validating the i2c transfer event*/
  47. struct ra_i2c_handle *obj = (struct ra_i2c_handle *)p_args->p_context;
  48. uint32_t event = 0;
  49. RT_ASSERT(obj != RT_NULL);
  50. switch (p_args->event)
  51. {
  52. case I2C_MASTER_EVENT_ABORTED:
  53. event |= RA_SCI_EVENT_ABORTED;
  54. break;
  55. case I2C_MASTER_EVENT_RX_COMPLETE:
  56. event |= RA_SCI_EVENT_RX_COMPLETE;
  57. break;
  58. case I2C_MASTER_EVENT_TX_COMPLETE:
  59. event |= RA_SCI_EVENT_TX_COMPLETE;
  60. break;
  61. }
  62. rt_event_send(&obj->event, event);
  63. }
  64. rt_interrupt_leave();
  65. }
  66. static rt_err_t validate_i2c_event(struct ra_i2c_handle *handle)
  67. {
  68. rt_uint32_t event = 0;
  69. if (RT_EOK != rt_event_recv(&handle->event, RA_SCI_EVENT_ALL, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, (int32_t)rt_tick_from_millisecond(100), &event))
  70. {
  71. return -RT_ETIMEOUT;
  72. }
  73. if ((event & (RA_SCI_EVENT_ABORTED | RA_SCI_EVENT_ERROR)) == 0)
  74. {
  75. return RT_EOK;
  76. }
  77. return -RT_ERROR;
  78. }
  79. static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
  80. struct rt_i2c_msg msgs[],
  81. rt_uint32_t num)
  82. {
  83. rt_size_t i;
  84. struct rt_i2c_msg *msg = msgs;
  85. RT_ASSERT(bus != RT_NULL);
  86. fsp_err_t err = FSP_SUCCESS;
  87. bool restart = false;
  88. struct ra_i2c_handle *ra_i2c = rt_container_of(bus, struct ra_i2c_handle, bus);
  89. i2c_master_ctrl_t *master_ctrl = ra_i2c->i2c_ctrl;
  90. for (i = 0; i < num; i++)
  91. {
  92. if (msg[i].flags & RT_I2C_NO_START)
  93. {
  94. restart = true;
  95. }
  96. if (msg[i].flags & RT_I2C_ADDR_10BIT)
  97. {
  98. R_IIC_MASTER_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT);
  99. }
  100. else
  101. {
  102. R_IIC_MASTER_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT);
  103. }
  104. if (msg[i].flags & RT_I2C_RD)
  105. {
  106. err = R_IIC_MASTER_Read(master_ctrl, msg[i].buf, msg[i].len, restart);
  107. if (FSP_SUCCESS == err)
  108. {
  109. if (RT_EOK != validate_i2c_event(ra_i2c))
  110. {
  111. LOG_E("POWER_CTL reg I2C read failed");
  112. break;
  113. }
  114. }
  115. /* handle error */
  116. else
  117. {
  118. /* Write API returns itself is not successful */
  119. LOG_E("R_I2C_MASTER_Write API failed");
  120. break;
  121. }
  122. }
  123. else
  124. {
  125. err = R_IIC_MASTER_Write(master_ctrl, msg[i].buf, msg[i].len, restart);
  126. if (FSP_SUCCESS == err)
  127. {
  128. if (RT_EOK != validate_i2c_event(ra_i2c))
  129. {
  130. LOG_E("POWER_CTL reg I2C write failed");
  131. break;
  132. }
  133. }
  134. /* handle error */
  135. else
  136. {
  137. /* Write API returns itself is not successful */
  138. LOG_E("R_I2C_MASTER_Write API failed");
  139. break;
  140. }
  141. }
  142. }
  143. return (rt_ssize_t)i;
  144. }
  145. static const struct rt_i2c_bus_device_ops ra_i2c_ops =
  146. {
  147. .master_xfer = ra_i2c_mst_xfer,
  148. .slave_xfer = RT_NULL,
  149. .i2c_bus_control = RT_NULL
  150. };
  151. int ra_hw_i2c_init(void)
  152. {
  153. fsp_err_t err = FSP_SUCCESS;
  154. for (rt_uint32_t i = 0; i < sizeof(ra_i2cs) / sizeof(ra_i2cs[0]); i++)
  155. {
  156. ra_i2cs[i].bus.ops = &ra_i2c_ops;
  157. ra_i2cs[i].bus.priv = 0;
  158. if (RT_EOK != rt_event_init(&ra_i2cs[i].event, ra_i2cs[i].bus_name, RT_IPC_FLAG_FIFO))
  159. {
  160. LOG_E("Init event failed");
  161. continue;
  162. }
  163. /* opening IIC master module */
  164. err = R_IIC_MASTER_Open(ra_i2cs[i].i2c_ctrl, ra_i2cs[i].i2c_cfg);
  165. if (FSP_SUCCESS != err)
  166. {
  167. LOG_E("R_I2C_MASTER_Open API failed,%d", err);
  168. continue;
  169. }
  170. err = R_IIC_MASTER_CallbackSet(ra_i2cs[i].i2c_ctrl, i2c_master_callback, &ra_i2cs[i], RT_NULL);
  171. /* handle error */
  172. if (FSP_SUCCESS != err)
  173. {
  174. LOG_E("R_I2C_CallbackSet API failed,%d", err);
  175. continue;
  176. }
  177. rt_i2c_bus_device_register(&ra_i2cs[i].bus, ra_i2cs[i].bus_name);
  178. }
  179. return 0;
  180. }
  181. INIT_DEVICE_EXPORT(ra_hw_i2c_init);
  182. #endif /* BSP_USING_I2C */