drv_usart.c 31 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. */
  10. #include "board.h"
  11. #include "drv_usart.h"
  12. #include "drv_config.h"
  13. #ifdef RT_USING_SERIAL
  14. //#define DRV_DEBUG
  15. #define LOG_TAG "drv.usart"
  16. #include <drv_log.h>
  17. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  18. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  19. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  20. #error "Please define at least one BSP_USING_UARTx"
  21. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  22. #endif
  23. #ifdef RT_SERIAL_USING_DMA
  24. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  25. #endif
  26. enum
  27. {
  28. #ifdef BSP_USING_UART1
  29. UART1_INDEX,
  30. #endif
  31. #ifdef BSP_USING_UART2
  32. UART2_INDEX,
  33. #endif
  34. #ifdef BSP_USING_UART3
  35. UART3_INDEX,
  36. #endif
  37. #ifdef BSP_USING_UART4
  38. UART4_INDEX,
  39. #endif
  40. #ifdef BSP_USING_UART5
  41. UART5_INDEX,
  42. #endif
  43. #ifdef BSP_USING_UART6
  44. UART6_INDEX,
  45. #endif
  46. #ifdef BSP_USING_UART7
  47. UART7_INDEX,
  48. #endif
  49. #ifdef BSP_USING_UART8
  50. UART8_INDEX,
  51. #endif
  52. #ifdef BSP_USING_LPUART1
  53. LPUART1_INDEX,
  54. #endif
  55. };
  56. static struct stm32_uart_config uart_config[] =
  57. {
  58. #ifdef BSP_USING_UART1
  59. UART1_CONFIG,
  60. #endif
  61. #ifdef BSP_USING_UART2
  62. UART2_CONFIG,
  63. #endif
  64. #ifdef BSP_USING_UART3
  65. UART3_CONFIG,
  66. #endif
  67. #ifdef BSP_USING_UART4
  68. UART4_CONFIG,
  69. #endif
  70. #ifdef BSP_USING_UART5
  71. UART5_CONFIG,
  72. #endif
  73. #ifdef BSP_USING_UART6
  74. UART6_CONFIG,
  75. #endif
  76. #ifdef BSP_USING_UART7
  77. UART7_CONFIG,
  78. #endif
  79. #ifdef BSP_USING_UART8
  80. UART8_CONFIG,
  81. #endif
  82. #ifdef BSP_USING_LPUART1
  83. LPUART1_CONFIG,
  84. #endif
  85. };
  86. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  87. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  88. {
  89. struct stm32_uart *uart;
  90. RT_ASSERT(serial != RT_NULL);
  91. RT_ASSERT(cfg != RT_NULL);
  92. uart = rt_container_of(serial, struct stm32_uart, serial);
  93. uart->handle.Instance = uart->config->Instance;
  94. uart->handle.Init.BaudRate = cfg->baud_rate;
  95. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  96. uart->handle.Init.Mode = UART_MODE_TX_RX;
  97. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  98. switch (cfg->data_bits)
  99. {
  100. case DATA_BITS_8:
  101. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  102. break;
  103. case DATA_BITS_9:
  104. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  105. break;
  106. default:
  107. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  108. break;
  109. }
  110. switch (cfg->stop_bits)
  111. {
  112. case STOP_BITS_1:
  113. uart->handle.Init.StopBits = UART_STOPBITS_1;
  114. break;
  115. case STOP_BITS_2:
  116. uart->handle.Init.StopBits = UART_STOPBITS_2;
  117. break;
  118. default:
  119. uart->handle.Init.StopBits = UART_STOPBITS_1;
  120. break;
  121. }
  122. switch (cfg->parity)
  123. {
  124. case PARITY_NONE:
  125. uart->handle.Init.Parity = UART_PARITY_NONE;
  126. break;
  127. case PARITY_ODD:
  128. uart->handle.Init.Parity = UART_PARITY_ODD;
  129. break;
  130. case PARITY_EVEN:
  131. uart->handle.Init.Parity = UART_PARITY_EVEN;
  132. break;
  133. default:
  134. uart->handle.Init.Parity = UART_PARITY_NONE;
  135. break;
  136. }
  137. #ifdef RT_SERIAL_USING_DMA
  138. uart->dma_rx.last_index = 0;
  139. #endif
  140. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  141. {
  142. return -RT_ERROR;
  143. }
  144. return RT_EOK;
  145. }
  146. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  147. {
  148. struct stm32_uart *uart;
  149. #ifdef RT_SERIAL_USING_DMA
  150. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  151. #endif
  152. RT_ASSERT(serial != RT_NULL);
  153. uart = rt_container_of(serial, struct stm32_uart, serial);
  154. switch (cmd)
  155. {
  156. /* disable interrupt */
  157. case RT_DEVICE_CTRL_CLR_INT:
  158. /* disable rx irq */
  159. NVIC_DisableIRQ(uart->config->irq_type);
  160. /* disable interrupt */
  161. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  162. #ifdef RT_SERIAL_USING_DMA
  163. /* disable DMA */
  164. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  165. {
  166. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  167. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  168. {
  169. RT_ASSERT(0);
  170. }
  171. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  172. {
  173. RT_ASSERT(0);
  174. }
  175. }
  176. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  177. {
  178. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  179. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  180. {
  181. RT_ASSERT(0);
  182. }
  183. }
  184. #endif
  185. break;
  186. /* enable interrupt */
  187. case RT_DEVICE_CTRL_SET_INT:
  188. /* enable rx irq */
  189. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  190. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  191. /* enable interrupt */
  192. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  193. break;
  194. #ifdef RT_SERIAL_USING_DMA
  195. case RT_DEVICE_CTRL_CONFIG:
  196. stm32_dma_config(serial, ctrl_arg);
  197. break;
  198. #endif
  199. case RT_DEVICE_CTRL_CLOSE:
  200. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  201. {
  202. RT_ASSERT(0)
  203. }
  204. break;
  205. }
  206. return RT_EOK;
  207. }
  208. static int stm32_putc(struct rt_serial_device *serial, char c)
  209. {
  210. struct stm32_uart *uart;
  211. RT_ASSERT(serial != RT_NULL);
  212. uart = rt_container_of(serial, struct stm32_uart, serial);
  213. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  214. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  215. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  216. || defined(SOC_SERIES_STM32G4)
  217. uart->handle.Instance->TDR = c;
  218. #else
  219. uart->handle.Instance->DR = c;
  220. #endif
  221. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  222. return 1;
  223. }
  224. static int stm32_getc(struct rt_serial_device *serial)
  225. {
  226. int ch;
  227. struct stm32_uart *uart;
  228. RT_ASSERT(serial != RT_NULL);
  229. uart = rt_container_of(serial, struct stm32_uart, serial);
  230. ch = -1;
  231. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  232. {
  233. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  234. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  235. || defined(SOC_SERIES_STM32G4)
  236. ch = uart->handle.Instance->RDR & 0xff;
  237. #else
  238. ch = uart->handle.Instance->DR & 0xff;
  239. #endif
  240. }
  241. return ch;
  242. }
  243. static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  244. {
  245. struct stm32_uart *uart;
  246. RT_ASSERT(serial != RT_NULL);
  247. RT_ASSERT(buf != RT_NULL);
  248. uart = rt_container_of(serial, struct stm32_uart, serial);
  249. if (size == 0)
  250. {
  251. return 0;
  252. }
  253. if (RT_SERIAL_DMA_TX == direction)
  254. {
  255. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  256. {
  257. return size;
  258. }
  259. else
  260. {
  261. return 0;
  262. }
  263. }
  264. return 0;
  265. }
  266. /**
  267. * Uart common interrupt process. This need add to uart ISR.
  268. *
  269. * @param serial serial device
  270. */
  271. static void uart_isr(struct rt_serial_device *serial)
  272. {
  273. struct stm32_uart *uart;
  274. #ifdef RT_SERIAL_USING_DMA
  275. rt_size_t recv_total_index, recv_len;
  276. rt_base_t level;
  277. #endif
  278. RT_ASSERT(serial != RT_NULL);
  279. uart = rt_container_of(serial, struct stm32_uart, serial);
  280. /* UART in mode Receiver -------------------------------------------------*/
  281. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  282. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  283. {
  284. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  285. }
  286. #ifdef RT_SERIAL_USING_DMA
  287. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  288. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  289. {
  290. level = rt_hw_interrupt_disable();
  291. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  292. recv_len = recv_total_index - uart->dma_rx.last_index;
  293. uart->dma_rx.last_index = recv_total_index;
  294. rt_hw_interrupt_enable(level);
  295. if (recv_len)
  296. {
  297. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  298. }
  299. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  300. }
  301. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  302. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  303. {
  304. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  305. {
  306. HAL_UART_IRQHandler(&(uart->handle));
  307. }
  308. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  309. }
  310. #endif
  311. else
  312. {
  313. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  314. {
  315. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  316. }
  317. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  318. {
  319. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  320. }
  321. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  322. {
  323. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  324. }
  325. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  326. {
  327. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  328. }
  329. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  330. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  331. && !defined(SOC_SERIES_STM32G4)
  332. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  333. {
  334. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  335. }
  336. #endif
  337. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  338. {
  339. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  340. }
  341. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  342. {
  343. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  344. }
  345. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  346. {
  347. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  348. }
  349. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  350. {
  351. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  352. }
  353. }
  354. }
  355. #ifdef RT_SERIAL_USING_DMA
  356. static void dma_isr(struct rt_serial_device *serial)
  357. {
  358. struct stm32_uart *uart;
  359. rt_size_t recv_total_index, recv_len;
  360. rt_base_t level;
  361. RT_ASSERT(serial != RT_NULL);
  362. uart = rt_container_of(serial, struct stm32_uart, serial);
  363. if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
  364. (__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
  365. {
  366. level = rt_hw_interrupt_disable();
  367. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  368. if (recv_total_index == 0)
  369. {
  370. recv_len = serial->config.bufsz - uart->dma_rx.last_index;
  371. }
  372. else
  373. {
  374. recv_len = recv_total_index - uart->dma_rx.last_index;
  375. }
  376. uart->dma_rx.last_index = recv_total_index;
  377. rt_hw_interrupt_enable(level);
  378. if (recv_len)
  379. {
  380. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  381. }
  382. }
  383. }
  384. #endif
  385. #if defined(BSP_USING_UART1)
  386. void USART1_IRQHandler(void)
  387. {
  388. /* enter interrupt */
  389. rt_interrupt_enter();
  390. uart_isr(&(uart_obj[UART1_INDEX].serial));
  391. /* leave interrupt */
  392. rt_interrupt_leave();
  393. }
  394. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  395. void UART1_DMA_RX_IRQHandler(void)
  396. {
  397. /* enter interrupt */
  398. rt_interrupt_enter();
  399. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  400. /* leave interrupt */
  401. rt_interrupt_leave();
  402. }
  403. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  404. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  405. void UART1_DMA_TX_IRQHandler(void)
  406. {
  407. /* enter interrupt */
  408. rt_interrupt_enter();
  409. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  410. /* leave interrupt */
  411. rt_interrupt_leave();
  412. }
  413. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  414. #endif /* BSP_USING_UART1 */
  415. #if defined(BSP_USING_UART2)
  416. void USART2_IRQHandler(void)
  417. {
  418. /* enter interrupt */
  419. rt_interrupt_enter();
  420. uart_isr(&(uart_obj[UART2_INDEX].serial));
  421. /* leave interrupt */
  422. rt_interrupt_leave();
  423. }
  424. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  425. void UART2_DMA_RX_IRQHandler(void)
  426. {
  427. /* enter interrupt */
  428. rt_interrupt_enter();
  429. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  430. /* leave interrupt */
  431. rt_interrupt_leave();
  432. }
  433. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  434. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  435. void UART2_DMA_TX_IRQHandler(void)
  436. {
  437. /* enter interrupt */
  438. rt_interrupt_enter();
  439. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  440. /* leave interrupt */
  441. rt_interrupt_leave();
  442. }
  443. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  444. #endif /* BSP_USING_UART2 */
  445. #if defined(BSP_USING_UART3)
  446. void USART3_IRQHandler(void)
  447. {
  448. /* enter interrupt */
  449. rt_interrupt_enter();
  450. uart_isr(&(uart_obj[UART3_INDEX].serial));
  451. /* leave interrupt */
  452. rt_interrupt_leave();
  453. }
  454. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  455. void UART3_DMA_RX_IRQHandler(void)
  456. {
  457. /* enter interrupt */
  458. rt_interrupt_enter();
  459. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  460. /* leave interrupt */
  461. rt_interrupt_leave();
  462. }
  463. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  464. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  465. void UART3_DMA_TX_IRQHandler(void)
  466. {
  467. /* enter interrupt */
  468. rt_interrupt_enter();
  469. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  470. /* leave interrupt */
  471. rt_interrupt_leave();
  472. }
  473. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  474. #endif /* BSP_USING_UART3*/
  475. #if defined(BSP_USING_UART4)
  476. void UART4_IRQHandler(void)
  477. {
  478. /* enter interrupt */
  479. rt_interrupt_enter();
  480. uart_isr(&(uart_obj[UART4_INDEX].serial));
  481. /* leave interrupt */
  482. rt_interrupt_leave();
  483. }
  484. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  485. void UART4_DMA_RX_IRQHandler(void)
  486. {
  487. /* enter interrupt */
  488. rt_interrupt_enter();
  489. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  490. /* leave interrupt */
  491. rt_interrupt_leave();
  492. }
  493. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  494. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  495. void UART4_DMA_TX_IRQHandler(void)
  496. {
  497. /* enter interrupt */
  498. rt_interrupt_enter();
  499. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  500. /* leave interrupt */
  501. rt_interrupt_leave();
  502. }
  503. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  504. #endif /* BSP_USING_UART4*/
  505. #if defined(BSP_USING_UART5)
  506. void UART5_IRQHandler(void)
  507. {
  508. /* enter interrupt */
  509. rt_interrupt_enter();
  510. uart_isr(&(uart_obj[UART5_INDEX].serial));
  511. /* leave interrupt */
  512. rt_interrupt_leave();
  513. }
  514. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  515. void UART5_DMA_RX_IRQHandler(void)
  516. {
  517. /* enter interrupt */
  518. rt_interrupt_enter();
  519. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  520. /* leave interrupt */
  521. rt_interrupt_leave();
  522. }
  523. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  524. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  525. void UART5_DMA_TX_IRQHandler(void)
  526. {
  527. /* enter interrupt */
  528. rt_interrupt_enter();
  529. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  530. /* leave interrupt */
  531. rt_interrupt_leave();
  532. }
  533. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  534. #endif /* BSP_USING_UART5*/
  535. #if defined(BSP_USING_UART6)
  536. void USART6_IRQHandler(void)
  537. {
  538. /* enter interrupt */
  539. rt_interrupt_enter();
  540. uart_isr(&(uart_obj[UART6_INDEX].serial));
  541. /* leave interrupt */
  542. rt_interrupt_leave();
  543. }
  544. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  545. void UART6_DMA_RX_IRQHandler(void)
  546. {
  547. /* enter interrupt */
  548. rt_interrupt_enter();
  549. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  550. /* leave interrupt */
  551. rt_interrupt_leave();
  552. }
  553. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  554. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  555. void UART6_DMA_TX_IRQHandler(void)
  556. {
  557. /* enter interrupt */
  558. rt_interrupt_enter();
  559. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  560. /* leave interrupt */
  561. rt_interrupt_leave();
  562. }
  563. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  564. #endif /* BSP_USING_UART6*/
  565. #if defined(BSP_USING_UART7)
  566. void UART7_IRQHandler(void)
  567. {
  568. /* enter interrupt */
  569. rt_interrupt_enter();
  570. uart_isr(&(uart_obj[UART7_INDEX].serial));
  571. /* leave interrupt */
  572. rt_interrupt_leave();
  573. }
  574. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  575. void UART7_DMA_RX_IRQHandler(void)
  576. {
  577. /* enter interrupt */
  578. rt_interrupt_enter();
  579. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  580. /* leave interrupt */
  581. rt_interrupt_leave();
  582. }
  583. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  584. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  585. void UART7_DMA_TX_IRQHandler(void)
  586. {
  587. /* enter interrupt */
  588. rt_interrupt_enter();
  589. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  590. /* leave interrupt */
  591. rt_interrupt_leave();
  592. }
  593. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  594. #endif /* BSP_USING_UART7*/
  595. #if defined(BSP_USING_UART8)
  596. void UART8_IRQHandler(void)
  597. {
  598. /* enter interrupt */
  599. rt_interrupt_enter();
  600. uart_isr(&(uart_obj[UART8_INDEX].serial));
  601. /* leave interrupt */
  602. rt_interrupt_leave();
  603. }
  604. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  605. void UART8_DMA_RX_IRQHandler(void)
  606. {
  607. /* enter interrupt */
  608. rt_interrupt_enter();
  609. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  610. /* leave interrupt */
  611. rt_interrupt_leave();
  612. }
  613. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  614. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  615. void UART8_DMA_TX_IRQHandler(void)
  616. {
  617. /* enter interrupt */
  618. rt_interrupt_enter();
  619. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  620. /* leave interrupt */
  621. rt_interrupt_leave();
  622. }
  623. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  624. #endif /* BSP_USING_UART8*/
  625. #if defined(BSP_USING_LPUART1)
  626. void LPUART1_IRQHandler(void)
  627. {
  628. /* enter interrupt */
  629. rt_interrupt_enter();
  630. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  631. /* leave interrupt */
  632. rt_interrupt_leave();
  633. }
  634. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  635. void LPUART1_DMA_RX_IRQHandler(void)
  636. {
  637. /* enter interrupt */
  638. rt_interrupt_enter();
  639. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  640. /* leave interrupt */
  641. rt_interrupt_leave();
  642. }
  643. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  644. #endif /* BSP_USING_LPUART1*/
  645. static void stm32_uart_get_dma_config(void)
  646. {
  647. #ifdef BSP_USING_UART1
  648. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  649. #ifdef BSP_UART1_RX_USING_DMA
  650. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  651. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  652. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  653. #endif
  654. #ifdef BSP_UART1_TX_USING_DMA
  655. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  656. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  657. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  658. #endif
  659. #endif
  660. #ifdef BSP_USING_UART2
  661. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  662. #ifdef BSP_UART2_RX_USING_DMA
  663. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  664. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  665. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  666. #endif
  667. #ifdef BSP_UART2_TX_USING_DMA
  668. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  669. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  670. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  671. #endif
  672. #endif
  673. #ifdef BSP_USING_UART3
  674. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  675. #ifdef BSP_UART3_RX_USING_DMA
  676. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  677. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  678. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  679. #endif
  680. #ifdef BSP_UART3_TX_USING_DMA
  681. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  682. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  683. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  684. #endif
  685. #endif
  686. #ifdef BSP_USING_UART4
  687. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  688. #ifdef BSP_UART4_RX_USING_DMA
  689. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  690. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  691. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  692. #endif
  693. #ifdef BSP_UART4_TX_USING_DMA
  694. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  695. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  696. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  697. #endif
  698. #endif
  699. #ifdef BSP_USING_UART5
  700. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  701. #ifdef BSP_UART5_RX_USING_DMA
  702. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  703. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  704. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  705. #endif
  706. #ifdef BSP_UART5_TX_USING_DMA
  707. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  708. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  709. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  710. #endif
  711. #endif
  712. #ifdef BSP_USING_UART6
  713. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  714. #ifdef BSP_UART6_RX_USING_DMA
  715. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  716. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  717. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  718. #endif
  719. #ifdef BSP_UART6_TX_USING_DMA
  720. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  721. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  722. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  723. #endif
  724. #endif
  725. }
  726. #ifdef RT_SERIAL_USING_DMA
  727. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  728. {
  729. struct rt_serial_rx_fifo *rx_fifo;
  730. DMA_HandleTypeDef *DMA_Handle;
  731. struct dma_config *dma_config;
  732. struct stm32_uart *uart;
  733. RT_ASSERT(serial != RT_NULL);
  734. uart = rt_container_of(serial, struct stm32_uart, serial);
  735. if (RT_DEVICE_FLAG_DMA_RX == flag)
  736. {
  737. DMA_Handle = &uart->dma_rx.handle;
  738. dma_config = uart->config->dma_rx;
  739. }
  740. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  741. {
  742. DMA_Handle = &uart->dma_tx.handle;
  743. dma_config = uart->config->dma_tx;
  744. }
  745. LOG_D("%s dma config start", uart->config->name);
  746. {
  747. rt_uint32_t tmpreg = 0x00U;
  748. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  749. || defined(SOC_SERIES_STM32L0)
  750. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  751. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  752. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  753. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
  754. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  755. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  756. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  757. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  758. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
  759. /* enable DMAMUX clock for L4+ and G4 */
  760. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  761. #elif defined(SOC_SERIES_STM32MP1)
  762. __HAL_RCC_DMAMUX_CLK_ENABLE();
  763. __HAL_RCC_DMA2_CLK_ENABLE();
  764. #endif
  765. #endif
  766. UNUSED(tmpreg); /* To avoid compiler warnings */
  767. }
  768. if (RT_DEVICE_FLAG_DMA_RX == flag)
  769. {
  770. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  771. }
  772. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  773. {
  774. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  775. }
  776. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
  777. DMA_Handle->Instance = dma_config->Instance;
  778. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  779. DMA_Handle->Instance = dma_config->Instance;
  780. DMA_Handle->Init.Channel = dma_config->channel;
  781. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  782. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  783. DMA_Handle->Instance = dma_config->Instance;
  784. DMA_Handle->Init.Request = dma_config->request;
  785. #endif
  786. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  787. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  788. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  789. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  790. if (RT_DEVICE_FLAG_DMA_RX == flag)
  791. {
  792. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  793. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  794. }
  795. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  796. {
  797. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  798. DMA_Handle->Init.Mode = DMA_NORMAL;
  799. }
  800. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  801. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  802. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  803. #endif
  804. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  805. {
  806. RT_ASSERT(0);
  807. }
  808. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  809. {
  810. RT_ASSERT(0);
  811. }
  812. /* enable interrupt */
  813. if (flag == RT_DEVICE_FLAG_DMA_RX)
  814. {
  815. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  816. /* Start DMA transfer */
  817. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  818. {
  819. /* Transfer error in reception process */
  820. RT_ASSERT(0);
  821. }
  822. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  823. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  824. }
  825. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  826. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  827. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  828. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  829. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  830. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  831. LOG_D("%s dma config done", uart->config->name);
  832. }
  833. /**
  834. * @brief UART error callbacks
  835. * @param huart: UART handle
  836. * @note This example shows a simple way to report transfer error, and you can
  837. * add your own implementation.
  838. * @retval None
  839. */
  840. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  841. {
  842. RT_ASSERT(huart != NULL);
  843. struct stm32_uart *uart = (struct stm32_uart *)huart;
  844. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  845. UNUSED(uart);
  846. }
  847. /**
  848. * @brief Rx Transfer completed callback
  849. * @param huart: UART handle
  850. * @note This example shows a simple way to report end of DMA Rx transfer, and
  851. * you can add your own implementation.
  852. * @retval None
  853. */
  854. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  855. {
  856. struct stm32_uart *uart;
  857. RT_ASSERT(huart != NULL);
  858. uart = (struct stm32_uart *)huart;
  859. dma_isr(&uart->serial);
  860. }
  861. /**
  862. * @brief Rx Half transfer completed callback
  863. * @param huart: UART handle
  864. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  865. * and you can add your own implementation.
  866. * @retval None
  867. */
  868. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  869. {
  870. struct stm32_uart *uart;
  871. RT_ASSERT(huart != NULL);
  872. uart = (struct stm32_uart *)huart;
  873. dma_isr(&uart->serial);
  874. }
  875. static void _dma_tx_complete(struct rt_serial_device *serial)
  876. {
  877. struct stm32_uart *uart;
  878. rt_size_t trans_total_index;
  879. rt_base_t level;
  880. RT_ASSERT(serial != RT_NULL);
  881. uart = rt_container_of(serial, struct stm32_uart, serial);
  882. level = rt_hw_interrupt_disable();
  883. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  884. rt_hw_interrupt_enable(level);
  885. if (trans_total_index == 0)
  886. {
  887. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  888. }
  889. }
  890. /**
  891. * @brief HAL_UART_TxCpltCallback
  892. * @param huart: UART handle
  893. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  894. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  895. * @retval None
  896. */
  897. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  898. {
  899. struct stm32_uart *uart;
  900. RT_ASSERT(huart != NULL);
  901. uart = (struct stm32_uart *)huart;
  902. _dma_tx_complete(&uart->serial);
  903. }
  904. #endif /* RT_SERIAL_USING_DMA */
  905. static const struct rt_uart_ops stm32_uart_ops =
  906. {
  907. .configure = stm32_configure,
  908. .control = stm32_control,
  909. .putc = stm32_putc,
  910. .getc = stm32_getc,
  911. .dma_transmit = stm32_dma_transmit
  912. };
  913. int rt_hw_usart_init(void)
  914. {
  915. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  916. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  917. rt_err_t result = 0;
  918. stm32_uart_get_dma_config();
  919. for (int i = 0; i < obj_num; i++)
  920. {
  921. uart_obj[i].config = &uart_config[i];
  922. uart_obj[i].serial.ops = &stm32_uart_ops;
  923. uart_obj[i].serial.config = config;
  924. /* register UART device */
  925. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  926. RT_DEVICE_FLAG_RDWR
  927. | RT_DEVICE_FLAG_INT_RX
  928. | RT_DEVICE_FLAG_INT_TX
  929. | uart_obj[i].uart_dma_flag
  930. , NULL);
  931. RT_ASSERT(result == RT_EOK);
  932. }
  933. return result;
  934. }
  935. #endif /* RT_USING_SERIAL */