sdk-rt-thread-source-code/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.icf

include "memory_regions.icf";

/* The memory information for each device is done in memory regions file.
 * The starting address and length of memory not defined in memory regions file are defined as 0. */

if (isdefinedsymbol(ATCM_START))
{
    define symbol ATCM_PRV_START = ATCM_START;
}
else
{
    define symbol ATCM_PRV_START = 0;
}

if (isdefinedsymbol(ATCM_LENGTH))
{
    define symbol ATCM_PRV_LENGTH = ATCM_LENGTH;
}
else
{
    define symbol ATCM_PRV_LENGTH = 0;
}

if (isdefinedsymbol(BTCM_START))
{
    define symbol BTCM_PRV_START = BTCM_START;
}
else
{
    define symbol BTCM_PRV_START = 0;
}

if (isdefinedsymbol(BTCM_LENGTH))
{
    define symbol BTCM_PRV_LENGTH = BTCM_LENGTH;
}
else
{
    define symbol BTCM_PRV_LENGTH = 0;
}

if (isdefinedsymbol(SYSTEM_RAM_START))
{
    define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START;
}
else
{
    define symbol SYSTEM_RAM_PRV_START = 0;
}

if (isdefinedsymbol(SYSTEM_RAM_LENGTH))
{
    define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH;
}
else
{
    define symbol SYSTEM_RAM_PRV_LENGTH = 0;
}

if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START))
{
    define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START;
}
else
{
    define symbol SYSTEM_RAM_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH))
{
    define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH;
}
else
{
    define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START))
{
    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START;
}
else
{
    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH))
{
    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START))
{
    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START;
}
else
{
    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH))
{
    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START))
{
    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START;
}
else
{
    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH))
{
    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START))
{
    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START;
}
else
{
    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH))
{
    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS0_SPACE_MIRROR_START))
{
    define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START;
}
else
{
    define symbol CS0_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH))
{
    define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS2_SPACE_MIRROR_START))
{
    define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START;
}
else
{
    define symbol CS2_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH))
{
    define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0;
}


if (isdefinedsymbol(CS3_SPACE_MIRROR_START))
{
    define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START;
}
else
{
    define symbol CS3_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH))
{
    define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS5_SPACE_MIRROR_START))
{
    define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START;
}
else
{
    define symbol CS5_SPACE_MIRROR_PRV_START = 0;
}

if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH))
{
    define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH;
}
else
{
    define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0;
}


if (isdefinedsymbol(xSPI0_CS0_SPACE_START))
{
    define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START;
}
else
{
    define symbol xSPI0_CS0_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH))
{
    define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH;
}
else
{
    define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI0_CS1_SPACE_START))
{
    define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START;
}
else
{
    define symbol xSPI0_CS1_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH))
{
    define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH;
}
else
{
    define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI1_CS0_SPACE_START))
{
    define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START;
}
else
{
    define symbol xSPI1_CS0_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH))
{
    define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH;
}
else
{
    define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(xSPI1_CS1_SPACE_START))
{
    define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START;
}
else
{
    define symbol xSPI1_CS1_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH))
{
    define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH;
}
else
{
    define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS0_SPACE_START))
{
    define symbol CS0_SPACE_PRV_START = CS0_SPACE_START;
}
else
{
    define symbol CS0_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(CS0_SPACE_LENGTH))
{
    define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH;
}
else
{
    define symbol CS0_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS2_SPACE_START))
{
    define symbol CS2_SPACE_PRV_START = CS2_SPACE_START;
}
else
{
    define symbol CS2_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(CS2_SPACE_LENGTH))
{
    define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH;
}
else
{
    define symbol CS2_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS3_SPACE_START))
{
    define symbol CS3_SPACE_PRV_START = CS3_SPACE_START;
}
else
{
    define symbol CS3_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(CS3_SPACE_LENGTH))
{
    define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH;
}
else
{
    define symbol CS3_SPACE_PRV_LENGTH = 0;
}

if (isdefinedsymbol(CS5_SPACE_START))
{
    define symbol CS5_SPACE_PRV_START = CS5_SPACE_START;
}
else
{
    define symbol CS5_SPACE_PRV_START = 0;
}

if (isdefinedsymbol(CS5_SPACE_LENGTH))
{
    define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH;
}
else
{
    define symbol CS5_SPACE_PRV_LENGTH = 0;
}

define symbol SYSTEM_RAM_END_OFFSET            = 0x00070000;
define symbol tmp_flash_address                = xSPI0_CS0_SPACE_PRV_START % 0x80000;
define symbol FLASH_ADDRESS                    = (0 == tmp_flash_address) ? xSPI0_CS0_SPACE_PRV_START : xSPI0_CS0_SPACE_PRV_START + (0x80000 - tmp_flash_address);

if (isdefinedsymbol(CR52_0))
{
    define symbol INTVEC_ADDRESS               = ATCM_PRV_START;
    define symbol RAM_ADDRESS                  = (ATCM_PRV_START + 0x100);
    define symbol RAM_END_ADDRESS              = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1);
    define symbol LOADER_STACK_ADDRESS         = (BTCM_PRV_START + 0x2000);
    define symbol LOADER_STACK_END_ADDRESS     = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1);
    define symbol DATA_NONCACHE_OFFSET         = 0x00070000;
    define symbol DATA_NONCACHE_END_OFFSET     = 0x0006C000;
    define symbol DMAC_LINK_MODE_OFFSET        = 0x00068000;
    define symbol DMAC_LINK_MODE_END_OFFSET    = 0x00064000;
    define symbol NONCACHE_BUFFER_OFFSET       = 0x00040000;
    define symbol NONCACHE_BUFFER_END_OFFSET   = 0x00020000;
}
else
{

    define symbol INTVEC_ADDRESS              = SYSTEM_RAM_PRV_START;
    define symbol LOADER_STACK_ADDRESS        = (SYSTEM_RAM_PRV_START + 0x10000);
    define symbol LOADER_STACK_END_ADDRESS    = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - 1);
    define symbol RAM_ADDRESS                 = (SYSTEM_RAM_PRV_START + 0x20000);
    define symbol RAM_END_ADDRESS             = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1);
    define symbol DATA_NONCACHE_OFFSET        = 0x0006C000;
    define symbol DATA_NONCACHE_END_OFFSET    = 0x00068000;
    define symbol DMAC_LINK_MODE_OFFSET       = 0x00064000;
    define symbol DMAC_LINK_MODE_END_OFFSET   = 0x00060000;
    define symbol NONCACHE_BUFFER_OFFSET      = 0x00020000;
    define symbol NONCACHE_BUFFER_END_OFFSET  = 0;
}

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100;
define symbol __ICFEDIT_region_ROM_end__   = FLASH_ADDRESS + 0x6FFFF;
define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS;
define symbol __ICFEDIT_region_RAM_end__   = RAM_END_ADDRESS;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];

define symbol __region_D_LOADER_STACK_start__    = LOADER_STACK_ADDRESS;
define symbol __region_D_LOADER_STACK_end__      = LOADER_STACK_END_ADDRESS;

define symbol __region_DATA_NONCACHE_start__          = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET;
define symbol __region_DATA_NONCACHE_end__            = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1;
define symbol __region_DMAC_LINK_MODE_start__         = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET;
define symbol __region_DMAC_LINK_MODE_end__           = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1;
define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00060000;
define symbol __region_SHARED_NONCACHE_BUFFER_end__   = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000 - 1;
define symbol __region_NONCACHE_BUFFER_start__        = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET;
define symbol __region_NONCACHE_BUFFER_end__          = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1;

define symbol __region_ATCM_start__              = ATCM_PRV_START;
define symbol __region_ATCM_end__                = ATCM_PRV_START + ATCM_PRV_LENGTH - 1;
define symbol __region_BTCM_start__              = BTCM_PRV_START;
define symbol __region_BTCM_end__                = BTCM_PRV_START + BTCM_PRV_LENGTH - 1;
define symbol __region_SYSTEM_RAM_start__        = SYSTEM_RAM_PRV_START;
define symbol __region_SYSTEM_RAM_end__          = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1;
define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START;
define symbol __region_SYSTEM_RAM_MIRROR_end__   = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1;

define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START;
define symbol __region_XSPI0_CS0_MIRROR_end__   = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START;
define symbol __region_XSPI0_CS1_MIRROR_end__   = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START;
define symbol __region_XSPI1_CS0_MIRROR_end__   = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START;
define symbol __region_XSPI1_CS1_MIRROR_end__   = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_CS0_MIRROR_start__       = CS0_SPACE_MIRROR_PRV_START;
define symbol __region_CS0_MIRROR_end__         = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_CS2_MIRROR_start__       = CS2_SPACE_MIRROR_PRV_START;
define symbol __region_CS2_MIRROR_end__         = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_CS3_MIRROR_start__       = CS3_SPACE_MIRROR_PRV_START;
define symbol __region_CS3_MIRROR_end__         = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_CS5_MIRROR_start__       = CS5_SPACE_MIRROR_PRV_START;
define symbol __region_CS5_MIRROR_end__         = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1;
define symbol __region_XSPI0_CS0_start__        = xSPI0_CS0_SPACE_PRV_START;
define symbol __region_XSPI0_CS0_end__          = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1;
define symbol __region_XSPI0_CS1_start__        = xSPI0_CS1_SPACE_PRV_START;
define symbol __region_XSPI0_CS1_end__          = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1;
define symbol __region_XSPI1_CS0_start__        = xSPI1_CS0_SPACE_PRV_START;
define symbol __region_XSPI1_CS0_end__          = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1;
define symbol __region_XSPI1_CS1_start__        = xSPI1_CS1_SPACE_PRV_START;
define symbol __region_XSPI1_CS1_end__          = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1;
define symbol __region_CS0_start__              = CS0_SPACE_PRV_START;
define symbol __region_CS0_end__                = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1;
define symbol __region_CS2_start__              = CS2_SPACE_PRV_START;
define symbol __region_CS2_end__                = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1;
define symbol __region_CS3_start__              = CS3_SPACE_PRV_START;
define symbol __region_CS3_end__                = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1;
define symbol __region_CS5_start__              = CS5_SPACE_PRV_START;
define symbol __region_CS5_end__                = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1;

/************** SPI boot mode setting **************/
define symbol __region_LDR_PARAM_start__        = FLASH_ADDRESS;
define symbol __region_LDR_PARAM_end__          = FLASH_ADDRESS + 0x0000004B;
define symbol __region_S_LOADER_STACK_start__   = FLASH_ADDRESS + 0x0000004C;
define symbol __region_S_LOADER_STACK_end__     = FLASH_ADDRESS + 0x0000804B;

define symbol __region_S_intvec_start__         = FLASH_ADDRESS + 0x20000;
define symbol __region_S_intvec_end__           = FLASH_ADDRESS + 0x200FF;
define symbol __region_S_RAM_start__            = FLASH_ADDRESS + 0x70000;
define symbol __region_S_RAM_end__              = FLASH_ADDRESS + 0x7FFFF;

define symbol __region_SECONDARY_start__        = FLASH_ADDRESS + 0x80000;
define symbol __region_SECONDARY_end__          = FLASH_ADDRESS + 0xFFFFF;
/****************************************************/

define exported symbol __ddsc_xSPI0_CS0_SPACE_START = FLASH_ADDRESS;

define region SECONDARY_region = mem:[from __region_SECONDARY_start__   to __region_SECONDARY_end__];

define region D_LOADER_STACK_region  = mem:[from __region_D_LOADER_STACK_start__   to __region_D_LOADER_STACK_end__];

define region LDR_PARAM_region       = mem:[from __region_LDR_PARAM_start__   to __region_LDR_PARAM_end__];
define region S_LOADER_STACK_region  = mem:[from __region_S_LOADER_STACK_start__   to __region_S_LOADER_STACK_end__];

define region S_intvec_region = mem:[from __region_S_intvec_start__  to __region_S_intvec_end__];
define region S_RAM_region    = mem:[from __region_S_RAM_start__  to __region_S_RAM_end__];

define region DATA_NONCACHE_region           = mem:[from __region_DATA_NONCACHE_start__   to __region_DATA_NONCACHE_end__];
define region DMAC_LINK_MODE_region          = mem:[from __region_DMAC_LINK_MODE_start__   to __region_DMAC_LINK_MODE_end__];
define region SHARED_NONCACHE_BUFFER_region  = mem:[from __region_SHARED_NONCACHE_BUFFER_start__   to __region_SHARED_NONCACHE_BUFFER_end__];
define region NONCACHE_BUFFER_region         = mem:[from __region_NONCACHE_BUFFER_start__   to __region_NONCACHE_BUFFER_end__];

define region ATCM_region              = mem:[from __region_ATCM_start__  to __region_ATCM_end__ ];
define region BTCM_region              = mem:[from __region_BTCM_start__  to __region_BTCM_end__ ];
define region SYSTEM_RAM_region        = mem:[from __region_SYSTEM_RAM_start__  to __region_SYSTEM_RAM_end__ ];
define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__  to __region_SYSTEM_RAM_MIRROR_end__ ];
define region XSPI0_CS0_MIRROR_region  = mem:[from __region_XSPI0_CS0_MIRROR_start__  to __region_XSPI0_CS0_MIRROR_end__ ];
define region XSPI0_CS1_MIRROR_region  = mem:[from __region_XSPI0_CS1_MIRROR_start__  to __region_XSPI0_CS1_MIRROR_end__ ];
define region XSPI1_CS0_MIRROR_region  = mem:[from __region_XSPI1_CS0_MIRROR_start__  to __region_XSPI1_CS0_MIRROR_end__ ];
define region XSPI1_CS1_MIRROR_region  = mem:[from __region_XSPI1_CS1_MIRROR_start__  to __region_XSPI1_CS1_MIRROR_end__ ];
define region CS0_MIRROR_region        = mem:[from __region_CS0_MIRROR_start__  to __region_CS0_MIRROR_end__ ];
define region CS2_MIRROR_region        = mem:[from __region_CS2_MIRROR_start__  to __region_CS2_MIRROR_end__ ];
define region CS3_MIRROR_region        = mem:[from __region_CS3_MIRROR_start__  to __region_CS3_MIRROR_end__ ];
define region CS5_MIRROR_region        = mem:[from __region_CS5_MIRROR_start__  to __region_CS5_MIRROR_end__ ];
define region XSPI0_CS0_region         = mem:[from __region_XSPI0_CS0_start__  to __region_XSPI0_CS0_end__ ];
define region XSPI0_CS1_region         = mem:[from __region_XSPI0_CS1_start__  to __region_XSPI0_CS1_end__ ];
define region XSPI1_CS0_region         = mem:[from __region_XSPI1_CS0_start__  to __region_XSPI1_CS0_end__ ];
define region XSPI1_CS1_region         = mem:[from __region_XSPI1_CS1_start__  to __region_XSPI1_CS1_end__ ];
define region CS0_region               = mem:[from __region_CS0_start__  to __region_CS0_end__ ];
define region CS2_region               = mem:[from __region_CS2_start__  to __region_CS2_end__ ];
define region CS3_region               = mem:[from __region_CS3_start__  to __region_CS3_end__ ];
define region CS5_region               = mem:[from __region_CS5_start__  to __region_CS5_end__ ];

/**************** RT-THREAD CINFIG *******************/
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
/**** End of ICF editor section. ###ICF###*/

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
/****************************************************/

define block LDR_PRG_RBLOCK with fixed order
                             { ro code section .loader_text_init object startup_core.o,
                               ro code object startup_core.o,
                               ro code object system_core.o,
                               ro code object startup.o,
                               ro code object system.o,
                               ro code object bsp_clocks.o,
                               ro code object bsp_irq_core.o,
                               ro code object bsp_irq.o,
                               ro code object bsp_semaphore.o,
                               ro code object bsp_register_protection.o,
                               ro code object r_ioport.o,
                               ro code object bsp_cache.o,
                               ro code section .warm_start_init }
                               except { ro code section .intvec_init,
                                        ro code section .reset_handler_init };
define block LDR_PRG_WBLOCK with fixed order
                             { rw code section .loader_text object startup_core.o,
                               rw code object startup_core.o,
                               rw code object system_core.o,
                               rw code object startup.o,
                               rw code object system.o,
                               rw code object bsp_clocks.o,
                               rw code object bsp_irq_core.o,
                               rw code object bsp_irq.o,
                               rw code object bsp_semaphore.o,
                               rw code object bsp_register_protection.o,
                               rw code object r_ioport.o,
                               rw code object bsp_cache.o,
                               rw code section .warm_start }
                               except { rw code section .intvec,
                                        rw code section .reset_handler };
define block LDR_DATA_ZBLOCK with alignment = 4
                             { section .bss object startup_core.o,
                               section .bss object system_core.o,
                               section .bss object startup.o,
                               section .bss object system.o,
                               section .bss object bsp_clocks.o,
                               section .bss object bsp_irq_core.o,
                               section .bss object bsp_irq.o,
                               section .bss object bsp_semaphore.o,
                               section .bss object bsp_register_protection.o,
                               section .bss object r_ioport.o,
                               section .bss object bsp_cache.o,
                               section .bss object bsp_io.o };
define block LDR_DATA_RBLOCK with fixed order, alignment = 4
                             { section .data_init object startup_core.o,
                               section .data_init object system_core.o,
                               section .data_init object startup.o,
                               section .data_init object system.o,
                               section .data_init object bsp_clocks.o,
                               section .data_init object bsp_irq_core.o,
                               section .data_init object bsp_irq.o,
                               section .data_init object bsp_semaphore.o,
                               section .data_init object bsp_register_protection.o,
                               section .data_init object r_ioport.o,
                               section .data_init object bsp_cache.o,
                               section .rodata_init object system_core.o };
define block LDR_DATA_WBLOCK with fixed order, alignment = 4
                             { section .data object startup_core.o,
                               section .data object system_core.o,
                               section .data object startup.o,
                               section .data object system.o,
                               section .data object bsp_clocks.o,
                               section .data object bsp_irq_core.o,
                               section .data object bsp_irq.o,
                               section .data object bsp_semaphore.o,
                               section .data object bsp_register_protection.o,
                               section .data object r_ioport.o,
                               section .data object bsp_cache.o,
                               section .rodata object system_core.o };

define block HEAP_BLOCK with alignment = 8 { rw section HEAP };
define block THREAD_STACK with alignment = 8 { rw section .stack* };
define block SYS_STACK with alignment = 8 { rw section .sys_stack };
define block SVC_STACK with alignment = 8 { rw section .svc_stack };
define block IRQ_STACK with alignment = 8 { rw section .irq_stack };
define block FIQ_STACK with alignment = 8 { rw section .fiq_stack };
define block UND_STACK with alignment = 8 { rw section .und_stack };
define block ABT_STACK with alignment = 8 { rw section .abt_stack };

define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init};
define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec};
define block USER_PRG_RBLOCK with alignment = 4 { ro code };
define block USER_PRG_WBLOCK with alignment = 4 { rw code };
define block USER_DATA_ZBLOCK with alignment = 4 { section .bss };
define block USER_DATA_RBLOCK with fixed order, alignment = 4
                              { section .data_init,
                                section __DLIB_PERTHREAD_init,
                                section .rodata_init,
                                section .version_init };
define block USER_DATA_WBLOCK with fixed order, alignment = 4
                              { section .data,
                                section __DLIB_PERTHREAD,
                                section .rodata,
                                section .version };
define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init };
define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache };
define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* };
define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* };
define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* };

define block xSPI0_CS0_SPACE_END_block { section .ddsc_xspi0_cs0_space_end };
define block xSPI0_CS0_SPACE_ALIGNMENT_block with alignment = 0x20000 {};

define block SECONDARY_RBLOCK { section SECONDARY };

initialize manually  { ro code object startup_core.o,
                       ro code object system_core.o,
                       ro code object startup.o,
                       ro code object system.o,
                       ro code object bsp_clocks.o,
                       ro code object bsp_irq_core.o,
                       ro code object bsp_irq.o,
                       ro code object bsp_semaphore.o,
                       ro code object bsp_register_protection.o,
                       ro code object r_ioport.o,
                       ro code object bsp_cache.o,
                       ro code section .intvec,
                       ro code section .reset_handler,
                       ro code section .warm_start,
                       ro code,
                       section .data,
                       section __DLIB_PERTHREAD,
                       section .rodata,
                       section .version,
                       section .data_noncache };

do not initialize   { section .noinit,
                      section .bss,
                      section .dmac_link_mode*,
                      section .shared_noncache_buffer*,
                      section .noncache_buffer*,
                      rw section HEAP,
                      rw section .stack*,
                      rw section .sys_stack,
                      rw section .svc_stack,
                      rw section .irq_stack,
                      rw section .fiq_stack,
                      rw section .und_stack,
                      rw section .abt_stack };

place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK };

place in LDR_PARAM_region { readonly section .loader_param };
place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK };
place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK };
place in S_intvec_region { block VECTOR_RBLOCK };
place in ROM_region   { block USER_PRG_RBLOCK, readonly };
place in S_RAM_region { readonly section .image_info };
place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK, block xSPI0_CS0_SPACE_END_block, last block xSPI0_CS0_SPACE_ALIGNMENT_block };

place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK };
place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK,
                                 section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK };
place in D_LOADER_STACK_region  { section SYS_STACK, block SYS_STACK,
                                  section SVC_STACK, block SVC_STACK,
                                  section IRQ_STACK, block IRQ_STACK,
                                  section FIQ_STACK, block FIQ_STACK,
                                  section UND_STACK, block UND_STACK,
                                  section ABT_STACK, block ABT_STACK };
place in RAM_region        { block USER_PRG_WBLOCK };
place in RAM_region        { readwrite };
place in RAM_region        { block USER_DATA_WBLOCK,
                             block USER_DATA_ZBLOCK,
                             block CSTACK };
place in RAM_region        { section HEAP_BLOCK, block HEAP_BLOCK,
                             section THREAD_STACK, block THREAD_STACK };

place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK };
place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK };
place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK };
place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK };
place in ATCM_region { };
place in BTCM_region { };
place in SYSTEM_RAM_region { };
place in SYSTEM_RAM_MIRROR_region { };
place in XSPI0_CS0_MIRROR_region { };
place in XSPI0_CS1_MIRROR_region { };
place in XSPI1_CS0_MIRROR_region { };
place in XSPI1_CS1_MIRROR_region { };
place in CS0_MIRROR_region { };
place in CS2_MIRROR_region { };
place in CS3_MIRROR_region { };
place in CS5_MIRROR_region { };
place in XSPI0_CS0_region { };
place in XSPI0_CS1_region { };
place in XSPI1_CS0_region { };
place in XSPI1_CS1_region { };
place in CS0_region { };
place in CS2_region { };
place in CS3_region { };
place in CS5_region { };
place in SECONDARY_region { block SECONDARY_RBLOCK };