clk.c 32 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455
  1. /*
  2. * Copyright (c) 2006-2025 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-11-26 GuEe-GUI first version
  9. * 2025-01-24 wumingzi add doxygen comment
  10. */
  11. #include <rtthread.h>
  12. #include <rtservice.h>
  13. #include <rtdevice.h>
  14. /**
  15. * @addtogroup group_driver_clock
  16. * @{
  17. */
  18. #define DBG_TAG "rtdm.clk"
  19. #define DBG_LVL DBG_INFO
  20. #include <rtdbg.h>
  21. static RT_DEFINE_SPINLOCK(_clk_lock);
  22. static rt_list_t _clk_nodes = RT_LIST_OBJECT_INIT(_clk_nodes);
  23. static rt_list_t _clk_notifier_nodes = RT_LIST_OBJECT_INIT(_clk_notifier_nodes);
  24. /**
  25. * @brief Release clock node
  26. *
  27. * @param r point to reference count of clock node
  28. * @warning The function only can print log and MORE DETAILS SHOULD BE IMPLEMENTED.
  29. */
  30. static void clk_release(struct rt_ref *r)
  31. {
  32. struct rt_clk_node *clk_np = rt_container_of(r, struct rt_clk_node, ref);
  33. LOG_E("%s is release", clk_np->name);
  34. (void)clk_np;
  35. RT_ASSERT(0);
  36. }
  37. /**
  38. * @brief Increase reference count for clock node
  39. *
  40. * @param clk_np point to clock node
  41. *
  42. * @return struct rt_clk_node * point to clock node whose reference count has increased
  43. */
  44. rt_inline struct rt_clk_node *clk_get(struct rt_clk_node *clk_np)
  45. {
  46. rt_ref_get(&clk_np->ref);
  47. return clk_np;
  48. }
  49. /**
  50. * @brief Decrease reference count for clock node
  51. *
  52. * @param clk_np point to clock node
  53. *
  54. */
  55. rt_inline void clk_put(struct rt_clk_node *clk_np)
  56. {
  57. rt_ref_put(&clk_np->ref, &clk_release);
  58. }
  59. /**
  60. * @brief Allocate memory space for struct clock and return it
  61. *
  62. * @param clk_np point to clock node
  63. * @param dev_id device identifier for the clock
  64. * @param con_id connection identifier for the clock
  65. * @param fw_node point to the firmware node associated with the clock
  66. *
  67. * @return struct rt_clk* point to clock
  68. */
  69. static struct rt_clk *clk_alloc(struct rt_clk_node *clk_np, const char *dev_id,
  70. const char *con_id, void *fw_node)
  71. {
  72. struct rt_clk *clk = rt_calloc(1, sizeof(*clk));
  73. if (clk)
  74. {
  75. clk->clk_np = clk_np;
  76. clk->dev_id = dev_id;
  77. clk->con_id = con_id;
  78. clk->fw_node = fw_node;
  79. }
  80. else
  81. {
  82. clk = rt_err_ptr(-RT_ENOMEM);
  83. }
  84. return clk;
  85. }
  86. /**
  87. * @brief Free memory space of clock object
  88. *
  89. * @param clk point to clock
  90. *
  91. */
  92. static void clk_free(struct rt_clk *clk)
  93. {
  94. struct rt_clk_node *clk_np = clk->clk_np;
  95. if (clk_np && clk_np->ops->finit)
  96. {
  97. clk_np->ops->finit(clk);
  98. }
  99. rt_free(clk);
  100. }
  101. /**
  102. * @brief Allocate memory space and creat clock object
  103. *
  104. * @param clk_np point to clock node
  105. * @param dev_id device identifier for the clock
  106. * @param con_id connection identifier for the clock
  107. * @param fw_data point to the firmware data associated with the clock
  108. * @param fw_node point to the firmware node associated with the clock
  109. *
  110. * @return struct rt_clk* point to clock
  111. */
  112. static struct rt_clk *clk_create(struct rt_clk_node *clk_np, const char *dev_id,
  113. const char *con_id, void *fw_data, void *fw_node)
  114. {
  115. struct rt_clk *clk = clk_alloc(clk_np, dev_id, con_id, fw_node);
  116. if (!rt_is_err(clk))
  117. {
  118. clk_get(clk_np);
  119. if (clk_np->ops->init && clk_np->ops->init(clk, fw_data))
  120. {
  121. LOG_E("Dev[%s] Con[%s] init fail", dev_id, con_id);
  122. clk_free(clk);
  123. clk = RT_NULL;
  124. }
  125. }
  126. return clk;
  127. }
  128. /**
  129. * @brief Notify corresponding clock from all
  130. *
  131. * @param clk_np point to clock node
  132. * @param msg message identifier for the event
  133. * @param old_rate old rate of the clock before the event
  134. * @param new_rate new rate of the clock after the event
  135. *
  136. * @return rt_err_t RT_EOK on notify clock sucessfully, and other value is failed.
  137. */
  138. static rt_err_t clk_notify(struct rt_clk_node *clk_np, rt_ubase_t msg, rt_ubase_t old_rate, rt_ubase_t new_rate)
  139. {
  140. rt_err_t err = RT_EOK;
  141. struct rt_clk_notifier *notifier;
  142. rt_list_for_each_entry(notifier, &_clk_notifier_nodes, list)
  143. {
  144. if (notifier->clk->clk_np == clk_np)
  145. {
  146. err = notifier->callback(notifier, msg, old_rate, new_rate);
  147. /* Only check hareware's error */
  148. if (err == -RT_EIO)
  149. {
  150. break;
  151. }
  152. }
  153. }
  154. return err;
  155. }
  156. /**
  157. * @brief Set parent clock
  158. *
  159. * @param clk_np point to clock node
  160. * @param parent_np point to parent rt_clk
  161. *
  162. */
  163. static void clk_set_parent(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np)
  164. {
  165. rt_hw_spin_lock(&_clk_lock.lock);
  166. clk_np->parent = parent_np;
  167. rt_list_insert_after(&parent_np->children_nodes, &clk_np->list);
  168. rt_hw_spin_unlock(&_clk_lock.lock);
  169. }
  170. static const struct rt_clk_ops unused_clk_ops =
  171. {
  172. };
  173. /**
  174. * @brief Register clock node into clock list
  175. *
  176. * @param clk_np point to child node that will be registered node.
  177. * @param parent_np point to parent rt_clk. If it is RT_NULL, clock node will be linked to init node.
  178. *
  179. * @retval RT_EOK
  180. * @retval -RT_ENOMEM
  181. */
  182. rt_err_t rt_clk_register(struct rt_clk_node *clk_np, struct rt_clk_node *parent_np)
  183. {
  184. rt_err_t err = RT_EOK;
  185. struct rt_clk *clk = RT_NULL;
  186. if (clk_np)
  187. {
  188. clk_np->clk = clk;
  189. if (!clk_np->ops)
  190. {
  191. clk_np->ops = &unused_clk_ops;
  192. }
  193. #if RT_NAME_MAX > 0
  194. rt_strncpy(clk_np->rt_parent.name, RT_CLK_NODE_OBJ_NAME, RT_NAME_MAX);
  195. #else
  196. clk_np->rt_parent.name = RT_CLK_NODE_OBJ_NAME;
  197. #endif
  198. rt_ref_init(&clk_np->ref);
  199. rt_list_init(&clk_np->list);
  200. rt_list_init(&clk_np->children_nodes);
  201. clk_np->multi_clk = 0;
  202. if (parent_np)
  203. {
  204. clk_np->clk = clk_alloc(clk_np, RT_NULL, RT_NULL, RT_NULL);
  205. if (clk_np->clk)
  206. {
  207. clk_set_parent(clk_np, parent_np);
  208. }
  209. else
  210. {
  211. err = -RT_ENOMEM;
  212. }
  213. }
  214. else
  215. {
  216. clk_np->parent = RT_NULL;
  217. rt_hw_spin_lock(&_clk_lock.lock);
  218. rt_list_insert_after(&_clk_nodes, &clk_np->list);
  219. rt_hw_spin_unlock(&_clk_lock.lock);
  220. }
  221. }
  222. else
  223. {
  224. err = -RT_ENOMEM;
  225. }
  226. return err;
  227. }
  228. /**
  229. * @brief Unregister clock node from clock list
  230. *
  231. * @param clk_np point to child node that will be Unregistered node.
  232. *
  233. * @retval RT_EOK
  234. * @retval -RT_EBUSY
  235. * @retval -RT_EINVAL
  236. */
  237. rt_err_t rt_clk_unregister(struct rt_clk_node *clk_np)
  238. {
  239. rt_err_t err = RT_EOK;
  240. if (clk_np)
  241. {
  242. err = -RT_EBUSY;
  243. rt_hw_spin_lock(&_clk_lock.lock);
  244. if (rt_list_isempty(&clk_np->children_nodes))
  245. {
  246. if (rt_ref_read(&clk_np->ref) <= 1)
  247. {
  248. rt_list_remove(&clk_np->list);
  249. clk_free(clk_np->clk);
  250. err = RT_EOK;
  251. }
  252. }
  253. rt_hw_spin_unlock(&_clk_lock.lock);
  254. }
  255. else
  256. {
  257. err = -RT_EINVAL;
  258. }
  259. return err;
  260. }
  261. /**
  262. * @brief Register clock notifier into notifier list
  263. *
  264. * @param clk point to clock
  265. * @param notifier point to notifier for register
  266. *
  267. * @retval RT_EOK
  268. * @retval -RT_EINVAL
  269. */
  270. rt_err_t rt_clk_notifier_register(struct rt_clk *clk, struct rt_clk_notifier *notifier)
  271. {
  272. if (!clk || !clk->clk_np || !notifier)
  273. {
  274. return -RT_EINVAL;
  275. }
  276. rt_hw_spin_lock(&_clk_lock.lock);
  277. ++clk->clk_np->notifier_count;
  278. rt_list_init(&notifier->list);
  279. rt_list_insert_after(&_clk_notifier_nodes, &notifier->list);
  280. rt_hw_spin_unlock(&_clk_lock.lock);
  281. return RT_EOK;
  282. }
  283. /**
  284. * @brief Unregister clock notifier into notifier list
  285. *
  286. * @param clk point to clock
  287. * @param notifier point to notifier for unregister
  288. *
  289. * @retval RT_EOK
  290. * @retval -RT_EINVAL
  291. */
  292. rt_err_t rt_clk_notifier_unregister(struct rt_clk *clk, struct rt_clk_notifier *notifier)
  293. {
  294. struct rt_clk_notifier *notifier_find;
  295. if (!clk || !notifier)
  296. {
  297. return -RT_EINVAL;
  298. }
  299. rt_hw_spin_lock(&_clk_lock.lock);
  300. rt_list_for_each_entry(notifier_find, &_clk_notifier_nodes, list)
  301. {
  302. if (notifier_find->clk->clk_np == notifier->clk->clk_np)
  303. {
  304. --clk->clk_np->notifier_count;
  305. rt_list_remove(&notifier->list);
  306. break;
  307. }
  308. }
  309. rt_hw_spin_unlock(&_clk_lock.lock);
  310. return RT_EOK;
  311. }
  312. /**
  313. * @brief Recursively prepare clock
  314. *
  315. * @param clk Ponit to clock that will be prepared
  316. * @param clk_np Ponit to clock node that will be prepared
  317. *
  318. * @return rt_err_t RT_EOK on prepare clock sucessfully, and other value is failed.
  319. */
  320. static rt_err_t clk_prepare(struct rt_clk *clk, struct rt_clk_node *clk_np)
  321. {
  322. rt_err_t err = RT_EOK;
  323. if (clk_np->parent)
  324. {
  325. clk_prepare(clk_np->clk, clk_np->parent);
  326. }
  327. if (clk->prepare_count == 0 && clk_np->ops->prepare)
  328. {
  329. err = clk_np->ops->prepare(clk);
  330. }
  331. if (!err)
  332. {
  333. ++clk->prepare_count;
  334. }
  335. return err;
  336. }
  337. /**
  338. * @brief Prepare clock
  339. *
  340. * @param clk
  341. *
  342. * @return rt_err_t RT_EOK on prepare clock sucessfully, and other value is failed.
  343. */
  344. rt_err_t rt_clk_prepare(struct rt_clk *clk)
  345. {
  346. rt_err_t err = RT_EOK;
  347. RT_DEBUG_NOT_IN_INTERRUPT;
  348. if (clk && clk->clk_np)
  349. {
  350. rt_hw_spin_lock(&_clk_lock.lock);
  351. err = clk_prepare(clk, clk->clk_np);
  352. rt_hw_spin_unlock(&_clk_lock.lock);
  353. }
  354. return err;
  355. }
  356. /**
  357. * @brief Recursively unprepare clock
  358. *
  359. * @param clk Ponit to clock that will be unprepared
  360. * @param clk_np Ponit to clock node that will be unprepared
  361. *
  362. */
  363. static void clk_unprepare(struct rt_clk *clk, struct rt_clk_node *clk_np)
  364. {
  365. if (clk_np->parent)
  366. {
  367. clk_unprepare(clk_np->clk, clk_np->parent);
  368. }
  369. if (clk->prepare_count == 1 && clk_np->ops->unprepare)
  370. {
  371. clk_np->ops->unprepare(clk);
  372. }
  373. if (clk->prepare_count)
  374. {
  375. --clk->prepare_count;
  376. }
  377. }
  378. rt_err_t rt_clk_unprepare(struct rt_clk *clk)
  379. {
  380. rt_err_t err = RT_EOK;
  381. RT_DEBUG_NOT_IN_INTERRUPT;
  382. if (clk && clk->clk_np)
  383. {
  384. rt_hw_spin_lock(&_clk_lock.lock);
  385. clk_unprepare(clk, clk->clk_np);
  386. rt_hw_spin_unlock(&_clk_lock.lock);
  387. }
  388. return err;
  389. }
  390. /**
  391. * @brief Enable clock
  392. *
  393. * @param clk point to clock
  394. *
  395. * @return rt_err_t RT_EOK on enable clock FOREVER.
  396. */
  397. static rt_err_t clk_enable(struct rt_clk *clk, struct rt_clk_node *clk_np)
  398. {
  399. rt_err_t err = RT_EOK;
  400. if (clk_np->parent)
  401. {
  402. clk_enable(clk_np->clk, clk_np->parent);
  403. }
  404. if (clk->enable_count == 0 && clk_np->ops->enable)
  405. {
  406. err = clk_np->ops->enable(clk);
  407. }
  408. if (!err)
  409. {
  410. ++clk->enable_count;
  411. }
  412. return err;
  413. }
  414. /**
  415. * @brief Enable clock
  416. *
  417. * @param clk point to clock
  418. *
  419. * @return rt_err_t RT_EOK on enable clock sucessfully, and other value is failed.
  420. */
  421. rt_err_t rt_clk_enable(struct rt_clk *clk)
  422. {
  423. rt_err_t err = RT_EOK;
  424. if (clk && clk->clk_np)
  425. {
  426. rt_hw_spin_lock(&_clk_lock.lock);
  427. err = clk_enable(clk, clk->clk_np);
  428. rt_hw_spin_unlock(&_clk_lock.lock);
  429. }
  430. return err;
  431. }
  432. /**
  433. * @brief Recursively disable clock
  434. *
  435. * @param clk Ponit to clock that will be disabled
  436. * @param clk_np Ponit to clock node that will be disabled
  437. *
  438. */
  439. static void clk_disable(struct rt_clk *clk, struct rt_clk_node *clk_np)
  440. {
  441. if (clk_np->parent)
  442. {
  443. clk_disable(clk_np->clk, clk_np->parent);
  444. }
  445. if (clk->enable_count == 1 && clk_np->ops->disable)
  446. {
  447. clk_np->ops->disable(clk);
  448. }
  449. if (clk->enable_count)
  450. {
  451. --clk->enable_count;
  452. }
  453. }
  454. /**
  455. * @brief Disable clock
  456. *
  457. * @param clk point to clock
  458. *
  459. */
  460. void rt_clk_disable(struct rt_clk *clk)
  461. {
  462. if (clk && clk->clk_np)
  463. {
  464. rt_hw_spin_lock(&_clk_lock.lock);
  465. clk_disable(clk, clk->clk_np);
  466. rt_hw_spin_unlock(&_clk_lock.lock);
  467. }
  468. }
  469. /**
  470. * @brief Prepare and enable clock
  471. *
  472. * @param clk point to clock
  473. *
  474. * @return rt_err_t RT_EOK on prepare and enable clock sucessfully, and other value is failed.
  475. */
  476. rt_err_t rt_clk_prepare_enable(struct rt_clk *clk)
  477. {
  478. rt_err_t err = RT_EOK;
  479. RT_DEBUG_NOT_IN_INTERRUPT;
  480. if (clk)
  481. {
  482. err = rt_clk_prepare(clk);
  483. if (!err)
  484. {
  485. err = rt_clk_enable(clk);
  486. if (err)
  487. {
  488. rt_clk_unprepare(clk);
  489. }
  490. }
  491. }
  492. return err;
  493. }
  494. /**
  495. * @brief Disable and unprepare clock
  496. *
  497. * @param clk point to clock
  498. *
  499. */
  500. void rt_clk_disable_unprepare(struct rt_clk *clk)
  501. {
  502. RT_DEBUG_NOT_IN_INTERRUPT;
  503. if (clk)
  504. {
  505. rt_clk_disable(clk);
  506. rt_clk_unprepare(clk);
  507. }
  508. }
  509. /**
  510. * @brief Prepare clock array for mutipule out clock
  511. *
  512. * @param clk_arr point to clock array
  513. *
  514. * @return rt_err_t RT_EOK on prepare clock array sucessfully, and other value is failed.
  515. */
  516. rt_err_t rt_clk_array_prepare(struct rt_clk_array *clk_arr)
  517. {
  518. rt_err_t err = RT_EOK;
  519. if (clk_arr)
  520. {
  521. for (int i = 0; i < clk_arr->count; ++i)
  522. {
  523. if ((err = rt_clk_prepare(clk_arr->clks[i])))
  524. {
  525. LOG_E("CLK Array[%d] %s failed error = %s", i,
  526. "prepare", rt_strerror(err));
  527. while (i --> 0)
  528. {
  529. rt_clk_unprepare(clk_arr->clks[i]);
  530. }
  531. break;
  532. }
  533. }
  534. }
  535. return err;
  536. }
  537. rt_err_t rt_clk_array_unprepare(struct rt_clk_array *clk_arr)
  538. {
  539. rt_err_t err = RT_EOK;
  540. if (clk_arr)
  541. {
  542. for (int i = 0; i < clk_arr->count; ++i)
  543. {
  544. if ((err = rt_clk_unprepare(clk_arr->clks[i])))
  545. {
  546. LOG_E("CLK Array[%d] %s failed error = %s", i,
  547. "unprepare", rt_strerror(err));
  548. break;
  549. }
  550. }
  551. }
  552. return err;
  553. }
  554. /**
  555. * @brief Enable clock array for mutipule out clock
  556. *
  557. * @param clk_arr point to clock array
  558. *
  559. * @return rt_err_t RT_EOK on Enable clock array sucessfully, and other value is failed.
  560. */
  561. rt_err_t rt_clk_array_enable(struct rt_clk_array *clk_arr)
  562. {
  563. rt_err_t err = RT_EOK;
  564. if (clk_arr)
  565. {
  566. for (int i = 0; i < clk_arr->count; ++i)
  567. {
  568. if ((err = rt_clk_enable(clk_arr->clks[i])))
  569. {
  570. LOG_E("CLK Array[%d] %s failed error = %s", i,
  571. "enable", rt_strerror(err));
  572. while (i --> 0)
  573. {
  574. rt_clk_disable(clk_arr->clks[i]);
  575. }
  576. break;
  577. }
  578. }
  579. }
  580. return err;
  581. }
  582. /**
  583. * @brief Enable clock array for mutipule out clock
  584. *
  585. * @param clk_arr point to clock array
  586. *
  587. */
  588. void rt_clk_array_disable(struct rt_clk_array *clk_arr)
  589. {
  590. if (clk_arr)
  591. {
  592. for (int i = 0; i < clk_arr->count; ++i)
  593. {
  594. rt_clk_disable(clk_arr->clks[i]);
  595. }
  596. }
  597. }
  598. /**
  599. * @brief Prepare and enable clock array
  600. *
  601. * @param clk_arr point to clock array
  602. *
  603. * @return rt_err_t RT_EOK on prepare and enable clock array sucessfully, and other
  604. value is failed.
  605. */
  606. rt_err_t rt_clk_array_prepare_enable(struct rt_clk_array *clk_arr)
  607. {
  608. rt_err_t err;
  609. if ((err = rt_clk_array_prepare(clk_arr)))
  610. {
  611. return err;
  612. }
  613. if ((err = rt_clk_array_enable(clk_arr)))
  614. {
  615. rt_clk_array_unprepare(clk_arr);
  616. }
  617. return err;
  618. }
  619. /**
  620. * @brief Disable and unprepare clock array
  621. *
  622. * @param clk_arr point to clock array
  623. *
  624. */
  625. void rt_clk_array_disable_unprepare(struct rt_clk_array *clk_arr)
  626. {
  627. rt_clk_array_disable(clk_arr);
  628. rt_clk_array_unprepare(clk_arr);
  629. }
  630. /**
  631. * @brief Set clock rate range
  632. *
  633. * @param clk point to clock
  634. * @param min minimum clock rate
  635. * @param max minimum clock rate
  636. *
  637. * @return rt_err_t RT_EOK on set clock rate range sucessfully, and other value is failed.
  638. */
  639. rt_err_t rt_clk_set_rate_range(struct rt_clk *clk, rt_ubase_t min, rt_ubase_t max)
  640. {
  641. rt_err_t err = RT_EOK;
  642. if (clk && clk->clk_np)
  643. {
  644. struct rt_clk_node *clk_np = clk->clk_np;
  645. rt_hw_spin_lock(&_clk_lock.lock);
  646. if (clk_np->ops->set_rate)
  647. {
  648. rt_ubase_t rate = clk_np->rate;
  649. rt_ubase_t old_min = clk_np->min_rate;
  650. rt_ubase_t old_max = clk_np->max_rate;
  651. clk_np->min_rate = min;
  652. clk_np->max_rate = max;
  653. rate = rt_clamp(rate, min, max);
  654. err = clk_np->ops->set_rate(clk, rate,
  655. rt_clk_get_rate(clk_np->parent ? clk_np->parent->clk : RT_NULL));
  656. if (err)
  657. {
  658. clk_np->min_rate = old_min;
  659. clk_np->max_rate = old_max;
  660. }
  661. }
  662. else
  663. {
  664. err = -RT_ENOSYS;
  665. }
  666. rt_hw_spin_unlock(&_clk_lock.lock);
  667. }
  668. return err;
  669. }
  670. /**
  671. * @brief Set minimum clock rate
  672. *
  673. * @param clk point to clock
  674. * @param rate miminum clock rate
  675. *
  676. * @return rt_err_t RT_EOK on set minimum clock rate sucessfully, and other value is failed.
  677. */
  678. rt_err_t rt_clk_set_min_rate(struct rt_clk *clk, rt_ubase_t rate)
  679. {
  680. rt_err_t err = RT_EOK;
  681. if (clk && clk->clk_np)
  682. {
  683. struct rt_clk_node *clk_np = clk->clk_np;
  684. err = rt_clk_set_rate_range(clk, rate, clk_np->max_rate);
  685. }
  686. return err;
  687. }
  688. /**
  689. * @brief Set maximum clock rate
  690. *
  691. * @param clk point to clock
  692. * @param rate maximum clock rate
  693. *
  694. * @return rt_err_t RT_EOK on set maximum clock rate sucessfully, and other value is failed.
  695. */
  696. rt_err_t rt_clk_set_max_rate(struct rt_clk *clk, rt_ubase_t rate)
  697. {
  698. rt_err_t err = RT_EOK;
  699. if (clk && clk->clk_np)
  700. {
  701. struct rt_clk_node *clk_np = clk->clk_np;
  702. err = rt_clk_set_rate_range(clk, clk_np->min_rate, rate);
  703. }
  704. return err;
  705. }
  706. /**
  707. * @brief Set clock rate
  708. *
  709. * @param clk point to clock
  710. * @param rate target rate
  711. *
  712. * @return rt_err_t RT_EOK on set clock rate sucessfully, and other value is failed.
  713. */
  714. rt_err_t rt_clk_set_rate(struct rt_clk *clk, rt_ubase_t rate)
  715. {
  716. rt_err_t err = RT_EOK;
  717. rate = rt_clk_round_rate(clk, rate);
  718. if (clk && clk->clk_np && rate > 0)
  719. {
  720. struct rt_clk_node *clk_np = clk->clk_np;
  721. rt_hw_spin_lock(&_clk_lock.lock);
  722. if (clk_np->min_rate && rate < clk_np->min_rate)
  723. {
  724. err = -RT_EINVAL;
  725. }
  726. if (clk_np->max_rate && rate > clk_np->max_rate)
  727. {
  728. err = -RT_EINVAL;
  729. }
  730. if (!err)
  731. {
  732. if (clk_np->ops->set_rate)
  733. {
  734. rt_ubase_t old_rate = clk_np->rate;
  735. err = clk_np->ops->set_rate(clk, rate,
  736. rt_clk_get_rate(clk_np->parent ? clk_np->parent->clk : RT_NULL));
  737. if (clk_np->rate != old_rate)
  738. {
  739. clk_notify(clk_np, RT_CLK_MSG_PRE_RATE_CHANGE, old_rate, clk_np->rate);
  740. }
  741. }
  742. else
  743. {
  744. err = -RT_ENOSYS;
  745. }
  746. }
  747. rt_hw_spin_unlock(&_clk_lock.lock);
  748. }
  749. return err;
  750. }
  751. /**
  752. * @brief Get clock rate
  753. *
  754. * @param clk point to clock
  755. *
  756. * @return rt_ubase_t clock rate or error code
  757. */
  758. rt_ubase_t rt_clk_get_rate(struct rt_clk *clk)
  759. {
  760. rt_ubase_t rate = 0;
  761. if (clk)
  762. {
  763. if (clk->rate)
  764. {
  765. rate = clk->rate;
  766. }
  767. else if (clk->clk_np)
  768. {
  769. rate = clk->clk_np->rate;
  770. }
  771. }
  772. return rate;
  773. }
  774. /**
  775. * @brief Set clock phase
  776. *
  777. * @param clk point to clock
  778. * @param degrees target phase and the unit of phase is degree
  779. *
  780. * @return rt_err_t RT_EOK on set clock phase sucessfully, and other value is failed.
  781. */
  782. rt_err_t rt_clk_set_phase(struct rt_clk *clk, int degrees)
  783. {
  784. rt_err_t err = RT_EOK;
  785. if (clk && clk->clk_np && clk->clk_np->ops->set_phase)
  786. {
  787. rt_hw_spin_lock(&_clk_lock.lock);
  788. err = clk->clk_np->ops->set_phase(clk, degrees);
  789. rt_hw_spin_unlock(&_clk_lock.lock);
  790. }
  791. return err;
  792. }
  793. /**
  794. * @brief Get clock phase
  795. *
  796. * @param clk point to clock
  797. *
  798. * @return rt_base_t clock phase or error code
  799. */
  800. rt_base_t rt_clk_get_phase(struct rt_clk *clk)
  801. {
  802. rt_base_t res = RT_EOK;
  803. if (clk && clk->clk_np && clk->clk_np->ops->get_phase)
  804. {
  805. rt_hw_spin_lock(&_clk_lock.lock);
  806. res = clk->clk_np->ops->get_phase(clk);
  807. rt_hw_spin_unlock(&_clk_lock.lock);
  808. }
  809. return res;
  810. }
  811. /**
  812. * @brief Check if clock rate is in the minimum to maximun and get it
  813. *
  814. * @param clk point to clock
  815. * @param rate rate will be checked
  816. *
  817. * @return rt_base_t get the correct rate
  818. * @note if parameter rate less than the minimum or more than maximum, the
  819. retrun rate will be set to minimum ormaximum value
  820. */
  821. rt_base_t rt_clk_round_rate(struct rt_clk *clk, rt_ubase_t rate)
  822. {
  823. rt_base_t res = -RT_EINVAL;
  824. if (clk && clk->clk_np)
  825. {
  826. struct rt_clk_node *clk_np = clk->clk_np;
  827. if (clk_np->ops->round_rate)
  828. {
  829. rt_ubase_t best_parent_rate;
  830. rt_hw_spin_lock(&_clk_lock.lock);
  831. if (clk_np->min_rate && clk_np->max_rate)
  832. {
  833. rate = rt_clamp(rate, clk_np->min_rate, clk_np->max_rate);
  834. }
  835. res = clk_np->ops->round_rate(clk, rate, &best_parent_rate);
  836. (void)best_parent_rate;
  837. rt_hw_spin_unlock(&_clk_lock.lock);
  838. }
  839. else
  840. {
  841. if (rate < clk_np->min_rate)
  842. {
  843. res = clk_np->min_rate;
  844. }
  845. else if (rate > clk_np->max_rate)
  846. {
  847. res = clk_np->max_rate;
  848. }
  849. else
  850. {
  851. res = rate;
  852. }
  853. }
  854. }
  855. return res;
  856. }
  857. /**
  858. * @brief Set clock parent object
  859. *
  860. * @param clk point to clock
  861. * @param clk_parent point to parent clock
  862. *
  863. * @return rt_err_t RT_EOK on set clock parent sucessfully, and other value is failed.
  864. */
  865. rt_err_t rt_clk_set_parent(struct rt_clk *clk, struct rt_clk *clk_parent)
  866. {
  867. rt_err_t err = RT_EOK;
  868. if (clk && clk->clk_np && clk->clk_np->ops->set_parent)
  869. {
  870. rt_hw_spin_lock(&_clk_lock.lock);
  871. err = clk->clk_np->ops->set_parent(clk, clk_parent);
  872. rt_hw_spin_unlock(&_clk_lock.lock);
  873. }
  874. return err;
  875. }
  876. /**
  877. * @brief Get parent clock pointer
  878. *
  879. * @param clk child clock
  880. *
  881. * @return struct rt_clk* parent clock object pointer will be return, unless child
  882. clock node havn't parent node instead return RT_NULL
  883. */
  884. struct rt_clk *rt_clk_get_parent(struct rt_clk *clk)
  885. {
  886. struct rt_clk *parent = RT_NULL;
  887. if (clk)
  888. {
  889. struct rt_clk_node *clk_np = clk->clk_np;
  890. rt_hw_spin_lock(&_clk_lock.lock);
  891. parent = clk_np->parent ? clk_np->parent->clk : RT_NULL;
  892. rt_hw_spin_unlock(&_clk_lock.lock);
  893. }
  894. return parent;
  895. }
  896. /**
  897. * @brief Get clock array pointer from ofw device node
  898. *
  899. * @param dev point to dev
  900. *
  901. * @return struct rt_clk_array* if use ofw and under normal circumstance, it will return
  902. clock array pointer and other value is RT_NULL
  903. */
  904. struct rt_clk_array *rt_clk_get_array(struct rt_device *dev)
  905. {
  906. struct rt_clk_array *clk_arr = RT_NULL;
  907. #ifdef RT_USING_OFW
  908. clk_arr = rt_ofw_get_clk_array(dev->ofw_node);
  909. #endif
  910. return clk_arr;
  911. }
  912. /**
  913. * @brief Get clock pointer from ofw device node by index
  914. *
  915. * @param dev point to dev
  916. * @param index index of clock object
  917. *
  918. * @return struct rt_clk* if use ofw and under normal circumstance, it will return clock
  919. pointer and other value is RT_NULL
  920. */
  921. struct rt_clk *rt_clk_get_by_index(struct rt_device *dev, int index)
  922. {
  923. struct rt_clk *clk = RT_NULL;
  924. #ifdef RT_USING_OFW
  925. clk = rt_ofw_get_clk(dev->ofw_node, index);
  926. #endif
  927. return clk;
  928. }
  929. /**
  930. * @brief Get clock pointer from ofw device node by name
  931. *
  932. * @param dev point to dev
  933. * @param name name of clock object
  934. *
  935. * @return struct rt_clk* if use ofw and under normal circumstance, it will return clock
  936. pointer and other value is RT_NULL
  937. */
  938. struct rt_clk *rt_clk_get_by_name(struct rt_device *dev, const char *name)
  939. {
  940. struct rt_clk *clk = RT_NULL;
  941. #ifdef RT_USING_OFW
  942. clk = rt_ofw_get_clk_by_name(dev->ofw_node, name);
  943. #endif
  944. return clk;
  945. }
  946. /**
  947. * @brief Put reference count of all colock in the clock array
  948. *
  949. * @param clk_arr point to clock array
  950. *
  951. */
  952. void rt_clk_array_put(struct rt_clk_array *clk_arr)
  953. {
  954. if (clk_arr)
  955. {
  956. for (int i = 0; i < clk_arr->count; ++i)
  957. {
  958. if (clk_arr->clks[i])
  959. {
  960. rt_clk_put(clk_arr->clks[i]);
  961. }
  962. else
  963. {
  964. break;
  965. }
  966. }
  967. rt_free(clk_arr);
  968. }
  969. }
  970. /**
  971. * @brief Put reference count of clock
  972. *
  973. * @param clk point to clock
  974. *
  975. */
  976. void rt_clk_put(struct rt_clk *clk)
  977. {
  978. if (clk)
  979. {
  980. clk_put(clk->clk_np);
  981. clk_free(clk);
  982. }
  983. }
  984. #ifdef RT_USING_OFW
  985. /**
  986. * @brief Get a clock object from a device tree node without acquiring a lock
  987. *
  988. * @param np point to ofw node
  989. * @param index index of clock in ofw
  990. * @param name connection identifier for the clock
  991. * @param locked lock flag for indicating whether the caller holds the lock
  992. *
  993. * @return struct rt_clk* point to the newly created clock object, or an error pointer
  994. */
  995. static struct rt_clk *ofw_get_clk_no_lock(struct rt_ofw_node *np, int index, const char *name, rt_bool_t locked)
  996. {
  997. struct rt_clk *clk = RT_NULL;
  998. struct rt_ofw_cell_args clk_args;
  999. if (!rt_ofw_parse_phandle_cells(np, "clocks", "#clock-cells", index, &clk_args))
  1000. {
  1001. int count;
  1002. struct rt_object *obj;
  1003. struct rt_clk_node *clk_np = RT_NULL;
  1004. struct rt_ofw_node *clk_ofw_np = clk_args.data;
  1005. if (!rt_ofw_data(clk_ofw_np))
  1006. {
  1007. if (locked)
  1008. {
  1009. rt_hw_spin_unlock(&_clk_lock.lock);
  1010. }
  1011. rt_platform_ofw_request(clk_ofw_np);
  1012. if (locked)
  1013. {
  1014. rt_hw_spin_lock(&_clk_lock.lock);
  1015. }
  1016. }
  1017. if (rt_ofw_data(clk_ofw_np) && (obj = rt_ofw_parse_object(clk_ofw_np,
  1018. RT_CLK_NODE_OBJ_NAME, "#clock-cells")))
  1019. {
  1020. clk_np = rt_container_of(obj, struct rt_clk_node, rt_parent);
  1021. count = rt_ofw_count_of_clk(clk_ofw_np);
  1022. }
  1023. rt_ofw_node_put(clk_ofw_np);
  1024. if (clk_np)
  1025. {
  1026. if (count > 1)
  1027. {
  1028. /* args[0] must be the index of CLK */
  1029. clk_np = &clk_np[clk_args.args[0]];
  1030. }
  1031. clk = clk_create(clk_np, np->full_name, name, &clk_args, np);
  1032. }
  1033. else
  1034. {
  1035. clk = rt_err_ptr(-RT_ERROR);
  1036. }
  1037. }
  1038. return clk;
  1039. }
  1040. /**
  1041. * @brief Get clock from ofw with acquiring a spin lock
  1042. *
  1043. * @param np point to ofw node
  1044. * @param index index of clock in ofw
  1045. * @param name connection identifier for the clock
  1046. *
  1047. * @return struct rt_clk* point to the newly created clock object, or an error pointer
  1048. */
  1049. static struct rt_clk *ofw_get_clk(struct rt_ofw_node *np, int index, const char *name)
  1050. {
  1051. struct rt_clk *clk;
  1052. rt_hw_spin_lock(&_clk_lock.lock);
  1053. clk = ofw_get_clk_no_lock(np, index, name, RT_TRUE);
  1054. rt_hw_spin_unlock(&_clk_lock.lock);
  1055. return clk;
  1056. }
  1057. /**
  1058. * @brief Get clock array from ofw
  1059. *
  1060. * @param np point to ofw node
  1061. *
  1062. * @return struct rt_clk_array* point to the newly created clock array, or an error pointer
  1063. */
  1064. struct rt_clk_array *rt_ofw_get_clk_array(struct rt_ofw_node *np)
  1065. {
  1066. int count;
  1067. struct rt_clk_array *clk_arr = RT_NULL;
  1068. if (!np)
  1069. {
  1070. return rt_err_ptr(-RT_EINVAL);
  1071. }
  1072. if ((count = rt_ofw_count_phandle_cells(np, "clocks", "#clock-cells")) > 0)
  1073. {
  1074. clk_arr = rt_calloc(1, sizeof(*clk_arr) + sizeof(clk_arr->clks[0]) * count);
  1075. if (clk_arr)
  1076. {
  1077. int i;
  1078. rt_err_t err = RT_EOK;
  1079. rt_bool_t has_name = rt_ofw_prop_read_bool(np, "clock-names");
  1080. clk_arr->count = count;
  1081. rt_hw_spin_lock(&_clk_lock.lock);
  1082. for (i = 0; i < count; ++i)
  1083. {
  1084. const char *name = RT_NULL;
  1085. if (has_name)
  1086. {
  1087. rt_ofw_prop_read_string_index(np, "clock-names", i, &name);
  1088. }
  1089. clk_arr->clks[i] = ofw_get_clk_no_lock(np, i, name, RT_FALSE);
  1090. if (rt_is_err(clk_arr->clks[i]))
  1091. {
  1092. err = rt_ptr_err(clk_arr->clks[i]);
  1093. --i;
  1094. break;
  1095. }
  1096. }
  1097. rt_hw_spin_unlock(&_clk_lock.lock);
  1098. if (i > 0 && i < count)
  1099. {
  1100. rt_clk_array_put(clk_arr);
  1101. clk_arr = rt_err_ptr(err);
  1102. }
  1103. }
  1104. }
  1105. return clk_arr;
  1106. }
  1107. /**
  1108. * @brief Get clock from ofw with acquiring a spin lock by index and node pointer
  1109. *
  1110. * @param np point to ofw node
  1111. * @param index index of clock in ofw
  1112. *
  1113. * @return struct rt_clk* point to the newly created clock object, or an error pointer
  1114. */
  1115. struct rt_clk *rt_ofw_get_clk(struct rt_ofw_node *np, int index)
  1116. {
  1117. struct rt_clk *clk = RT_NULL;
  1118. if (np && index >= 0)
  1119. {
  1120. clk = ofw_get_clk(np, index, RT_NULL);
  1121. }
  1122. return clk;
  1123. }
  1124. /**
  1125. * @brief Get clock from ofw with acquiring a spin lock by name
  1126. *
  1127. * @param np point to ofw node
  1128. * @param name name of clock will be returned
  1129. *
  1130. * @return struct rt_clk* point to the newly created clock object, or an error pointer
  1131. */
  1132. struct rt_clk *rt_ofw_get_clk_by_name(struct rt_ofw_node *np, const char *name)
  1133. {
  1134. struct rt_clk *clk = RT_NULL;
  1135. if (np && name)
  1136. {
  1137. int index = rt_ofw_prop_index_of_string(np, "clock-names", name);
  1138. if (index >= 0)
  1139. {
  1140. clk = ofw_get_clk(np, index, name);
  1141. }
  1142. }
  1143. return clk;
  1144. }
  1145. /**
  1146. * @brief Count number of clocks in ofw
  1147. *
  1148. * @param clk_ofw_np point to ofw node
  1149. *
  1150. * @return rt_ssize_t number of clocks
  1151. */
  1152. rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np)
  1153. {
  1154. if (clk_ofw_np)
  1155. {
  1156. struct rt_clk_node *clk_np = rt_ofw_data(clk_ofw_np);
  1157. if (clk_np && clk_np->multi_clk)
  1158. {
  1159. return clk_np->multi_clk;
  1160. }
  1161. else
  1162. {
  1163. const fdt32_t *cell;
  1164. rt_uint32_t count = 0;
  1165. struct rt_ofw_prop *prop;
  1166. prop = rt_ofw_get_prop(clk_ofw_np, "clock-indices", RT_NULL);
  1167. if (prop)
  1168. {
  1169. rt_uint32_t max_idx = 0, idx;
  1170. for (cell = rt_ofw_prop_next_u32(prop, RT_NULL, &idx);
  1171. cell;
  1172. cell = rt_ofw_prop_next_u32(prop, cell, &idx))
  1173. {
  1174. if (idx > max_idx)
  1175. {
  1176. max_idx = idx;
  1177. }
  1178. }
  1179. count = max_idx + 1;
  1180. }
  1181. else
  1182. {
  1183. rt_ssize_t len;
  1184. if ((prop = rt_ofw_get_prop(clk_ofw_np, "clock-output-names", &len)))
  1185. {
  1186. char *value = prop->value;
  1187. for (int i = 0; i < len; ++i, ++value)
  1188. {
  1189. if (*value == '\0')
  1190. {
  1191. ++count;
  1192. }
  1193. }
  1194. }
  1195. else
  1196. {
  1197. count = 1;
  1198. }
  1199. }
  1200. if (clk_np)
  1201. {
  1202. clk_np->multi_clk = count;
  1203. }
  1204. return count;
  1205. }
  1206. }
  1207. return -RT_EINVAL;
  1208. }
  1209. #endif /* RT_USING_OFW */
  1210. /**@}*/