Removed the Compute Graph since it is now the new CMSIS-Stream project

ARM.CMSIS-DSP.pdsc

@@ -105,15 +105,6 @@
       </files>
     </component>
 
-    <component Cclass="CMSIS" Cgroup="DSP" Csub="Compute Graph" Cversion="0.0.0" isDefaultVariant="true" condition="CMSISDSPLIB">
-      <description>CMSIS-DSP Compute Graph</description>
-      <files>
-          <file category="header" name="ComputeGraph/cg/src/GenericNodes.h"/>
-          <file category="include"  name="ComputeGraph/cg/nodes/cpp/"/>
-          <file category="include"  name="ComputeGraph/cg/src/"/>
-          <file category="other"  name="ComputeGraph/cg.scvd" />
-      </files>
-    </component>
   </components>
 
   <examples>

ComputeGraph/.gitignore

@@ -1,21 +0,0 @@
-__pycache__
-examples/build/CMakeCache.txt
-examples/build/CMakeFiles/
-examples/build/Makefile
-examples/build/bin2_example1/
-examples/build/bin_example1/
-examples/build/cmake_install.cmake
-examples/build/bin_example2
-examples/build/bin_dsp/
-examples/build/bin_example3/
-*.pyd
-examples/build/localcreate.bat
-examples/build/input_example3.txt
-examples/build/bin_example6/
-examples/build/input_example6.txt
-examples/build/output_example3.txt
-examples/build/output_example6.txt
-examples/eventrecorder/tmp/
-examples/eventrecorder/out/
-examples/eventrecorder/DebugConfig/
-

ComputeGraph/Async.md

@@ -1,147 +0,0 @@
-# Dynamic Data Flow
-
-This feature is illustrated in the [Example 10 : The dynamic dataflow mode](examples/example10/README.md)
-
-Versions of the compute graph corresponding to CMSIS-DSP Version >= `1.14.3` and Python wrapper version >= `1.10.0` are supporting  a new dynamic / asynchronous mode.
-
- With a dynamic flow, the flow of data is potentially changing at each execution. The IOs can generate or consume a different amount of data at each execution of their node (including no data).
-
-This can be useful for sample oriented use cases where not all samples are available but a processing must nevertheless take place each time a subset of samples is available (samples could come from sensors).
-
-With a dynamic flow and scheduling, there is no more any way to ensure that there won't be FIFO underflow of overflow due to scheduling. As consequence, the nodes must be able to check for this problem and decide what to do.
-
-* A sink may decide to generate fake data in case of FIFO underflow
-* A source may decide to skip some data in case of FIFO overflow
-* Another node may decide to do nothing and skip the execution
-* Another node may decide to raise an error.
-
-With dynamic flow, a node must implement the function `prepareForRunning` and decide what to do.
-
-3 error / status codes are reserved for this. They are defined in the header `cg_status.h`. This header is not included by default, but if you define you own error codes, they should be coherent with `cg_status` and use the same values for the 3 status / error codes which are used in dynamic mode:
-
-* `CG_SUCCESS`  = 0 : Node can execute
-* `CG_SKIP_EXECUTION` = -5 : Node will skip the execution
-* `CG_BUFFER_ERROR` = -6 : Unrecoverable error due to FIFO underflow / overflow (only raised in pure function like CMSIS-DSP ones called directly)
-
-Any other returned value will stop the execution.
-
-The dynamic mode (also named asynchronous), is enabled with option : `asynchronous` of the configuration object used with the scheduling functions.
-
-The system will still compute a synchronous scheduling and FIFO sizes as if the flow was static. We can see the static flow as an average of the dynamic flow. In dynamic mode, the FIFOs may need to be bigger than the ones computed in static mode.  The static estimation is giving a first idea of what the size of the FIFOs should be. The size can be increased by specifying a percent increase with option `FIFOIncrease`.
-
-For pure compute functions (like CMSIS-DSP ones), which are not packaged into a C++ class, there is no way to customize the decision logic in case of a problem with FIFO. There is a global option : `asyncDefaultSkip`. 
-
-When `true`, a pure function that cannot run will just skip the execution. With `false`, the execution will stop. For any other decision algorithm, the pure function needs to be packaged in a C++ class.
-
-`Duplicate` nodes are skipping the execution in case of problems with FIFOs. If it is not the wanted behavior, you can either:
-
-* Replace the Duplicate class by a custom one by changing the class name with option `duplicateNodeClassName` on the graph.
-* Don't use the automatic duplication feature and introduce your duplicate nodes in the compute graph
-
-When you don't want to generate or consume data in a node, just don't call the functions `getReadBuffer` or `getWriteBuffer` for your IOs.
-
-## prepareForRunning
-
-The method `prepareForRunning` is needed to check if the node execution is going to be possible.
-
-Inside this function, you have access to methods like:
-
-* `willOverflow`
-* `willUnderflow`
-
-In case of several IOs, you may also have:
-
-* `willOverflow1`
-* `willOverflow2` 
-
-etc ...
-
-The functions have an interface like:
-
-```C++
-bool willOverflow(int nb = outputSize)
-```
-
-or
-
-```C++
-bool willUnderflow(int nb = inputSize)
-```
-
-The `inputSize` and `outputSize` are coming from the template arguments. So, by default the node is using the parameters of the static compute graph.
-
-You may want to read or write more or less than what is defined in the static compute graph. But it must be coherent with the `run` function.
-
-If you use `willOverflow(4)` to check if you can write `4` samples in the output in the `prepareForRunning` function, then in the `run` function you must access to the write buffer by requesting `4` samples with `getWriteBuffer(4)`
-
-If you don't want to write or read on an IO, just don't use the function `getWriteBuffer` and `getReadBuffer` in the `run` function.
-
-It is also possible to use the functions `willOverflow`, `willUnderflow` in the `run` function. It can be used to avoid calling the `getReadBuffer` and `getWriteBuffer` when you nevertheless want to run the node although some FIFOs cannot be used.
-
-**WARNING**: You are responsible for checking if a FIFO is going to underflow or overflow **before** using `getReadBuffer` or `getWriteBuffer`.
-
-If the `getReadBuffer` and `getWriteBuffer` are causing an underflow or overflow of the FIFO, you'll have memory corruptions and the compute graph will no more work.
-
-## Graph constraints
-
-The dynamic mode is using a synchronous graph as average / ideal case. But it is important to understand that we are no more in static / synchronous mode and some static graph may be too complex for the dynamic mode. Let's take the following graph as example:
-
-![async_topological2](documentation/async_topological2.png)
-
-The generated schedule is:
-
-```
-src
-src
-src
-src
-src
-filter
-sink
-sink
-sink
-sink
-sink
-```
-
-If we use a strategy of skipping the execution of a node in case of overflow / underflow, what will happen is:
-
-* Schedule iteration  1
-  * First `src` node execution is successful since there is a sample
-  * All other execution attempts will be skipped 
-* Schedule iteration  2
-  * First `src` node execution is successful since there is a sample
-  * All other execution attempt will be skipped 
-* ...
-* Schedule iteration  5:
-  * First `src` node execution is successful since there is a sample
-  * 4 other `src` node executions are skipped
-  * The `filter` execution can finally take place since enough data has been generated
-
-
-
-In summary , it is totally useless in asynchronous mode to attempt to run the same node several times in the same scheduling iteration except if we are sure there will always be enough data. In previous example, we see that only the first attempt at running `src` is doing something. Other attempts are always skipped.
-
-
-
-Instead, one could try the following graph:
-
-![async_topological1](documentation/async_topological1.png)
-
-With this graph, each node execution will be attempted only once during an execution.
-
-But the `filter` needs 5 samples, so we need to increase the size of the FIFOs from `1` to `5` or the `filter` node will never be executed. 
-
-It is possible with the option `FIFOIncrease` but it is better to make it explicit with the following graph:
-
-![async_topological3](documentation/async_topological3.png)
-
-In this case, the FIFO is big enough. `src` node will be executed each time there is a sample. `filter` will execute only when 5 samples have been accumulated in the FIFO. Each node execution is only attempted once during a schedule.
-
-
-
-As consequence, the recommendation in dynamic / asynchronous mode is to:
-
-* Ensure that the amount of data produced and consumed on each FIFO end is the same (so that each node execution is attempted only once during a schedule)
-* Use the maximum amount of samples required on both ends of the FIFO
-  * Here `sink` is generating  at most `1` sample, `filter` needs 5. So we use `5` on both ends of the FIFO

ComputeGraph/CycloStatic.md

@@ -1,48 +0,0 @@
-# Cyclo static scheduling
-
-This feature is illustrated in the  [cyclo](examples/cyclo/README.md) example.
-
-Beginning with the version `1.7.0` of the Python wrapper and version >= `1.12` of CMSIS-DSP, cyclo static scheduling has been added.
-
-## What is the problem it is trying to solve ?
-
-Let's consider a sample rate converter from 48 kHz to 44.1 kHz.
-
-For each input sample, on average it produces 44.1 / 48 = 0.91875 samples.
-
-There are two ways to do this:
-
-- One can observe that 48000/44100 = 160/147. So each time 160 samples are consumed, 147 samples are produced
-- The number of sample produced can vary from one execution of the node to the other so that on average, 0.91875 samples are generated per execution
-
-In the first case, it is synchronous but you need to wait for 160 input samples before being able to do some processing. It is introducing a latency and depending on the sample rate and use case, this latency may be too big. We need more flexibility.
-
-In the second case, we have the flexibility but it is no more synchronous because the resampler is not producing the same amount of samples at each execution.
-
-But we can observe that even if is is no more stationary, it is periodic. After consuming 160 samples the behavior should repeat.
-
-One can use the resampler in the [SpeexDSP](https://gitlab.xiph.org/xiph/speexdsp) project to test. If we decide to consume only 40 samples in input to have less latency, then the resampler of SpeexDSP will produce 37,37,37 and 36 samples for the first 4 executions.
-
-And (40+40+40+40)/(37+37+37+36) = 160 / 147.
-
-So the flow of data on the output is not static but it is periodic.
-
-This is now supported in the CMSIS-DSP compute graph and on each IO one can define a period. For this example, it could be:
-
-```python
-b=Sampler("sampler",floatType,40,[37,37,37,36])
-```
-
-Note that in the C++ class, the template parameters giving the number of samples produced or consumed on an IO cannot be used any more in this case. The value is still generated but now represent the maximum on a period.
-
-And, in the run function you need to pass the number of sample read or written to the read and write buffer functions:
-
-```c
-this->getWriteBuffer(nbOfSamplesForCurrentExecution)
-```
-
-For synchronous node, nothing is changed and they are coded as in the previous versions.
-
-The drawback of cyclo static scheduling is that the schedule length is increased. If we take the first example with a source producing 5 samples and a node consuming 7 samples and if the source is replaced by another source producing [5,5] then it is not equivalent. In the first case we can have only one execution of the source. In the second case, the scheduling will always contain an even number of executions of the sources. So the schedule length will be bigger. But memory usage will be the same (FIFOs of same size).
-
-Since schedule tend to be bigger with cyclo static scheduling, a new code generation mode has been introduced and is enabled by default : now instead of having a sequence of function calls, the schedule is coded by an array of number and there is a switch / case to select the function to be called.

ComputeGraph/FAQ.md

@@ -1,398 +0,0 @@
-# FAQ
-
-## Table of contents
-
-* [Alignment](#alignment)
-* [Memory sharing](#memory-sharing-example)
-* [Latencies](#latencies)
-* [Performances](#performances)
-
-## Alignment
-
-When the `memoryOptimization` mode is enabled, the memory can be shared between different FIFOs (when the FIFOs are in fact used as simple arrays).
-
-In this case, the type of the memory buffers is `uint8_t`. And this memory can be used with FIFOs of different types (`float32_t`, `q31_t`).
-
-So, it is important to align the buffers because the compiler may generate instructions which are requiring an aligned buffer thinking that the type of the buffer is different from `uint8_t`.
-
-This can be achieved by defining `CG_BEFORE_BUFFER` in the global custom header included by the scheduler.
-
-For instance:
-
-`#define CG_BEFORE_BUFFER __ALIGNED(4)`
-
-This is not needed when `memoryOptimization` is `False` in the Python configuration.
-
-The read buffer and write buffers used to interact with a FIFO have the alignment of the FIFO datatype but no more (assuming the underlying memory is aligned in case its type is `uint8_t`)
-
-If the number of samples read is `NR` and the number of samples written if `NW`, the alignments (in number of samples) may be:
-
-* `r0 . NR` for a read buffer in the FIFO (where `r0 ` if an integer with `r0 >= 0`)
-* `w . NW - r1 . NR` for a write buffer in the FIFO (where `r1 ` and `w` are integers with `r1 >= 0` and `w >= 0`)
-
-If you need a stronger alignment, you'll need to chose `NR` and `NW` in the right way.
-
-For instance, if you need an alignment on a multiple of `16` bytes with a buffer containing `q31_t`, then `NW` and `NR` need to be multiple of `4`.
-
-If you can't choose freely the values of `NR` and `NW` then you may need to do a copy inside your component to align the buffer (of course only if the overhead due to the lack of alignment is bigger than doing a copy.)
-
-## Memory sharing example
-
-When the `memoryOptimization` is enabled, the memory may be reused for different FIFOs to minimize the memory usage. But the scheduling algorithm is not trying to optimize this. So depending on how the graph was scheduled, the level of sharing may be different.
-
-If you need to share as much as possible memory (to minimize memory usage or the amount of memory copied), you can do it if you respect a fundamental constraint : the values in the FIFOs must have value semantic and not reference semantic. 
-
-If you share memory, you are using reference semantic and it should be hidden from the graph : one could use a copy-on-write strategy with a reference count inside the shared buffers. The reference count could also be computed statically using C++ templates if the graph has no loops:
-
-
-
-One could define an audio buffer data type :
-
-```c++
-template<int nbSamples,
-         int refCount>
-struct SharedAudioBuf
-{
- float32_t *buf;
- static int getNbSamples() {return nbSamples;};
-};
-
-template<int nbSamples,
-         int refCount>
-using SharedBuf = struct SharedAudioBuf<nbSamples,refCount>;
-
-```
-
-The template tracks the number of samples and the reference count statically. `refCount` is not a value of the struct. It is a template argument : a number at type level.
-
-The FIFOs are no more containing the audio samples but only a pointer to a shared buffers of samples.
-
-In this example, instead of having a length of 128 `float` samples, a FIFO would have a length of one `SharedBuf<128,r>` samples.
-
-An example of compute graph could be:
-
-![shared_buffer](documentation/shared_buffer.png)
-
-A copy of the struct `SharedBuf<NB,REF>` is copying a pointer to a buffer and not the buffer. It is reference semantic and the buffer should not be modified if the ref count is > 1.
-
-In the above graph, there is a processing node doing in-place modification of the buffer and it could have a template specialization defined as:
-
-```c++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class ProcessingNode;
-
-
-template<int NB>
-class ProcessingNode<SharedBuf<NB,1>,1,
-                     SharedBuf<NB,1>,1>: 
-public GenericNode<SharedBuf<NB,1>,1,
-                   SharedBuf<NB,1>,1>
-```
-
-The meaning is:
-
-* The input and output FIFOs have a length of 1 sample
-* The sample has a type `SharedBuf<NB,1>` for both input and output
-* The reference count is statically known to be 1 so it is safe to do in place modifications of the buffer and the output buffer is a pointer to the input one
-
-In case of duplication, the template specialization could look like:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT1,int outputSize1,
-         typename OUT2,int outputSize2>
-class DupNode;
-
-template<int NB, int REF>
-class DupNode<SharedBuf<NB,REF>,1,
-              SharedBuf<NB,REF+1>,1,
-              SharedBuf<NB,REF+1>,1>: 
-public GenericNode12<SharedBuf<NB,REF>,1,
-                     SharedBuf<NB,REF+1>,1,
-                     SharedBuf<NB,REF+1>,1>
-```
-
-If the input buffer has a reference count `REF`, the two output buffers will have a reference count of `REF+1`. The node is introducing some sharing. We statically know and compute the new reference count which will prevent other nodes in the graph from doing in place modifications of the buffer.
-
-If another node needs to modify the content of this buffer, it should allocate a new buffer. Such a node could have the following template specializations:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class ProcessingNode;
-
-template<int NB>
-class ProcessingNode<SharedBuf<NB,1>,1,
-                     SharedBuf<NB,1>,1>: 
-public GenericNode<SharedBuf<NB,1>,1,
-                   SharedBuf<NB,1>,1>
-
-template<int NB>
-class ProcessingNode<SharedBuf<NB,REF>,1,
-                     SharedBuf<NB,1>,1>: 
-public GenericNode<SharedBuf<NB,REF>,1,
-                   SharedBuf<NB,1>,1>
-```
-
-The first specialization is working with a reference count of 1 and doing in place modification.
-
-The second implementation is working with a reference count > 1 (and is selected if the first specialization cannot be used). In this second implementation, a new output buffer should be allocated. This new buffer would have a reference count of 1.
-
-The memory allocation can use a custom made memory allocator and so be acceptable in case of real-time:
-
-* The amount of memory to allocate during one iteration of the scheduling is constant and can be known at compile time. It depends on the level of sharing in the compute graph
-* After each iteration of the schedule, this allocated memory can be released
-
-## Latencies
-
-The compute graph schedule is computed only based on the dataflow dependencies and with an attempt at minimizing the FIFO sizes.
-
-No other constraint is used. But in a real application, it is not enough. For instance, this kind of scheduling would be acceptable from a pure data flow point of view (ignoring FIFO sizes for this example):
-
-* source, source, sink, sink
-
-But from a latency point of view it would not be good and the following schedule should be prefered:
-
-* source, sink, source, sink 
-
-The scheduling algorithm is thus using a topological sort of the compute graph to try to schedule the sinks as soon as possible in order to minimize the source to sink latency. This optimization is disabled when the graph has some loops because in this case there is no possible topological sort.
-
-But, even with topological sorting, there may be cases where the latency is unavoidable without changing the amount of samples read and written by the nodes. In a dynamic scheduler it is something which is more difficult to track. With a static scheduler you can see it in the generated schedule.
-
-As an example, if you use 10 ms audio blocks at 16 kHz you get 160 samples.
-
-Now, if you want to want to compute a FFT of 256 samples (smallest power of 2 > 160), then you'll need to receive 2 audio blocks before you can start to compute the FFT and generate output samples.
-
-So, in the generated schedule you'll see sequences like :
-
-* source, source ... sink 
-
-which is showing there will be a latency issue. The connection between the sink and an audio DMA will require more buffers than with a schedule like source ... sink ... source ... sink.
-
-To solve this problem you need either to:
-
-* Use different length for the audio blocks
-* Use a FFT which is not a power of 2 
-
-
-
-## Performances
-
-The use of C++ templates is giving more visibility to the compiler:
-
-* The number of samples read and written on the FIFOs are statically known ;
-* When a FIFO is used as a simple array : it is statically visible to the compiler 
-* The dataflow between the nodes is statically visible
-
-It enables the compiler to generate better code for the C++ wrappers and minimize the overhead.
-
-As an example, let's look at the graph:
-
-![perf](documentation/perf.png)
-
-The full code for all the nodes is:
-
-```C++
-template<typename IN, int inputSize>
-class Sink;
-
-template<int inputSize>
-class Sink<float32_t,inputSize>: 
-public GenericSink<float32_t, inputSize>
-{
-public:
-    Sink(FIFOBase<float32_t> &src):
-    GenericSink<float32_t,inputSize>(src){
-    };
-
-    int run()
-    {
-        float32_t *b=this->getReadBuffer();
-        for(int i=0;i<inputSize;i++)
-        {
-            output[i] = b[i];
-        }
-        return(0);
-    };
-
-    
-
-};
-
-template<typename OUT,int outputSize>
-class Source;
-
-template<int outputSize>
-class Source<float32_t,outputSize>: GenericSource<float32_t,outputSize>
-{
-public:
-    Source(FIFOBase<float32_t> &dst):
-    GenericSource<float32_t,outputSize>(dst){};
-
-    int run(){
-        float32_t *b=this->getWriteBuffer();
-        for(int i=0;i<outputSize;i++)
-        {
-            b[i] = input[i];
-        }
-        return(0);
-    };
-
-
-};
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ProcessingNode;
-
-template<int inputSize>
-class ProcessingNode<float32_t,inputSize,float32_t,inputSize>: 
-public GenericNode<float32_t,inputSize,float32_t,inputSize>
-{
-public:
-    ProcessingNode(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):
-    GenericNode<float32_t,inputSize,float32_t,inputSize>(src,dst){};
-
-    int run(){
-        float32_t *a=this->getReadBuffer();
-        float32_t *b=this->getWriteBuffer();
-        arm_offset_f32(a,0.5,b,inputSize);
-       
-        return(0);
-    };
-
-};
-```
-
-The `input` and `output` arrays, used in the sink / source, are defined as extern. The source is reading from `input` and the sink is writing to `output`.
-
-The generated scheduler is:
-
-```C++
-uint32_t scheduler(int *error)
-{
-    int cgStaticError=0;
-    uint32_t nbSchedule=0;
-    int32_t debugCounter=1;
-
-    CG_BEFORE_FIFO_INIT;
-    /*
-    Create FIFOs objects
-    */
-    FIFO<float32_t,FIFOSIZE0,1,0> fifo0(buf0);
-    FIFO<float32_t,FIFOSIZE1,1,0> fifo1(buf1);
-
-    CG_BEFORE_NODE_INIT;
-    /* 
-    Create node objects
-    */
-    ProcessingNode<float32_t,128,float32_t,128> proc(fifo0,fifo1);
-    Sink<float32_t,128> sink(fifo1);
-    Source<float32_t,128> source(fifo0);
-
-    /* Run several schedule iterations */
-    CG_BEFORE_SCHEDULE;
-    while((cgStaticError==0) && (debugCounter > 0))
-    {
-        /* Run a schedule iteration */
-        CG_BEFORE_ITERATION;
-        for(unsigned long id=0 ; id < 3; id++)
-        {
-            CG_BEFORE_NODE_EXECUTION;
-
-            switch(schedule[id])
-            {
-                case 0:
-                {
-                   cgStaticError = proc.run();
-                }
-                break;
-
-                case 1:
-                {
-                   cgStaticError = sink.run();
-                }
-                break;
-
-                case 2:
-                {
-                   cgStaticError = source.run();
-                }
-                break;
-
-                default:
-                break;
-            }
-            CG_AFTER_NODE_EXECUTION;
-            CHECKERROR;
-        }
-       debugCounter--;
-       CG_AFTER_ITERATION;
-       nbSchedule++;
-    }
-
-errorHandling:
-    CG_AFTER_SCHEDULE;
-    *error=cgStaticError;
-    return(nbSchedule);
-}
-```
-
-If we look at the asm of the scheduler generated for a Cortex-M7 with `-Ofast` with armclang `AC6.19` and for **one** iteration of the schedule, we get (disassembly is from uVision IDE):
-
-```txt
-0x000004B0 B570      PUSH          {r4-r6,lr}
-    97:             b[i] = input[i]; 
-0x000004B2 F2402518  MOVW          r5,#0x218
-0x000004B6 F2406118  MOVW          r1,#0x618
-0x000004BA F2C20500  MOVT          r5,#0x2000
-0x000004BE 4604      MOV           r4,r0
-0x000004C0 F2C20100  MOVT          r1,#0x2000
-0x000004C4 F44F7200  MOV           r2,#0x200
-0x000004C8 4628      MOV           r0,r5
-0x000004CA F00BF8E6  BL.W          0x0000B69A __aeabi_memcpy4
-0x000004CE EEB60A00  VMOV.F32      s0,#0.5
-   131:         arm_offset_f32(a,0.5,b,inputSize); 
-0x000004D2 F2404618  MOVW          r6,#0x418
-0x000004D6 F2C20600  MOVT          r6,#0x2000
-0x000004DA 2280      MOVS          r2,#0x80
-0x000004DC 4628      MOV           r0,r5
-0x000004DE 4631      MOV           r1,r6
-0x000004E0 F002FC5E  BL.W          0x00002DA0 arm_offset_f32
-    63:             output[i] = b[i]; 
-0x000004E4 F648705C  MOVW          r0,#0x8F5C
-0x000004E8 F44F7200  MOV           r2,#0x200
-0x000004EC F2C20000  MOVT          r0,#0x2000
-0x000004F0 4631      MOV           r1,r6
-0x000004F2 F00BF8D2  BL.W          0x0000B69A __aeabi_memcpy4
-   163:        CG_AFTER_ITERATION; 
-   164:        nbSchedule++; 
-   165:     } 
-   166:  
-   167: errorHandling: 
-   168:     CG_AFTER_SCHEDULE; 
-   169:     *error=cgStaticError; 
-   170:     return(nbSchedule); 
-0x000004F6 F2402014  MOVW          r0,#0x214
-0x000004FA F2C20000  MOVT          r0,#0x2000
-0x000004FE 6801      LDR           r1,[r0,#0x00]
-0x00000500 3101      ADDS          r1,r1,#0x01
-0x00000502 6001      STR           r1,[r0,#0x00]
-   171: } 
-0x00000504 2001      MOVS          r0,#0x01
-0x00000506 2100      MOVS          r1,#0x00
-   169:     *error=cgStaticError; 
-0x00000508 6021      STR           r1,[r4,#0x00]
-0x0000050A BD70      POP           {r4-r6,pc}
-```
-
-It is the code you would get if you was manually writing a call to the corresponding CMSIS-DSP functions. All the C++ templates have disappeared. The switch / case used to implement the scheduler has also been removed.
-
-The code was generated with `memoryOptimization` enabled and the Python script detected in this case that the FIFOs are used as arrays. As consequence, there is no FIFO update code. They are used as normal arrays.
-
-The generated code is as efficient as something manually coded.
-
-The sink and the sources have been replaced by a `memcpy`. The call to the CMSIS-DSP function is just loading the registers and branching to the CMSIS-DSP function.
-
-It is not always as ideal as in this example. But it demonstrates that the use of C++ templates and a Python code generator is enabling a low overhead solution to the problem of streaming and compute graph.
-

ComputeGraph/Introduction.md

@@ -1,98 +0,0 @@
-# Introduction
-
-Embedded systems are often used to implement streaming solutions : the software is processing and / or generating stream of samples. The software is made of components that have no concept of streams : they are working with buffers. As a consequence, implementing a streaming solution is forcing the developer to think about scheduling questions, FIFO sizing etc ...
-
-The CMSIS-DSP compute graph is a **low overhead** solution to this problem : it makes it easier to build streaming solutions by connecting components and computing a scheduling at **build time**. The use of C++ template also enables the compiler to have more information about the components for better code generation.
-
-A dataflow graph is a representation of how compute blocks are connected to implement a streaming processing. 
-
-Here is an example with 3 nodes:
-
-- A source
-- A filter
-- A sink
-
-Each node is producing and consuming some amount of samples. For instance, the source node is producing 5 samples each time it is run. The filter node is consuming 7 samples each time it is run.
-
-The FIFOs lengths are represented on each edge of the graph : 11 samples for the leftmost FIFO and 5 for the other one.
-
-In blue, the amount of samples generated or consumed by a node each time it is called.
-
-<img src="examples/example1/docassets/graph1.PNG" alt="graph1" style="zoom:100%;" />
-
-When the processing is applied to a stream of samples then the problem to solve is : 
-
-> **how the blocks must be scheduled and the FIFOs connecting the block dimensioned**
-
-The general problem can be very difficult. But, if some constraints are applied to the graph then some algorithms can compute a static schedule at build time.
-
-When the following constraints are satisfied we say we have a Synchronous / Static Dataflow Graph:
-
-- Each node is always consuming and producing the same number of samples (static / synchronous flow)
-
-The CMSIS-DSP Compute Graph Tools are a set of Python scripts and C++ classes with following features:
-
-- A compute graph and its static flow can be described in Python
-- The Python script will compute a static schedule and the optimal FIFOs size
-- A static schedule is:
-  - A periodic sequence of functions calls
-  - A periodic execution where the FIFOs remain bounded
-  - A periodic execution with no deadlock : when a node is run there is enough data available to run it 
-- The Python script will generate a [Graphviz](https://graphviz.org/) representation of the graph 
-- The Python script will generate a C++ implementation of the static schedule 
-- The Python script can also generate a Python implementation of the static schedule (for use with the CMSIS-DSP Python wrapper)
-
-There is no FIFO underflow or overflow due to the scheduling. If there are not enough cycles to run the processing, the real-time will be broken and the solution won't work. But this problem is independent from the scheduling itself. 
-
-# Why it is useful
-
-Without any scheduling tool for a dataflow graph, there is a problem of modularity : a change on a node may impact other nodes in the graph. For instance, if the number of samples consumed by a node is changed:
-
-- You may need to change how many samples are produced by the predecessor blocks  in the graph (assuming it is possible)
-- You may need to change how many times the predecessor blocks must run
-- You may have to change the FIFOs sizes
-
-With the CMSIS-DSP Compute Graph (CG) Tools you don't have to think about those details while you are still experimenting with your data processing pipeline. It makes it easier to experiment, add or remove blocks, change their parameters.
-
-The tools will generate a schedule and the FIFOs. Even if you don't use this at the end for a final implementation, the information could be useful : is the schedule too long ? Are the FIFOs too big ? Is there too much latency between the sources and the sinks ?
-
-Let's look at an (artificial) example:
-
-<img src="examples/example1/docassets/graph1.PNG" alt="graph1" style="zoom:100%;" />
-
-Without a tool, the user would probably try to modify the number of samples so that the number of sample produced is equal to the number of samples consumed. With the CG Tools  we know that such a graph can be scheduled and that the FIFO sizes need to be 11 and 5.
-
-The periodic schedule generated for this graph has a length of 19. It is big for such a small graph and it is because, indeed 5 and 7 are not very well chosen values. But, it is working even with those values.
-
-The schedule is (the number of samples in the FIFOs after the execution of the nodes are displayed in the brackets):
-
-```
-source [ 5   0]
-source [10   0]
-filter [ 3   5]
-sink   [ 3   0]
-source [ 8   0]
-filter [ 1   5]
-sink   [ 1   0]
-source [ 6   0]
-source [11   0]
-filter [ 4   5]
-sink   [ 4   0]
-source [ 9   0]
-filter [ 2   5]
-sink   [ 2   0]
-source [ 7   0]
-filter [ 0   5]
-sink   [ 0   0]
-```
-
-At the end, both FIFOs are empty so the schedule can be run again : it is periodic !
-
-The compute graph is focusing on the synchronous / static case but some extensions have been introduced for more flexibility:
-
-* A [cyclo-static scheduling](CycloStatic.md) (nearly static)
-* A [dynamic/asynchronous](Async.md) mode
-
-Here is a summary of the different configuration supported by the compute graph. The cyclo-static scheduling is part of the static flow mode.
-
-![supported_configs](documentation/supported_configs.png)

ComputeGraph/MATHS.md

@@ -1,79 +0,0 @@
-# Mathematical principles
-
-This document explains the mathematical ideas used in the algorithm (Python script) to compute the static (or cyclo-static) scheduling.
-
-The details and demonstrations (for the static scheduling) can be found in the reference paper:
-
-> Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing
-> EDWARD ASHFORD LEE, MEMBER, IEEE, AND DAVID G. MESSERSCHMITT, FELLOW, IEEE
-
-## Static scheduling
-
-The following graph will be used as an example for the explanations:
-
-![graph_math1](documentation/graph_math1.png)
-
-A topology matrix can be created from each graph where the columns describe the nodes, and the rows describe the edges.
-
-The values represent how many samples are produced or consumed on each edge.
-
-The following matrix `M` is created from the previous graph. The first column represents the filter. The second column represents the sink and the last column represents the source.
-
-![math-matrix1](documentation/math-matrix1.png)
-
-The first row means that an execution of the filter is consuming 7 samples on the first edge and execution of the source is producing 5 samples. The sink is not connected to the first edge so the value is 0.
-
-If a node is run `nb` times then the matrix can be used to compute the state of the edges after this execution.
-
-A vector `s` can be used to represent how many time each node is executed. Then `M.s` is the amount of data produced / consumed on each edge.
-
-If `f` is the state of the edges (amount of data on each edge) then, after execution of the nodes as described with `s`, we have:
-
-`f' = M . s + f`
-
-where `f'` is the new state after the execution of the nodes.
-
-If we want to find a scheduling of this graph allowing to stream samples from the source to the sink, then a periodic solution must be found. It is equivalent to finding a solution of:
-
-`M . s = 0`
-
-The theory is showing that if the graph is schedulable, the space of solution has dimension 1. So we can find a solution with minimal integer values for the coefficients by :
-
-* Converting the solution (which may be rational) to integers
-* Using the greatest common divider to find the smallest solution
-
-In the above example, we find the scheduling vector : `s={5,5,7}`
-
-Once we know how many time each node must be executed, we can try to find a schedule minimizing the memory usage. The algorithm computes a topological sort of the graph and starts from the sinks. A node is scheduled if it has enough data on its edges : a normalized measure is being used on each edge. The amount of data is not directly used but it is normalized by the amount of data read or produced by the node in a given execution. The idea is to run the node as soon as enough data is available to make the execution of the node possible:
-
-For instance, the 2 following cases are equivalent for the algorithm:
-
-* A FIFO containing 128 samples and connected to a node consuming 128 samples
-* A FIFO containing 1 sample and connected to a node consuming 1 sample
-
-The algorithm is considering those 2 FIFOs as filled in the same way.
-
-The graph is structured in layers : nodes are in the same layer if their distance to the sinks is the same.
-
-To select a node in a layer, a round robin strategy is used so that all nodes are given equal chances to be executed. A node having enough data on its edges won't be executed if it has recently been executed.
-
-The scheduling is stopping as soon as each node has been executed the number of times described by the scheduling vector. This scheduling is a period and by executing several time this schedule we stream the samples through the compute graph from the sources to the sinks.
-
-## Cyclo static scheduling
-
-In case a node is not always producing or consuming the same amount of data, but is periodically doing so, we can reuse the previous theory and methods.
-
-If we look at a node `n` connected to other nodes, we know that if we want a possible schedule we need to find a periodic execution. 
-
-The node `n` will see a similar environment only when all surrounding node periods have been executed. It implies that the node must be executed a number of times which is a multiple of the least common multiple of the periods.
-
-For instance, if the node is connected to a node of period 3 and a node of period 5, then it is only after 15 executions minimum that we can expect to have a periodic execution. For less than 15 executions, one of the nodes will be still running its cycle. 
-
-Of course, it does not mean that, from a data point of view, 15 may be enough. But we know that it will be a multiple of 15.
-
-So we can reuse the previous theory if we assume that each node execution is in fact the least common multiple of the periods of the surrounding nodes.
-
-Once we have computed the matrix and the scheduling solution, the details of the schedule are computed using a different granularity : the cycles are no more considered as a whole but instead  each execution step inside each cycle is used.
-
-As consequence, the effect of the cyclo-static scheduling is just to increase the length of the final scheduling sequence since each node will have to be executed a number of times which is constrained by the least common multiples of the period of the connected nodes.
-

ComputeGraph/README.md

@@ -1,34 +0,0 @@
-# Compute Graph for streaming with CMSIS-DSP
-
-## Table of contents
-
-1. ### [Introduction](Introduction.md)
-
-2. ### How to get started
-
-   1. [Simple graph creation example](examples/simple/README.md)
-
-   2. [Simple graph creation example with CMSIS-DSP](examples/simpledsp/README.md)
-
-3. ### [Examples](examples/README.md)
-
-4. ### [Python API for creating graphs and schedulers](documentation/PythonAPI.md)
-
-5. ### [C++ default nodes for C++ schedulers](documentation/CPPNodes.md)
-
-6. ### [Python default nodes for Python schedulers](documentation/PythonNodes.md)
-
-7. ### [Memory optimizations](documentation/Memory.md)
-
-8. ### Extensions
-
-   1. #### [Cyclo-static scheduling](CycloStatic.md)
-
-   2. #### [Dynamic / Asynchronous mode](Async.md)
-
-9. ### [Maths principles](MATHS.md)
-
-10. ### [FAQ](FAQ.md)
-
-
-

ComputeGraph/cg.scvd

@@ -1,48 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
- <!--      
-   
-   Project:      CMSIS DSP Library
-   Title:        cg.SCVD
-   Description:  Event definitions for use in Keil MDK
-  
-   $Date:        19 September 2022
-  
-   Target Processor: Cortex-M and Cortex-A cores
-   
-  
-   Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
-  
-   SPDX-License-Identifier: Apache-2.0
-  
-   Licensed under the Apache License, Version 2.0 (the License); you may
-   not use this file except in compliance with the License.
-   You may obtain a copy of the License at
-  
-   www.apache.org/licenses/LICENSE-2.0
-  
-   Unless required by applicable law or agreed to in writing, software
-   distributed under the License is distributed on an AS IS BASIS, WITHOUT
-   WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-   See the License for the specific language governing permissions and
-   limitations under the License.
-  
--->
-
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
-  <component name="CMSIS-DSP Compute Graph" version="1.0.0"/>    <!-- name and version of the component  -->
- 
-    <events>
-      <group name="CMSIS-DSP Compute Graph">
-         <component name="Scheduler"   brief="CG"    no="0x01" prefix="EvrSchedCG_"    info="CG Static Scheduler"/>
-      </group>  
- 
-      <event id="0x0100 + 0x00" level="API" property="ScheduleIteration" info="New iteration of scheduling loop" value="nb=%d[val1]" />
-
-      <event id="0x0100 + 0x01" level="API" property="NodeExecution" info="Execution of a node" value="ID=%d[val1]" />
-
-      <event id="0x0100 + 0x02" level="Error" property="Error" info="Error during execution of a node" value="err=%d[val1]" />
-    
-      
-    </events>
- 
-</component_viewer>

ComputeGraph/cg/nodes/README.md

@@ -1,6 +0,0 @@
-# Nodes
-
-Some nodes. Some are used in the examples.
-
-There are CPP and Python versions for most of the nodes.
-

ComputeGraph/cg/nodes/cpp/CFFT.h

@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        CFFT.h
- * Description:  Node for CMSIS-DSP cfft
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _CFFT_H_ 
-#define _CFFT_H_
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class CFFT;
-
-/*
-
-The CMSIS-DSP CFFT F32
-
-*/
-template<int inputSize>
-class CFFT<float32_t,inputSize,float32_t,inputSize>: public GenericNode<float32_t,inputSize,float32_t,inputSize>
-{
-public:
-    CFFT(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):GenericNode<float32_t,inputSize,float32_t,inputSize>(src,dst){
-         status=arm_cfft_init_f32(&sfft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        float32_t *a=this->getReadBuffer();
-        float32_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(float32_t));
-        arm_cfft_f32(&sfft,b,0,1);
-        return(0);
-    };
-
-    arm_cfft_instance_f32 sfft;
-    arm_status status;
-
-};
-
-#if defined(ARM_FLOAT16_SUPPORTED)
-/*
-
-The CMSIS-DSP CFFT F32
-
-*/
-template<int inputSize>
-class CFFT<float16_t,inputSize,float16_t,inputSize>: public GenericNode<float16_t,inputSize,float16_t,inputSize>
-{
-public:
-    CFFT(FIFOBase<float16_t> &src,FIFOBase<float16_t> &dst):GenericNode<float16_t,inputSize,float16_t,inputSize>(src,dst){
-         status=arm_cfft_init_f16(&sfft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        float16_t *a=this->getReadBuffer();
-        float16_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(float16_t));
-        arm_cfft_f16(&sfft,b,0,1);
-        return(0);
-    };
-
-    arm_cfft_instance_f16 sfft;
-    arm_status status;
-
-};
-#endif
-/*
-
-The CMSIS-DSP CFFT Q15
-
-*/
-template<int inputSize>
-class CFFT<q15_t,inputSize,q15_t,inputSize>: public GenericNode<q15_t,inputSize,q15_t,inputSize>
-{
-public:
-    CFFT(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst):GenericNode<q15_t,inputSize,q15_t,inputSize>(src,dst){
-         status=arm_cfft_init_q15(&sfft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        q15_t *a=this->getReadBuffer();
-        q15_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(q15_t));
-        arm_cfft_q15(&sfft,b,0,1);
-        return(0);
-    };
-
-    arm_cfft_instance_q15 sfft;
-    arm_status status;
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/ICFFT.h

@@ -1,162 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        ICFFT.h
- * Description:  Node for CMSIS-DSP icfft
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _ICFFT_H_
-#define _ICFFT_H_ 
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ICFFT;
-
-/*
-
-The CMSIS-DSP ICFFT F32
-
-*/
-template<int inputSize>
-class ICFFT<float32_t,inputSize,float32_t,inputSize>: public GenericNode<float32_t,inputSize,float32_t,inputSize>
-{
-public:
-    ICFFT(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):GenericNode<float32_t,inputSize,float32_t,inputSize>(src,dst){
-         status=arm_cfft_init_f32(&sifft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        float32_t *a=this->getReadBuffer();
-        float32_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(float32_t));
-        arm_cfft_f32(&sifft,b,1,1);
-        return(0);
-    };
-
-    arm_cfft_instance_f32 sifft;
-    arm_status status;
-
-};
-
-#if defined(ARM_FLOAT16_SUPPORTED)
-/*
-
-The CMSIS-DSP ICFFT F32
-
-*/
-template<int inputSize>
-class ICFFT<float16_t,inputSize,float16_t,inputSize>: public GenericNode<float16_t,inputSize,float16_t,inputSize>
-{
-public:
-    ICFFT(FIFOBase<float16_t> &src,FIFOBase<float16_t> &dst):GenericNode<float16_t,inputSize,float16_t,inputSize>(src,dst){
-         status=arm_cfft_init_f16(&sifft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        float16_t *a=this->getReadBuffer();
-        float16_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(float16_t));
-        arm_cfft_f16(&sifft,b,1,1);
-        return(0);
-    };
-
-    arm_cfft_instance_f16 sifft;
-    arm_status status;
-
-};
-#endif
-
-/*
-
-The CMSIS-DSP ICFFT Q15
-
-*/
-template<int inputSize>
-class ICFFT<q15_t,inputSize,q15_t,inputSize>: public GenericNode<q15_t,inputSize,q15_t,inputSize>
-{
-public:
-    ICFFT(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst):GenericNode<q15_t,inputSize,q15_t,inputSize>(src,dst){
-         status=arm_cfft_init_q15(&sifft,inputSize>>1);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final
-    {
-        if (status!=ARM_MATH_SUCCESS)
-        {
-            return(CG_INIT_FAILURE);
-        }
-        q15_t *a=this->getReadBuffer();
-        q15_t *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)a,inputSize*sizeof(q15_t));
-        arm_cfft_q15(&sifft,b,1,1);
-        return(0);
-    };
-
-    arm_cfft_instance_q15 sifft;
-    arm_status status;
-
-};
-#endif

ComputeGraph/cg/nodes/cpp/InterleavedStereoToMono.h

@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        InterleavedStereoToMono.h
- * Description:  Interleaved Stereo to mono stream in Q15
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _STEREOTOMONO_H_
-#define _STEREOTOMONO_H_ 
-
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class InterleavedStereoToMono;
-
-template<int inputSize,int outputSize>
-class InterleavedStereoToMono<q15_t,inputSize,q15_t,outputSize>: public GenericNode<q15_t,inputSize,q15_t,outputSize>
-{
-public:
-    InterleavedStereoToMono(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst):
-    GenericNode<q15_t,inputSize,q15_t,outputSize>(src,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        q15_t *a=this->getReadBuffer();
-        q15_t *b=this->getWriteBuffer();
-        for(int i = 0; i<outputSize; i++)
-        {
-           b[i] = (a[2*i]>>1) + (a[2*i+1]>>1);
-        }
-        return(0);
-    };
-
-};
-
-template<int inputSize,int outputSize>
-class InterleavedStereoToMono<q31_t,inputSize,q31_t,outputSize>: public GenericNode<q31_t,inputSize,q31_t,outputSize>
-{
-public:
-    InterleavedStereoToMono(FIFOBase<q31_t> &src,FIFOBase<q31_t> &dst):
-    GenericNode<q31_t,inputSize,q31_t,outputSize>(src,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        q31_t *a=this->getReadBuffer();
-        q31_t *b=this->getWriteBuffer();
-        for(int i = 0; i<outputSize; i++)
-        {
-           b[i] = (a[2*i]>>1) + (a[2*i+1]>>1);
-        }
-        return(0);
-    };
-
-};
-
-template<int inputSize,int outputSize>
-class InterleavedStereoToMono<float32_t,inputSize,float32_t,outputSize>: public GenericNode<float32_t,inputSize,float32_t,outputSize>
-{
-public:
-    InterleavedStereoToMono(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):
-    GenericNode<float32_t,inputSize,float32_t,outputSize>(src,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final
-    {
-        float32_t *a=this->getReadBuffer();
-        float32_t *b=this->getWriteBuffer();
-        for(int i = 0; i<outputSize; i++)
-        {
-           b[i] = 0.5f * (a[2*i] + a[2*i+1]);
-        }
-        return(0);
-    };
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/MFCC.h

@@ -1,204 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        MFCC.h
- * Description:  Node for CMSIS-DSP MFCC
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _MFCC_H_ 
-#define _MFCC_H_
-
-#include <vector>
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class MFCC;
-
-/*
-
-The MFCC configuration data has to be generated with the script DSP/Scripts/GenMFCCDataForCPP.py.
-It is using a yaml file to describe the configuration
-
-*/
-
-/*
-
-The CMSIS-DSP MFCC F32
-
-*/
-template<int inputSize,int outputSize>
-class MFCC<float32_t,inputSize,float32_t,outputSize>: public GenericNode<float32_t,inputSize,float32_t,outputSize>
-{
-public:
-    MFCC(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst,const arm_mfcc_instance_f32 *config):GenericNode<float32_t,inputSize,float32_t,outputSize>(src,dst){
-         mfccConfig = config;
-#if defined(ARM_MFCC_CFFT_BASED)
-         memory.resize(2*inputSize);
-#else
-         memory.resize(inputSize + 2);
-#endif
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        float32_t *a=this->getReadBuffer();
-        float32_t *b=this->getWriteBuffer();
-        arm_mfcc_f32(mfccConfig,a,b,memory.data());
-        return(0);
-    };
-
-    const arm_mfcc_instance_f32 *mfccConfig;
-    std::vector<float32_t> memory;
-};
-
-#if defined(ARM_FLOAT16_SUPPORTED)
-/*
-
-The CMSIS-DSP MFCC F16
-
-*/
-template<int inputSize,int outputSize>
-class MFCC<float16_t,inputSize,float16_t,outputSize>: public GenericNode<float16_t,inputSize,float16_t,outputSize>
-{
-public:
-    MFCC(FIFOBase<float16_t> &src,FIFOBase<float16_t> &dst,const arm_mfcc_instance_f16 *config):GenericNode<float16_t,inputSize,float16_t,outputSize>(src,dst){
-         mfccConfig = config;
-#if defined(ARM_MFCC_CFFT_BASED)
-         memory.resize(2*inputSize);
-#else
-         memory.resize(inputSize + 2);
-#endif
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        float16_t *a=this->getReadBuffer();
-        float16_t *b=this->getWriteBuffer();
-        arm_mfcc_f16(mfccConfig,a,b,memory.data());
-        return(0);
-    };
-
-    const arm_mfcc_instance_f16 *mfccConfig;
-    std::vector<float16_t> memory;
-};
-#endif 
-
-/*
-
-The CMSIS-DSP MFCC Q31
-
-*/
-template<int inputSize,int outputSize>
-class MFCC<q31_t,inputSize,q31_t,outputSize>: public GenericNode<q31_t,inputSize,q31_t,outputSize>
-{
-public:
-    MFCC(FIFOBase<q31_t> &src,FIFOBase<q31_t> &dst,const arm_mfcc_instance_q31 *config):GenericNode<q31_t,inputSize,q31_t,outputSize>(src,dst){
-         mfccConfig = config;
-         memory.resize(2*inputSize);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        q31_t *a=this->getReadBuffer();
-        q31_t *b=this->getWriteBuffer();
-        arm_mfcc_q31(mfccConfig,a,b,memory.data());
-        return(0);
-    };
-
-    const arm_mfcc_instance_q31 *mfccConfig;
-    std::vector<q31_t> memory;
-};
-
-/*
-
-The CMSIS-DSP MFCC Q15
-
-*/
-template<int inputSize,int outputSize>
-class MFCC<q15_t,inputSize,q15_t,outputSize>: public GenericNode<q15_t,inputSize,q15_t,outputSize>
-{
-public:
-    MFCC(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst,const arm_mfcc_instance_q15 *config):GenericNode<q15_t,inputSize,q15_t,outputSize>(src,dst){
-         mfccConfig = config;
-         memory.resize(2*inputSize);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        q15_t *a=this->getReadBuffer();
-        q15_t *b=this->getWriteBuffer();
-        arm_mfcc_q15(mfccConfig,a,b,memory.data());
-        return(0);
-    };
-
-    const arm_mfcc_instance_q15 *mfccConfig;
-    std::vector<q31_t> memory;
-};
-
-
-#endif

ComputeGraph/cg/nodes/cpp/NullSink.h

@@ -1,58 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        NullSink.h
- * Description:  Sink doing nothing for debug
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */ 
-#ifndef _NULLSINK_H_
-#define _NULLSINK_H_
-
-/* Write a list of samples to a file in text form */
-template<typename IN, int inputSize>
-class NullSink: public GenericSink<IN, inputSize>
-{
-public:
-    NullSink(FIFOBase<IN> &src):GenericSink<IN,inputSize>(src){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *b=this->getReadBuffer();
-
-        
-
-        return(0);
-    };
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/OverlapAndAdd.h

@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        OverlapAndAdd.h
- * Description:  Overlap And Add
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _OVERLAPANDADD_H_
-#define _OVERLAPANDADD_H_ 
-
-
-template<typename IN,int windowSize, int overlap>
-class OverlapAdd: public GenericNode<IN,windowSize,IN,windowSize-overlap>
-{
-public:
-    OverlapAdd(FIFOBase<IN> &src,FIFOBase<IN> &dst):GenericNode<IN,windowSize,IN,windowSize-overlap>(src,dst)
-    {
-        static_assert((windowSize-overlap)>0, "Overlap is too big");
-        memory.resize(overlap);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        int i;
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-
-        for(i=0;i<overlap;i++)
-        {
-            memory[i] = a[i] + memory[i];
-        }
-
-        if (2*overlap - windowSize > 0)
-        {
-            
-            memcpy((void*)b,(void*)memory.data(),(windowSize-overlap)*sizeof(IN));
-
-            memmove(memory.data(),memory.data()+windowSize-overlap,(2*overlap - windowSize)*sizeof(IN));
-            memcpy(memory.data()+2*overlap - windowSize,a+overlap,(windowSize-overlap)*sizeof(IN));
-        }
-        else if (2*overlap - windowSize < 0)
-        {
-            memcpy((void*)b,(void*)memory.data(),overlap*sizeof(IN));
-            memcpy((void*)(b+overlap),(void*)(a+overlap),(windowSize - 2*overlap)*sizeof(IN));
-
-            memcpy((void*)memory.data(),(void*)(a+windowSize-overlap),overlap*sizeof(IN));
-        }
-        else
-        {
-            memcpy((void*)b,(void*)memory.data(),overlap*sizeof(IN));
-
-            memcpy((void*)memory.data(),(void*)(a+overlap),overlap*sizeof(IN));
-        }
-        
-        return(0);
-    };
-protected:
-    std::vector<IN> memory;
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/SlidingBuffer.h

@@ -1,67 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        SlidingBuffer.h
- * Description:  Sliding buffer
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _SLIDINGBUFFER_H_
-#define _SLIDINGBUFFER_H_ 
-
-
-template<typename IN,int windowSize, int overlap>
-class SlidingBuffer: public GenericNode<IN,windowSize-overlap,IN,windowSize>
-{
-public:
-    SlidingBuffer(FIFOBase<IN> &src,FIFOBase<IN> &dst):GenericNode<IN,windowSize-overlap,IN,windowSize>(src,dst)
-    {
-        static_assert((windowSize-overlap)>0, "Overlap is too big");
-        memory.resize(overlap);
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-        memcpy((void*)b,(void*)memory.data(),overlap*sizeof(IN));
-        memcpy((void*)(b+overlap),(void*)a,(windowSize-overlap)*sizeof(IN));
-        memcpy((void*)memory.data(),(void*)(b+windowSize-overlap),overlap*sizeof(IN)) ;
-        return(0);
-    };
-protected:
-    std::vector<IN> memory;
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/ToComplex.h

@@ -1,72 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        ToComplex.h
- * Description:  Node to convert real to complex 
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _TOCOMPLEX_H_
-#define _TOCOMPLEX_H_
-
-/*
-
-Convert a stream of reals a b c d ...
-to complexes a 0 b 0 c 0 d 0 ...
-*/
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ToComplex;
-
-template<typename IN, int inputSize,int outputSize>
-class ToComplex<IN,inputSize,IN,outputSize>: public GenericNode<IN,inputSize,IN,outputSize>
-{
-public:
-    ToComplex(FIFOBase<IN> &src,FIFOBase<IN> &dst):GenericNode<IN,inputSize,IN,outputSize>(src,dst){
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-        for(int i=0;i<inputSize;i++)
-        {
-            b[2*i]=a[i];
-            b[2*i+1]=0;
-        }
-        return(0);
-    };
-
-
-};
-
-#endif 

ComputeGraph/cg/nodes/cpp/ToReal.h

@@ -1,70 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        ToReal.h
- * Description:  Node to convert complex to reals
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _TOREAL_H_ 
-#define _TOREAL_H_
-
-/*
-
-Convert a stream of complex a 0 b 0 c 0 ...
-to reals a b c ...
-*/
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ToReal;
-
-template<typename IN, int inputSize,int outputSize>
-class ToReal<IN,inputSize,IN,outputSize>: public GenericNode<IN,inputSize,IN,outputSize>
-{
-public:
-    ToReal(FIFOBase<IN> &src,FIFOBase<IN> &dst):GenericNode<IN,inputSize,IN,outputSize>(src,dst){
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-        for(int i=0;i<outputSize;i++)
-        {
-            b[i]=a[2*i];
-        }
-        return(0);
-    };
-
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/Unzip.h

@@ -1,78 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        Unzip.h
- * Description:  Node to unzip a stream of pair
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _UNZIP_H_
-#define _UNZIP_H_ 
-
-/*
-
-Unzip a stream a1 a2 b1 b2 c1 c2 ...
-Into 2 streams:
-a1 b1 c1 ...
-a2 b2 c2 ...
-
-*/
-template<typename IN, int inputSize,typename OUT1,int output1Size,typename OUT2,int output2Size>
-class Unzip;
-
-template<typename IN, int inputSize,int output1Size,int output2Size>
-class Unzip<IN,inputSize,IN,output1Size,IN,output2Size>: public GenericNode12<IN,inputSize,IN,output1Size,IN,output2Size>
-{
-public:
-    Unzip(FIFOBase<IN> &src,FIFOBase<IN> &dst1,FIFOBase<IN> &dst2):
-    GenericNode12<IN,inputSize,IN,output1Size,IN,output2Size>(src,dst1,dst2){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow1() ||
-            this->willOverflow2() ||
-            this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    /*
-          2*outputSize1 == 2*outSize2 == inputSize
-    */
-    int run() final
-    {
-        IN *a=this->getReadBuffer();
-        IN *b1=this->getWriteBuffer1();
-        IN *b2=this->getWriteBuffer2();
-        for(int i = 0; i<output1Size; i++)
-        {
-           b1[i] =(IN)a[2*i];
-           b2[i] =(IN)a[2*i+1];
-        }
-        return(0);
-    };
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/Zip.h

@@ -1,68 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        Zip.h
- * Description:  Node to zip a pair of stream
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _ZIP_H_
-#define _ZIP_H_ 
-
-
-template<typename IN1, int inputSize1,typename IN2,int inputSize2,typename OUT,int outputSize>
-class Zip;
-
-template<typename IN, int inputSize,int outputSize>
-class Zip<IN,inputSize,IN,inputSize,IN,outputSize>: public GenericNode21<IN,inputSize,IN,inputSize,IN,outputSize>
-{
-public:
-    Zip(FIFOBase<IN> &src1,FIFOBase<IN> &src2,FIFOBase<IN> &dst):
-    GenericNode21<IN,inputSize,IN,inputSize,IN,outputSize>(src1,src2,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow1() ||
-            this->willUnderflow2()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *a1=this->getReadBuffer1();
-        IN *a2=this->getReadBuffer2();
-        IN *b=this->getWriteBuffer1();
-        for(int i = 0; i<inputSize; i++)
-        {
-           b[2*i] = a1[i];
-           b[2*i+1] = a2[i];
-        }
-        return(0);
-    };
-
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/host/FileSink.h

@@ -1,62 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        FileSink.h
- * Description:  Node for creating File sinks
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */ 
-#ifndef _FILESINK_H_
-#define _FILESINK_H_
-
-/* Write a list of samples to a file in text form */
-template<typename IN, int inputSize>
-class FileSink: public GenericSink<IN, inputSize>
-{
-public:
-    FileSink(FIFOBase<IN> &src, std::string name):GenericSink<IN,inputSize>(src),output(name){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final
-    {
-        IN *b=this->getReadBuffer();
-
-        for(int i=0;i<inputSize;i++)
-        {
-            output << b[i] << std::endl;
-        }
-
-        return(0);
-    };
-
-    ofstream output;
-};
-
-#endif

ComputeGraph/cg/nodes/cpp/host/FileSource.h

@@ -1,97 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        FileSource.h
- * Description:  Node for creating File sources
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */ 
-#ifndef _FILESOURCE_H_
-#define _FILESOURCE_H_
-
-template<typename OUT,int outputSize> class FileSource;
-
-/* 
-
-Real a list of floats from a file and pad with zeros indefinitely when end of
-file is reached.
-
-*/
-template<int outputSize>
-class FileSource<float32_t,outputSize>: public GenericSource<float32_t,outputSize>
-{
-public:
-    FileSource(FIFOBase<float32_t> &dst,std::string name):GenericSource<float32_t,outputSize>(dst),
-    input(name)
-    {
-
-    };
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow()
-           )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        string str;
-        int i;
-        float32_t *b=this->getWriteBuffer();
-
-        if (input.eof())
-        {
-            for(i=0;i<outputSize;i++)
-            {
-                b[i] = 0;
-            }
-
-        }
-        else
-        {
-             for(i=0;i<outputSize;i++)
-             {
-                 if (!getline(input, str))
-                 {
-                     b[i] = 0;
-                     break;
-                 }
-                 b[i] = (float)atof(str.c_str());
-             }
-     
-             for(;i<outputSize;i++)
-             {
-                 b[i] = 0;
-             }
-        }
-        return(0);
-    };
-
-
-    ifstream input;
-
-};
-
-#endif

ComputeGraph/cg/src/GenericNodes.h

@@ -1,518 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        GenericNodes.h
- * Description:  C++ support templates for the compute graph with static scheduler
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _SCHEDGEN_H_
-#define _SCHEDGEN_H_
-
-#include <vector>
-
-/* 
-Defined in cg_status.h by default but user
-may want to use a different header to define the 
-error codes of the application
-*/
-#define CG_SKIP_EXECUTION_ID_CODE (-5)
-#define CG_BUFFER_ERROR_ID_CODE (-6)
-
-// FIFOS 
-
-#ifdef DEBUGSCHED
-
-#include <iostream>
-
-template<typename T>
-struct debugtype{
-    typedef T type;
-};
-
-template<>
-struct debugtype<char>{
-    typedef int type;
-};
-
-template<typename T>
-using Debug = struct debugtype<T>;
-
-#endif
-
-template<typename T>
-class FIFOBase{
-public:
-    virtual T* getWriteBuffer(int nb)=0;
-    virtual T* getReadBuffer(int nb)=0;
-    virtual bool willUnderflowWith(int nb) const = 0;
-    virtual bool willOverflowWith(int nb) const = 0;
-    virtual int nbSamplesInFIFO() const = 0;
-
-};
-
-template<typename T, int length, int isArray=0, int isAsync = 0>
-class FIFO;
-
-/* Real FIFO, Synchronous */
-template<typename T, int length>
-class FIFO<T,length,0,0>: public FIFOBase<T> 
-{
-    public:
-        FIFO(T *buffer,int delay=0):mBuffer(buffer),readPos(0),writePos(delay) {};
-        FIFO(uint8_t *buffer,int delay=0):mBuffer((T*)buffer),readPos(0),writePos(delay) {};
-
-        /* Not used in synchronous mode */
-        bool willUnderflowWith(int nb) const final {(void)nb;return false;};
-        bool willOverflowWith(int nb) const final {(void)nb;return false;};
-        int nbSamplesInFIFO() const final {return 0;};
-
-        T * getWriteBuffer(int nb) final
-        {
-            
-            T *ret;
-            if (readPos > 0)
-            {
-                /* This is re-aligning the read buffer.
-                   Aligning buffer is better for vectorized code.
-                   But it has an impact since more memcpy are
-                   executed than required.
-                   This is likely to be not so useful in practice
-                   so a future version will optimize the memcpy usage
-                   */
-                memcpy((void*)mBuffer,(void*)(mBuffer+readPos),(writePos-readPos)*sizeof(T));
-                writePos -= readPos;
-                readPos = 0;
-            }
-            
-            ret = mBuffer + writePos;
-            writePos += nb; 
-            return(ret);
-        };
-
-        T* getReadBuffer(int nb) final
-        {
-            
-            T *ret = mBuffer + readPos;
-            readPos += nb;
-            return(ret);
-        }
-
-        #ifdef DEBUGSCHED
-        void dump()
-        {
-            int nb=0;
-            std::cout << std::endl;
-            for(int i=0; i < length ; i++)
-            {
-                std::cout << (typename Debug<T>::type)mBuffer[i] << " ";
-                nb++;
-                if (nb == 10)
-                {
-                    nb=0;
-                    std::cout << std::endl;
-                }
-            }
-            std::cout << std::endl;
-            std::cout << std::endl;
-        }
-        #endif
-
-    protected:
-        T *mBuffer;
-        int readPos,writePos;
-};
-
-/* Buffer, Synchronous */
-template<typename T, int length>
-class FIFO<T,length,1,0>: public FIFOBase<T> 
-{
-    public:
-        FIFO(T *buffer,int delay=0):mBuffer(buffer),readPos(0),writePos(delay) {};
-        FIFO(uint8_t *buffer,int delay=0):mBuffer((T*)buffer),readPos(0),writePos(delay) {};
-
-        /* Not used in synchronous mode */
-        bool willUnderflowWith(int nb) const final {(void)nb;return false;};
-        bool willOverflowWith(int nb) const final {(void)nb;return false;};
-        int nbSamplesInFIFO() const final {return 0;};
-
-        T * getWriteBuffer(int nb) final
-        {
-            (void)nb;
-            return(mBuffer);
-        };
-
-        T* getReadBuffer(int nb) final
-        {
-            (void)nb;
-            return(mBuffer);
-        }
-
-        #ifdef DEBUGSCHED
-        void dump()
-        {
-            int nb=0;
-            std::cout << std::endl;
-            for(int i=0; i < length ; i++)
-            {
-                std::cout << (typename Debug<T>::type)mBuffer[i] << " ";
-                nb++;
-                if (nb == 10)
-                {
-                    nb=0;
-                    std::cout << std::endl;
-                }
-            }
-            std::cout << std::endl;
-            std::cout << std::endl;
-        }
-        #endif
-
-    protected:
-        T *mBuffer;
-        int readPos,writePos;
-};
-
-/* Real FIFO, Asynchronous */
-template<typename T, int length>
-class FIFO<T,length,0,1>: public FIFOBase<T> 
-{
-    public:
-        FIFO(T *buffer,int delay=0):mBuffer(buffer),readPos(0),writePos(delay),nbSamples(delay) {};
-        FIFO(uint8_t *buffer,int delay=0):mBuffer((T*)buffer),readPos(0),writePos(delay),nbSamples(delay) {};
-
-        /* 
-
-        Check for overflow must have been done
-        before using this function 
-        
-        */
-        T * getWriteBuffer(int nb) final
-        {
-            
-            T *ret;
-            if (readPos > 0)
-            {
-                memcpy((void*)mBuffer,(void*)(mBuffer+readPos),(writePos-readPos)*sizeof(T));
-                writePos -= readPos;
-                readPos = 0;
-            }
-            
-            ret = mBuffer + writePos;
-            writePos += nb; 
-            nbSamples += nb;
-            return(ret);
-        };
-
-        /* 
-        
-        Check for undeflow must have been done
-        before using this function 
-        
-        */
-        T* getReadBuffer(int nb) final
-        {
-           
-            T *ret = mBuffer + readPos;
-            readPos += nb;
-            nbSamples -= nb;
-            return(ret);
-        }
-
-        bool willUnderflowWith(int nb) const final
-        {
-            return((nbSamples - nb)<0);
-        }
-
-        bool willOverflowWith(int nb) const final
-        {
-            return((nbSamples + nb)>length);
-        }
-
-        int nbSamplesInFIFO() const final {return nbSamples;};
-
-        #ifdef DEBUGSCHED
-        void dump()
-        {
-            int nb=0;
-            std::cout << std::endl;
-            std::cout << "FIFO nb samples = " << nbSamples << std::endl;
-            for(int i=0; i < length ; i++)
-            {
-                std::cout << (typename Debug<T>::type)mBuffer[i] << " ";
-                nb++;
-                if (nb == 10)
-                {
-                    nb=0;
-                    std::cout << std::endl;
-                }
-            }
-            std::cout << std::endl;
-            std::cout << std::endl;
-        }
-        #endif
-
-    protected:
-        T *mBuffer;
-        int readPos,writePos;
-        int nbSamples;
-};
-
-// GENERIC NODES 
-
-class NodeBase
-{
-public:
-    virtual int run()=0;
-    virtual int prepareForRunning()=0;
-};
-
-template<typename IN, int inputSize,typename OUT, int outputSize>
-class GenericNode:public NodeBase
-{
-public:
-     GenericNode(FIFOBase<IN> &src,FIFOBase<OUT> &dst):mSrc(src),mDst(dst){};
-
-protected:
-     OUT * getWriteBuffer(int nb = outputSize){return mDst.getWriteBuffer(nb);};
-     IN * getReadBuffer(int nb = inputSize){return mSrc.getReadBuffer(nb);};
-
-     bool willOverflow(int nb = outputSize){return mDst.willOverflowWith(nb);};
-     bool willUnderflow(int nb = inputSize){return mSrc.willUnderflowWith(nb);};
-
-private:
-    FIFOBase<IN> &mSrc;
-    FIFOBase<OUT> &mDst;
-};
-
-template<typename IN, int inputSize,typename OUT1, int output1Size,typename OUT2, int output2Size>
-class GenericNode12:public NodeBase
-{
-public:
-     GenericNode12(FIFOBase<IN> &src,FIFOBase<OUT1> &dst1,FIFOBase<OUT2> &dst2):mSrc(src),
-     mDst1(dst1),mDst2(dst2){};
-
-protected:
-     OUT1 * getWriteBuffer1(int nb=output1Size){return mDst1.getWriteBuffer(nb);};
-     OUT2 * getWriteBuffer2(int nb=output2Size){return mDst2.getWriteBuffer(nb);};
-     IN * getReadBuffer(int nb=inputSize){return mSrc.getReadBuffer(nb);};
-
-     bool willOverflow1(int nb = output1Size){return mDst1.willOverflowWith(nb);};
-     bool willOverflow2(int nb = output2Size){return mDst2.willOverflowWith(nb);};
-
-     bool willUnderflow(int nb = inputSize){return mSrc.willUnderflowWith(nb);};
-
-private:
-    FIFOBase<IN> &mSrc;
-    FIFOBase<OUT1> &mDst1;
-    FIFOBase<OUT2> &mDst2;
-};
-
-template<typename IN,   int inputSize,
-         typename OUT1, int output1Size,
-         typename OUT2, int output2Size,
-         typename OUT3, int output3Size>
-class GenericNode13:public NodeBase
-{
-public:
-     GenericNode13(FIFOBase<IN> &src,
-                   FIFOBase<OUT1> &dst1,
-                   FIFOBase<OUT2> &dst2,
-                   FIFOBase<OUT3> &dst3
-                   ):mSrc(src),
-     mDst1(dst1),mDst2(dst2),mDst3(dst3){};
-
-protected:
-     OUT1 * getWriteBuffer1(int nb=output1Size){return mDst1.getWriteBuffer(nb);};
-     OUT2 * getWriteBuffer2(int nb=output2Size){return mDst2.getWriteBuffer(nb);};
-     OUT3 * getWriteBuffer3(int nb=output3Size){return mDst3.getWriteBuffer(nb);};
-
-     IN * getReadBuffer(int nb=inputSize){return mSrc.getReadBuffer(nb);};
-
-     bool willOverflow1(int nb = output1Size){return mDst1.willOverflowWith(nb);};
-     bool willOverflow2(int nb = output2Size){return mDst2.willOverflowWith(nb);};
-     bool willOverflow3(int nb = output3Size){return mDst3.willOverflowWith(nb);};
-
-     bool willUnderflow(int nb = inputSize){return mSrc.willUnderflowWith(nb);};
-
-private:
-    FIFOBase<IN> &mSrc;
-    FIFOBase<OUT1> &mDst1;
-    FIFOBase<OUT2> &mDst2;
-    FIFOBase<OUT3> &mDst3;
-
-};
-
-template<typename IN1, int input1Size,typename IN2, int input2Size,typename OUT, int outputSize>
-class GenericNode21:public NodeBase
-{
-public:
-     GenericNode21(FIFOBase<IN1> &src1,FIFOBase<IN2> &src2,FIFOBase<OUT> &dst):mSrc1(src1),
-     mSrc2(src2),
-     mDst(dst){};
-
-protected:
-     OUT * getWriteBuffer(int nb=outputSize){return mDst.getWriteBuffer(nb);};
-     IN1 * getReadBuffer1(int nb=input1Size){return mSrc1.getReadBuffer(nb);};
-     IN2 * getReadBuffer2(int nb=input2Size){return mSrc2.getReadBuffer(nb);};
-
-     bool willOverflow(int nb = outputSize){return mDst.willOverflowWith(nb);};
-     bool willUnderflow1(int nb = input1Size){return mSrc1.willUnderflowWith(nb);};
-     bool willUnderflow2(int nb = input2Size){return mSrc2.willUnderflowWith(nb);};
-
-private:
-    FIFOBase<IN1> &mSrc1;
-    FIFOBase<IN2> &mSrc2;
-    FIFOBase<OUT> &mDst;
-};
-
-
-
-template<typename OUT, int outputSize>
-class GenericSource:public NodeBase
-{
-public:
-     GenericSource(FIFOBase<OUT> &dst):mDst(dst){};
-
-protected:
-     OUT * getWriteBuffer(int nb=outputSize){return mDst.getWriteBuffer(nb);};
-
-     bool willOverflow(int nb = outputSize){return mDst.willOverflowWith(nb);};
-
-private:
-    FIFOBase<OUT> &mDst;
-};
-
-template<typename IN,int inputSize>
-class GenericSink:public NodeBase
-{
-public:
-     GenericSink(FIFOBase<IN> &src):mSrc(src){};
-
-protected:
-     IN * getReadBuffer(int nb=inputSize){return mSrc.getReadBuffer(nb);};
-
-     bool willUnderflow(int nb = inputSize){return mSrc.willUnderflowWith(nb);};
-
-private:
-    FIFOBase<IN> &mSrc;
-};
-
-
-#define REPEAT(N) for(int i=0;i<N;i++)
-
-
-template<typename IN, int inputSize,typename OUT1,int output1Size,typename OUT2,int output2Size>
-class Duplicate2;
-
-template<typename IN, int inputSize>
-class Duplicate2<IN,inputSize,IN,inputSize,IN,inputSize>: public GenericNode12<IN,inputSize,IN,inputSize,IN,inputSize>
-{
-public:
-    Duplicate2(FIFOBase<IN> &src,FIFOBase<IN> &dst1,FIFOBase<IN> &dst2):
-    GenericNode12<IN,inputSize,IN,inputSize,IN,inputSize>(src,dst1,dst2){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow() || 
-            this->willOverflow1() ||
-            this->willOverflow2())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final {
-        IN *a=this->getReadBuffer();
-        IN *b1=this->getWriteBuffer1();
-        IN *b2=this->getWriteBuffer2();
-        for(int i = 0; i<inputSize; i++)
-        {
-           b1[i] = a[i];
-           b2[i] = a[i];
-        }
-        return(0);
-    };
-
-};
-
-template<typename IN, int inputSize,
-         typename OUT1,int output1Size,
-         typename OUT2,int output2Size,
-         typename OUT3,int output3Size>
-class Duplicate3;
-
-template<typename IN, int inputSize>
-class Duplicate3<IN,inputSize,
-                 IN,inputSize,
-                 IN,inputSize,
-                 IN,inputSize>: 
-                 public GenericNode13<IN,inputSize,
-                                      IN,inputSize,
-                                      IN,inputSize,
-                                      IN,inputSize>
-{
-public:
-    Duplicate3(FIFOBase<IN> &src,
-               FIFOBase<IN> &dst1,
-               FIFOBase<IN> &dst2,
-               FIFOBase<IN> &dst3):
-    GenericNode13<IN,inputSize,
-                  IN,inputSize,
-                  IN,inputSize,
-                  IN,inputSize>(src,dst1,dst2,dst3){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow() || 
-            this->willOverflow1() ||
-            this->willOverflow2() ||
-            this->willOverflow3()
-            )
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final {
-        IN *a=this->getReadBuffer();
-        IN *b1=this->getWriteBuffer1();
-        IN *b2=this->getWriteBuffer2();
-        IN *b3=this->getWriteBuffer3();
-        for(int i = 0; i<inputSize; i++)
-        {
-           b1[i] = a[i];
-           b2[i] = a[i];
-           b3[i] = a[i];
-        }
-        return(0);
-    };
-
-};
-
-
-       
-
-#endif

ComputeGraph/cg/src/cg_status.h

@@ -1,44 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        cg_status.h
- * Description:  Error code for the Compute Graph
- *
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
- *
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _CG_STATUS_H_
-
-
- typedef enum
-  {
-    CG_SUCCESS                    =  0, /**< No error */
-    CG_BUFFER_UNDERFLOW           = -1, /**< FIFO underflow */
-    CG_BUFFER_OVERFLOW            = -2, /**< FIFO overflow */
-    CG_MEMORY_ALLOCATION_FAILURE  = -3, /**< Memory allocation failure */
-    CG_INIT_FAILURE               = -4, /**< Node initialization failure */
-    CG_SKIP_EXECUTION             = -5, /**< Skip node execution (asynchronous mode) */
-    CG_BUFFER_ERROR               = -6, /**< Stop execution due to FIFO overflow or underflow (asynchronous mode for pure function) */
-    CG_OS_ERROR                   = -7  /**< RTOS API error */
-  } cg_status;
-
-
-
-#endif /* _CG_STATUS_H_ */

ComputeGraph/documentation/CCodeGen.md

@@ -1,112 +0,0 @@
-# C++ Code generation
-
-## API
-
-```python
-def ccode(self,directory,config=Configuration())
-```
-
-It is a method of the `Schedule` object returned by `computeSchedule`.
-
-It generate C++ code implementing the static schedule.
-
-* `directory` : The directory where to generate the C++ files
-* `config` : An optional configuration object
-
-## Options for C Code Generation
-
-### cOptionalArgs (default = "")
-
-Optional arguments to pass to the C API of the scheduler function
-
-It can either use a `string` or a list of `string` where an element is an argument of the function (and should be valid `C`).
-
-For instance, with:
-
-```Python
-conf.cOptionalArgs=["int someVariable"]
-```
-
-The API of the generated scheduler function would be:
-
-```C++
-uint32_t scheduler(int *error,int someVariable)
-```
-
-### codeArray (default = True)
-
-When true, the scheduling is defined as an array. Otherwise, a list of function calls is generated.
-
-A list of function call may be easier to read but if the schedule is long, it is not good for code size. In that case, it is better to encode the schedule as an array rather than a list of functions.
-
-When `codeArray` is True, the option `switchCase`can also be used.
-
-### switchCase (default = True)
-
-`codeArray` must be true or this option is ignored.
-
-When the schedule is encoded as an array, it can either be an array of function pointers (`switchCase` false) or an array of indexes for a state machine (`switchCase` true)
-
-### eventRecorder (default = False)
-
-Enable the generation of `CMSIS EventRecorder` intrumentation in the code. The CMSIS-DSP Pack is providing definition of 3 events:
-
-* Schedule iteration
-* Node execution
-* Error
-
-### customCName (default = "custom.h")
-
-Name of custom header in generated C code. If you use several scheduler, you may want to use different headers for each one.
-
-### postCustomCName (default = "")
-
-Name of custom header in generated C code coming after all of the other includes.  By default none is used.
-
-### genericNodeCName (default = "GenericNodes.h")
-
-Name of GenericNodes header in generated C code. If you use several scheduler, you may want to use different headers for each one.
-
-### appNodesCName (default = "AppNodes.h")
-
-Name of AppNodes header in generated C code. If you use several scheduler, you may want to use different headers for each one.
-
-### schedulerCFileName (default = "scheduler")
-
-Name of scheduler `cpp` and header in generated C code. If you use several scheduler, you may want to use different headers for each one.
-
-If the option is set to `xxx`, the names generated will be `xxx.cpp` and `xxx.h`
-
-### CAPI (default = True)
-
-By default, the scheduler function is callable from C. When false, it is a standard C++ API.
-
-### CMSISDSP (default = True)
-
-If you don't use any of the datatypes or functions of the CMSIS-DSP, you don't need to include the `arm_math.h` in the scheduler file. This option can thus be set to `False`.
-
-### asynchronous (default = False)
-
-When true, the scheduling is for a dynamic / asynchronous flow. A node may not always produce or consume the same amount of data. As consequence, a scheduling can fail. Each node needs to implement a `prepareForRunning` function to identify and recover from FIFO underflows and overflows.
-
-A synchronous schedule is used as start and should describe the average case.
-
-This implies `codeArray` and `switchCase`. This disables `memoryOptimizations`.
-
-Synchronous FIFOs that are just buffers will be considered as FIFOs in asynchronous mode.
-
-More info are available in the documentation for [this mode](../Async.md).
-
-### FIFOIncrease (default 0)
-
-In case of dynamic / asynchronous scheduling, the FIFOs may need to be bigger than what is computed assuming a static / synchronous scheduling. This option is used to increase the FIFO size. It represents a percent increase.
-
-For instance, a value of `10` means the FIFO will have their size updated from `oldSize` to `1.1 * oldSize` which is ` (1 + 10%)* oldSize`
-
-If the value is a `float` instead of an `int` it will be used as is. For instance, `1.1` would increase the size by `1.1` and be equivalent to the setting `10` (for 10 percent).
-
-### asyncDefaultSkip (default True)
-
-Behavior of a pure function (like CMSIS-DSP) in asynchronous mode. When `True`, the execution is skipped if the function can't be executed. If `False`, an error is raised.
-
-If another error recovery is needed, the function must be packaged into a C++ class to implement a `prepareForRun` function.

ComputeGraph/documentation/CPPNodes.md

@@ -1,455 +0,0 @@
-# CPP Nodes and classes
-
-## Mandatory classes
-
-Those classes are defined in `GenericNodes.h` a header that is always included by the scheduler.
-
-As consequence, the definition for those classes is always included.
-
-### FIFO
-
-FIFO classes are inheriting from the virtual class `FIFOBase`:
-
-```C++
-template<typename T>
-class FIFOBase{
-public:
-    virtual T* getWriteBuffer(int nb)=0;
-    virtual T* getReadBuffer(int nb)=0;
-    virtual bool willUnderflowWith(int nb) const = 0;
-    virtual bool willOverflowWith(int nb) const = 0;
-    virtual int nbSamplesInFIFO() const = 0;
-
-};
-```
-
-The functions `willUnderflowWith`, `willOverflowWith` and `nbSamplesInFIFO` are only used in asynchronous mode.
-
-If you implement a FIFO for synchronous mode you only need to implement `getWriteBuffer` and `getReadBuffer`.
-
-FIFO must be templates with a type defined as:
-
-```C++
-template<typename T, int length, int isArray=0, int isAsync = 0>
-class FIFO;
-```
-
-* `T` is a C datatype that must have value semantic : standard C type like `float` or `struct`
-* `length` is the length of the FIFO in **samples**
-* `isArray` is set to 1 when the scheduler has identified that the FIFO is always used as a buffer. So it is possible to provide a more optimized implementation for this case
-* `isAsync` is set to 1 for the asynchronous mode
-
-If you implement you own FIFO class, it should come from a template with the same arguments. For instance:
-
-```C++
-template<typename T, int length, int isArray=0, int isAsync = 0>
-class MyCustomFIFO;
-```
-
-and it should inherit from `FIFOBase<T>`.
-
-`GenericNodes.h` is providing 3 default implementations. Their are specialization of the FIFO template:
-
-#### FIFO for synchronous mode
-
-```C++
-template<typename T, int length>
-class FIFO<T,length,0,0>: public FIFOBase<T> 
-```
-
-#### Buffer for synchronous mode
-
-In some case a FIFO is just used as a buffer. An optimized implementation for this case is provided
-
-```C++
-template<typename T, int length>
-class FIFO<T,length,1,0>: public FIFOBase<T> 
-```
-
-In this mode, the FIFO implementation is very light. For instance, for `getWriteBuffer` we have:
-
-```C++
-T * getWriteBuffer(int nb) const final
-{
-    return(mBuffer);
-};
-```
-
-#### FIFO for asynchronous mode
-
-```C++
-template<typename T, int length>
-class FIFO<T,length,0,1>: public FIFOBase<T> 
-```
-
-This implementation is a bit more heavy and is providing implementations of following function :
-
-```C++
-bool willUnderflowWith(int nb) const;
-bool willOverflowWith(int nb) const;
-int nbSamplesInFIFO() const;
-```
-
-### Nodes
-
-All nodes are inheriting from the virtual class `NodeBase`:
-
-```C++
-class NodeBase
-{
-public:
-    virtual int run()=0;
-    virtual int prepareForRunning()=0;
-};
-```
-
-`GenericNode`, `GenericSource` and `GenericSink` are providing accesses to the FIFOs for each IO. The goal of those wrappers is to define the IOs (number of IO, their type and length) and hide the API to the FIFOs.
-
-There are different versions depending on the number of inputs and/or output. Other nodes of that kind can be created by the user if different IO configurations are required:
-
-#### GenericNode
-
-The template is:
-
-```C++
-template<typename IN,  int inputSize,
-         typename OUT, int outputSize>
-class GenericNode:public NodeBase
-```
-
-There is one input and one output.
-
-The constructor is:
-
-```C++
-GenericNode(FIFOBase<IN> &src,FIFOBase<OUT> &dst);
-```
-
-It is taking the input and output FIFOs as argument. The real type of the FIFO is hidden since the type `FIFOBase` is used. So `GenericNode` can be used with any FIFO implementation.
-
-The main role of this `GenericNode` class is to provide functions to connect to the FIFOs.
-
-The functions to access the FIFO buffers are:
-
-```C++
-OUT * getWriteBuffer(int nb = outputSize);
-IN * getReadBuffer(int nb = inputSize);
-```
-
-`getWriteBuffer` is getting a pointer to a buffer of length `nb` to write the output samples.
-
-`getReadBuffer` is getting a pointer to a buffer of length `nb` to read the input samples.
-
-`nb` must be chosen so that there is no underflow / overflow. In synchronous mode, it will work by design if the length defined in the template argument is used.  The template length is thus chosen as default value for `nb`.
-
-This value may be changed in cyclo-static or asynchronous mode. In asynchronous mode, additional functions are provided to test for a possibility of underflow / overflow **before** getting a pointer to the buffer.
-
-It is done with following function that are also provided by `GenericNode`:
-
-```C++
-bool willOverflow(int nb = outputSize);
-bool willUnderflow(int nb = inputSize);
-```
-
-All of those functions introduced by `GenericNode` are doing nothing more than calling the underlying FIFO methods. But they hide those FIFOs from the user code. The FIFO can only be accessed through those APIs.
-
-#### GenericNode12
-
-Same as `GenericNode` but with two outputs.
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT1, int output1Size
-         typename OUT2, int output2Size>
-class GenericNode12:public NodeBase
-```
-
-It provides:
-
-```C++
-IN * getReadBuffer(int nb=inputSize);
-OUT1 * getWriteBuffer1(int nb=output1Size);
-OUT2 * getWriteBuffer2(int nb=output2Size);
-
-bool willUnderflow(int nb = inputSize);
-bool willOverflow1(int nb = output1Size);
-bool willOverflow2(int nb = output2Size);
-```
-
-#### GenericNode13
-
-Same but with 3 outputs.
-
-#### GenericNode21
-
-Same but with 2 inputs and 1 output.
-
-#### GenericSource
-
-Similar to a `GenericNode` but there is no inputs.
-
-#### GenericSink
-
-Similar to a `GenericNode` but there is no outputs.
-
-#### Duplicate2
-
-This node is duplicating its input to 2 outputs.
-
-The template is:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT1,int output1Size,
-         typename OUT2,int output2Size>
-class Duplicate2;
-```
-
-Only one specialization of this template makes sense : the output must have same type and same length as the input. 
-
-```C++
-template<typename IN, int inputSize>
-class Duplicate2<IN,inputSize,
-                 IN,inputSize,
-                 IN,inputSize> : 
-public GenericNode12<IN,inputSize,
-                     IN,inputSize,
-                     IN,inputSize>
-```
-
-
-
-#### Duplicate3
-
-Similar to `Duplicate2` but with 3 outputs.
-
-## Optional nodes
-
-Those nodes are not included by default. They can be found in `ComputeGraph/cg/nodes/cpp`
-
-To use any of them you just need to include the header (for instance in your `AppNodes.h` file):
-
-```C++
-#include "CFFT.h"
-```
-
-### CFFT / CIFFT
-
-Those nodes are for using the CMSIS-DSP FFT.
-
-Template:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class CFFT;
-```
-
-Specialization provided only for `float32_t`, `float16_t`,`q15_t`.
-
-The wrapper is copying the input buffer before doing the FFT (since CMSIS-DSP FFT is modifying the input buffer). It is normally possible to modify the input buffer even if it is in the input FIFO.
-
-This implementation has made the choice of not touching the input FIFO with the cost of an additional copy.
-
-Other data types can be easily added based on the current provided example. The user can just implement other specializations.
-
-`CIFFT` is defined with class `CIFFT`.
-
-### InterleavedStereoToMono
-
-Deinterleave a stream of stereo samples to **one** stream of mono samples.
-
-Template:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class InterleavedStereoToMono;
-```
-
-For specialization `q15_t` and `q31_t`, the inputs are divided by 2 before being added to avoid any overflow.
-
-For specialization `float32_t` : The output is multiplied by `0.5f` for consistency with the fixed point version.
-
-### MFCC
-
-Those nodes are for using the CMSIS-DSP MFCC.
-
-Template:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class MFCC;
-```
-
-Specializations provided for `float32_t`, `float16_t`, `q31_t` and `q15_t`.
-
-The MFCC is requiring a temporary buffer. The wrappers are thus allocating a memory buffer during initialization of the node.
-
-The buffer is allocated as a C++ vector. See the documentation of the MFCC in CMSIS-DSP to know more about the size of this buffer.
-
-### NullSink
-
-Template:
-
-```C++
-template<typename IN, int inputSize>
-class NullSink: public GenericSink<IN, inputSize>
-```
-
-It is useful for development and debug. This node is doing nothing and just consuming its input.
-
-### OverlapAndAdd
-
-Template:
-
-```c++
-template<typename IN,int windowSize, int overlap>
-class OverlapAdd: public GenericNode<IN,windowSize,IN,windowSize-overlap>
-```
-
-There are two sizes in the template arguments : `windowSize` and `overlap`.
-
-From those size, the template is computing the number of samples consumed and produced by the node.
-
-The implementation is generic but will only build for a type `IN` having an addition operator.
-
-This node is using a little memory (C++ vector) of size `overlap` that is allocated during creation of the node.
-
-This node will overlap input data by `overlap` samples and sum the common overlapping samples.
-
-### SlidingBuffer
-
-Template:
-
-```C++
-template<typename IN,int windowSize, int overlap>
-class SlidingBuffer: public GenericNode<IN,windowSize-overlap,IN,windowSize>
-
-```
-
-There are two sizes in the template arguments :  `windowSize` and `overlap`.
-
-For those size, the template is computing the number of samples consumed and produced by the node.
-
-The implementation is generic and will work with all types.
-
-This node is using a little memory (C++ vector) of size `overlap` allocated during creation of the node.
-
-This node is moving a window on the input data with an overlap. The output data is the content of the window.
-
-Note that this node is not doing any multiplication with window functions that can be found in signal processing literature. This multiplication has to be implemented in the compute graph in a separate node.
-
-### ToComplex
-
-Template:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT,int outputSize>
-class ToComplex;
-```
-
-Convert a stream of reals a b c d ... to complexes a 0 b 0 c 0 d 0 ...
-
-The implementation is generic and does not enforce the required size constraints.
-
-### ToReal
-
-Template:
-
-```C++
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ToReal;
-```
-
-Convert a stream of complex a 0 b 0 c 0 ... to reals a b c ...
-
-The implementation is generic and does not enforce the required size constraints.
-
-### Unzip
-
-Template:
-
-```C++
-template<typename IN, int inputSize,
-         typename OUT1,int output1Size,
-         typename OUT2,int output2Size>
-class Unzip;
-```
-
-Unzip a stream a1 a2 b1 b2 c1 c2 ...
-
-Into 2 streams:
-a1 b1 c1 ...
-a2 b2 c2 ...
-
-The implementation is generic and does not enforce the required size constraints.
-
-### Zip
-
-Template:
-
-```C++
-template<typename IN1, int inputSize1,
-         typename IN2,int inputSize2,
-         typename OUT,int outputSize>
-class Zip;
-```
-
-Transform two input streams:
-
-a1 b1 c1 ...
-
-a2 b2 c2 ...
-
-into one output stream:
-
-a1 a2 b1 b2 c1 c2 ...
-
-The implementation is generic and does not enforce the required size constraints
-
-### Host
-
-Those nodes are for host (Windows, Linux, Mac). They can be useful to experiment with a compute graph.
-
-By default there is no nodes to read / write `.wav` files but you can  easily add some if needed (`dr_wav.h` is a simple way to add `.wav` reading / writing and is freely available from the web).
-
-#### FileSink
-
-Template
-
-```C++
-template<typename IN, int inputSize>
-class FileSink: public GenericSink<IN, inputSize>
-```
-
-Write the input samples to a file. The implementation is generic and use iostream for writing the datatype.
-
-The constructor has an additional argument : the name/path of the output file:
-
-```C++
-FileSink(FIFOBase<IN> &src, std::string name)
-```
-
-#### FileSource
-
-Template:
-
-```C++
-template<typename OUT,int outputSize> class FileSource;
-```
-
-There is only one specialization for the `float32_t` type.
-
-It is reading text file with one float per line and generating a stream of float.
-
-At the end of file, 0.0f  are generated on the output indefinitely.
-
-The constructor has an additional argument : the name/path of the input file:
-
-```C++
-FileSource(FIFOBase<float32_t> &dst,std::string name)
-```
-

ComputeGraph/documentation/CodegenOptions.md

@@ -1,29 +0,0 @@
-# Common options for the code generators
-
-Global options for the code generators. There are specific options for the C, Python and Graphviz generators. They are described in different part of the documentation.
-
-## debugLimit (default = 0)
-
-When `debugLimit` is > 0, the number of iterations of the scheduling is limited to  `debugLimit`. Otherwise, the scheduling is running forever or until an error has occured.
-
-## dumpFIFO (default = False)
-
-When true, generate some code to dump the FIFO content at **runtime**. Only useful for debug.
-
-In C++ code generation, it is only available when using the mode `codeArray == False`.
-
-When this mode is enabled, the first line of the scheduler file is :
-
-`#define DEBUGSCHED 1`
-
-and it also enable some debug code in `GenericNodes.h`
-
-## schedName (default = "scheduler")
-
-Name of the scheduler function used in the generated code.
-
-## prefix (default = "")
-
-Prefix to add before the FIFO buffer definitions. Those buffers are not static and are global. If you want to use several schedulers in your code, the buffer names used by each should be different.
-
-Another possibility would be to make the buffer static by redefining the macro `CG_BEFORE_BUFFER`

ComputeGraph/documentation/Generic.md

@@ -1,155 +0,0 @@
-# Description of the nodes
-
-The generic and function nodes are the basic nodes that you use to create other kind of nodes in the graph.
-
-There are 3 generic classes provided by the framework to be used to create new nodes.
-
-To create a new kind of node, you inherit from one of those classes:
-
-* `GenericSource`
-* `GenericNode`
-* `GenericSink`
-
-They are defined in `cmsisdsp.cg.scheduler`.
-
-There are 3 other classes that can be used to create new nodes from functions. A function has no state and a C++ wrapper is not required. In this case, the tool is generating code for calling the function directly rather than using a C++ wrapper.
-
-* `Unary` (unary operators like `negate`, `inverse` ...)
-* `Binary` (binary operators like `add`, `mul` ...)
-* `Dsp` (Some CMSIS-DSP function either binary or unary)
-
-# Generic Nodes
-
-When you define a new kind of node, it must inherit from one of those classes. Those classes are providing the methods `addInput` and/or `addOutput` to define new inputs / outputs.
-
-A new kind of node is generally defined as:
-
-```python
-class ProcessingNode(GenericNode):
-    def __init__(self,name,theType,inLength,outLength):
-        GenericNode.__init__(self,name)
-        self.addInput("i",theType,inLength)
-        self.addOutput("o",theType,outLength)
-
-    @property
-    def typeName(self):
-        return "ProcessingNode"
-```
-
-The method `typeName` from the parent class must be overridden and provide the name of the `C++` wrapper to be used for this node.
-
-The object constructor is defining the inputs / outputs : number of samples and datatype.
-
-The object constructor is also defining the name used to identity this node in the generated code (so it must be a valid C variable name).
-
-`GenericSink` is only providing the `addInput` function.
-
-`GenericSource` is only providing the `addOutput` function
-
-`GenericNode` is providing both.
-
-You can use each function as much as you want to create several inputs and / or several outputs for a node.
-
-See the [simple](../examples/simple/README.md) example for more explanation about how to define a new node.
-
-## Methods
-
-The constructor of the node is using the `addInput` and/or `addOutput` to define new IOs.
-
-```python
-def addInput(self,name,theType,theLength):
-```
-
-* `name` is the name of the input. It will becomes a property of the Python object so it must not conflict with existing properties. If `name` is, for instance, `"i"` then it can be accessed with `node.i` in the code
-* `theType` is the datatype of the IO. It must inherit from `CGStaticType` (see below for more details about defining the types)
-* `theLength` is the amount of **samples** consumed by this IO at each execution of the node
-
-```python
-def addOutput(self,name,theType,theLength):
-```
-
-* `name` is the name of the output. It will becomes a property of the Python object so it must not conflict with existing properties. If `name` is, for instance, `"o"` then it can be accessed with `node.o` in the code
-* `theType` is the datatype of the IO. It must inherit from `CGStaticType` (see below for more details about defining the types)
-* `theLength` is the amount of **samples** produced by this IO at each execution of the node
-
-```python
-@property
-def typeName(self):
-    return "ProcessingNode"
-```
-
-This method defines the name of the C++ class implementing the wrapper for this node.
-
-# Datatypes
-
-Datatypes for the IOs are inheriting from `CGStaticType`.
-
-Currently there are 3 classes defined in the project:
-
-* `CType` for the standard CMSIS-DSP types like `q15_t`, `float32_t` ...
-* `CStructType` for a C struct
-* `PythonClassType` to create structured datatype for the Python scheduler
-
-## CType
-
-You create such a type with `CType(id)` where `id` is one of the constant coming from the Python wrapper:
-
-* F64
-* F32
-* F16
-* Q31
-* Q15
-* Q7
-* UINT32
-* UINT16
-* UINT8
-* SINT32
-* SINT16
-* SINT8
-
-For instance, to define a `float32_t` type for an IO you can use `CType(F32)`
-
-## CStructType
-
-The constructor has the following definition
-
-```python
-def __init__(self,name,size_in_bytes): 
-```
-
-* `name` is the name of the C struct
-* `size_in_bytes` is the size of the C struct. It should take into account padding. It is used when the compute graph memory optimization is used since size of the datatype is needed. 
-
-## PythonClassType
-
-```python
-def __init__(self,python_name)
-```
-
-In Python, there is no `struct`. This datatype is mapped to an object. Object have reference type. Compute graph FIFOs are assuming a value type semantic.
-
-As consequence, in Python side you should never copy those structs since it would copy the reference. You should instead copy the members of the struct and they should be scalar values.
-
-# Function and constant nodes
-
-A Compute graph C++ wrapper is useful when the software components you use have a state that needs to be initialized in the C++ constructor, and preserved between successive calls to the `run` method of the wrapper.
-
-Most CMSIS-DSP functions have no state. The compute graph framework is providing some ways to easily use functions in the graph without having to write a wrapper.
-
-This feature is relying on the nodes:
-
-* `Unary`
-  * To use an unary operator like `negate`, `inverse` ...
-
-* `Binary`
-  * To use a binary operator like `add`, `mul` ...
-
-* `Dsp`
-  * Should detect if the CMSIS-DSP operator is unary or binary and use the datatype to compute the name of the function. In practice, only a subset of CMSIS-DSP function is supported so you should use `Unary` or `Binary` nodes
-
-* `Constant`
-  * Special node to be used **only** with function nodes when some arguments cannot be connected to a FIFO. For instance, with `arm_scale_f32` the scaling factor is a scalar value and a FIFO cannot be connected to this argument. The function is a binary operator but between a stream and a scalar.
-
-
-All of this is explained in detail in the [simple example with CMSIS-DSP](../examples/simpledsp/README.md).
-

ComputeGraph/documentation/Graph.md

@@ -1,62 +0,0 @@
-# Adding nodes to the graph
-
-## Creating a connection
-
-Those methods must be applied to a graph object created with `Graph()`. The `Graph` class is defined inside `cmsisdsp.cg.scheduler` from the CMSIS-DSP Python wrapper.
-
-```python
-def connect(self,input_io,output_io,fifoClass=None,fifoScale = 1.0):
-```
-
-Typically this method is used as:
-
-```python
-the_graph = Graph()
-
-# Connect the source output to the processing node input and add this directed
-# edge to the object the_graph
-the_graph.connect(src.o,processing.i)
-```
-
-There are two optional arguments for the `connect` function:
-
-* `fifoClass` : To use a different C++ class for implementing the connection between the two IOs. (it is also possible to change the FIFO class globally by setting an option on the graph. See below). The `FIFO` class is provided by default. Any new implementation must inherit from `FIFObase<T>`
-* `fifoScale` : In asynchronous mode, it is a scaling factor to increase the length of the FIFO compared to what has been computed by the synchronous approximation. This setting can also be set globally using the scheduler options. `fifoScale` is overriding the global setting. It must be a `float` (not an `int`).
-
-```python
-def connectWithDelay(self,input_io,output_io,delay,fifoClass=None,fifoScale=1.0):  
-```
-
-The only difference with the previous function is the `delay` argument. It could be used like:
-
-```python
-the_graph.connect(src.o,processing.i, 10)
-```
-
-The `delay` is the number of samples contained in the FIFO at start (initialized to zero). The FIFO length (computed by the scheduling) is generally bigger by this amount of sample. The result is that it is delaying the output by `delay` samples.
-
-It is generally useful when the graph has some loops to make it schedulable.
-
-## Options for the graph
-
-Those options needs to be used on the graph object created with `Graph()`.
-
-For instance :
-
-```python
-g = Graph()
-g.defaultFIFOClass = "FIFO"
-```
-
-### defaultFIFOClass (default = "FIFO")
-
-Class used for FIFO by default. Can also be customized for each connection (`connect` of `connectWithDelay` call).
-
-### duplicateNodeClassName(default="Duplicate")
-
-Prefix used to generate the duplicate node classes like `Duplicate2`, `Duplicate3` ...
-
-Those nodes are inserted automatically to implement one-to-many connections.
-
-If you need to connect an output to more than 3 nodes, you'll have to create the `Duplicate` nodes.
-

ComputeGraph/documentation/GraphvizGen.md

@@ -1,24 +0,0 @@
-
-
-# Graphviz generation
-
-## API
-
-```python
-def graphviz(self,f,config=Configuration())
-```
-
-It is a method of the `Schedule` object returned by `computeSchedule`.
-
-* `f` : Opened file where to write the graphviz description
-* `config` : An optional configuration object
-
-## Options for the graphviz generator
-
-### horizontal (default = True)
-
-Horizontal or vertical layout for the graph.
-
-### displayFIFOBuf (default = False)
-
-By default, the graph is displaying the FIFO sizes computed as result of the scheduling. If you want to know the FIFO variable names used in the code, you can set this option to true and the graph will display the FIFO variable names.

ComputeGraph/documentation/Memory.md

@@ -1,79 +0,0 @@
-# Memory optimizations
-
-## Buffers
-
-Sometimes, a FIFO is in fact a buffer. In below graph, the source is writing 5 samples and the sink is reading 5 samples.
-
-![buffer](buffer.png)
-
-The scheduling will obviously be something like:
-
-`Source, Sink, Source, Sink ...`
-
-In this case, the FIFO is used as a simple buffer. The read and the write are always taking place from the start of the buffer.
-
-The schedule generator will detect FIFOs that are used as buffer and the FIFO implementation will be replaced by buffers : the third argument of the template (`isArray`) is set to one:
-
-```C++
-FIFO<float32_t,FIFOSIZE0,1,0> fifo0(buf1);
-```
-
-## Buffer sharing
-
-When several FIFOs are used as buffers then it may be possible to share the underlying memory for all of those buffers. This optimization is enabled by setting `memoryOptimization` to `true` in the configuration object:
-
-```python
-conf.memoryOptimization=True
-```
-
-The optimization depends on how the graph has been scheduled.
-
-With the following graph there is a possibility for buffer sharing:
-
-![memory](memory.png)
-
-Without `memoryOptimization`, the FIFO are consuming 60 bytes (4*5 * 3 FIFOs). With `memoryOptimization`, only 40 bytes are needed.
-
-You cannot share memory for the input / output of a node since a node needs both to read and write for its execution. This imposes some constraints on the graph.
-
-The constraints are internally represented by a different graph that represents when buffers are live at the same time : the interference graph. The input / output buffers of a node are live at the same time. Graph coloring is used to identify, from this graph of interferences, when memory for buffers can be shared. 
-
-The interference graph is highly depend on how the compute graph is scheduled : a buffer is live when a write has taken place but no read has yet read the full content.
-
-For the above compute graph and its computed schedule, the interference graph would be:
-
-![inter](inter.png)
-
-
-
-Adjacent vertices in the graph should use different colors. A coloring of this graph is equivalent to assigning memory areas. Graph coloring of the previous interference graph is giving the following buffer sharing:
-
-![fifos](fifos.png)
-
-The dimension of the buffer is the maximum for all the edges using this buffers.
-
-In the C++ code it is represented as:
-
-```C++
-#define BUFFERSIZE0 20
-CG_BEFORE_BUFFER
-uint8_t buf0[BUFFERSIZE0]={0};
-```
-
-`uint8_t` is used (instead of the `float32_t` of this example) because different edges of the graph may use different datatypes.
-
-It is really important that you use the macro `CG_BEFORE_BUFFER` to align this buffer so that the alignment is coherent with the datatype used on all the FIFOs.
-
-### Shared buffer sizing
-
-Let's look at a more complex example to see how the size of the shared buffer is computed:
-
-![shared_complex](shared_complex.png)
-
-The source is generating 10 samples instead of 5. The FIFOs are using 80 bytes without buffer sharing.
-
-With buffer sharing, 60 bytes are used. The buffer sharing is:
-
-![shared_complex_buffer](shared_complex_buffer.png)
-
-Buffer 1 is used by first and last edge in the graph. The dimension of this buffer is 40 bytes : big enough to be usable by edge 0 and edge 3 in the graph.

ComputeGraph/documentation/PythonAPI.md

@@ -1,34 +0,0 @@
-# Python API 
-
-When you describe a graph and generate a scheduler there are 4 mandatory steps and one optional one:
-
-* Describing the nodes
-* Adding the nodes to the graph
-* Computing the schedule
-* Generating the C++ and/or Python scheduler implementation
-* Optional : Generating a graphviz `.dot` file with the graphical representation of the graph
-
-1. ## [Description of the nodes](Generic.md)
-
-2. ## [Adding nodes to the graph](Graph.md)
-
-3. ## [Schedule computation](SchedOptions.md)
-
-4. ## Code generation
-
-   1. #### [C++ Code generation](CCodeGen.md)
-
-   2. #### [Python code generation](PythonGen.md)
-
-   3. #### [Graphviz representation](GraphvizGen.md)
-
-   4. #### [Common options](CodegenOptions.md)
-
-
-
-
-
-
-
-
-

ComputeGraph/documentation/PythonGen.md

@@ -1,34 +0,0 @@
-# Python code generation
-
-## API
-
-```python
-def pythoncode(self,directory,config=Configuration())
-```
-
-It is a method of the `Schedule` object returned by `computeSchedule`.
-
-It generate Python code to implement the static schedule.
-
-* `directory` : The directory where to generate the C++ files
-* `config` : An optional configuration object
-
-## Options for Python code generation
-
-### pyOptionalArgs (default = "")
-
-Optional arguments to pass to the Python version of the scheduler function
-
-### customPythonName (default = "custom")
-
-Name of custom header in generated Python code. If you use several scheduler, you may want to use different headers for each one.
-
-### appNodesPythonName (default = "appnodes")
-
-Name of AppNodes header in generated Python code. If you use several scheduler, you may want to use different headers for each one.
-
-### schedulerPythonFileName (default = "sched")
-
-Name of scheduler file in generated Python code. If you use several scheduler, you may want to use different headers for each one.
-
-If the option is set to `xxx`, the name generated will be `xxx.py`

ComputeGraph/documentation/PythonNodes.md

@@ -1,69 +0,0 @@
-# Python Nodes and classes
-
-Python implementation of the nodes to be run from a Python scheduler.
-
-You don't need this if you're only working with C++ schedulers.
-
-(DOCUMENTATION TO BE WRITTEN)
-
-## Mandatory classes
-
-FIFO
-
-GenericNode
-
-GenericNode12
-
-GenericNode13
-
-GenericNode21
-
-GenericSource
-
-GenericSink
-
-OverlapAdd
-
-SlidingBuffer
-
-## Optional nodes
-
-CFFT
-
-CIFFT
-
-InterleavedStereoToMono
-
-MFCC
-
-NullSink
-
-ToComplex
-
-ToReal
-
-Unzip
-
-Zip
-
-Duplicate
-
-Duplicate2
-
-Duplicate3
-
-### Host
-
-FileSink
-
-FileSource
-
-WavSource
-
-WavSink 
-
-NumpySink
-
-VHTSource
-
-VHTSink

ComputeGraph/documentation/SchedOptions.md

@@ -1,49 +0,0 @@
-# Schedule computation
-
-## API
-
-```python
-def computeSchedule(self,config=Configuration()):
-```
-
-This is a method on the `Graph` object. It can take an optional `Configuration` object.
-
-It returns a `Schedule` object. This object contains:
-
-* A description of the static schedule
-* The computed size of the FIFOs
-* The FIFOs
-* The buffers for the FIFOs (with sharing when possible if memory optimizations were enabled)
-* A rewritten graph with `Duplicate` nodes inserted
-
-## Options for the scheduling
-
-Those options needs to be used on a configuration objects passed as argument of the scheduling function. For instance:
-
-```python
-conf = Configuration()
-conf.debugLimit = 10
-sched = g.computeSchedule(config = conf)
-```
-
-Note that the configuration object also contain options for the code generators. They are described in different part of the documentation.
-
-### memoryOptimization (default = False)
-
-When the amount of data written to a FIFO and read from the FIFO is the same, the FIFO is just an array. In this case, depending on the scheduling, the memory used by different arrays may be reused if those arrays are not needed at the same time.
-
-This option is enabling an analysis to optimize the memory usage by merging some buffers when it is possible.
-
-### sinkPriority (default = True)
-
-Try to prioritize the scheduling of the sinks to minimize the latency between sources and sinks.
-
-When  this option is enabled, the tool may not be able to find a schedule in all cases. If it can't find a schedule, it will raise a `DeadLock` exception.
-
-### displayFIFOSizes (default = False)
-
-During computation of the schedule, the evolution of the FIFO sizes is generated on `stdout`.
-
-### dumpSchedule (default = False)
-
-During computation of the schedule, the human readable schedule is generated on `stdout`.

ComputeGraph/examples/CMakeLists.txt

@@ -1,82 +0,0 @@
-cmake_minimum_required (VERSION 3.21)
-include(CMakePrintHelpers)
-
-set(Python_FIND_REGISTRY "LAST")
-
-find_package (Python COMPONENTS Interpreter)
-
-function(sdf TARGET SCRIPT DOTNAME)
-    if (DOT)
-    add_custom_command(TARGET ${TARGET} PRE_BUILD 
-        BYPRODUCTS ${CMAKE_CURRENT_SOURCE_DIR}/${DOTNAME}.pdf
-        COMMAND ${DOT} -Tpdf -o ${CMAKE_CURRENT_SOURCE_DIR}/${DOTNAME}.pdf ${CMAKE_CURRENT_SOURCE_DIR}/${DOTNAME}.dot
-        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
-        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/${DOTNAME}.dot
-        VERBATIM
-        )
-    endif()
-
-    add_custom_command(OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/generated/scheduler.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/${DOTNAME}.dot
-        COMMAND ${Python_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/${SCRIPT}
-        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
-        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/${SCRIPT}
-        VERBATIM
-        )
-    target_sources(${TARGET} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/generated/scheduler.cpp)
-endfunction()
-
-function(sdfpython TARGET)
-    if (DOT)
-    add_custom_command(TARGET ${TARGET} PRE_BUILD 
-        BYPRODUCTS ${CMAKE_CURRENT_SOURCE_DIR}/test.pdf
-        COMMAND ${DOT} -Tpdf -o ${CMAKE_CURRENT_SOURCE_DIR}/test.pdf ${CMAKE_CURRENT_SOURCE_DIR}/test.dot
-        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
-        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/test.dot
-        VERBATIM
-        )
-    endif()
-
-    add_custom_command(OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/sched.py
-        ${CMAKE_CURRENT_SOURCE_DIR}/test.dot
-        COMMAND ${Python_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/graph.py
-        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
-        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/graph.py
-        VERBATIM
-        )
-endfunction()
-
-set(CGDIR ${CMAKE_CURRENT_SOURCE_DIR}/../cg)
-
-set(DSP ${CMAKE_CURRENT_SOURCE_DIR}/../..)
-
-function(add_sdf_dir TARGET)
-    target_include_directories(${TARGET} PRIVATE ${CGDIR}/src)
-    target_include_directories(${TARGET} PRIVATE ${CGDIR}/nodes/cpp)
-    target_include_directories(${TARGET} PRIVATE ${CMSISCORE})
-    target_include_directories(${TARGET} PRIVATE ${DSP}/Include)
-endfunction()
-
-project(Examples)
-
-# Add DSP folder to module path
-list(APPEND CMAKE_MODULE_PATH ${DSP})
-
-add_subdirectory(${DSP}/Source bin_dsp)
-
-
-add_subdirectory(example1 bin_example1)
-add_subdirectory(example2 bin_example2)
-add_subdirectory(example3 bin_example3)
-add_subdirectory(example6 bin_example6)
-add_subdirectory(example8 bin_example8)
-add_subdirectory(example9 bin_example9)
-add_subdirectory(example10 bin_example10)
-add_subdirectory(simple bin_simple)
-add_subdirectory(simpledsp bin_simpledsp)
-add_subdirectory(cyclo bin_cyclo)
-
-# Python examples
-add_subdirectory(example4 bin_example4)
-add_subdirectory(example5 bin_example5)
-add_subdirectory(example7 bin_example7)

ComputeGraph/examples/README.md

@@ -1,65 +0,0 @@
-## How to build the examples
-
-First, you must install the `CMSIS-DSP` PythonWrapper:
-
-```
-pip install cmsisdsp
-```
-
-The functions and classes inside the cmsisdsp wrapper can be used to describe and generate the schedule.
-
-You need a recent Graphviz dot tool supporting the HTML-like labels. You'll need `cmake` and `make`
-
-In folder `ComputeGraph/example/build`, type the `cmake` command:
-
-```bash
-cmake -DHOST=YES \
-   -DDOT="path to dot.EXE" \
-   -DCMSISCORE="path to cmsis core include directory" \
-   -G "Unix Makefiles" ..
-```
-
-The core include directory is something like `CMSIS_5/Core` ...
-
-If cmake is successful, you can type `make` to build the examples. It will also build CMSIS-DSP for the host.
-
-If you don't have graphviz, the option -DDOT can be removed.
-
-If for some reason it does not work, you can go into an example folder (for instance example1), and type the commands:
-
-```bash
-python graph.py 
-dot -Tpdf -o test.pdf test.dot
-```
-
-It will generate the C++ files for the schedule and a pdf representation of the graph.
-
-Note that the Python code is relying on the CMSIS-DSP PythonWrapper which is now also containing the Python scripts for the Synchronous Data Flow.
-
-For `example3` which is using an input file, `cmake` should have copied the input test pattern `input_example3.txt` inside the build folder. The output file will also be generated in the build folder.
-
-`example4` is like `example3` but in pure Python and using the CMSIS-DSP Python wrapper (which must already be installed before trying the example). To run a Python example, you need to go into an example folder and type:
-
-```bash
-python main.py
-```
-
-`example7` is communicating with `OpenModelica`. You need to install the VHTModelica blocks from the [AVH-SystemModeling](https://github.com/ARM-software/VHT-SystemModeling) project on our GitHub
-
-# List of examples
-
-* [Simple example without CMSIS-DSP](simple/README.md) : **How to get started**
-* [Simple example with CMSIS-DSP](simpledsp/README.md) : **How to get started with CMSIS-DSP**
-* [Example 1](example1/README.md) : Same as the simple example but explaining how to add arguments to the scheduler API and node constructors. This example is also giving a **detailed explanation of the C++ code** generated for the scheduler
-* [Example 2](example2/README.md) : Explain how to use CMSIS-DSP pure functions (no state) and add delay on the arcs of the graph. Explain some configuration options for the schedule generation.
-* [Example 3](example3/README.md) : A full signal processing example with CMSIS-DSP using FFT and sliding windows and overlap and add node
-* [Example 4](example4/README.md) : Same as example 3 but where we generate a Python implementation rather than a C++ implementation. The resulting graph can be executed thanks to the CMSIS-DSP Python wrapper
-* [Example 5](example5/README.md) : Another pure Python example showing how to compute a sequence of Q15 MFCC and generate an animation (using also the CMSIS-DSP Python wrapper)
-* [Example 6](example6/README.md) : Same as example 5 but with C++ code generation
-* [Example 7](example7/README.md) : Pure Python example demonstrating a communication between the compute graph and OpenModelica to generate a Larsen effect
-* [Example 8](example8/README.md) : Introduce structured datatype for the samples and implicit `Duplicate` nodes for the graph
-* [Example 9](example9/README.md) : Check that duplicate nodes and arc delays are working together and a scheduling is generated
-* [Example 10 : The dynamic dataflow mode](example10/README.md)
-* [Cyclo-static scheduling](cyclo/README.md)
-* [Simple example with the event recorder](eventrecorder/README.md)
-

ComputeGraph/examples/cyclo/AppNodes.h

@@ -1,155 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        AppNodes.h
- * Description:  Application nodes for Example cyclo
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _APPNODES_H_
-#define _APPNODES_H_
-
-#include <iostream>
-
-template<typename IN, int inputSize>
-class Sink: public GenericSink<IN, inputSize>
-{
-public:
-    Sink(FIFOBase<IN> &src):GenericSink<IN,inputSize>(src){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *b=this->getReadBuffer();
-        printf("Sink\n");
-        for(int i=0;i<inputSize;i++)
-        {
-            std::cout << (int)b[i] << std::endl;
-        }
-        return(0);
-    };
-
-};
-
-template<typename OUT,int outputSize>
-class Source: public GenericSource<OUT,outputSize>
-{
-public:
-    Source(FIFOBase<OUT> &dst):GenericSource<OUT,outputSize>(dst),
-    mPeriod(0),mValuePeriodStart(0){};
-
-    int getSamplesForPeriod() const 
-    {
-        if (mPeriod == 0)
-        { 
-            return(3);
-        }
-        return(2);
-    }
-
-    void updatePeriod(){
-        mPeriod++;
-        mValuePeriodStart = 3;
-        if (mPeriod == 2)
-        {
-            mPeriod = 0;
-            mValuePeriodStart = 0;
-        }
-    }
-
-    int prepareForRunning() final
-    {
-        /* Cyclo static scheduling do not make sense in
-           asynchronous mode so the default outputSize is used.
-           This function is never used in cyclo-static scheduling
-        */
-        if (this->willOverflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final{
-        OUT *b=this->getWriteBuffer(getSamplesForPeriod());
-
-        printf("Source\n");
-        for(int i=0;i<getSamplesForPeriod();i++)
-        {
-            b[i] = mValuePeriodStart + (OUT)i;
-
-        }
-        updatePeriod();
-        return(0);
-    };
-
-protected:
-    int mPeriod;
-    OUT mValuePeriodStart;
-
-};
-
-template<typename IN, int inputSize,typename OUT,int outputSize>
-class ProcessingNode;
-
-
-template<typename IN, int inputOutputSize>
-class ProcessingNode<IN,inputOutputSize,IN,inputOutputSize>: 
-      public GenericNode<IN,inputOutputSize,IN,inputOutputSize>
-{
-public:
-    ProcessingNode(FIFOBase<IN> &src,
-                   FIFOBase<IN> &dst):GenericNode<IN,inputOutputSize,
-                                                  IN,inputOutputSize>(src,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final{
-        printf("ProcessingNode\n");
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-        for(int i=0;i<inputOutputSize;i++)
-        {
-            b[i] = a[i]+1;
-        }
-        return(0);
-    };
-
-};
-
-#endif

ComputeGraph/examples/cyclo/CMakeLists.txt

@@ -1,13 +0,0 @@
-cmake_minimum_required (VERSION 3.14)
-include(CMakePrintHelpers)
-
-project(cyclo)
-
-
-add_executable(cyclo main.cpp)
-
-sdf(cyclo create.py cyclo)
-add_sdf_dir(cyclo)
-
-target_include_directories(cyclo PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
-target_include_directories(cyclo PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/generated)

ComputeGraph/examples/cyclo/Makefile

@@ -1,18 +0,0 @@
-# Makefile for MSVC compiler on Windows
-SHELL = cmd
-CC = cl.exe
-RM = del /Q /F
-
-INCLUDES = /Igenerated /I../../cg/src /I.
-WINFLAGS = /DWIN32 /D_WINDOWS /EHsc /Zi /Ob0 /Od /RTC1 -MDd 
-CFLAGS =  $(INCLUDES) $(WINFLAGS)
-
-all:
-	$(CC) /Fecyclo.exe $(CFLAGS) generated/scheduler.cpp main.cpp
-
-clean:
-	$(RM) main.obj
-	$(RM) scheduler.obj 
-	$(RM) cyclo.ilk 
-	$(RM) cyclo.exe 
-	$(RM) *.pdb 

ComputeGraph/examples/cyclo/README.md

@@ -1,143 +0,0 @@
-# README
-
-This example is inside the folder `examples/cyclo` of the Compute graph folder. Before reading this documentation you need to understand the principles explained in the [simple example without CMSIS-DSP](../simple/README.md)
-
-
-
-![cyclo](docassets/cyclo.png)
-
-The nodes are:
-
-* A source generating floating point values (0,1,2,3,4).
-* A processing node adding 1 to those values 
-* A sink printing its input values (1,2,3,4,5)
-
-The graph generates an infinite streams of values : 1,2,3,4,5,1,2,3,4,5,1,2,3,4,5 ... For this example, the number of iterations will be limited so that it does not run forever.
-
-The big difference compared to the  [simple example without CMSIS-DSP](../simple/README.md) is the source node:
-
-* The source node is no more generating samples per packet of 5
-* The first call to the source node will generate 3 samples
-* The second call to the source node will generate 2 samples
-* Other execution will just reproduce this schedule : 3,2,3,2 ...
-
-The flow is not static, but it is periodically static  : **cyclo-static scheduling**.
-
-## C++ Implementation
-
-The C++ wrapper must take into account this periodic schedule of sample generation.
-
-First call should generate only 3 samples and second call generate 2.
-
-We want the first call to generate `0,1,2` and the second call to generate `3,4`.
-
-The C++ wrapper has been modified for this. Here is the body of the `run` function:
-
-```C++
-OUT *b=this->getWriteBuffer(getSamplesForPeriod());
-
-printf("Source\n");
-for(int i=0;i<getSamplesForPeriod();i++)
-{
-    b[i] = mValuePeriodStart + (OUT)i;
-}
-updatePeriod();
-```
-
-The `run` function is generating only the number of samples required in a given period.
-
-The value generated is using `mValuePeriodStart`.
-
-The template for `Source` has not changed and is :
-
-```C++
-template<typename OUT,int outputSize>
-class Source: public GenericSource<OUT,outputSize>
-```
-
-`outputSize` cannot be the list `[3,2]`.
-
-The generated code is using the max of the values, so here `3`:
-
-```C++
-Source<float32_t,3> source(fifo0);
-```
-
-## Expected output:
-
-```
-Schedule length = 26
-Memory usage 88 bytes
-```
-
-The schedule length is `26` compared to `19` for the simple example where source is generating samples by packet of 5. The source node executions must be a multiple of 2 in this graph because the period of sample generation has length 2. In the original graph, the number of executions could be an odd number. That's why there are more executions in this cyclo-static scheduling.
-
-The memory usage (FIFO) is the same as the one for the simple example without cyclo-static scheduling.
-
-The expected output of the execution is still 1,2,3,4,5,1,2,3,4,5 ... but the scheduling is different. There are more source executions.
-
-```
-Start
-Source
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Sink
-1
-2
-3
-4
-5
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Sink
-1
-2
-3
-4
-5
-```
-

ComputeGraph/examples/cyclo/create.py

@@ -1,31 +0,0 @@
-# Include definition of the nodes
-from nodes import * 
-# Include definition of the graph
-from graph import * 
-
-# Create a configuration object
-conf=Configuration()
-# The number of schedule iteration is limited to 1
-# to prevent the scheduling from running forever
-# (which should be the case for a stream computation)
-conf.debugLimit=1
-# Disable inclusion of CMSIS-DSP headers so that we don't have
-# to recompile CMSIS-DSP for such a simple example
-conf.CMSISDSP = False
-
-# Compute a static scheduling of the graph 
-# The size of FIFO is also computed
-scheduling = the_graph.computeSchedule(config=conf)
-
-# Print some statistics about the compute schedule
-# and the memory usage
-print("Schedule length = %d" % scheduling.scheduleLength)
-print("Memory usage %d bytes" % scheduling.memory)
-
-# Generate the C++ code for the static scheduler
-scheduling.ccode("generated",conf)
-
-# Generate a graphviz representation of the graph
-with open("cyclo.dot","w") as f:
-    scheduling.graphviz(f)
-

ComputeGraph/examples/cyclo/custom.h

@@ -1,5 +0,0 @@
-#ifndef _CUSTOM_H_
-
-typedef float float32_t;
-
-#endif 

ComputeGraph/examples/cyclo/cyclo.dot

@@ -1,48 +0,0 @@
-
-
-
-
-digraph structs {
-    node [shape=plaintext]
-    rankdir=LR
-    edge [arrowsize=0.5]
-    fontname="times"
-
-
-processing [label=<
-<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
-  <TR>
-    <TD ALIGN="CENTER" PORT="i">processing<BR/>(ProcessingNode)</TD>
-  </TR>
-</TABLE>>];
-
-sink [label=<
-<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
-  <TR>
-    <TD ALIGN="CENTER" PORT="i">sink<BR/>(Sink)</TD>
-  </TR>
-</TABLE>>];
-
-source [label=<
-<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
-  <TR>
-    <TD ALIGN="CENTER" PORT="i">source<BR/>(Source)</TD>
-  </TR>
-</TABLE>>];
-
-
-
-source:i -> processing:i [label="f32(11)"
-,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >7</FONT>
-</TD></TR></TABLE>>
-,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >[3, 2]</FONT>
-</TD></TR></TABLE>>]
-
-processing:i -> sink:i [label="f32(11)"
-,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >5</FONT>
-</TD></TR></TABLE>>
-,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >7</FONT>
-</TD></TR></TABLE>>]
-
-
-}

ComputeGraph/examples/cyclo/generated/scheduler.cpp

@@ -1,170 +0,0 @@
-/*
-
-Generated with CMSIS-DSP Compute Graph Scripts.
-The generated code is not covered by CMSIS-DSP license.
-
-The support classes and code is covered by CMSIS-DSP license.
-
-*/
-
-
-#include "custom.h"
-#include "GenericNodes.h"
-#include "AppNodes.h"
-#include "scheduler.h"
-
-#if !defined(CHECKERROR)
-#define CHECKERROR       if (cgStaticError < 0) \
-       {\
-         goto errorHandling;\
-       }
-
-#endif
-
-#if !defined(CG_BEFORE_ITERATION)
-#define CG_BEFORE_ITERATION
-#endif 
-
-#if !defined(CG_AFTER_ITERATION)
-#define CG_AFTER_ITERATION
-#endif 
-
-#if !defined(CG_BEFORE_SCHEDULE)
-#define CG_BEFORE_SCHEDULE
-#endif
-
-#if !defined(CG_AFTER_SCHEDULE)
-#define CG_AFTER_SCHEDULE
-#endif
-
-#if !defined(CG_BEFORE_BUFFER)
-#define CG_BEFORE_BUFFER
-#endif
-
-#if !defined(CG_BEFORE_FIFO_BUFFERS)
-#define CG_BEFORE_FIFO_BUFFERS
-#endif
-
-#if !defined(CG_BEFORE_FIFO_INIT)
-#define CG_BEFORE_FIFO_INIT
-#endif
-
-#if !defined(CG_BEFORE_NODE_INIT)
-#define CG_BEFORE_NODE_INIT
-#endif
-
-#if !defined(CG_AFTER_INCLUDES)
-#define CG_AFTER_INCLUDES
-#endif
-
-#if !defined(CG_BEFORE_SCHEDULER_FUNCTION)
-#define CG_BEFORE_SCHEDULER_FUNCTION
-#endif
-
-#if !defined(CG_BEFORE_NODE_EXECUTION)
-#define CG_BEFORE_NODE_EXECUTION
-#endif
-
-#if !defined(CG_AFTER_NODE_EXECUTION)
-#define CG_AFTER_NODE_EXECUTION
-#endif
-
-CG_AFTER_INCLUDES
-
-
-/*
-
-Description of the scheduling. 
-
-*/
-static unsigned int schedule[26]=
-{ 
-2,2,2,0,1,2,2,2,0,1,2,2,2,0,1,1,2,2,0,1,2,2,2,0,1,1,
-};
-
-CG_BEFORE_FIFO_BUFFERS
-/***********
-
-FIFO buffers
-
-************/
-#define FIFOSIZE0 11
-#define FIFOSIZE1 11
-
-#define BUFFERSIZE1 11
-CG_BEFORE_BUFFER
-float32_t buf1[BUFFERSIZE1]={0};
-
-#define BUFFERSIZE2 11
-CG_BEFORE_BUFFER
-float32_t buf2[BUFFERSIZE2]={0};
-
-
-CG_BEFORE_SCHEDULER_FUNCTION
-uint32_t scheduler(int *error)
-{
-    int cgStaticError=0;
-    uint32_t nbSchedule=0;
-    int32_t debugCounter=1;
-
-    CG_BEFORE_FIFO_INIT;
-    /*
-    Create FIFOs objects
-    */
-    FIFO<float32_t,FIFOSIZE0,0,0> fifo0(buf1);
-    FIFO<float32_t,FIFOSIZE1,0,0> fifo1(buf2);
-
-    CG_BEFORE_NODE_INIT;
-    /* 
-    Create node objects
-    */
-    ProcessingNode<float32_t,7,float32_t,7> processing(fifo0,fifo1);
-    Sink<float32_t,5> sink(fifo1);
-    Source<float32_t,3> source(fifo0);
-
-    /* Run several schedule iterations */
-    CG_BEFORE_SCHEDULE;
-    while((cgStaticError==0) && (debugCounter > 0))
-    {
-        /* Run a schedule iteration */
-        CG_BEFORE_ITERATION;
-        for(unsigned long id=0 ; id < 26; id++)
-        {
-            CG_BEFORE_NODE_EXECUTION;
-
-            switch(schedule[id])
-            {
-                case 0:
-                {
-                   cgStaticError = processing.run();
-                }
-                break;
-
-                case 1:
-                {
-                   cgStaticError = sink.run();
-                }
-                break;
-
-                case 2:
-                {
-                   cgStaticError = source.run();
-                }
-                break;
-
-                default:
-                break;
-            }
-            CG_AFTER_NODE_EXECUTION;
-            CHECKERROR;
-        }
-       debugCounter--;
-       CG_AFTER_ITERATION;
-       nbSchedule++;
-    }
-
-errorHandling:
-    CG_AFTER_SCHEDULE;
-    *error=cgStaticError;
-    return(nbSchedule);
-}

ComputeGraph/examples/cyclo/generated/scheduler.h

@@ -1,26 +0,0 @@
-/*
-
-Generated with CMSIS-DSP Compute Graph Scripts.
-The generated code is not covered by CMSIS-DSP license.
-
-The support classes and code is covered by CMSIS-DSP license.
-
-*/
-
-#ifndef _SCHEDULER_H_ 
-#define _SCHEDULER_H_
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-extern uint32_t scheduler(int *error);
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif
-

ComputeGraph/examples/cyclo/graph.py

@@ -1,39 +0,0 @@
-# Include definitions from the Python package to
-# define datatype for the IOs and to have access to the
-# Graph class
-from cmsisdsp.cg.scheduler import *
-# Include definition of the nodes
-from nodes import * 
-
-# Define the datatype we are using for all the IOs in this
-# example
-floatType=CType(F32)
-
-# Instantiate a Source node with a float datatype and
-# working with packet of 5 samples (each execution of the
-# source in the C code will generate 5 samples)
-# "source" is the name of the C variable that will identify
-# this node
-src=Source("source",floatType,[3,2])
-# Instantiate a Processing node using a float data type for
-# both the input and output. The number of samples consumed
-# on the input and produced on the output is 7 each time
-# the node is executed in the C code
-# "processing" is the name of the C variable that will identify
-# this node
-processing=ProcessingNode("processing",floatType,7,7)
-# Instantiate a Sink node with a float datatype and consuming
-# 5 samples each time the node is executed in the C code
-# "sink" is the name of the C variable that will identify
-# this node
-sink=Sink("sink",floatType,5)
-
-# Create a Graph object
-the_graph = Graph()
-
-# Connect the source to the processing node
-the_graph.connect(src.o,processing.i)
-# Connect the processing node to the sink
-the_graph.connect(processing.o,sink.i)
-
-

ComputeGraph/examples/cyclo/main.cpp

@@ -1,11 +0,0 @@
-#include <cstdio>
-#include <cstdint>
-#include "scheduler.h"
-
-int main(int argc, char const *argv[])
-{
-    int error;
-    printf("Start\n");
-    uint32_t nbSched=scheduler(&error);
-    return 0;
-}

ComputeGraph/examples/cyclo/nodes.py

@@ -1,77 +0,0 @@
-# Include definitions from the Python package
-from cmsisdsp.cg.scheduler import GenericNode,GenericSink,GenericSource
-
-### Define new types of Nodes 
-
-class ProcessingNode(GenericNode):
-    """
-    Definition of a ProcessingNode for the graph
-
-    Parameters
-    ----------
-    name : str
-         Name of the C variable identifying this node 
-         in the C code
-    theType : CGStaticType
-            The datatype for the input and output
-    inLength : int
-             The number of samples consumed by input
-    outLength : int 
-              The number of samples produced on output
-    """
-    def __init__(self,name,theType,inLength,outLength):
-        GenericNode.__init__(self,name)
-        self.addInput("i",theType,inLength)
-        self.addOutput("o",theType,outLength)
-
-    @property
-    def typeName(self):
-        """The name of the C++ class implementing this node"""
-        return "ProcessingNode"
-
-class Sink(GenericSink):
-    """
-    Definition of a Sink node for the graph
-
-    Parameters
-    ----------
-    name : str
-         Name of the C variable identifying this node 
-         in the C code
-    theType : CGStaticType
-            The datatype for the input
-    inLength : int
-             The number of samples consumed by input
-    """
-    def __init__(self,name,theType,inLength):
-        GenericSink.__init__(self,name)
-        self.addInput("i",theType,inLength)
-
-    @property
-    def typeName(self):
-        """The name of the C++ class implementing this node"""
-        return "Sink"
-
-class Source(GenericSource):
-    """
-    Definition of a Source node for the graph
-
-    Parameters
-    ----------
-    name : str
-         Name of the C variable identifying this node 
-         in the C code
-    theType : CGStaticType
-            The datatype for the output
-    outLength : int 
-              The number of samples produced on output
-    """
-    def __init__(self,name,theType,outLength):
-        GenericSource.__init__(self,name)
-        self.addOutput("o",theType,outLength)
-
-    @property
-    def typeName(self):
-        """The name of the C++ class implementing this node"""
-        return "Source"
-

ComputeGraph/examples/eventrecorder/ARMCM55_FP_MVE_config.txt

@@ -1,9 +0,0 @@
-core_clk.mul=50000000
-mps3_board.visualisation.disable-visualisation=1
-cpu0.semihosting-enable=0
-cpu0.FPU=1
-cpu0.MVE=2
-cpu0.SAU=0
-cpu0.SECEXT=1
-cpu0.INITSVTOR=0
-cpu0.INITNSVTOR=0

ComputeGraph/examples/eventrecorder/AppNodes.h

@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        AppNodes.h
- * Description:  Application nodes for Example simple
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- 
-*
- * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef _APPNODES_H_
-#define _APPNODES_H_
-
-#include <iostream>
-
-template<typename IN, int inputSize>
-class Sink: public GenericSink<IN, inputSize>
-{
-public:
-    Sink(FIFOBase<IN> &src):GenericSink<IN,inputSize>(src){};
-
-    int prepareForRunning() final
-    {
-        if (this->willUnderflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final
-    {
-        IN *b=this->getReadBuffer();
-        printf("Sink\n");
-        for(int i=0;i<inputSize;i++)
-        {
-            std::cout << (int)b[i] << std::endl;
-        }
-        return(0);
-    };
-
-};
-
-template<typename OUT,int outputSize>
-class Source: public GenericSource<OUT,outputSize>
-{
-public:
-    Source(FIFOBase<OUT> &dst):GenericSource<OUT,outputSize>(dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-
-    int run() final{
-        OUT *b=this->getWriteBuffer();
-
-        printf("Source\n");
-        for(int i=0;i<outputSize;i++)
-        {
-            b[i] = (OUT)i;
-        }
-        return(0);
-    };
-
-};
-
-
-template<typename IN, int inputSize,
-         typename OUT, int outputSize>
-class ProcessingNode;
-
-
-template<typename IN, int inputOutputSize>
-class ProcessingNode<IN,inputOutputSize,IN,inputOutputSize>: public GenericNode<IN,inputOutputSize,IN,inputOutputSize>
-{
-public:
-    ProcessingNode(FIFOBase<IN> &src,
-                   FIFOBase<IN> &dst):GenericNode<IN,inputOutputSize,
-                                                  IN,inputOutputSize>(src,dst){};
-
-    int prepareForRunning() final
-    {
-        if (this->willOverflow() ||
-            this->willUnderflow())
-        {
-           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
-        }
-
-        return(0);
-    };
-    
-    int run() final{
-        printf("ProcessingNode\n");
-        IN *a=this->getReadBuffer();
-        IN *b=this->getWriteBuffer();
-        for(int i=0;i<inputOutputSize;i++)
-        {
-            b[i] = a[i]+1;
-        }
-        return(0);
-    };
-
-};
-
-
-
-
-#endif

ComputeGraph/examples/eventrecorder/CMakeLists.txt

@@ -1,13 +0,0 @@
-cmake_minimum_required (VERSION 3.14)
-include(CMakePrintHelpers)
-
-project(Simple)
-
-
-add_executable(simple main.cpp)
-
-sdf(simple create.py simple)
-add_sdf_dir(simple)
-
-target_include_directories(simple PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
-target_include_directories(simple PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/generated)

ComputeGraph/examples/eventrecorder/EventRecorderStub.scvd

@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
-
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
-  <events>
-  </events>
-
-</component_viewer>

ComputeGraph/examples/eventrecorder/GetEvent_cs300.bat

@@ -1,10 +0,0 @@
-eventlist.exe ^
- -a out\eventrecorder\VHT-Corstone-300\CommandLine\eventrecorder.CommandLine+VHT-Corstone-300.axf ^
- -I C:\Keil_v5\ARM\PACK\ARM\CMSIS-DSP\1.14.3\ComputeGraph\cg.scvd ^
- -I C:\Keil_v5\ARM\PACK\Keil\ARM_Compiler\1.7.2\EventRecorder.scvd ^
- -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\ARM.CMSIS.pdsc ^
- -I C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.9.0\CMSIS\RTOS2\RTX\RTX5.scvd ^
- -b EventRecorder.log
-
-
-

ComputeGraph/examples/eventrecorder/README.md

@@ -1,220 +0,0 @@
-# README
-
-This example is inside the folder `examples/eventrecorder` of the Compute graph folder.
-
-This example explains how to enable the [Event Recorder](https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html) for the scheduling of the following graph:
-
-![event_recorder](docassets/event_recorder.png)
-
-You need to understand the [simple example](../simple/README.md) before reading this documentation
-
-This example is using [CMSIS build tools](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools) and the command line tool [eventlist](https://github.com/ARM-software/CMSIS-View/tree/main/tools/eventlist) to format the events from the  [Event Recorder](https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html) .
-
-You need to understand how to use the  [CMSIS build tools](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools) before reading this documentation if you want to run the example from command line.
-
-You can also use an IDE supporting the CMSIS-Pack and Event Recorder technology : uVision is used for this example.
-
-## Event recording in the compute graph
-
-You can enable Event recorder for the code generation by setting the following property to `true` before generating the C++ code.
-
-```Python
-conf.eventRecorder = True
-```
-
-The C++ code will contain calls to `EventRecord2`.
-
-The event recorder header must be included from the scheduler. In can be done, for instance, in the `custom.h` file that is included by default by the scheduler:
-
-```c
-#if defined(RTE_Compiler_EventRecorder)
-#include "EventRecorder.h"
-#endif 
-```
-
-The `EventRecord2` calls are using some constant to identify the events to generate. Those constants are generated in the header `scheduler.h`
-
-```C++
-#define CG_EvtSched 0x01 
-
-#define CG_Evt_Scheduler   EventID (EventLevelAPI,   EvtSched, 0x00)
-#define CG_Evt_Node        EventID (EventLevelAPI,   EvtSched, 0x01)
-#define CG_Evt_Error       EventID (EventLevelError,   EvtSched, 0x02)
-```
-
-Three events are defined:
-
-* An event for the start of the scheduling iteration
-* An event for execution of a node
-* An event in case of error
-
-In this example, the computed scheduling is described by the array:
-
-```C++
-static unsigned int schedule[19]=
-{ 
-2,2,0,1,2,0,1,2,2,0,1,1,2,0,1,2,0,1,1,
-};
-```
-
-We should be able to see this schedule thanks to the recorder events.
-
-## Command line execution
-
-You need to build the example with the cmsis build tools (assuming all the needed packs are already installed):
-
-`csolution convert -s example.csolution_ac6.yml`
-
-`cbuild "eventrecorder.CommandLine+VHT-Corstone-300.cprj"`
-
-Now, you can run the example on AVH using the command:
-
-`run.bat`
-
-if you're not on Windows, you can just change the paths in this script.
-
-The execution on AVH should display:
-
-```
-telnetterminal0: Listening for serial connection on port 5000
-telnetterminal2: Listening for serial connection on port 5001
-telnetterminal5: Listening for serial connection on port 5002
-telnetterminal1: Listening for serial connection on port 5003
-
-    Ethos-U rev 136b7d75 --- Feb 16 2022 15:53:42
-    (C) COPYRIGHT 2019-2022 Arm Limited
-    ALL RIGHTS RESERVED
-
-Start
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Sink
-1
-2
-3
-4
-5
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Source
-ProcessingNode
-Sink
-1
-2
-3
-4
-5
-Sink
-1
-2
-3
-4
-5
-Number of schedule iterations = 1
-Error code = 0
-
-Info: /OSCI/SystemC: Simulation stopped by user.
-[warning ][main@0][01 ns] Simulation stopped by user
-```
-
-A file `EventRecorder.log` have been generated. This file can be parsed with the `eventlist` tool. It can be done with the script:
-
-`GetEvent_cs300.bat`
-
-If you are not on windows, you'll need to change the paths in the script.
-
-The output should be:
-
-```
-Index Time (s)   Component    Event Property          Value
------ --------   ---------    --------------          -----
-    0 0.00000012 EvCtrl       EventRecorderInitialize Restart Count = 1, Timestamp Frequency = 50000000
-    1 0.00000046 EvCtrl       EventRecorderStart
-    2 0.00002752 RTX MsgQueue ThreadCreated           thread_id=30001640
-    3 0.00002862 RTX MsgQueue ThreadCreated           thread_id=300097e0
-    4 0.00002992 RTX MsgQueue ThreadCreated           thread_id=30009824
-    5 0.00003060 RTX MsgQueue ThreadSwitched          thread_id=30009824
-    6 0.00003182 RTX MsgQueue ThreadSwitched          thread_id=30001640
-    7 0.00003684 CG           ScheduleIteration       nb=0
-    8 0.00003724 CG           NodeExecution           ID=2
-    9 0.00004022 CG           NodeExecution           ID=2
-   10 0.00004320 CG           NodeExecution           ID=0
-   11 0.00004780 CG           NodeExecution           ID=1
-   12 0.00008716 CG           NodeExecution           ID=2
-   13 0.00009022 CG           NodeExecution           ID=0
-   14 0.00009490 CG           NodeExecution           ID=1
-   15 0.00013430 CG           NodeExecution           ID=2
-   16 0.00013736 CG           NodeExecution           ID=2
-   17 0.00014034 CG           NodeExecution           ID=0
-   18 0.00014502 CG           NodeExecution           ID=1
-   19 0.00018422 CG           NodeExecution           ID=1
-   20 0.00022376 CG           NodeExecution           ID=2
-   21 0.00022682 CG           NodeExecution           ID=0
-   22 0.00023152 CG           NodeExecution           ID=1
-   23 0.00027072 CG           NodeExecution           ID=2
-   24 0.00027378 CG           NodeExecution           ID=0
-   25 0.00027846 CG           NodeExecution           ID=1
-   26 0.00031784 CG           NodeExecution           ID=1
-```
-
-The scheduling is clearly visible:
-
-* First an event `ScheduleIteration` is generated. The first iteration has number `0`
-* Then, there is a sequence of node executions with the node ID
-
-This sequence reflects what is in the scheduling array of the C++ code:
-
-```C++
-static unsigned int schedule[19]=
-{ 
-2,2,0,1,2,0,1,2,2,0,1,1,2,0,1,2,0,1,1,
-};
-```
-
-Enabling the event recorder in the compute graph is very useful to understand real-time problems.
-
-## Execution with uVision
-
-You can import `eventrecorder.IDE+VHT-Corstone-300.cprj` from the uVision IDE.
-
-The project sidebar should display:
-
-![project](docassets/project.png)
-
-You need to select the AVH model and use the configuration file `ARMCM55_FP_MVE_config.txt`.
-
-This document will not explain the details of how to use the event recorder in uVision. You should already know how to open the Event Recorder window.
-
-If you build and run the solution, you should get something like:
-
-<img src="docassets/ide_events.PNG" alt="ide_events" style="zoom:75%;" />

ComputeGraph/examples/eventrecorder/RTE/CMSIS/RTX_Config.c

@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision:   V5.1.1
- *
- * Project:     CMSIS-RTOS RTX
- * Title:       RTX Configuration
- *
- * -----------------------------------------------------------------------------
- */
- 
-#include "cmsis_compiler.h"
-#include "rtx_os.h"
- 
-// OS Idle Thread
-__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
-  (void)argument;
-
-  for (;;) {}
-}
- 
-// OS Error Callback function
-__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
-  (void)object_id;
-
-  switch (code) {
-    case osRtxErrorStackOverflow:
-      // Stack overflow detected for thread (thread_id=object_id)
-      break;
-    case osRtxErrorISRQueueOverflow:
-      // ISR Queue overflow detected when inserting object (object_id)
-      break;
-    case osRtxErrorTimerQueueOverflow:
-      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
-      break;
-    case osRtxErrorClibSpace:
-      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
-      break;
-    case osRtxErrorClibMutex:
-      // Standard C/C++ library mutex initialization failed
-      break;
-    default:
-      // Reserved
-      break;
-  }
-  for (;;) {}
-//return 0U;
-}

ComputeGraph/examples/eventrecorder/RTE/CMSIS/RTX_Config.c.base@5.1.1

@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision:   V5.1.1
- *
- * Project:     CMSIS-RTOS RTX
- * Title:       RTX Configuration
- *
- * -----------------------------------------------------------------------------
- */
- 
-#include "cmsis_compiler.h"
-#include "rtx_os.h"
- 
-// OS Idle Thread
-__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
-  (void)argument;
-
-  for (;;) {}
-}
- 
-// OS Error Callback function
-__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
-  (void)object_id;
-
-  switch (code) {
-    case osRtxErrorStackOverflow:
-      // Stack overflow detected for thread (thread_id=object_id)
-      break;
-    case osRtxErrorISRQueueOverflow:
-      // ISR Queue overflow detected when inserting object (object_id)
-      break;
-    case osRtxErrorTimerQueueOverflow:
-      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
-      break;
-    case osRtxErrorClibSpace:
-      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
-      break;
-    case osRtxErrorClibMutex:
-      // Standard C/C++ library mutex initialization failed
-      break;
-    default:
-      // Reserved
-      break;
-  }
-  for (;;) {}
-//return 0U;
-}

ComputeGraph/examples/eventrecorder/RTE/CMSIS/RTX_Config.h

@@ -1,580 +0,0 @@
-/*
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision:   V5.5.2
- *
- * Project:     CMSIS-RTOS RTX
- * Title:       RTX Configuration definitions
- *
- * -----------------------------------------------------------------------------
- */
- 
-#ifndef RTX_CONFIG_H_
-#define RTX_CONFIG_H_
- 
-#ifdef   _RTE_
-#include "RTE_Components.h"
-#ifdef    RTE_RTX_CONFIG_H
-#include  RTE_RTX_CONFIG_H
-#endif
-#endif
- 
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
- 
-// <h>System Configuration
-// =======================
- 
-//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
-//   <i> Defines the combined global dynamic memory size.
-//   <i> Default: 32768
-#ifndef OS_DYNAMIC_MEM_SIZE
-#define OS_DYNAMIC_MEM_SIZE         32768
-#endif
- 
-//   <o>Kernel Tick Frequency [Hz] <1-1000000>
-//   <i> Defines base time unit for delays and timeouts.
-//   <i> Default: 1000 (1ms tick)
-#ifndef OS_TICK_FREQ
-#define OS_TICK_FREQ                1000
-#endif
- 
-//   <e>Round-Robin Thread switching
-//   <i> Enables Round-Robin Thread switching.
-#ifndef OS_ROBIN_ENABLE
-#define OS_ROBIN_ENABLE             1
-#endif
- 
-//     <o>Round-Robin Timeout <1-1000>
-//     <i> Defines how many ticks a thread will execute before a thread switch.
-//     <i> Default: 5
-#ifndef OS_ROBIN_TIMEOUT
-#define OS_ROBIN_TIMEOUT            5
-#endif
- 
-//   </e>
- 
-//   <o>ISR FIFO Queue
-//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
-//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
-//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
-//   <i> RTOS Functions called from ISR store requests to this buffer.
-//   <i> Default: 16 entries
-#ifndef OS_ISR_FIFO_QUEUE
-#define OS_ISR_FIFO_QUEUE           16
-#endif
- 
-//   <q>Object Memory usage counters
-//   <i> Enables object memory usage counters (requires RTX source variant).
-#ifndef OS_OBJ_MEM_USAGE
-#define OS_OBJ_MEM_USAGE            0
-#endif
- 
-// </h>
- 
-// <h>Thread Configuration
-// =======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_THREAD_OBJ_MEM
-#define OS_THREAD_OBJ_MEM           0
-#endif
- 
-//     <o>Number of user Threads <1-1000>
-//     <i> Defines maximum number of user threads that can be active at the same time.
-//     <i> Applies to user threads with system provided memory for control blocks.
-#ifndef OS_THREAD_NUM
-#define OS_THREAD_NUM               1
-#endif
- 
-//     <o>Number of user Threads with default Stack size <0-1000>
-//     <i> Defines maximum number of user threads with default stack size.
-//     <i> Applies to user threads with zero stack size specified.
-#ifndef OS_THREAD_DEF_STACK_NUM
-#define OS_THREAD_DEF_STACK_NUM     0
-#endif
- 
-//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
-//     <i> Defines the combined stack size for user threads with user-provided stack size.
-//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
-//     <i> Default: 0
-#ifndef OS_THREAD_USER_STACK_SIZE
-#define OS_THREAD_USER_STACK_SIZE   0
-#endif
- 
-//   </e>
- 
-//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
-//   <i> Defines stack size for threads with zero stack size specified.
-//   <i> Default: 3072
-#ifndef OS_STACK_SIZE
-#define OS_STACK_SIZE               3072
-#endif
- 
-//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
-//   <i> Defines stack size for Idle thread.
-//   <i> Default: 512
-#ifndef OS_IDLE_THREAD_STACK_SIZE
-#define OS_IDLE_THREAD_STACK_SIZE   512
-#endif
- 
-//   <o>Idle Thread TrustZone Module Identifier
-//   <i> Defines TrustZone Thread Context Management Identifier.
-//   <i> Applies only to cores with TrustZone technology.
-//   <i> Default: 0 (not used)
-#ifndef OS_IDLE_THREAD_TZ_MOD_ID
-#define OS_IDLE_THREAD_TZ_MOD_ID    0
-#endif
- 
-//   <q>Stack overrun checking
-//   <i> Enables stack overrun check at thread switch (requires RTX source variant).
-//   <i> Enabling this option increases slightly the execution time of a thread switch.
-#ifndef OS_STACK_CHECK
-#define OS_STACK_CHECK              0
-#endif
- 
-//   <q>Stack usage watermark
-//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.
-//   <i> Enabling this option increases significantly the execution time of thread creation.
-#ifndef OS_STACK_WATERMARK
-#define OS_STACK_WATERMARK          0
-#endif
- 
-//   <o>Processor mode for Thread execution
-//     <0=> Unprivileged mode
-//     <1=> Privileged mode
-//   <i> Default: Privileged mode
-#ifndef OS_PRIVILEGE_MODE
-#define OS_PRIVILEGE_MODE           1
-#endif
- 
-// </h>
- 
-// <h>Timer Configuration
-// ======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_TIMER_OBJ_MEM
-#define OS_TIMER_OBJ_MEM            0
-#endif
- 
-//     <o>Number of Timer objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_TIMER_NUM
-#define OS_TIMER_NUM                1
-#endif
- 
-//   </e>
- 
-//   <o>Timer Thread Priority
-//      <8=> Low
-//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
-//     <40=> High
-//     <48=> Realtime
-//   <i> Defines priority for timer thread
-//   <i> Default: High
-#ifndef OS_TIMER_THREAD_PRIO
-#define OS_TIMER_THREAD_PRIO        40
-#endif
- 
-//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
-//   <i> Defines stack size for Timer thread.
-//   <i> May be set to 0 when timers are not used.
-//   <i> Default: 512
-#ifndef OS_TIMER_THREAD_STACK_SIZE
-#define OS_TIMER_THREAD_STACK_SIZE  512
-#endif
- 
-//   <o>Timer Thread TrustZone Module Identifier
-//   <i> Defines TrustZone Thread Context Management Identifier.
-//   <i> Applies only to cores with TrustZone technology.
-//   <i> Default: 0 (not used)
-#ifndef OS_TIMER_THREAD_TZ_MOD_ID
-#define OS_TIMER_THREAD_TZ_MOD_ID   0
-#endif
- 
-//   <o>Timer Callback Queue entries <0-256>
-//   <i> Number of concurrent active timer callback functions.
-//   <i> May be set to 0 when timers are not used.
-//   <i> Default: 4
-#ifndef OS_TIMER_CB_QUEUE
-#define OS_TIMER_CB_QUEUE           4
-#endif
- 
-// </h>
- 
-// <h>Event Flags Configuration
-// ============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_EVFLAGS_OBJ_MEM
-#define OS_EVFLAGS_OBJ_MEM          0
-#endif
- 
-//     <o>Number of Event Flags objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_EVFLAGS_NUM
-#define OS_EVFLAGS_NUM              1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Mutex Configuration
-// ======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MUTEX_OBJ_MEM
-#define OS_MUTEX_OBJ_MEM            0
-#endif
- 
-//     <o>Number of Mutex objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MUTEX_NUM
-#define OS_MUTEX_NUM                1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Semaphore Configuration
-// ==========================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_SEMAPHORE_OBJ_MEM
-#define OS_SEMAPHORE_OBJ_MEM        0
-#endif
- 
-//     <o>Number of Semaphore objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_SEMAPHORE_NUM
-#define OS_SEMAPHORE_NUM            1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Memory Pool Configuration
-// ============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MEMPOOL_OBJ_MEM
-#define OS_MEMPOOL_OBJ_MEM          0
-#endif
- 
-//     <o>Number of Memory Pool objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MEMPOOL_NUM
-#define OS_MEMPOOL_NUM              1
-#endif
- 
-//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
-//     <i> Defines the combined data storage memory size.
-//     <i> Applies to objects with system provided memory for data storage.
-//     <i> Default: 0
-#ifndef OS_MEMPOOL_DATA_SIZE
-#define OS_MEMPOOL_DATA_SIZE        0
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Message Queue Configuration
-// ==============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MSGQUEUE_OBJ_MEM
-#define OS_MSGQUEUE_OBJ_MEM         0
-#endif
- 
-//     <o>Number of Message Queue objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MSGQUEUE_NUM
-#define OS_MSGQUEUE_NUM             1
-#endif
- 
-//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
-//     <i> Defines the combined data storage memory size.
-//     <i> Applies to objects with system provided memory for data storage.
-//     <i> Default: 0
-#ifndef OS_MSGQUEUE_DATA_SIZE
-#define OS_MSGQUEUE_DATA_SIZE       0
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Event Recorder Configuration
-// ===============================
- 
-//   <e>Global Initialization
-//   <i> Initialize Event Recorder during 'osKernelInitialize'.
-#ifndef OS_EVR_INIT
-#define OS_EVR_INIT                 1
-#endif
- 
-//     <q>Start recording
-//     <i> Start event recording after initialization.
-#ifndef OS_EVR_START
-#define OS_EVR_START                1
-#endif
- 
-//     <h>Global Event Filter Setup
-//     <i> Initial recording level applied to all components.
-//       <o.0>Error events
-//       <o.1>API function call events
-//       <o.2>Operation events
-//       <o.3>Detailed operation events
-//     </h>
-#ifndef OS_EVR_LEVEL
-#define OS_EVR_LEVEL                0x00U
-#endif
- 
-//     <h>RTOS Event Filter Setup
-//     <i> Recording levels for RTX components.
-//     <i> Only applicable if events for the respective component are generated.
- 
-//       <e.7>Memory Management
-//       <i> Recording level for Memory Management events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MEMORY_LEVEL
-#define OS_EVR_MEMORY_LEVEL         0x81U
-#endif
- 
-//       <e.7>Kernel
-//       <i> Recording level for Kernel events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_KERNEL_LEVEL
-#define OS_EVR_KERNEL_LEVEL         0x81U
-#endif
- 
-//       <e.7>Thread
-//       <i> Recording level for Thread events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_THREAD_LEVEL
-#define OS_EVR_THREAD_LEVEL         0x85U
-#endif
- 
-//       <e.7>Generic Wait
-//       <i> Recording level for Generic Wait events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_WAIT_LEVEL
-#define OS_EVR_WAIT_LEVEL           0x81U
-#endif
- 
-//       <e.7>Thread Flags
-//       <i> Recording level for Thread Flags events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_THFLAGS_LEVEL
-#define OS_EVR_THFLAGS_LEVEL        0x81U
-#endif
- 
-//       <e.7>Event Flags
-//       <i> Recording level for Event Flags events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_EVFLAGS_LEVEL
-#define OS_EVR_EVFLAGS_LEVEL        0x81U
-#endif
- 
-//       <e.7>Timer
-//       <i> Recording level for Timer events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_TIMER_LEVEL
-#define OS_EVR_TIMER_LEVEL          0x81U
-#endif
- 
-//       <e.7>Mutex
-//       <i> Recording level for Mutex events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MUTEX_LEVEL
-#define OS_EVR_MUTEX_LEVEL          0x81U
-#endif
- 
-//       <e.7>Semaphore
-//       <i> Recording level for Semaphore events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_SEMAPHORE_LEVEL
-#define OS_EVR_SEMAPHORE_LEVEL      0x81U
-#endif
- 
-//       <e.7>Memory Pool
-//       <i> Recording level for Memory Pool events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MEMPOOL_LEVEL
-#define OS_EVR_MEMPOOL_LEVEL        0x81U
-#endif
- 
-//       <e.7>Message Queue
-//       <i> Recording level for Message Queue events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MSGQUEUE_LEVEL
-#define OS_EVR_MSGQUEUE_LEVEL       0x81U
-#endif
- 
-//     </h>
- 
-//   </e>
- 
-//   <h>RTOS Event Generation
-//   <i> Enables event generation for RTX components (requires RTX source variant).
- 
-//     <q>Memory Management
-//     <i> Enables Memory Management event generation.
-#ifndef OS_EVR_MEMORY
-#define OS_EVR_MEMORY               1
-#endif
- 
-//     <q>Kernel
-//     <i> Enables Kernel event generation.
-#ifndef OS_EVR_KERNEL
-#define OS_EVR_KERNEL               1
-#endif
- 
-//     <q>Thread
-//     <i> Enables Thread event generation.
-#ifndef OS_EVR_THREAD
-#define OS_EVR_THREAD               1
-#endif
- 
-//     <q>Generic Wait
-//     <i> Enables Generic Wait event generation.
-#ifndef OS_EVR_WAIT
-#define OS_EVR_WAIT                 1
-#endif
- 
-//     <q>Thread Flags
-//     <i> Enables Thread Flags event generation.
-#ifndef OS_EVR_THFLAGS
-#define OS_EVR_THFLAGS              1
-#endif
- 
-//     <q>Event Flags
-//     <i> Enables Event Flags event generation.
-#ifndef OS_EVR_EVFLAGS
-#define OS_EVR_EVFLAGS              1
-#endif
- 
-//     <q>Timer
-//     <i> Enables Timer event generation.
-#ifndef OS_EVR_TIMER
-#define OS_EVR_TIMER                1
-#endif
- 
-//     <q>Mutex
-//     <i> Enables Mutex event generation.
-#ifndef OS_EVR_MUTEX
-#define OS_EVR_MUTEX                1
-#endif
- 
-//     <q>Semaphore
-//     <i> Enables Semaphore event generation.
-#ifndef OS_EVR_SEMAPHORE
-#define OS_EVR_SEMAPHORE            1
-#endif
- 
-//     <q>Memory Pool
-//     <i> Enables Memory Pool event generation.
-#ifndef OS_EVR_MEMPOOL
-#define OS_EVR_MEMPOOL              1
-#endif
- 
-//     <q>Message Queue
-//     <i> Enables Message Queue event generation.
-#ifndef OS_EVR_MSGQUEUE
-#define OS_EVR_MSGQUEUE             1
-#endif
- 
-//   </h>
- 
-// </h>
- 
-// Number of Threads which use standard C/C++ library libspace
-// (when thread specific memory allocation is not used).
-#if (OS_THREAD_OBJ_MEM == 0)
-#ifndef OS_THREAD_LIBSPACE_NUM
-#define OS_THREAD_LIBSPACE_NUM      4
-#endif
-#else
-#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
-#endif
- 
-//------------- <<< end of configuration section >>> ---------------------------
- 
-#endif  // RTX_CONFIG_H_

ComputeGraph/examples/eventrecorder/RTE/CMSIS/RTX_Config.h.base@5.5.2

@@ -1,580 +0,0 @@
-/*
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * $Revision:   V5.5.2
- *
- * Project:     CMSIS-RTOS RTX
- * Title:       RTX Configuration definitions
- *
- * -----------------------------------------------------------------------------
- */
- 
-#ifndef RTX_CONFIG_H_
-#define RTX_CONFIG_H_
- 
-#ifdef   _RTE_
-#include "RTE_Components.h"
-#ifdef    RTE_RTX_CONFIG_H
-#include  RTE_RTX_CONFIG_H
-#endif
-#endif
- 
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
- 
-// <h>System Configuration
-// =======================
- 
-//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
-//   <i> Defines the combined global dynamic memory size.
-//   <i> Default: 32768
-#ifndef OS_DYNAMIC_MEM_SIZE
-#define OS_DYNAMIC_MEM_SIZE         32768
-#endif
- 
-//   <o>Kernel Tick Frequency [Hz] <1-1000000>
-//   <i> Defines base time unit for delays and timeouts.
-//   <i> Default: 1000 (1ms tick)
-#ifndef OS_TICK_FREQ
-#define OS_TICK_FREQ                1000
-#endif
- 
-//   <e>Round-Robin Thread switching
-//   <i> Enables Round-Robin Thread switching.
-#ifndef OS_ROBIN_ENABLE
-#define OS_ROBIN_ENABLE             1
-#endif
- 
-//     <o>Round-Robin Timeout <1-1000>
-//     <i> Defines how many ticks a thread will execute before a thread switch.
-//     <i> Default: 5
-#ifndef OS_ROBIN_TIMEOUT
-#define OS_ROBIN_TIMEOUT            5
-#endif
- 
-//   </e>
- 
-//   <o>ISR FIFO Queue
-//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
-//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
-//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
-//   <i> RTOS Functions called from ISR store requests to this buffer.
-//   <i> Default: 16 entries
-#ifndef OS_ISR_FIFO_QUEUE
-#define OS_ISR_FIFO_QUEUE           16
-#endif
- 
-//   <q>Object Memory usage counters
-//   <i> Enables object memory usage counters (requires RTX source variant).
-#ifndef OS_OBJ_MEM_USAGE
-#define OS_OBJ_MEM_USAGE            0
-#endif
- 
-// </h>
- 
-// <h>Thread Configuration
-// =======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_THREAD_OBJ_MEM
-#define OS_THREAD_OBJ_MEM           0
-#endif
- 
-//     <o>Number of user Threads <1-1000>
-//     <i> Defines maximum number of user threads that can be active at the same time.
-//     <i> Applies to user threads with system provided memory for control blocks.
-#ifndef OS_THREAD_NUM
-#define OS_THREAD_NUM               1
-#endif
- 
-//     <o>Number of user Threads with default Stack size <0-1000>
-//     <i> Defines maximum number of user threads with default stack size.
-//     <i> Applies to user threads with zero stack size specified.
-#ifndef OS_THREAD_DEF_STACK_NUM
-#define OS_THREAD_DEF_STACK_NUM     0
-#endif
- 
-//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
-//     <i> Defines the combined stack size for user threads with user-provided stack size.
-//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
-//     <i> Default: 0
-#ifndef OS_THREAD_USER_STACK_SIZE
-#define OS_THREAD_USER_STACK_SIZE   0
-#endif
- 
-//   </e>
- 
-//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
-//   <i> Defines stack size for threads with zero stack size specified.
-//   <i> Default: 3072
-#ifndef OS_STACK_SIZE
-#define OS_STACK_SIZE               3072
-#endif
- 
-//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
-//   <i> Defines stack size for Idle thread.
-//   <i> Default: 512
-#ifndef OS_IDLE_THREAD_STACK_SIZE
-#define OS_IDLE_THREAD_STACK_SIZE   512
-#endif
- 
-//   <o>Idle Thread TrustZone Module Identifier
-//   <i> Defines TrustZone Thread Context Management Identifier.
-//   <i> Applies only to cores with TrustZone technology.
-//   <i> Default: 0 (not used)
-#ifndef OS_IDLE_THREAD_TZ_MOD_ID
-#define OS_IDLE_THREAD_TZ_MOD_ID    0
-#endif
- 
-//   <q>Stack overrun checking
-//   <i> Enables stack overrun check at thread switch (requires RTX source variant).
-//   <i> Enabling this option increases slightly the execution time of a thread switch.
-#ifndef OS_STACK_CHECK
-#define OS_STACK_CHECK              0
-#endif
- 
-//   <q>Stack usage watermark
-//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.
-//   <i> Enabling this option increases significantly the execution time of thread creation.
-#ifndef OS_STACK_WATERMARK
-#define OS_STACK_WATERMARK          0
-#endif
- 
-//   <o>Processor mode for Thread execution
-//     <0=> Unprivileged mode
-//     <1=> Privileged mode
-//   <i> Default: Privileged mode
-#ifndef OS_PRIVILEGE_MODE
-#define OS_PRIVILEGE_MODE           1
-#endif
- 
-// </h>
- 
-// <h>Timer Configuration
-// ======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_TIMER_OBJ_MEM
-#define OS_TIMER_OBJ_MEM            0
-#endif
- 
-//     <o>Number of Timer objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_TIMER_NUM
-#define OS_TIMER_NUM                1
-#endif
- 
-//   </e>
- 
-//   <o>Timer Thread Priority
-//      <8=> Low
-//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
-//     <40=> High
-//     <48=> Realtime
-//   <i> Defines priority for timer thread
-//   <i> Default: High
-#ifndef OS_TIMER_THREAD_PRIO
-#define OS_TIMER_THREAD_PRIO        40
-#endif
- 
-//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
-//   <i> Defines stack size for Timer thread.
-//   <i> May be set to 0 when timers are not used.
-//   <i> Default: 512
-#ifndef OS_TIMER_THREAD_STACK_SIZE
-#define OS_TIMER_THREAD_STACK_SIZE  512
-#endif
- 
-//   <o>Timer Thread TrustZone Module Identifier
-//   <i> Defines TrustZone Thread Context Management Identifier.
-//   <i> Applies only to cores with TrustZone technology.
-//   <i> Default: 0 (not used)
-#ifndef OS_TIMER_THREAD_TZ_MOD_ID
-#define OS_TIMER_THREAD_TZ_MOD_ID   0
-#endif
- 
-//   <o>Timer Callback Queue entries <0-256>
-//   <i> Number of concurrent active timer callback functions.
-//   <i> May be set to 0 when timers are not used.
-//   <i> Default: 4
-#ifndef OS_TIMER_CB_QUEUE
-#define OS_TIMER_CB_QUEUE           4
-#endif
- 
-// </h>
- 
-// <h>Event Flags Configuration
-// ============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_EVFLAGS_OBJ_MEM
-#define OS_EVFLAGS_OBJ_MEM          0
-#endif
- 
-//     <o>Number of Event Flags objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_EVFLAGS_NUM
-#define OS_EVFLAGS_NUM              1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Mutex Configuration
-// ======================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MUTEX_OBJ_MEM
-#define OS_MUTEX_OBJ_MEM            0
-#endif
- 
-//     <o>Number of Mutex objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MUTEX_NUM
-#define OS_MUTEX_NUM                1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Semaphore Configuration
-// ==========================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_SEMAPHORE_OBJ_MEM
-#define OS_SEMAPHORE_OBJ_MEM        0
-#endif
- 
-//     <o>Number of Semaphore objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_SEMAPHORE_NUM
-#define OS_SEMAPHORE_NUM            1
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Memory Pool Configuration
-// ============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MEMPOOL_OBJ_MEM
-#define OS_MEMPOOL_OBJ_MEM          0
-#endif
- 
-//     <o>Number of Memory Pool objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MEMPOOL_NUM
-#define OS_MEMPOOL_NUM              1
-#endif
- 
-//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
-//     <i> Defines the combined data storage memory size.
-//     <i> Applies to objects with system provided memory for data storage.
-//     <i> Default: 0
-#ifndef OS_MEMPOOL_DATA_SIZE
-#define OS_MEMPOOL_DATA_SIZE        0
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Message Queue Configuration
-// ==============================
- 
-//   <e>Object specific Memory allocation
-//   <i> Enables object specific memory allocation.
-#ifndef OS_MSGQUEUE_OBJ_MEM
-#define OS_MSGQUEUE_OBJ_MEM         0
-#endif
- 
-//     <o>Number of Message Queue objects <1-1000>
-//     <i> Defines maximum number of objects that can be active at the same time.
-//     <i> Applies to objects with system provided memory for control blocks.
-#ifndef OS_MSGQUEUE_NUM
-#define OS_MSGQUEUE_NUM             1
-#endif
- 
-//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
-//     <i> Defines the combined data storage memory size.
-//     <i> Applies to objects with system provided memory for data storage.
-//     <i> Default: 0
-#ifndef OS_MSGQUEUE_DATA_SIZE
-#define OS_MSGQUEUE_DATA_SIZE       0
-#endif
- 
-//   </e>
- 
-// </h>
- 
-// <h>Event Recorder Configuration
-// ===============================
- 
-//   <e>Global Initialization
-//   <i> Initialize Event Recorder during 'osKernelInitialize'.
-#ifndef OS_EVR_INIT
-#define OS_EVR_INIT                 0
-#endif
- 
-//     <q>Start recording
-//     <i> Start event recording after initialization.
-#ifndef OS_EVR_START
-#define OS_EVR_START                1
-#endif
- 
-//     <h>Global Event Filter Setup
-//     <i> Initial recording level applied to all components.
-//       <o.0>Error events
-//       <o.1>API function call events
-//       <o.2>Operation events
-//       <o.3>Detailed operation events
-//     </h>
-#ifndef OS_EVR_LEVEL
-#define OS_EVR_LEVEL                0x00U
-#endif
- 
-//     <h>RTOS Event Filter Setup
-//     <i> Recording levels for RTX components.
-//     <i> Only applicable if events for the respective component are generated.
- 
-//       <e.7>Memory Management
-//       <i> Recording level for Memory Management events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MEMORY_LEVEL
-#define OS_EVR_MEMORY_LEVEL         0x81U
-#endif
- 
-//       <e.7>Kernel
-//       <i> Recording level for Kernel events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_KERNEL_LEVEL
-#define OS_EVR_KERNEL_LEVEL         0x81U
-#endif
- 
-//       <e.7>Thread
-//       <i> Recording level for Thread events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_THREAD_LEVEL
-#define OS_EVR_THREAD_LEVEL         0x85U
-#endif
- 
-//       <e.7>Generic Wait
-//       <i> Recording level for Generic Wait events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_WAIT_LEVEL
-#define OS_EVR_WAIT_LEVEL           0x81U
-#endif
- 
-//       <e.7>Thread Flags
-//       <i> Recording level for Thread Flags events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_THFLAGS_LEVEL
-#define OS_EVR_THFLAGS_LEVEL        0x81U
-#endif
- 
-//       <e.7>Event Flags
-//       <i> Recording level for Event Flags events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_EVFLAGS_LEVEL
-#define OS_EVR_EVFLAGS_LEVEL        0x81U
-#endif
- 
-//       <e.7>Timer
-//       <i> Recording level for Timer events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_TIMER_LEVEL
-#define OS_EVR_TIMER_LEVEL          0x81U
-#endif
- 
-//       <e.7>Mutex
-//       <i> Recording level for Mutex events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MUTEX_LEVEL
-#define OS_EVR_MUTEX_LEVEL          0x81U
-#endif
- 
-//       <e.7>Semaphore
-//       <i> Recording level for Semaphore events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_SEMAPHORE_LEVEL
-#define OS_EVR_SEMAPHORE_LEVEL      0x81U
-#endif
- 
-//       <e.7>Memory Pool
-//       <i> Recording level for Memory Pool events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MEMPOOL_LEVEL
-#define OS_EVR_MEMPOOL_LEVEL        0x81U
-#endif
- 
-//       <e.7>Message Queue
-//       <i> Recording level for Message Queue events.
-//         <o.0>Error events
-//         <o.1>API function call events
-//         <o.2>Operation events
-//         <o.3>Detailed operation events
-//       </e>
-#ifndef OS_EVR_MSGQUEUE_LEVEL
-#define OS_EVR_MSGQUEUE_LEVEL       0x81U
-#endif
- 
-//     </h>
- 
-//   </e>
- 
-//   <h>RTOS Event Generation
-//   <i> Enables event generation for RTX components (requires RTX source variant).
- 
-//     <q>Memory Management
-//     <i> Enables Memory Management event generation.
-#ifndef OS_EVR_MEMORY
-#define OS_EVR_MEMORY               1
-#endif
- 
-//     <q>Kernel
-//     <i> Enables Kernel event generation.
-#ifndef OS_EVR_KERNEL
-#define OS_EVR_KERNEL               1
-#endif
- 
-//     <q>Thread
-//     <i> Enables Thread event generation.
-#ifndef OS_EVR_THREAD
-#define OS_EVR_THREAD               1
-#endif
- 
-//     <q>Generic Wait
-//     <i> Enables Generic Wait event generation.
-#ifndef OS_EVR_WAIT
-#define OS_EVR_WAIT                 1
-#endif
- 
-//     <q>Thread Flags
-//     <i> Enables Thread Flags event generation.
-#ifndef OS_EVR_THFLAGS
-#define OS_EVR_THFLAGS              1
-#endif
- 
-//     <q>Event Flags
-//     <i> Enables Event Flags event generation.
-#ifndef OS_EVR_EVFLAGS
-#define OS_EVR_EVFLAGS              1
-#endif
- 
-//     <q>Timer
-//     <i> Enables Timer event generation.
-#ifndef OS_EVR_TIMER
-#define OS_EVR_TIMER                1
-#endif
- 
-//     <q>Mutex
-//     <i> Enables Mutex event generation.
-#ifndef OS_EVR_MUTEX
-#define OS_EVR_MUTEX                1
-#endif
- 
-//     <q>Semaphore
-//     <i> Enables Semaphore event generation.
-#ifndef OS_EVR_SEMAPHORE
-#define OS_EVR_SEMAPHORE            1
-#endif
- 
-//     <q>Memory Pool
-//     <i> Enables Memory Pool event generation.
-#ifndef OS_EVR_MEMPOOL
-#define OS_EVR_MEMPOOL              1
-#endif
- 
-//     <q>Message Queue
-//     <i> Enables Message Queue event generation.
-#ifndef OS_EVR_MSGQUEUE
-#define OS_EVR_MSGQUEUE             1
-#endif
- 
-//   </h>
- 
-// </h>
- 
-// Number of Threads which use standard C/C++ library libspace
-// (when thread specific memory allocation is not used).
-#if (OS_THREAD_OBJ_MEM == 0)
-#ifndef OS_THREAD_LIBSPACE_NUM
-#define OS_THREAD_LIBSPACE_NUM      4
-#endif
-#else
-#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
-#endif
- 
-//------------- <<< end of configuration section >>> ---------------------------
- 
-#endif  // RTX_CONFIG_H_

ComputeGraph/examples/eventrecorder/RTE/Compiler/EventRecorderConf.h

@@ -1,34 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK - Component ::Event Recorder
- * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    EventRecorderConf.h
- * Purpose: Event Recorder Configuration
- * Rev.:    V1.1.0
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>Event Recorder
-
-//   <o>Number of Records
-//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
-//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
-//     <65536=>65536
-//   <i>Configures size of Event Record Buffer (each record is 16 bytes)
-//   <i>Must be 2^n (min=8, max=65536)
-#define EVENT_RECORD_COUNT      64U
-
-//   <o>Time Stamp Source
-//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer
-//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
-//   <i>Selects source for 32-bit time stamp
-#define EVENT_TIMESTAMP_SOURCE  0
-
-//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
-//   <i>Defines initial time stamp clock frequency (0 when not used)
-#define EVENT_TIMESTAMP_FREQ    50000000U
-
-// </h>
-
-//------------- <<< end of configuration section >>> ---------------------------

ComputeGraph/examples/eventrecorder/RTE/Compiler/EventRecorderConf.h.base@1.1.0

@@ -1,34 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK - Component ::Event Recorder
- * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    EventRecorderConf.h
- * Purpose: Event Recorder Configuration
- * Rev.:    V1.1.0
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>Event Recorder
-
-//   <o>Number of Records
-//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
-//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
-//     <65536=>65536
-//   <i>Configures size of Event Record Buffer (each record is 16 bytes)
-//   <i>Must be 2^n (min=8, max=65536)
-#define EVENT_RECORD_COUNT      64U
-
-//   <o>Time Stamp Source
-//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer
-//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
-//   <i>Selects source for 32-bit time stamp
-#define EVENT_TIMESTAMP_SOURCE  0
-
-//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
-//   <i>Defines initial time stamp clock frequency (0 when not used)
-#define EVENT_TIMESTAMP_FREQ    0U
-
-// </h>
-
-//------------- <<< end of configuration section >>> ---------------------------

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/RTE_Device.h

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
-// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
-#define   RTE_USART0                     1
-
-// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
-// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
-#define   RTE_USART1                     1
-
-// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
-// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
-#define   RTE_ISRAM0_MPC                 1
-
-// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
-// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
-#define   RTE_ISRAM1_MPC                 1
-
-// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
-// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
-#define   RTE_SRAM_MPC                   1
-
-// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
-// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
-#define   RTE_QSPI_MPC                   1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN_EXP0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN_EXP1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP2             1
-
-// <q> Flash device emulated by SRAM [Driver_Flash0]
-// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
-#define   RTE_FLASH0                     1
-
-// <q> I2C SBCon [Driver_I2C0]
-// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
-#define   RTE_I2C0                    1
-
-#endif  /* __RTE_DEVICE_H */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
-// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
-#define   RTE_USART0                     1
-
-// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
-// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
-#define   RTE_USART1                     1
-
-// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
-// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
-#define   RTE_ISRAM0_MPC                 1
-
-// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
-// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
-#define   RTE_ISRAM1_MPC                 1
-
-// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
-// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
-#define   RTE_SRAM_MPC                   1
-
-// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
-// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
-#define   RTE_QSPI_MPC                   1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN_EXP0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
-// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_MAIN_EXP1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP0             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP1             1
-
-// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
-// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
-#define   RTE_PPC_SSE300_PERIPH_EXP2             1
-
-// <q> Flash device emulated by SRAM [Driver_Flash0]
-// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
-#define   RTE_FLASH0                     1
-
-// <q> I2C SBCon [Driver_I2C0]
-// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
-#define   RTE_I2C0                    1
-
-#endif  /* __RTE_DEVICE_H */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h

@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_DRIVER_CONFIG_H__
-#define __CMSIS_DRIVER_CONFIG_H__
-
-#include "system_SSE300MPS3.h"
-#include "device_cfg.h"
-#include "device_definition.h"
-#include "platform_base_address.h"
-
-#endif  /* __CMSIS_DRIVER_CONFIG_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1

@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_DRIVER_CONFIG_H__
-#define __CMSIS_DRIVER_CONFIG_H__
-
-#include "system_SSE300MPS3.h"
-#include "device_cfg.h"
-#include "device_definition.h"
-#include "platform_base_address.h"
-
-#endif  /* __CMSIS_DRIVER_CONFIG_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/device_cfg.h

@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DEVICE_CFG_H__
-#define __DEVICE_CFG_H__
-
-/**
- * \file device_cfg.h
- * \brief Configuration file native driver re-targeting
- *
- * \details This file can be used to add native driver specific macro
- *          definitions to select which peripherals are available in the build.
- *
- * This is a default device configuration file with all peripherals enabled.
- */
-
-/* Secure only peripheral configuration */
-
-/* ARM MPS3 IO SCC */
-#define MPS3_IO_S
-#define MPS3_IO_DEV                 MPS3_IO_DEV_S
-
-/* I2C_SBCon */
-#define I2C0_SBCON_S
-#define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
-
-/* I2S */
-#define MPS3_I2S_S
-#define MPS3_I2S_DEV                MPS3_I2S_DEV_S
-
-/* ARM UART Controller PL011 */
-#define UART0_CMSDK_S
-#define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
-#define UART1_CMSDK_S
-#define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
-
-#define DEFAULT_UART_BAUDRATE    115200U
-
-/* To be used as CODE and DATA sram */
-#define MPC_ISRAM0_S
-#define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
-
-#define MPC_ISRAM1_S
-#define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
-
-#define MPC_SRAM_S
-#define MPC_SRAM_DEV                MPC_SRAM_DEV_S
-
-#define MPC_QSPI_S
-#define MPC_QSPI_DEV                MPC_QSPI_DEV_S
-
-/** System Counter Armv8-M */
-#define SYSCOUNTER_CNTRL_ARMV8_M_S
-#define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
-
-#define SYSCOUNTER_READ_ARMV8_M_S
-#define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
-/**
- * Arbitrary scaling values for test purposes
- */
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
-
-/* System timer */
-#define SYSTIMER0_ARMV8_M_S
-#define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
-#define SYSTIMER1_ARMV8_M_S
-#define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
-#define SYSTIMER2_ARMV8_M_S
-#define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
-#define SYSTIMER3_ARMV8_M_S
-#define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
-
-#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-
-/* CMSDK GPIO driver structures */
-#define GPIO0_CMSDK_S
-#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
-#define GPIO1_CMSDK_S
-#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
-#define GPIO2_CMSDK_S
-#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
-#define GPIO3_CMSDK_S
-#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
-
-/* System Watchdogs */
-#define SYSWDOG_ARMV8_M_S
-#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
-
-/* ARM MPC SIE 300 driver structures */
-#define MPC_VM0_S
-#define MPC_VM0_DEV MPC_VM0_DEV_S
-#define MPC_VM1_S
-#define MPC_VM1_DEV MPC_VM1_DEV_S
-#define MPC_SSRAM2_S
-#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
-#define MPC_SSRAM3_S
-#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
-
-/* ARM PPC driver structures */
-#define PPC_SSE300_MAIN0_S
-#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
-#define PPC_SSE300_MAIN_EXP0_S
-#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
-#define PPC_SSE300_MAIN_EXP1_S
-#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
-#define PPC_SSE300_MAIN_EXP2_S
-#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
-#define PPC_SSE300_MAIN_EXP3_S
-#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
-#define PPC_SSE300_PERIPH0_S
-#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
-#define PPC_SSE300_PERIPH1_S
-#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
-#define PPC_SSE300_PERIPH_EXP0_S
-#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
-#define PPC_SSE300_PERIPH_EXP1_S
-#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
-#define PPC_SSE300_PERIPH_EXP2_S
-#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
-#define PPC_SSE300_PERIPH_EXP3_S
-#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
-
-/* ARM SPI PL022 */
-/* Invalid device stubs are not defined */
-#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
-#define SPI1_PL022_S
-#define SPI1_PL022_DEV SPI1_PL022_DEV_S
-
-
-#endif  /* __DEVICE_CFG_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3

@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DEVICE_CFG_H__
-#define __DEVICE_CFG_H__
-
-/**
- * \file device_cfg.h
- * \brief Configuration file native driver re-targeting
- *
- * \details This file can be used to add native driver specific macro
- *          definitions to select which peripherals are available in the build.
- *
- * This is a default device configuration file with all peripherals enabled.
- */
-
-/* Secure only peripheral configuration */
-
-/* ARM MPS3 IO SCC */
-#define MPS3_IO_S
-#define MPS3_IO_DEV                 MPS3_IO_DEV_S
-
-/* I2C_SBCon */
-#define I2C0_SBCON_S
-#define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
-
-/* I2S */
-#define MPS3_I2S_S
-#define MPS3_I2S_DEV                MPS3_I2S_DEV_S
-
-/* ARM UART Controller PL011 */
-#define UART0_CMSDK_S
-#define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
-#define UART1_CMSDK_S
-#define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
-
-#define DEFAULT_UART_BAUDRATE    115200U
-
-/* To be used as CODE and DATA sram */
-#define MPC_ISRAM0_S
-#define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
-
-#define MPC_ISRAM1_S
-#define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
-
-#define MPC_SRAM_S
-#define MPC_SRAM_DEV                MPC_SRAM_DEV_S
-
-#define MPC_QSPI_S
-#define MPC_QSPI_DEV                MPC_QSPI_DEV_S
-
-/** System Counter Armv8-M */
-#define SYSCOUNTER_CNTRL_ARMV8_M_S
-#define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
-
-#define SYSCOUNTER_READ_ARMV8_M_S
-#define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
-/**
- * Arbitrary scaling values for test purposes
- */
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
-#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
-
-/* System timer */
-#define SYSTIMER0_ARMV8_M_S
-#define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
-#define SYSTIMER1_ARMV8_M_S
-#define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
-#define SYSTIMER2_ARMV8_M_S
-#define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
-#define SYSTIMER3_ARMV8_M_S
-#define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
-
-#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
-
-/* CMSDK GPIO driver structures */
-#define GPIO0_CMSDK_S
-#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
-#define GPIO1_CMSDK_S
-#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
-#define GPIO2_CMSDK_S
-#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
-#define GPIO3_CMSDK_S
-#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
-
-/* System Watchdogs */
-#define SYSWDOG_ARMV8_M_S
-#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
-
-/* ARM MPC SIE 300 driver structures */
-#define MPC_VM0_S
-#define MPC_VM0_DEV MPC_VM0_DEV_S
-#define MPC_VM1_S
-#define MPC_VM1_DEV MPC_VM1_DEV_S
-#define MPC_SSRAM2_S
-#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
-#define MPC_SSRAM3_S
-#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
-
-/* ARM PPC driver structures */
-#define PPC_SSE300_MAIN0_S
-#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
-#define PPC_SSE300_MAIN_EXP0_S
-#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
-#define PPC_SSE300_MAIN_EXP1_S
-#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
-#define PPC_SSE300_MAIN_EXP2_S
-#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
-#define PPC_SSE300_MAIN_EXP3_S
-#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
-#define PPC_SSE300_PERIPH0_S
-#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
-#define PPC_SSE300_PERIPH1_S
-#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
-#define PPC_SSE300_PERIPH_EXP0_S
-#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
-#define PPC_SSE300_PERIPH_EXP1_S
-#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
-#define PPC_SSE300_PERIPH_EXP2_S
-#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
-#define PPC_SSE300_PERIPH_EXP3_S
-#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
-
-/* ARM SPI PL022 */
-/* Invalid device stubs are not defined */
-#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
-#define SPI1_PL022_S
-#define SPI1_PL022_DEV SPI1_PL022_DEV_S
-
-
-#endif  /* __DEVICE_CFG_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct

@@ -1,78 +0,0 @@
-#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
-
-;/*
-; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; *     http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; */
-
-#include "region_defs.h"
-
-LR_CODE S_CODE_START {
-    ER_CODE S_CODE_START {
-        *.o (RESET +First)
-        .ANY (+RO)
-    }
-
-    /*
-     * Place the CMSE Veneers (containing the SG instruction) after the code, in
-     * a separate 32 bytes aligned region so that the SAU can programmed to just
-     * set this region as Non-Secure Callable. The maximum size of this
-     * executable region makes it only used the space left over by the ER_CODE
-     * region so that you can rely on code+veneer size combined will not exceed
-     * the S_CODE_SIZE value. We also substract from the available space the
-     * area used to align this section on 32 bytes boundary (for SAU conf).
-     */
-    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
-        *(Veneer$$CMSE)
-    }
-    /*
-     * This dummy region ensures that the next one will be aligned on a 32 bytes
-     * boundary, so that the following region will not be mistakenly configured
-     * as Non-Secure Callable by the SAU.
-     */
-    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
-
-    /* This empty, zero long execution region is here to mark the limit address
-     * of the last execution region that is allocated in SRAM.
-     */
-    CODE_WATERMARK +0 EMPTY 0x0 {
-    }
-    /* Make sure that the sections allocated in the SRAM does not exceed the
-     * size of the SRAM available.
-     */
-    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
-
-    ER_DATA S_DATA_START {
-        .ANY (+ZI +RW)
-    }
-
-    #if HEAP_SIZE > 0
-    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
-    }
-    #endif
-
-    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
-    }
-
-    /* This empty, zero long execution region is here to mark the limit address
-     * of the last execution region that is allocated in SRAM.
-     */
-    SRAM_WATERMARK +0 EMPTY 0x0 {
-    }
-    /* Make sure that the sections allocated in the SRAM does not exceed the
-     * size of the SRAM available.
-     */
-    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
-}

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0

@@ -1,78 +0,0 @@
-#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
-
-;/*
-; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; *     http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; */
-
-#include "region_defs.h"
-
-LR_CODE S_CODE_START {
-    ER_CODE S_CODE_START {
-        *.o (RESET +First)
-        .ANY (+RO)
-    }
-
-    /*
-     * Place the CMSE Veneers (containing the SG instruction) after the code, in
-     * a separate 32 bytes aligned region so that the SAU can programmed to just
-     * set this region as Non-Secure Callable. The maximum size of this
-     * executable region makes it only used the space left over by the ER_CODE
-     * region so that you can rely on code+veneer size combined will not exceed
-     * the S_CODE_SIZE value. We also substract from the available space the
-     * area used to align this section on 32 bytes boundary (for SAU conf).
-     */
-    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
-        *(Veneer$$CMSE)
-    }
-    /*
-     * This dummy region ensures that the next one will be aligned on a 32 bytes
-     * boundary, so that the following region will not be mistakenly configured
-     * as Non-Secure Callable by the SAU.
-     */
-    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
-
-    /* This empty, zero long execution region is here to mark the limit address
-     * of the last execution region that is allocated in SRAM.
-     */
-    CODE_WATERMARK +0 EMPTY 0x0 {
-    }
-    /* Make sure that the sections allocated in the SRAM does not exceed the
-     * size of the SRAM available.
-     */
-    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
-
-    ER_DATA S_DATA_START {
-        .ANY (+ZI +RW)
-    }
-
-    #if HEAP_SIZE > 0
-    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
-    }
-    #endif
-
-    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
-    }
-
-    /* This empty, zero long execution region is here to mark the limit address
-     * of the last execution region that is allocated in SRAM.
-     */
-    SRAM_WATERMARK +0 EMPTY 0x0 {
-    }
-    /* Make sure that the sections allocated in the SRAM does not exceed the
-     * size of the SRAM available.
-     */
-    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
-}

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/platform_base_address.h

@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2019-2021 Arm Limited
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * \file platform_base_address.h
- * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
- *        Ethos-U55 platform.
- */
-
-#ifndef __PLATFORM_BASE_ADDRESS_H__
-#define __PLATFORM_BASE_ADDRESS_H__
-
-/* ======= Defines peripherals memory map addresses ======= */
-/* Non-secure memory map addresses */
-#define ITCM_BASE_NS                     0x00000000 /* Instruction TCM Non-Secure base address */
-#define SRAM_BASE_NS                     0x01000000 /* CODE SRAM Non-Secure base address */
-#define DTCM0_BASE_NS                    0x20000000 /* Data TCM block 0 Non-Secure base address */
-#define DTCM1_BASE_NS                    0x20020000 /* Data TCM block 1 Non-Secure base address */
-#define DTCM2_BASE_NS                    0x20040000 /* Data TCM block 2 Non-Secure base address */
-#define DTCM3_BASE_NS                    0x20060000 /* Data TCM block 3 Non-Secure base address */
-#define ISRAM0_BASE_NS                   0x21000000 /* Internal SRAM Area Non-Secure base address */
-#define ISRAM1_BASE_NS                   0x21100000 /* Internal SRAM Area Non-Secure base address */
-#define QSPI_SRAM_BASE_NS                0x28000000 /* QSPI SRAM Non-Secure base address */
-/* Non-Secure Subsystem peripheral region */
-#define CPU0_PWRCTRL_BASE_NS             0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
-#define CPU0_IDENTITY_BASE_NS            0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
-#define SSE300_NSACFG_BASE_NS            0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
-/* Non-Secure MSTEXPPILL Peripheral region */
-#define GPIO0_CMSDK_BASE_NS              0x41100000 /* GPIO 0 Non-Secure base address */
-#define GPIO1_CMSDK_BASE_NS              0x41101000 /* GPIO 1 Non-Secure base address */
-#define GPIO2_CMSDK_BASE_NS              0x41102000 /* GPIO 2 Non-Secure base address */
-#define GPIO3_CMSDK_BASE_NS              0x41103000 /* GPIO 3 Non-Secure base address */
-#define FMC_CMSDK_GPIO_0_BASE_NS         0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
-#define FMC_CMSDK_GPIO_1_BASE_NS         0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
-#define FMC_CMSDK_GPIO_2_BASE_NS         0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
-#define FMC_CMSDK_GPIO_3_BASE_NS         0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
-#define EXTERNAL_MANAGER_0_BASE_NS       0x41200000 /* External manager 0 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_1_BASE_NS       0x41201000 /* External manager 1 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_2_BASE_NS       0x41202000 /* External manager 2 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_3_BASE_NS       0x41203000 /* External manager 3 (Unused) Non-Secure base address */
-#define ETHERNET_BASE_NS                 0x41400000 /* Ethernet Non-Secure base address */
-#define USB_BASE_NS                      0x41500000 /* USB Non-Secure base address */
-#define USER_APB0_BASE_NS                0x41700000 /* User APB 0 Non-Secure base address */
-#define USER_APB1_BASE_NS                0x41701000 /* User APB 1 Non-Secure base address */
-#define USER_APB2_BASE_NS                0x41702000 /* User APB 2 Non-Secure base address */
-#define USER_APB3_BASE_NS                0x41703000 /* User APB 3 Non-Secure base address */
-#define QSPI_CONFIG_BASE_NS              0x41800000 /* QSPI Config Non-Secure base address */
-#define QSPI_WRITE_BASE_NS               0x41801000 /* QSPI Write Non-Secure base address */
-/* Non-Secure Subsystem peripheral region */
-#define SYSTIMER0_ARMV8_M_BASE_NS        0x48000000 /* System Timer 0 Non-Secure base address */
-#define SYSTIMER1_ARMV8_M_BASE_NS        0x48001000 /* System Timer 1 Non-Secure base address */
-#define SYSTIMER2_ARMV8_M_BASE_NS        0x48002000 /* System Timer 2 Non-Secure base address */
-#define SYSTIMER3_ARMV8_M_BASE_NS        0x48003000 /* System Timer 3 Non-Secure base address */
-#define SSE300_SYSINFO_BASE_NS           0x48020000 /* SSE-300 System info Block Non-Secure base address */
-#define SLOWCLK_TIMER_CMSDK_BASE_NS      0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
-#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS    0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
-#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS  0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
-#define SYSCNTR_READ_BASE_NS             0x48101000 /* System Counter Read Secure base address */
-/* Non-Secure MSTEXPPIHL Peripheral region */
-#define ETHOS_U55_APB_BASE_NS            0x48102000 /* Ethos-U55 APB Non-Secure base address */
-#define U55_TIMING_ADAPTER_0_BASE_NS     0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
-#define U55_TIMING_ADAPTER_1_BASE_NS     0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
-#define FPGA_SBCon_I2C_TOUCH_BASE_NS     0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
-#define FPGA_SBCon_I2C_AUDIO_BASE_NS     0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
-#define FPGA_SPI_ADC_BASE_NS             0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
-#define FPGA_SPI_SHIELD0_BASE_NS         0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
-#define FPGA_SPI_SHIELD1_BASE_NS         0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
-#define SBCon_I2C_SHIELD0_BASE_NS        0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
-#define SBCon_I2C_SHIELD1_BASE_NS        0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
-#define USER_APB_BASE_NS                 0x49207000 /* USER APB Non-Secure base address */
-#define FPGA_DDR4_EEPROM_BASE_NS         0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
-#define FMC_USER_APB0                    0x4920C000 /* FMC User APB0 */
-#define FMC_USER_APB1                    0x4920D000 /* FMC User APB1 */
-#define FMC_USER_APB2                    0x4920E000 /* FMC User APB2 */
-#define FMC_USER_APB3                    0x4920F000 /* FMC User APB3 */
-#define FPGA_SCC_BASE_NS                 0x49300000 /* FPGA - SCC registers Non-Secure base address */
-#define FPGA_I2S_BASE_NS                 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
-#define FPGA_IO_BASE_NS                  0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
-#define UART0_BASE_NS                    0x49303000 /* UART 0 Non-Secure base address */
-#define UART1_BASE_NS                    0x49304000 /* UART 1 Non-Secure base address */
-#define UART2_BASE_NS                    0x49305000 /* UART 2 Non-Secure base address */
-#define UART3_BASE_NS                    0x49306000 /* UART 3 Non-Secure base address */
-#define UART4_BASE_NS                    0x49307000 /* UART 4 Non-Secure base address */
-#define UART5_BASE_NS                    0x49308000 /* UART 5 Non-Secure base address */
-#define CLCD_Config_Reg_BASE_NS          0x4930A000 /* CLCD Config Reg Non-Secure base address */
-#define RTC_BASE_NS                      0x4930B000 /* RTC Non-Secure base address */
-#define DDR4_BLK0_BASE_NS                0x60000000 /* DDR4 block 0 Non-Secure base address */
-#define DDR4_BLK2_BASE_NS                0x80000000 /* DDR4 block 2 Non-Secure base address */
-#define DDR4_BLK4_BASE_NS                0xA0000000 /* DDR4 block 4 Non-Secure base address */
-#define DDR4_BLK6_BASE_NS                0xC0000000 /* DDR4 block 6 Non-Secure base address */
-
-/* Secure memory map addresses */
-#define ITCM_BASE_S                      0x10000000 /* Instruction TCM Secure base address */
-#define SRAM_BASE_S                      0x11000000 /* CODE SRAM Secure base address */
-#define DTCM0_BASE_S                     0x30000000 /* Data TCM block 0 Secure base address */
-#define DTCM1_BASE_S                     0x30020000 /* Data TCM block 1 Secure base address */
-#define DTCM2_BASE_S                     0x30040000 /* Data TCM block 2 Secure base address */
-#define DTCM3_BASE_S                     0x30060000 /* Data TCM block 3 Secure base address */
-#define ISRAM0_BASE_S                    0x31000000 /* Internal SRAM Area Secure base address */
-#define ISRAM1_BASE_S                    0x31100000 /* Internal SRAM Area Secure base address */
-#define QSPI_SRAM_BASE_S                 0x38000000 /* QSPI SRAM Secure base address */
-/* Secure Subsystem peripheral region */
-#define CPU0_SECCTRL_BASE_S              0x50011000 /* CPU 0 Local Security Control Block Secure base address */
-#define CPU0_PWRCTRL_BASE_S              0x50012000 /* CPU 0 Power Control Block Secure base address */
-#define CPU0_IDENTITY_BASE_S             0x5001F000 /* CPU 0 Identity Block Secure base address */
-#define SSE300_SACFG_BASE_S              0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
-#define MPC_ISRAM0_BASE_S                0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
-#define MPC_ISRAM1_BASE_S                0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
-/* Secure MSTEXPPILL Peripheral region */
-#define GPIO0_CMSDK_BASE_S               0x51100000 /* GPIO 0 Secure base address */
-#define GPIO1_CMSDK_BASE_S               0x51101000 /* GPIO 1 Secure base address */
-#define GPIO2_CMSDK_BASE_S               0x51102000 /* GPIO 2 Secure base address */
-#define GPIO3_CMSDK_BASE_S               0x51103000 /* GPIO 3 Secure base address */
-#define FMC_CMSDK_GPIO_0_BASE_S          0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
-#define FMC_CMSDK_GPIO_1_BASE_S          0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
-#define FMC_CMSDK_GPIO_2_BASE_S          0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
-#define FMC_CMSDK_GPIO_3_BASE_S          0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
-#define EXTERNAL_MANAGER0_BASE_S         0x51200000 /* External Manager 0 (Unused) Secure base address */
-#define EXTERNAL_MANAGER1_BASE_S         0x51201000 /* External Manager 1 (Unused) Secure base address */
-#define EXTERNAL_MANAGER2_BASE_S         0x51202000 /* External Manager 2 (Unused) Secure base address */
-#define EXTERNAL_MANAGER3_BASE_S         0x51203000 /* External Manager 3 (Unused) Secure base address */
-#define ETHERNET_BASE_S                  0x51400000 /* Ethernet Secure base address */
-#define USB_BASE_S                       0x51500000 /* USB Secure base address */
-#define USER_APB0_BASE_S                 0x51700000 /* User APB 0 Secure base address */
-#define USER_APB1_BASE_S                 0x51701000 /* User APB 1 Secure base address */
-#define USER_APB2_BASE_S                 0x51702000 /* User APB 2 Secure base address */
-#define USER_APB3_BASE_S                 0x51703000 /* User APB 3 Secure base address */
-#define QSPI_CONFIG_BASE_S               0x51800000 /* QSPI Config Secure base address */
-#define QSPI_WRITE_BASE_S                0x51801000 /* QSPI Write Secure base address */
-#define MPC_SRAM_BASE_S                  0x57000000 /* SRAM Memory Protection Controller Secure base address */
-#define MPC_QSPI_BASE_S                  0x57001000 /* QSPI Memory Protection Controller Secure base address */
-#define MPC_DDR4_BASE_S                  0x57002000 /* DDR4 Memory Protection Controller Secure base address */
-/* Secure Subsystem peripheral region */
-#define SYSTIMER0_ARMV8_M_BASE_S         0x58000000 /* System Timer 0 Secure base address */
-#define SYSTIMER1_ARMV8_M_BASE_S         0x58001000 /* System Timer 1 Secure base address */
-#define SYSTIMER2_ARMV8_M_BASE_S         0x58002000 /* System Timer 0 Secure base address */
-#define SYSTIMER3_ARMV8_M_BASE_S         0x58003000 /* System Timer 1 Secure base address */
-#define SSE300_SYSINFO_BASE_S            0x58020000 /* SSE-300 System info Block Secure base address */
-#define SSE300_SYSCTRL_BASE_S            0x58021000 /* SSE-300 System control Block Secure base address */
-#define SSE300_SYSPPU_BASE_S             0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
-#define SSE300_CPU0PPU_BASE_S            0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
-#define SSE300_MGMTPPU_BASE_S            0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
-#define SSE300_DBGPPU_BASE_S             0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
-#define SLOWCLK_WDOG_CMSDK_BASE_S        0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
-#define SLOWCLK_TIMER_CMSDK_BASE_S       0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
-#define SYSWDOG_ARMV8_M_CNTRL_BASE_S     0x58040000 /* Secure Watchdog Timer control frame Secure base address */
-#define SYSWDOG_ARMV8_M_REFRESH_BASE_S   0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
-#define SYSCNTR_CNTRL_BASE_S             0x58100000 /* System Counter Control Secure base address */
-#define SYSCNTR_READ_BASE_S              0x58101000 /* System Counter Read Secure base address */
-/* Secure MSTEXPPIHL Peripheral region */
-#define ETHOS_U55_APB_BASE_S             0x58102000 /* Ethos-U55 APB Secure base address */
-#define U55_TIMING_ADAPTER_0_BASE_S      0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
-#define U55_TIMING_ADAPTER_1_BASE_S      0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
-#define FPGA_SBCon_I2C_TOUCH_BASE_S      0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
-#define FPGA_SBCon_I2C_AUDIO_BASE_S      0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
-#define FPGA_SPI_ADC_BASE_S              0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
-#define FPGA_SPI_SHIELD0_BASE_S          0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
-#define FPGA_SPI_SHIELD1_BASE_S          0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
-#define SBCon_I2C_SHIELD0_BASE_S         0x59205000 /* SBCon (I2C - Shield0) Secure base address */
-#define SBCon_I2C_SHIELD1_BASE_S         0x59206000 /* SBCon (I2C – Shield1) Secure base address */
-#define USER_APB_BASE_S                  0x59207000 /* USER APB Secure base address */
-#define FPGA_DDR4_EEPROM_BASE_S          0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
-#define FMC_USER_APB_0_BASE_S            0x5920C000 /* FMC User APB0 registers Secure base address */
-#define FMC_USER_APB_1_BASE_S            0x5920D000 /* FMC User APB1 registers Secure base address */
-#define FMC_USER_APB_2_BASE_S            0x5920E000 /* FMC User APB2 registers Secure base address */
-#define FMC_USER_APB_3_BASE_S            0x5920F000 /* FMC User APB3 registers Secure base address */
-#define FPGA_SCC_BASE_S                  0x59300000 /* FPGA - SCC registers Secure base address */
-#define FPGA_I2S_BASE_S                  0x59301000 /* FPGA - I2S (Audio) Secure base address */
-#define FPGA_IO_BASE_S                   0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
-#define UART0_BASE_S                     0x59303000 /* UART 0 Secure base address */
-#define UART1_BASE_S                     0x59304000 /* UART 1 Secure base address */
-#define UART2_BASE_S                     0x59305000 /* UART 2 Secure base address */
-#define UART3_BASE_S                     0x59306000 /* UART 3 Secure base address */
-#define UART4_BASE_S                     0x59307000 /* UART 4 Secure base address */
-#define UART5_BASE_S                     0x59308000 /* UART 5 Secure base address */
-#define CLCD_Config_Reg_BASE_S           0x5930A000 /* CLCD Config Reg Secure base address */
-#define RTC_BASE_S                       0x5930B000 /* RTC Secure base address */
-#define DDR4_BLK1_BASE_S                 0x70000000 /* DDR4 block 1 Secure base address */
-#define DDR4_BLK3_BASE_S                 0x90000000 /* DDR4 block 3 Secure base address */
-#define DDR4_BLK5_BASE_S                 0xB0000000 /* DDR4 block 5 Secure base address */
-#define DDR4_BLK7_BASE_S                 0xD0000000 /* DDR4 block 7 Secure base address */
-
-/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
-#define SSE300_EWIC_BASE                 0xE0047000 /* External Wakeup Interrupt Controller
-                                                     * Access from Non-secure software is only allowed
-                                                     * if AIRCR.BFHFNMINS is set to 1 */
-
-/* Memory size definitions */
-#define ITCM_SIZE       (0x00080000) /* 512 kB */
-#define DTCM_BLK_SIZE   (0x00020000) /* 128 kB */
-#define DTCM_BLK_NUM    (0x4)        /* Number of DTCM blocks */
-#define SRAM_SIZE       (0x00100000) /* 1 MB */
-#define ISRAM0_SIZE     (0x00100000) /* 1 MB */
-#define ISRAM1_SIZE     (0x00100000) /* 1 MB */
-#define QSPI_SRAM_SIZE  (0x00800000) /* 8 MB */
-#define DDR4_BLK_SIZE   (0x10000000) /* 256 MB */
-#define DDR4_BLK_NUM    (0x8)        /* Number of DDR4 blocks */
-
-/* Defines for Driver MPC's */
-/* SRAM -- 2 MB */
-#define MPC_SRAM_RANGE_BASE_NS   (SRAM_BASE_NS)
-#define MPC_SRAM_RANGE_LIMIT_NS  (SRAM_BASE_NS + SRAM_SIZE-1)
-#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
-#define MPC_SRAM_RANGE_BASE_S    (SRAM_BASE_S)
-#define MPC_SRAM_RANGE_LIMIT_S   (SRAM_BASE_S + SRAM_SIZE-1)
-#define MPC_SRAM_RANGE_OFFSET_S  (0x0)
-
-/* QSPI -- 8 MB*/
-#define MPC_QSPI_RANGE_BASE_NS   (QSPI_SRAM_BASE_NS)
-#define MPC_QSPI_RANGE_LIMIT_NS  (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
-#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
-#define MPC_QSPI_RANGE_BASE_S    (QSPI_SRAM_BASE_S)
-#define MPC_QSPI_RANGE_LIMIT_S   (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
-#define MPC_QSPI_RANGE_OFFSET_S  (0x0)
-
-/* ISRAM0 -- 2 MB*/
-#define MPC_ISRAM0_RANGE_BASE_NS   (ISRAM0_BASE_NS)
-#define MPC_ISRAM0_RANGE_LIMIT_NS  (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
-#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
-#define MPC_ISRAM0_RANGE_BASE_S    (ISRAM0_BASE_S)
-#define MPC_ISRAM0_RANGE_LIMIT_S   (ISRAM0_BASE_S + ISRAM0_SIZE-1)
-#define MPC_ISRAM0_RANGE_OFFSET_S  (0x0)
-
-/* ISRAM1 -- 2 MB*/
-#define MPC_ISRAM1_RANGE_BASE_NS   (ISRAM1_BASE_NS)
-#define MPC_ISRAM1_RANGE_LIMIT_NS  (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
-#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
-#define MPC_ISRAM1_RANGE_BASE_S    (ISRAM1_BASE_S)
-#define MPC_ISRAM1_RANGE_LIMIT_S   (ISRAM1_BASE_S + ISRAM1_SIZE-1)
-#define MPC_ISRAM1_RANGE_OFFSET_S  (0x0)
-
-/* DDR4 -- 2GB (8 * 256 MB) */
-#define MPC_DDR4_BLK0_RANGE_BASE_NS   (DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK0_RANGE_LIMIT_NS  (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
-#define MPC_DDR4_BLK1_RANGE_BASE_S    (DDR4_BLK1_BASE_S)
-#define MPC_DDR4_BLK1_RANGE_LIMIT_S   (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK1_RANGE_OFFSET_S  (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK2_RANGE_BASE_NS   (DDR4_BLK2_BASE_NS)
-#define MPC_DDR4_BLK2_RANGE_LIMIT_NS  (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK3_RANGE_BASE_S    (DDR4_BLK3_BASE_S)
-#define MPC_DDR4_BLK3_RANGE_LIMIT_S   (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK3_RANGE_OFFSET_S  (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK4_RANGE_BASE_NS   (DDR4_BLK4_BASE_NS)
-#define MPC_DDR4_BLK4_RANGE_LIMIT_NS  (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK5_RANGE_BASE_S    (DDR4_BLK5_BASE_S)
-#define MPC_DDR4_BLK5_RANGE_LIMIT_S   (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK5_RANGE_OFFSET_S  (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK6_RANGE_BASE_NS   (DDR4_BLK6_BASE_NS)
-#define MPC_DDR4_BLK6_RANGE_LIMIT_NS  (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK7_RANGE_BASE_S    (DDR4_BLK7_BASE_S)
-#define MPC_DDR4_BLK7_RANGE_LIMIT_S   (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK7_RANGE_OFFSET_S  (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
-
-#endif  /* __PLATFORM_BASE_ADDRESS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2

@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2019-2021 Arm Limited
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * \file platform_base_address.h
- * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
- *        Ethos-U55 platform.
- */
-
-#ifndef __PLATFORM_BASE_ADDRESS_H__
-#define __PLATFORM_BASE_ADDRESS_H__
-
-/* ======= Defines peripherals memory map addresses ======= */
-/* Non-secure memory map addresses */
-#define ITCM_BASE_NS                     0x00000000 /* Instruction TCM Non-Secure base address */
-#define SRAM_BASE_NS                     0x01000000 /* CODE SRAM Non-Secure base address */
-#define DTCM0_BASE_NS                    0x20000000 /* Data TCM block 0 Non-Secure base address */
-#define DTCM1_BASE_NS                    0x20020000 /* Data TCM block 1 Non-Secure base address */
-#define DTCM2_BASE_NS                    0x20040000 /* Data TCM block 2 Non-Secure base address */
-#define DTCM3_BASE_NS                    0x20060000 /* Data TCM block 3 Non-Secure base address */
-#define ISRAM0_BASE_NS                   0x21000000 /* Internal SRAM Area Non-Secure base address */
-#define ISRAM1_BASE_NS                   0x21100000 /* Internal SRAM Area Non-Secure base address */
-#define QSPI_SRAM_BASE_NS                0x28000000 /* QSPI SRAM Non-Secure base address */
-/* Non-Secure Subsystem peripheral region */
-#define CPU0_PWRCTRL_BASE_NS             0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
-#define CPU0_IDENTITY_BASE_NS            0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
-#define SSE300_NSACFG_BASE_NS            0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
-/* Non-Secure MSTEXPPILL Peripheral region */
-#define GPIO0_CMSDK_BASE_NS              0x41100000 /* GPIO 0 Non-Secure base address */
-#define GPIO1_CMSDK_BASE_NS              0x41101000 /* GPIO 1 Non-Secure base address */
-#define GPIO2_CMSDK_BASE_NS              0x41102000 /* GPIO 2 Non-Secure base address */
-#define GPIO3_CMSDK_BASE_NS              0x41103000 /* GPIO 3 Non-Secure base address */
-#define FMC_CMSDK_GPIO_0_BASE_NS         0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
-#define FMC_CMSDK_GPIO_1_BASE_NS         0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
-#define FMC_CMSDK_GPIO_2_BASE_NS         0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
-#define FMC_CMSDK_GPIO_3_BASE_NS         0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
-#define EXTERNAL_MANAGER_0_BASE_NS       0x41200000 /* External manager 0 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_1_BASE_NS       0x41201000 /* External manager 1 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_2_BASE_NS       0x41202000 /* External manager 2 (Unused) Non-Secure base address */
-#define EXTERNAL_MANAGER_3_BASE_NS       0x41203000 /* External manager 3 (Unused) Non-Secure base address */
-#define ETHERNET_BASE_NS                 0x41400000 /* Ethernet Non-Secure base address */
-#define USB_BASE_NS                      0x41500000 /* USB Non-Secure base address */
-#define USER_APB0_BASE_NS                0x41700000 /* User APB 0 Non-Secure base address */
-#define USER_APB1_BASE_NS                0x41701000 /* User APB 1 Non-Secure base address */
-#define USER_APB2_BASE_NS                0x41702000 /* User APB 2 Non-Secure base address */
-#define USER_APB3_BASE_NS                0x41703000 /* User APB 3 Non-Secure base address */
-#define QSPI_CONFIG_BASE_NS              0x41800000 /* QSPI Config Non-Secure base address */
-#define QSPI_WRITE_BASE_NS               0x41801000 /* QSPI Write Non-Secure base address */
-/* Non-Secure Subsystem peripheral region */
-#define SYSTIMER0_ARMV8_M_BASE_NS        0x48000000 /* System Timer 0 Non-Secure base address */
-#define SYSTIMER1_ARMV8_M_BASE_NS        0x48001000 /* System Timer 1 Non-Secure base address */
-#define SYSTIMER2_ARMV8_M_BASE_NS        0x48002000 /* System Timer 2 Non-Secure base address */
-#define SYSTIMER3_ARMV8_M_BASE_NS        0x48003000 /* System Timer 3 Non-Secure base address */
-#define SSE300_SYSINFO_BASE_NS           0x48020000 /* SSE-300 System info Block Non-Secure base address */
-#define SLOWCLK_TIMER_CMSDK_BASE_NS      0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
-#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS    0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
-#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS  0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
-#define SYSCNTR_READ_BASE_NS             0x48101000 /* System Counter Read Secure base address */
-/* Non-Secure MSTEXPPIHL Peripheral region */
-#define ETHOS_U55_APB_BASE_NS            0x48102000 /* Ethos-U55 APB Non-Secure base address */
-#define U55_TIMING_ADAPTER_0_BASE_NS     0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
-#define U55_TIMING_ADAPTER_1_BASE_NS     0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
-#define FPGA_SBCon_I2C_TOUCH_BASE_NS     0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
-#define FPGA_SBCon_I2C_AUDIO_BASE_NS     0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
-#define FPGA_SPI_ADC_BASE_NS             0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
-#define FPGA_SPI_SHIELD0_BASE_NS         0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
-#define FPGA_SPI_SHIELD1_BASE_NS         0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
-#define SBCon_I2C_SHIELD0_BASE_NS        0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
-#define SBCon_I2C_SHIELD1_BASE_NS        0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
-#define USER_APB_BASE_NS                 0x49207000 /* USER APB Non-Secure base address */
-#define FPGA_DDR4_EEPROM_BASE_NS         0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
-#define FMC_USER_APB0                    0x4920C000 /* FMC User APB0 */
-#define FMC_USER_APB1                    0x4920D000 /* FMC User APB1 */
-#define FMC_USER_APB2                    0x4920E000 /* FMC User APB2 */
-#define FMC_USER_APB3                    0x4920F000 /* FMC User APB3 */
-#define FPGA_SCC_BASE_NS                 0x49300000 /* FPGA - SCC registers Non-Secure base address */
-#define FPGA_I2S_BASE_NS                 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
-#define FPGA_IO_BASE_NS                  0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
-#define UART0_BASE_NS                    0x49303000 /* UART 0 Non-Secure base address */
-#define UART1_BASE_NS                    0x49304000 /* UART 1 Non-Secure base address */
-#define UART2_BASE_NS                    0x49305000 /* UART 2 Non-Secure base address */
-#define UART3_BASE_NS                    0x49306000 /* UART 3 Non-Secure base address */
-#define UART4_BASE_NS                    0x49307000 /* UART 4 Non-Secure base address */
-#define UART5_BASE_NS                    0x49308000 /* UART 5 Non-Secure base address */
-#define CLCD_Config_Reg_BASE_NS          0x4930A000 /* CLCD Config Reg Non-Secure base address */
-#define RTC_BASE_NS                      0x4930B000 /* RTC Non-Secure base address */
-#define DDR4_BLK0_BASE_NS                0x60000000 /* DDR4 block 0 Non-Secure base address */
-#define DDR4_BLK2_BASE_NS                0x80000000 /* DDR4 block 2 Non-Secure base address */
-#define DDR4_BLK4_BASE_NS                0xA0000000 /* DDR4 block 4 Non-Secure base address */
-#define DDR4_BLK6_BASE_NS                0xC0000000 /* DDR4 block 6 Non-Secure base address */
-
-/* Secure memory map addresses */
-#define ITCM_BASE_S                      0x10000000 /* Instruction TCM Secure base address */
-#define SRAM_BASE_S                      0x11000000 /* CODE SRAM Secure base address */
-#define DTCM0_BASE_S                     0x30000000 /* Data TCM block 0 Secure base address */
-#define DTCM1_BASE_S                     0x30020000 /* Data TCM block 1 Secure base address */
-#define DTCM2_BASE_S                     0x30040000 /* Data TCM block 2 Secure base address */
-#define DTCM3_BASE_S                     0x30060000 /* Data TCM block 3 Secure base address */
-#define ISRAM0_BASE_S                    0x31000000 /* Internal SRAM Area Secure base address */
-#define ISRAM1_BASE_S                    0x31100000 /* Internal SRAM Area Secure base address */
-#define QSPI_SRAM_BASE_S                 0x38000000 /* QSPI SRAM Secure base address */
-/* Secure Subsystem peripheral region */
-#define CPU0_SECCTRL_BASE_S              0x50011000 /* CPU 0 Local Security Control Block Secure base address */
-#define CPU0_PWRCTRL_BASE_S              0x50012000 /* CPU 0 Power Control Block Secure base address */
-#define CPU0_IDENTITY_BASE_S             0x5001F000 /* CPU 0 Identity Block Secure base address */
-#define SSE300_SACFG_BASE_S              0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
-#define MPC_ISRAM0_BASE_S                0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
-#define MPC_ISRAM1_BASE_S                0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
-/* Secure MSTEXPPILL Peripheral region */
-#define GPIO0_CMSDK_BASE_S               0x51100000 /* GPIO 0 Secure base address */
-#define GPIO1_CMSDK_BASE_S               0x51101000 /* GPIO 1 Secure base address */
-#define GPIO2_CMSDK_BASE_S               0x51102000 /* GPIO 2 Secure base address */
-#define GPIO3_CMSDK_BASE_S               0x51103000 /* GPIO 3 Secure base address */
-#define FMC_CMSDK_GPIO_0_BASE_S          0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
-#define FMC_CMSDK_GPIO_1_BASE_S          0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
-#define FMC_CMSDK_GPIO_2_BASE_S          0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
-#define FMC_CMSDK_GPIO_3_BASE_S          0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
-#define EXTERNAL_MANAGER0_BASE_S         0x51200000 /* External Manager 0 (Unused) Secure base address */
-#define EXTERNAL_MANAGER1_BASE_S         0x51201000 /* External Manager 1 (Unused) Secure base address */
-#define EXTERNAL_MANAGER2_BASE_S         0x51202000 /* External Manager 2 (Unused) Secure base address */
-#define EXTERNAL_MANAGER3_BASE_S         0x51203000 /* External Manager 3 (Unused) Secure base address */
-#define ETHERNET_BASE_S                  0x51400000 /* Ethernet Secure base address */
-#define USB_BASE_S                       0x51500000 /* USB Secure base address */
-#define USER_APB0_BASE_S                 0x51700000 /* User APB 0 Secure base address */
-#define USER_APB1_BASE_S                 0x51701000 /* User APB 1 Secure base address */
-#define USER_APB2_BASE_S                 0x51702000 /* User APB 2 Secure base address */
-#define USER_APB3_BASE_S                 0x51703000 /* User APB 3 Secure base address */
-#define QSPI_CONFIG_BASE_S               0x51800000 /* QSPI Config Secure base address */
-#define QSPI_WRITE_BASE_S                0x51801000 /* QSPI Write Secure base address */
-#define MPC_SRAM_BASE_S                  0x57000000 /* SRAM Memory Protection Controller Secure base address */
-#define MPC_QSPI_BASE_S                  0x57001000 /* QSPI Memory Protection Controller Secure base address */
-#define MPC_DDR4_BASE_S                  0x57002000 /* DDR4 Memory Protection Controller Secure base address */
-/* Secure Subsystem peripheral region */
-#define SYSTIMER0_ARMV8_M_BASE_S         0x58000000 /* System Timer 0 Secure base address */
-#define SYSTIMER1_ARMV8_M_BASE_S         0x58001000 /* System Timer 1 Secure base address */
-#define SYSTIMER2_ARMV8_M_BASE_S         0x58002000 /* System Timer 0 Secure base address */
-#define SYSTIMER3_ARMV8_M_BASE_S         0x58003000 /* System Timer 1 Secure base address */
-#define SSE300_SYSINFO_BASE_S            0x58020000 /* SSE-300 System info Block Secure base address */
-#define SSE300_SYSCTRL_BASE_S            0x58021000 /* SSE-300 System control Block Secure base address */
-#define SSE300_SYSPPU_BASE_S             0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
-#define SSE300_CPU0PPU_BASE_S            0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
-#define SSE300_MGMTPPU_BASE_S            0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
-#define SSE300_DBGPPU_BASE_S             0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
-#define SLOWCLK_WDOG_CMSDK_BASE_S        0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
-#define SLOWCLK_TIMER_CMSDK_BASE_S       0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
-#define SYSWDOG_ARMV8_M_CNTRL_BASE_S     0x58040000 /* Secure Watchdog Timer control frame Secure base address */
-#define SYSWDOG_ARMV8_M_REFRESH_BASE_S   0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
-#define SYSCNTR_CNTRL_BASE_S             0x58100000 /* System Counter Control Secure base address */
-#define SYSCNTR_READ_BASE_S              0x58101000 /* System Counter Read Secure base address */
-/* Secure MSTEXPPIHL Peripheral region */
-#define ETHOS_U55_APB_BASE_S             0x58102000 /* Ethos-U55 APB Secure base address */
-#define U55_TIMING_ADAPTER_0_BASE_S      0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
-#define U55_TIMING_ADAPTER_1_BASE_S      0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
-#define FPGA_SBCon_I2C_TOUCH_BASE_S      0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
-#define FPGA_SBCon_I2C_AUDIO_BASE_S      0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
-#define FPGA_SPI_ADC_BASE_S              0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
-#define FPGA_SPI_SHIELD0_BASE_S          0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
-#define FPGA_SPI_SHIELD1_BASE_S          0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
-#define SBCon_I2C_SHIELD0_BASE_S         0x59205000 /* SBCon (I2C - Shield0) Secure base address */
-#define SBCon_I2C_SHIELD1_BASE_S         0x59206000 /* SBCon (I2C – Shield1) Secure base address */
-#define USER_APB_BASE_S                  0x59207000 /* USER APB Secure base address */
-#define FPGA_DDR4_EEPROM_BASE_S          0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
-#define FMC_USER_APB_0_BASE_S            0x5920C000 /* FMC User APB0 registers Secure base address */
-#define FMC_USER_APB_1_BASE_S            0x5920D000 /* FMC User APB1 registers Secure base address */
-#define FMC_USER_APB_2_BASE_S            0x5920E000 /* FMC User APB2 registers Secure base address */
-#define FMC_USER_APB_3_BASE_S            0x5920F000 /* FMC User APB3 registers Secure base address */
-#define FPGA_SCC_BASE_S                  0x59300000 /* FPGA - SCC registers Secure base address */
-#define FPGA_I2S_BASE_S                  0x59301000 /* FPGA - I2S (Audio) Secure base address */
-#define FPGA_IO_BASE_S                   0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
-#define UART0_BASE_S                     0x59303000 /* UART 0 Secure base address */
-#define UART1_BASE_S                     0x59304000 /* UART 1 Secure base address */
-#define UART2_BASE_S                     0x59305000 /* UART 2 Secure base address */
-#define UART3_BASE_S                     0x59306000 /* UART 3 Secure base address */
-#define UART4_BASE_S                     0x59307000 /* UART 4 Secure base address */
-#define UART5_BASE_S                     0x59308000 /* UART 5 Secure base address */
-#define CLCD_Config_Reg_BASE_S           0x5930A000 /* CLCD Config Reg Secure base address */
-#define RTC_BASE_S                       0x5930B000 /* RTC Secure base address */
-#define DDR4_BLK1_BASE_S                 0x70000000 /* DDR4 block 1 Secure base address */
-#define DDR4_BLK3_BASE_S                 0x90000000 /* DDR4 block 3 Secure base address */
-#define DDR4_BLK5_BASE_S                 0xB0000000 /* DDR4 block 5 Secure base address */
-#define DDR4_BLK7_BASE_S                 0xD0000000 /* DDR4 block 7 Secure base address */
-
-/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
-#define SSE300_EWIC_BASE                 0xE0047000 /* External Wakeup Interrupt Controller
-                                                     * Access from Non-secure software is only allowed
-                                                     * if AIRCR.BFHFNMINS is set to 1 */
-
-/* Memory size definitions */
-#define ITCM_SIZE       (0x00080000) /* 512 kB */
-#define DTCM_BLK_SIZE   (0x00020000) /* 128 kB */
-#define DTCM_BLK_NUM    (0x4)        /* Number of DTCM blocks */
-#define SRAM_SIZE       (0x00100000) /* 1 MB */
-#define ISRAM0_SIZE     (0x00100000) /* 1 MB */
-#define ISRAM1_SIZE     (0x00100000) /* 1 MB */
-#define QSPI_SRAM_SIZE  (0x00800000) /* 8 MB */
-#define DDR4_BLK_SIZE   (0x10000000) /* 256 MB */
-#define DDR4_BLK_NUM    (0x8)        /* Number of DDR4 blocks */
-
-/* Defines for Driver MPC's */
-/* SRAM -- 2 MB */
-#define MPC_SRAM_RANGE_BASE_NS   (SRAM_BASE_NS)
-#define MPC_SRAM_RANGE_LIMIT_NS  (SRAM_BASE_NS + SRAM_SIZE-1)
-#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
-#define MPC_SRAM_RANGE_BASE_S    (SRAM_BASE_S)
-#define MPC_SRAM_RANGE_LIMIT_S   (SRAM_BASE_S + SRAM_SIZE-1)
-#define MPC_SRAM_RANGE_OFFSET_S  (0x0)
-
-/* QSPI -- 8 MB*/
-#define MPC_QSPI_RANGE_BASE_NS   (QSPI_SRAM_BASE_NS)
-#define MPC_QSPI_RANGE_LIMIT_NS  (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
-#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
-#define MPC_QSPI_RANGE_BASE_S    (QSPI_SRAM_BASE_S)
-#define MPC_QSPI_RANGE_LIMIT_S   (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
-#define MPC_QSPI_RANGE_OFFSET_S  (0x0)
-
-/* ISRAM0 -- 2 MB*/
-#define MPC_ISRAM0_RANGE_BASE_NS   (ISRAM0_BASE_NS)
-#define MPC_ISRAM0_RANGE_LIMIT_NS  (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
-#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
-#define MPC_ISRAM0_RANGE_BASE_S    (ISRAM0_BASE_S)
-#define MPC_ISRAM0_RANGE_LIMIT_S   (ISRAM0_BASE_S + ISRAM0_SIZE-1)
-#define MPC_ISRAM0_RANGE_OFFSET_S  (0x0)
-
-/* ISRAM1 -- 2 MB*/
-#define MPC_ISRAM1_RANGE_BASE_NS   (ISRAM1_BASE_NS)
-#define MPC_ISRAM1_RANGE_LIMIT_NS  (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
-#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
-#define MPC_ISRAM1_RANGE_BASE_S    (ISRAM1_BASE_S)
-#define MPC_ISRAM1_RANGE_LIMIT_S   (ISRAM1_BASE_S + ISRAM1_SIZE-1)
-#define MPC_ISRAM1_RANGE_OFFSET_S  (0x0)
-
-/* DDR4 -- 2GB (8 * 256 MB) */
-#define MPC_DDR4_BLK0_RANGE_BASE_NS   (DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK0_RANGE_LIMIT_NS  (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
-#define MPC_DDR4_BLK1_RANGE_BASE_S    (DDR4_BLK1_BASE_S)
-#define MPC_DDR4_BLK1_RANGE_LIMIT_S   (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK1_RANGE_OFFSET_S  (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK2_RANGE_BASE_NS   (DDR4_BLK2_BASE_NS)
-#define MPC_DDR4_BLK2_RANGE_LIMIT_NS  (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK3_RANGE_BASE_S    (DDR4_BLK3_BASE_S)
-#define MPC_DDR4_BLK3_RANGE_LIMIT_S   (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK3_RANGE_OFFSET_S  (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK4_RANGE_BASE_NS   (DDR4_BLK4_BASE_NS)
-#define MPC_DDR4_BLK4_RANGE_LIMIT_NS  (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK5_RANGE_BASE_S    (DDR4_BLK5_BASE_S)
-#define MPC_DDR4_BLK5_RANGE_LIMIT_S   (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK5_RANGE_OFFSET_S  (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK6_RANGE_BASE_NS   (DDR4_BLK6_BASE_NS)
-#define MPC_DDR4_BLK6_RANGE_LIMIT_NS  (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_BLK7_RANGE_BASE_S    (DDR4_BLK7_BASE_S)
-#define MPC_DDR4_BLK7_RANGE_LIMIT_S   (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_BLK7_RANGE_OFFSET_S  (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
-
-#endif  /* __PLATFORM_BASE_ADDRESS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/region_defs.h

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Arm Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __REGION_DEFS_H__
-#define __REGION_DEFS_H__
-
-#include "region_limits.h"
-
-/* **************************************************************
- * WARNING: this file is parsed both by the C/C++ compiler
- * and the linker. As a result the syntax must be valid not only
- * for C/C++ but for the linker scripts too.
- * Beware of the following limitations:
- *   - LD (GCC linker) requires white space around operators.
- *   - UL postfix for macros is not suported by the linker script
- ****************************************************************/
-
-/* Secure regions */
-#define S_CODE_START     ( S_ROM_ALIAS )
-#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
-#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
-
-#define S_DATA_START     ( S_RAM_ALIAS )
-#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
-#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
-
-#define S_DDR4_START     ( S_DDR4_ALIAS )
-#define S_DDR4_SIZE      ( TOTAL_S_DDR4_SIZE )
-#define S_DDR4_LIMIT     ( S_DDR4_START + S_DDR4_SIZE )
-
-#endif /* __REGION_DEFS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Arm Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __REGION_DEFS_H__
-#define __REGION_DEFS_H__
-
-#include "region_limits.h"
-
-/* **************************************************************
- * WARNING: this file is parsed both by the C/C++ compiler
- * and the linker. As a result the syntax must be valid not only
- * for C/C++ but for the linker scripts too.
- * Beware of the following limitations:
- *   - LD (GCC linker) requires white space around operators.
- *   - UL postfix for macros is not suported by the linker script
- ****************************************************************/
-
-/* Secure regions */
-#define S_CODE_START     ( S_ROM_ALIAS )
-#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
-#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
-
-#define S_DATA_START     ( S_RAM_ALIAS )
-#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
-#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
-
-#define S_DDR4_START     ( S_DDR4_ALIAS )
-#define S_DDR4_SIZE      ( TOTAL_S_DDR4_SIZE )
-#define S_DDR4_LIMIT     ( S_DDR4_START + S_DDR4_SIZE )
-
-#endif /* __REGION_DEFS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/region_limits.h

@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2018-2022 Arm Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __REGION_LIMITS_H__
-#define __REGION_LIMITS_H__
-
-/* **************************************************************
- * WARNING: this file is parsed both by the C/C++ compiler
- * and the linker. As a result the syntax must be valid not only
- * for C/C++ but for the linker scripts too.
- * Beware of the following limitations:
- *   - LD (GCC linker) requires white space around operators.
- *   - UL postfix for macros is not suported by the linker script
- ****************************************************************/
-
-/* Secure Code */
-#define S_ROM_ALIAS               (0x10000000) /* ITCM_BASE_S */
-#define TOTAL_S_ROM_SIZE          (0x00080000) /* 512 kB */
-
-/* Secure Data */
-#define S_RAM_ALIAS               (0x30000000) /* DTCM_BASE_S */
-#define TOTAL_S_RAM_SIZE          (0x00080000) /* 512 kB */
-
-/* Secure DDR4 */
-#define S_DDR4_ALIAS              (0x70000000) /* DDR4_BLK1_BASE_S */
-#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */
-
-/* Heap and Stack sizes for secure and nonsecure applications */
-#define HEAP_SIZE                 (0x00000400) /* 1 KiB */
-#define STACK_SIZE                (0x00000400) /* 1 KiB */
-
-#endif /* __REGION_LIMITS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0

@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2018-2022 Arm Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __REGION_LIMITS_H__
-#define __REGION_LIMITS_H__
-
-/* **************************************************************
- * WARNING: this file is parsed both by the C/C++ compiler
- * and the linker. As a result the syntax must be valid not only
- * for C/C++ but for the linker scripts too.
- * Beware of the following limitations:
- *   - LD (GCC linker) requires white space around operators.
- *   - UL postfix for macros is not suported by the linker script
- ****************************************************************/
-
-/* Secure Code */
-#define S_ROM_ALIAS               (0x10000000) /* ITCM_BASE_S */
-#define TOTAL_S_ROM_SIZE          (0x00080000) /* 512 kB */
-
-/* Secure Data */
-#define S_RAM_ALIAS               (0x30000000) /* DTCM_BASE_S */
-#define TOTAL_S_RAM_SIZE          (0x00080000) /* 512 kB */
-
-/* Secure DDR4 */
-#define S_DDR4_ALIAS              (0x70000000) /* DDR4_BLK1_BASE_S */
-#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */
-
-/* Heap and Stack sizes for secure and nonsecure applications */
-#define HEAP_SIZE                 (0x00000400) /* 1 KiB */
-#define STACK_SIZE                (0x00000400) /* 1 KiB */
-
-#endif /* __REGION_LIMITS_H__ */

ComputeGraph/examples/eventrecorder/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c

@@ -1,344 +0,0 @@
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
- * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
- */
-
-#include "SSE300MPS3.h"
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-/*----------------------------------------------------------------------------
-  External References
- *----------------------------------------------------------------------------*/
-extern uint32_t __INITIAL_SP;
-extern uint32_t __STACK_LIMIT;
-
-extern void __PROGRAM_START(void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
-  Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler  (void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-#define DEFAULT_IRQ_HANDLER(handler_name)  \
-void __WEAK __NO_RETURN handler_name(void); \
-void handler_name(void) { \
-    while(1); \
-}
-
-/* Exceptions */
-DEFAULT_IRQ_HANDLER(NMI_Handler)
-DEFAULT_IRQ_HANDLER(HardFault_Handler)
-DEFAULT_IRQ_HANDLER(MemManage_Handler)
-DEFAULT_IRQ_HANDLER(BusFault_Handler)
-DEFAULT_IRQ_HANDLER(UsageFault_Handler)
-DEFAULT_IRQ_HANDLER(SecureFault_Handler)
-DEFAULT_IRQ_HANDLER(SVC_Handler)
-DEFAULT_IRQ_HANDLER(DebugMon_Handler)
-DEFAULT_IRQ_HANDLER(PendSV_Handler)
-DEFAULT_IRQ_HANDLER(SysTick_Handler)
-
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
-DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
-DEFAULT_IRQ_HANDLER(TIMER0_Handler)
-DEFAULT_IRQ_HANDLER(TIMER1_Handler)
-DEFAULT_IRQ_HANDLER(TIMER2_Handler)
-DEFAULT_IRQ_HANDLER(MPC_Handler)
-DEFAULT_IRQ_HANDLER(PPC_Handler)
-DEFAULT_IRQ_HANDLER(MSC_Handler)
-DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
-DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
-DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
-DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
-DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
-DEFAULT_IRQ_HANDLER(TIMER3_Handler)
-DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
-DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
-
-DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
-DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
-DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
-DEFAULT_IRQ_HANDLER(I2S_Handler)
-DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
-DEFAULT_IRQ_HANDLER(USB_Handler)
-DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
-DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
-DEFAULT_IRQ_HANDLER(UART5_Handler)
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-
-extern const pFunc __VECTOR_TABLE[496];
-       const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
-  (pFunc)(&__INITIAL_SP),           /*      Initial Stack Pointer */
-  Reset_Handler,                    /*      Reset Handler */
-  NMI_Handler,                      /* -14: NMI Handler */
-  HardFault_Handler,                /* -13: Hard Fault Handler */
-  MemManage_Handler,                /* -12: MPU Fault Handler */
-  BusFault_Handler,                 /* -11: Bus Fault Handler */
-  UsageFault_Handler,               /* -10: Usage Fault Handler */
-  SecureFault_Handler,              /*  -9: Secure Fault Handler */
-  0,                                /*      Reserved */
-  0,                                /*      Reserved */
-  0,                                /*      Reserved */
-  SVC_Handler,                      /*  -5: SVCall Handler */
-  DebugMon_Handler,                 /*  -4: Debug Monitor Handler */
-  0,                                /*      Reserved */
-  PendSV_Handler,                   /*  -2: PendSV Handler */
-  SysTick_Handler,                  /*  -1: SysTick Handler */
-
-  NONSEC_WATCHDOG_RESET_Handler,    /*   0: Non-Secure Watchdog Reset Handler */
-  NONSEC_WATCHDOG_Handler,          /*   1: Non-Secure Watchdog Handler */
-  SLOWCLK_Timer_Handler,            /*   2: SLOWCLK Timer Handler */
-  TIMER0_Handler,                   /*   3: TIMER 0 Handler */
-  TIMER1_Handler,                   /*   4: TIMER 1 Handler */
-  TIMER2_Handler,                   /*   5: TIMER 2 Handler */
-  0,                                /*   6: Reserved */
-  0,                                /*   7: Reserved */
-  0,                                /*   8: Reserved */
-  MPC_Handler,                      /*   9: MPC Combined (Secure) Handler */
-  PPC_Handler,                      /*  10: PPC Combined (Secure) Handler */
-  MSC_Handler,                      /*  11: MSC Combined (Secure) Handler */
-  BRIDGE_ERROR_Handler,             /*  12: Bridge Error (Secure) Handler */
-  0,                                /*  13: Reserved */
-  MGMT_PPU_Handler,                 /*  14: MGMT PPU Handler */
-  SYS_PPU_Handler,                  /*  15: SYS PPU Handler */
-  CPU0_PPU_Handler,                 /*  16: CPU0 PPU Handler */
-  0,                                /*  17: Reserved */
-  0,                                /*  18: Reserved */
-  0,                                /*  19: Reserved */
-  0,                                /*  20: Reserved */
-  0,                                /*  21: Reserved */
-  0,                                /*  22: Reserved */
-  0,                                /*  23: Reserved */
-  0,                                /*  24: Reserved */
-  0,                                /*  25: Reserved */
-  DEBUG_PPU_Handler,                /*  26: DEBUG PPU Handler */
-  TIMER3_Handler,                   /*  27: TIMER 3 Handler */
-  CTI_REQ0_IRQHandler,              /*  28: CTI request 0 IRQ Handler */
-  CTI_REQ1_IRQHandler,              /*  29: CTI request 1 IRQ Handler */
-  0,                                /*  30: Reserved */
-  0,                                /*  31: Reserved */
-
-  /* External interrupts */
-  System_Timestamp_Counter_Handler, /*  32: System timestamp counter Handler */
-  UARTRX0_Handler,                  /*  33: UART 0 RX Handler */
-  UARTTX0_Handler,                  /*  34: UART 0 TX Handler */
-  UARTRX1_Handler,                  /*  35: UART 1 RX Handler */
-  UARTTX1_Handler,                  /*  36: UART 1 TX Handler */
-  UARTRX2_Handler,                  /*  37: UART 2 RX Handler */
-  UARTTX2_Handler,                  /*  38: UART 2 TX Handler */
-  UARTRX3_Handler,                  /*  39: UART 3 RX Handler */
-  UARTTX3_Handler,                  /*  40: UART 3 TX Handler */
-  UARTRX4_Handler,                  /*  41: UART 4 RX Handler */
-  UARTTX4_Handler,                  /*  42: UART 4 TX Handler */
-  UART0_Combined_Handler,           /*  43: UART 0 Combined Handler */
-  UART1_Combined_Handler,           /*  44: UART 1 Combined Handler */
-  UART2_Combined_Handler,           /*  45: UART 2 Combined Handler */
-  UART3_Combined_Handler,           /*  46: UART 3 Combined Handler */
-  UART4_Combined_Handler,           /*  47: UART 4 Combined Handler */
-  UARTOVF_Handler,                  /*  48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
-  ETHERNET_Handler,                 /*  49: Ethernet Handler */
-  I2S_Handler,                      /*  50: Audio I2S Handler */
-  TOUCH_SCREEN_Handler,             /*  51: Touch Screen Handler */
-  USB_Handler,                      /*  52: USB Handler */
-  SPI_ADC_Handler,                  /*  53: SPI ADC Handler */
-  SPI_SHIELD0_Handler,              /*  54: SPI (Shield 0) Handler */
-  SPI_SHIELD1_Handler,              /*  55: SPI (Shield 0) Handler */
-  ETHOS_U55_Handler,                /*  56: Ethos-U55 Handler */
-  0,                                /*  57: Reserved */
-  0,                                /*  58: Reserved */
-  0,                                /*  59: Reserved */
-  0,                                /*  60: Reserved */
-  0,                                /*  61: Reserved */
-  0,                                /*  62: Reserved */
-  0,                                /*  63: Reserved */
-  0,                                /*  64: Reserved */
-  0,                                /*  65: Reserved */
-  0,                                /*  66: Reserved */
-  0,                                /*  67: Reserved */
-  0,                                /*  68: Reserved */
-  GPIO0_Combined_Handler,           /*  69: GPIO 0 Combined Handler */
-  GPIO1_Combined_Handler,           /*  70: GPIO 1 Combined Handler */
-  GPIO2_Combined_Handler,           /*  71: GPIO 2 Combined Handler */
-  GPIO3_Combined_Handler,           /*  72: GPIO 3 Combined Handler */
-  GPIO0_0_Handler,                  /*  73: GPIO0 Pin 0 Handler */
-  GPIO0_1_Handler,                  /*  74: GPIO0 Pin 1 Handler */
-  GPIO0_2_Handler,                  /*  75: GPIO0 Pin 2 Handler */
-  GPIO0_3_Handler,                  /*  76: GPIO0 Pin 3 Handler */
-  GPIO0_4_Handler,                  /*  77: GPIO0 Pin 4 Handler */
-  GPIO0_5_Handler,                  /*  78: GPIO0 Pin 5 Handler */
-  GPIO0_6_Handler,                  /*  79: GPIO0 Pin 6 Handler */
-  GPIO0_7_Handler,                  /*  80: GPIO0 Pin 7 Handler */
-  GPIO0_8_Handler,                  /*  81: GPIO0 Pin 8 Handler */
-  GPIO0_9_Handler,                  /*  82: GPIO0 Pin 9 Handler */
-  GPIO0_10_Handler,                 /*  83: GPIO0 Pin 10 Handler */
-  GPIO0_11_Handler,                 /*  84: GPIO0 Pin 11 Handler */
-  GPIO0_12_Handler,                 /*  85: GPIO0 Pin 12 Handler */
-  GPIO0_13_Handler,                 /*  86: GPIO0 Pin 13 Handler */
-  GPIO0_14_Handler,                 /*  87: GPIO0 Pin 14 Handler */
-  GPIO0_15_Handler,                 /*  88: GPIO0 Pin 15 Handler */
-  GPIO1_0_Handler,                  /*  89: GPIO1 Pin 0 Handler */
-  GPIO1_1_Handler,                  /*  90: GPIO1 Pin 1 Handler */
-  GPIO1_2_Handler,                  /*  91: GPIO1 Pin 2 Handler */
-  GPIO1_3_Handler,                  /*  92: GPIO1 Pin 3 Handler */
-  GPIO1_4_Handler,                  /*  93: GPIO1 Pin 4 Handler */
-  GPIO1_5_Handler,                  /*  94: GPIO1 Pin 5 Handler */
-  GPIO1_6_Handler,                  /*  95: GPIO1 Pin 6 Handler */
-  GPIO1_7_Handler,                  /*  96: GPIO1 Pin 7 Handler */
-  GPIO1_8_Handler,                  /*  97: GPIO1 Pin 8 Handler */
-  GPIO1_9_Handler,                  /*  98: GPIO1 Pin 9 Handler */
-  GPIO1_10_Handler,                 /*  99: GPIO1 Pin 10 Handler */
-  GPIO1_11_Handler,                 /*  100: GPIO1 Pin 11 Handler */
-  GPIO1_12_Handler,                 /*  101: GPIO1 Pin 12 Handler */
-  GPIO1_13_Handler,                 /*  102: GPIO1 Pin 13 Handler */
-  GPIO1_14_Handler,                 /*  103: GPIO1 Pin 14 Handler */
-  GPIO1_15_Handler,                 /*  104: GPIO1 Pin 15 Handler */
-  GPIO2_0_Handler,                  /*  105: GPIO2 Pin 0 Handler */
-  GPIO2_1_Handler,                  /*  106: GPIO2 Pin 1 Handler */
-  GPIO2_2_Handler,                  /*  107: GPIO2 Pin 2 Handler */
-  GPIO2_3_Handler,                  /*  108: GPIO2 Pin 3 Handler */
-  GPIO2_4_Handler,                  /*  109: GPIO2 Pin 4 Handler */
-  GPIO2_5_Handler,                  /*  110: GPIO2 Pin 5 Handler */
-  GPIO2_6_Handler,                  /*  111: GPIO2 Pin 6 Handler */
-  GPIO2_7_Handler,                  /*  112: GPIO2 Pin 7 Handler */
-  GPIO2_8_Handler,                  /*  113: GPIO2 Pin 8 Handler */
-  GPIO2_9_Handler,                  /*  114: GPIO2 Pin 9 Handler */
-  GPIO2_10_Handler,                 /*  115: GPIO2 Pin 10 Handler */
-  GPIO2_11_Handler,                 /*  116: GPIO2 Pin 11 Handler */
-  GPIO2_12_Handler,                 /*  117: GPIO2 Pin 12 Handler */
-  GPIO2_13_Handler,                 /*  118: GPIO2 Pin 13 Handler */
-  GPIO2_14_Handler,                 /*  119: GPIO2 Pin 14 Handler */
-  GPIO2_15_Handler,                 /*  120: GPIO2 Pin 15 Handler */
-  GPIO3_0_Handler,                  /*  121: GPIO3 Pin 0 Handler */
-  GPIO3_1_Handler,                  /*  122: GPIO3 Pin 1 Handler */
-  GPIO3_2_Handler,                  /*  123: GPIO3 Pin 2 Handler */
-  GPIO3_3_Handler,                  /*  124: GPIO3 Pin 3 Handler */
-  UARTRX5_Handler,                  /*  125: UART 5 RX Interrupt */
-  UARTTX5_Handler,                  /*  126: UART 5 TX Interrupt */
-  UART5_Handler,                    /*  127: UART 5 combined Interrupt */
-  0,                                /*  128: Reserved */
-  0,                                /*  129: Reserved */
-  0,                                /*  130: Reserved */
-};
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-/*----------------------------------------------------------------------------
-  Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void)
-{
-  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
-
-  SystemInit();                             /* CMSIS System Initialization */
-  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
-}