Added some tests for the ComputeGraph.

ComputeGraph/FAQ.md

@@ -1,5 +1,12 @@
 # FAQ
 
+## Table of contents
+
+* [Alignment](#alignment)
+* [Memory sharing](#memory-sharing-example)
+* [Latencies](#latencies)
+* [Performances](#performances)
+
 ## Alignment
 
 When the `memoryOptimization` mode is enabled, the memory can be shared between different FIFOs (when the FIFOs are in fact used as simple arrays).

ComputeGraph/cg/nodes/cpp/CFFT.h

@@ -39,7 +39,6 @@ class CFFT<float32_t,inputSize,float32_t,inputSize>: public GenericNode<float32_
 {
 public:
     CFFT(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):GenericNode<float32_t,inputSize,float32_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_f32(&sfft,inputSize>>1);
     };
 
@@ -57,6 +56,10 @@ public:
 
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         float32_t *a=this->getReadBuffer();
         float32_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(float32_t));
@@ -65,6 +68,7 @@ public:
     };
 
     arm_cfft_instance_f32 sfft;
+    arm_status status;
 
 };
 
@@ -79,7 +83,6 @@ class CFFT<float16_t,inputSize,float16_t,inputSize>: public GenericNode<float16_
 {
 public:
     CFFT(FIFOBase<float16_t> &src,FIFOBase<float16_t> &dst):GenericNode<float16_t,inputSize,float16_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_f16(&sfft,inputSize>>1);
     };
 
@@ -97,6 +100,10 @@ public:
 
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         float16_t *a=this->getReadBuffer();
         float16_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(float16_t));
@@ -105,6 +112,7 @@ public:
     };
 
     arm_cfft_instance_f16 sfft;
+    arm_status status;
 
 };
 #endif
@@ -118,7 +126,6 @@ class CFFT<q15_t,inputSize,q15_t,inputSize>: public GenericNode<q15_t,inputSize,
 {
 public:
     CFFT(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst):GenericNode<q15_t,inputSize,q15_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_q15(&sfft,inputSize>>1);
     };
 
@@ -136,6 +143,10 @@ public:
     
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         q15_t *a=this->getReadBuffer();
         q15_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(q15_t));
@@ -144,6 +155,7 @@ public:
     };
 
     arm_cfft_instance_q15 sfft;
+    arm_status status;
 
 };
 

ComputeGraph/cg/nodes/cpp/ICFFT.h

@@ -39,7 +39,6 @@ class ICFFT<float32_t,inputSize,float32_t,inputSize>: public GenericNode<float32
 {
 public:
     ICFFT(FIFOBase<float32_t> &src,FIFOBase<float32_t> &dst):GenericNode<float32_t,inputSize,float32_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_f32(&sifft,inputSize>>1);
     };
 
@@ -57,6 +56,10 @@ public:
 
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         float32_t *a=this->getReadBuffer();
         float32_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(float32_t));
@@ -65,6 +68,7 @@ public:
     };
 
     arm_cfft_instance_f32 sifft;
+    arm_status status;
 
 };
 
@@ -79,7 +83,6 @@ class ICFFT<float16_t,inputSize,float16_t,inputSize>: public GenericNode<float16
 {
 public:
     ICFFT(FIFOBase<float16_t> &src,FIFOBase<float16_t> &dst):GenericNode<float16_t,inputSize,float16_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_f16(&sifft,inputSize>>1);
     };
 
@@ -97,6 +100,10 @@ public:
 
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         float16_t *a=this->getReadBuffer();
         float16_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(float16_t));
@@ -105,6 +112,7 @@ public:
     };
 
     arm_cfft_instance_f16 sifft;
+    arm_status status;
 
 };
 #endif
@@ -119,7 +127,6 @@ class ICFFT<q15_t,inputSize,q15_t,inputSize>: public GenericNode<q15_t,inputSize
 {
 public:
     ICFFT(FIFOBase<q15_t> &src,FIFOBase<q15_t> &dst):GenericNode<q15_t,inputSize,q15_t,inputSize>(src,dst){
-         arm_status status;
          status=arm_cfft_init_q15(&sifft,inputSize>>1);
     };
 
@@ -137,6 +144,10 @@ public:
     
     int run() final
     {
+        if (status!=ARM_MATH_SUCCESS)
+        {
+            return(CG_INIT_FAILURE);
+        }
         q15_t *a=this->getReadBuffer();
         q15_t *b=this->getWriteBuffer();
         memcpy((void*)b,(void*)a,inputSize*sizeof(q15_t));
@@ -144,7 +155,8 @@ public:
         return(0);
     };
 
-    arm_cfft_instance_f32 sifft;
+    arm_cfft_instance_q15 sifft;
+    arm_status status;
 
 };
 #endif

ComputeGraph/tests/.gitignore

@@ -0,0 +1,3 @@
+cprj/out 
+cprj/tmp
+__pycache__

ComputeGraph/tests/ARMCM55_FP_MVE_config.txt

@@ -0,0 +1,9 @@
+core_clk.mul=50000000
+mps3_board.visualisation.disable-visualisation=1
+cpu0.semihosting-enable=0
+cpu0.FPU=1
+cpu0.MVE=2
+cpu0.SAU=0
+cpu0.SECEXT=1
+cpu0.INITSVTOR=0
+cpu0.INITNSVTOR=0

ComputeGraph/tests/AppNodes.h

@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        AppNodes.h
+ * Description:  Application nodes for Example simple
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- 
+*
+ * Copyright (C) 2021-2023 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _APPNODES_H_
+#define _APPNODES_H_
+
+#include <iostream>
+
+template<typename IN, int inputSize>
+class Sink: public GenericSink<IN, inputSize>
+{
+public:
+    Sink(FIFOBase<IN> &src):GenericSink<IN,inputSize>(src){};
+
+    int prepareForRunning() final
+    {
+        if (this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+    int run() final
+    {
+        IN *b=this->getReadBuffer();
+        printf("Sink\n");
+        for(int i=0;i<inputSize;i++)
+        {
+            std::cout << (int)b[i] << std::endl;
+        }
+        return(0);
+    };
+
+};
+
+template<typename OUT,int outputSize>
+class Source: public GenericSource<OUT,outputSize>
+{
+public:
+    Source(FIFOBase<OUT> &dst):GenericSource<OUT,outputSize>(dst){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+    int run() final{
+        OUT *b=this->getWriteBuffer();
+
+        printf("Source\n");
+        for(int i=0;i<outputSize;i++)
+        {
+            b[i] = (OUT)i;
+        }
+        return(0);
+    };
+
+};
+
+
+template<typename IN, int inputSize,
+         typename OUT, int outputSize>
+class ProcessingNode;
+
+
+template<typename IN, int inputOutputSize>
+class ProcessingNode<IN,inputOutputSize,IN,inputOutputSize>: public GenericNode<IN,inputOutputSize,IN,inputOutputSize>
+{
+public:
+    ProcessingNode(FIFOBase<IN> &src,
+                   FIFOBase<IN> &dst):GenericNode<IN,inputOutputSize,
+                                                  IN,inputOutputSize>(src,dst){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow() ||
+            this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+    
+    int run() final{
+        printf("ProcessingNode\n");
+        IN *a=this->getReadBuffer();
+        IN *b=this->getWriteBuffer();
+        for(int i=0;i<inputOutputSize;i++)
+        {
+            b[i] = a[i]+1;
+        }
+        return(0);
+    };
+
+};
+
+
+
+
+#endif

ComputeGraph/tests/BenchAppNodes.h

@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        AppNodes.h
+ * Description:  Application nodes for Example 1
+ *
+ * $Date:        29 July 2021
+ * $Revision:    V1.10.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _APPNODES_H_
+#define _APPNODES_H_
+
+#include <cstdio>
+#include "arm_math.h"
+#include "cg_status.h"
+
+#include "CFFT.h"
+#include "ICFFT.h"
+
+#include "ToComplex.h"
+#include "ToReal.h"
+#include "SlidingBuffer.h"
+#include "OverlapAndAdd.h"
+
+
+template<typename IN, int inputSize>
+class ArraySink:public GenericSink<IN, inputSize>
+{
+public:
+    ArraySink(FIFOBase<IN> &src,IN* outputBuf):
+    GenericSink<IN,inputSize>(src),mOutputBuf(outputBuf){
+    };
+
+    int prepareForRunning() final
+    {
+        if (this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+
+    int run() final
+    {
+        IN *b=this->getReadBuffer();
+        memcpy(mOutputBuf,b,sizeof(IN)*inputSize);
+        
+        return(0);
+    };
+
+protected:
+    IN* mOutputBuf;
+
+};
+
+template<typename OUT,int outputSize>
+class ArraySource: GenericSource<OUT,outputSize>
+{
+public:
+    ArraySource(FIFOBase<OUT> &dst, OUT *inputBuf):
+    GenericSource<OUT,outputSize>(dst),mInputBuf(inputBuf){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+
+    int run() final{
+        OUT *b=this->getWriteBuffer();
+        memcpy(b,mInputBuf,sizeof(OUT)*outputSize);
+        
+        return(0);
+    };
+protected:
+    OUT *mInputBuf;
+
+};
+
+
+#endif

ComputeGraph/tests/CMakeLists.txt

@@ -0,0 +1,13 @@
+cmake_minimum_required (VERSION 3.14)
+include(CMakePrintHelpers)
+
+project(Simple)
+
+
+add_executable(simple main.cpp)
+
+sdf(simple create.py simple)
+add_sdf_dir(simple)
+
+target_include_directories(simple PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
+target_include_directories(simple PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/generated)

ComputeGraph/tests/ComplexAppNodes.h

@@ -0,0 +1,273 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        AppNodes.h
+ * Description:  Application nodes for Example 1
+ *
+ * $Date:        29 July 2021
+ * $Revision:    V1.10.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _APPNODES_H_
+#define _APPNODES_H_
+
+#include <cstring>
+#include <cstdio>
+
+
+template<typename IN, int inputSize>
+class Sink;
+
+template<int inputSize>
+class Sink<float32_t,inputSize>: 
+public GenericSink<float32_t, inputSize>
+{
+public:
+    Sink(FIFOBase<float32_t> &src):
+    GenericSink<float32_t,inputSize>(src){
+    };
+
+    int prepareForRunning() final
+    {
+        if (this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+
+    int run() final
+    {
+        float32_t *b=this->getReadBuffer();
+        (void)b;
+        
+        return(0);
+    };
+
+    
+
+};
+
+template<typename OUT,int outputSize>
+class Source;
+
+template<int outputSize>
+class Source<float32_t,outputSize>: GenericSource<float32_t,outputSize>
+{
+public:
+    Source(FIFOBase<float32_t> &dst):
+    GenericSource<float32_t,outputSize>(dst){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+
+    int run() final{
+        float32_t *b=this->getWriteBuffer();
+        (void)b;
+        
+        return(0);
+    };
+
+
+};
+
+template<typename IN, int inputSize,typename OUT,int outputSize>
+class ProcessingNode;
+
+
+
+template<int inputSize,int outputSize>
+class ProcessingNode<float32_t,inputSize,
+                     float32_t,outputSize>: 
+public GenericNode<float32_t,inputSize,
+                   float32_t,outputSize>
+{
+public:
+    ProcessingNode(FIFOBase<float32_t> &src,
+                   FIFOBase<float32_t> &dst):
+    GenericNode<float32_t,inputSize,
+                float32_t,outputSize>(src,dst){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow() ||
+            this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+
+
+    int run() final{
+        float32_t *a=this->getReadBuffer();
+        float32_t *b=this->getWriteBuffer();
+        (void)a;
+        (void)b;
+        
+        return(0);
+    };
+
+};
+
+template<typename IN, int inputSize,
+         typename OUTA,int outputSizeA,
+         typename OUTB,int outputSizeB>
+class ProcessingNode12:public GenericNode12<IN, inputSize,
+                     OUTA,outputSizeA,
+                     OUTB,outputSizeB>
+{
+public:
+    ProcessingNode12(FIFOBase<IN> &src,
+                   FIFOBase<OUTA> &dst1,
+                   FIFOBase<OUTB> &dst2):
+    GenericNode12<IN,inputSize,
+                  OUTA,outputSizeA,
+                  OUTB,outputSizeB>(src,dst1,dst2){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow1() ||
+            this->willOverflow2() ||
+            this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+    
+    int run() final{
+        IN *a=this->getReadBuffer();
+        OUTA *ba=this->getWriteBuffer1();
+        OUTB *bb=this->getWriteBuffer2();
+
+        (void)a;
+        (void)ba;
+        (void)bb;
+
+        return(0);
+    };
+
+};
+
+template<typename IN, int inputSize,
+         typename OUTA,int outputSizeA,
+         typename OUTB,int outputSizeB,
+         typename OUTC,int outputSizeC>
+class ProcessingNode13:public GenericNode13<IN,inputSize,
+                     OUTA,outputSizeA,
+                     OUTB,outputSizeB,
+                     OUTC,outputSizeC>
+{
+public:
+    ProcessingNode13(FIFOBase<IN> &src,
+                   FIFOBase<OUTA> &dst1,
+                   FIFOBase<OUTB> &dst2,
+                   FIFOBase<OUTC> &dst3):
+    GenericNode13<IN,inputSize,
+                  OUTA,outputSizeA,
+                  OUTB,outputSizeB,
+                  OUTC,outputSizeC>(src,dst1,dst2,dst3){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow1() ||
+            this->willOverflow2() ||
+            this->willOverflow3() ||
+            this->willUnderflow())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+    
+    int run() final{
+        IN *a=this->getReadBuffer();
+        OUTA *ba=this->getWriteBuffer1();
+        OUTB *bb=this->getWriteBuffer2();
+        OUTC *bc=this->getWriteBuffer3();
+
+        (void)a;
+        (void)ba;
+        (void)bb;
+        (void)bc;
+
+        return(0);
+    };
+
+};
+
+template<typename INA, int inputSizeA,
+         typename INB, int inputSizeB,
+         typename OUT, int outputSize
+         >
+class ProcessingNode21: 
+      public GenericNode21<INA,inputSizeA,
+                           INB,inputSizeB,
+                           OUT,outputSize>
+{
+public:
+    ProcessingNode21(FIFOBase<INA> &srcA,
+                     FIFOBase<INB> &srcB,
+                     FIFOBase<OUT> &dst):GenericNode21<INA,inputSizeA,
+                                                     INB,inputSizeB,
+                                                     OUT,outputSize>(srcA,srcB,dst){};
+
+    int prepareForRunning() final
+    {
+        if (this->willOverflow() ||
+            this->willUnderflow1() ||
+            this->willUnderflow2())
+        {
+           return(CG_SKIP_EXECUTION_ID_CODE); // Skip execution
+        }
+
+        return(0);
+    };
+    
+    int run() final{
+        printf("ProcessingNode\n");
+        INA *a=this->getReadBuffer1();
+        INB *b=this->getReadBuffer2();
+        OUT *c=this->getWriteBuffer();
+        (void)a;
+        (void)b;
+        (void)c;
+        
+        return(0);
+    };
+
+};
+
+
+#endif

ComputeGraph/tests/README.md

@@ -0,0 +1,20 @@
+# README
+
+Some tests to validate some parts of the Compute graph. They all rely on the CMSIS build tools and Arm Virtual Hardware.
+
+## List of tests
+
+* `create_sync.py`
+  * Create a complex graph containing all classes defined in `GenericNodes.h` (synchronous mode). Used to test that it builds and that there are no errors in the templates
+  * `cbuild "cprj\syncgraph.CommandLine+VHT-Corstone-300.cprj" `
+* `create_async.py`
+  * Create a complex graph containing all classes defined in `GenericNodes.h` (ssynchronous mode). Used to test that it builds and that there are no errors in the templates
+  * `cbuild "cprj\asyncgraph.CommandLine+VHT-Corstone-300.cprj" `
+* `create_fifobench_sync.py`
+  * Create a graph with FFT / IFFT : the graph is decomposing a signal and rebuilding it. It is used to test the performance of different FIFOs implementations (synchronous mode)
+  * `cbuild "cprj\fifobench_sync.CommandLine+VHT-Corstone-300.cprj"`
+* `create_fifobench_async.py`
+  * Create a graph with FFT / IFFT : the graph is decomposing a signal and rebuilding it. It is used to test the performance of different FIFOs implementations (asynchronous mode)
+  * `cbuild "cprj\fifobench_async.CommandLine+VHT-Corstone-300.cprj"`
+* There is a simple FIFO test to check the behavior of the FIFO implementation:
+  * `cbuild "cprj\fifo.CommandLine+VHT-Corstone-300.cprj" `

ComputeGraph/tests/RTE/CMSIS/RTX_Config.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.1.1
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+ 
+// OS Idle Thread
+__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
+  (void)argument;
+
+  for (;;) {}
+}
+ 
+// OS Error Callback function
+__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
+  (void)object_id;
+
+  switch (code) {
+    case osRtxErrorStackOverflow:
+      // Stack overflow detected for thread (thread_id=object_id)
+      break;
+    case osRtxErrorISRQueueOverflow:
+      // ISR Queue overflow detected when inserting object (object_id)
+      break;
+    case osRtxErrorTimerQueueOverflow:
+      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+      break;
+    case osRtxErrorClibSpace:
+      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+      break;
+    case osRtxErrorClibMutex:
+      // Standard C/C++ library mutex initialization failed
+      break;
+    default:
+      // Reserved
+      break;
+  }
+  for (;;) {}
+//return 0U;
+}

ComputeGraph/tests/RTE/CMSIS/RTX_Config.c.base@5.1.1

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.1.1
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+ 
+// OS Idle Thread
+__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
+  (void)argument;
+
+  for (;;) {}
+}
+ 
+// OS Error Callback function
+__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
+  (void)object_id;
+
+  switch (code) {
+    case osRtxErrorStackOverflow:
+      // Stack overflow detected for thread (thread_id=object_id)
+      break;
+    case osRtxErrorISRQueueOverflow:
+      // ISR Queue overflow detected when inserting object (object_id)
+      break;
+    case osRtxErrorTimerQueueOverflow:
+      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+      break;
+    case osRtxErrorClibSpace:
+      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+      break;
+    case osRtxErrorClibMutex:
+      // Standard C/C++ library mutex initialization failed
+      break;
+    default:
+      // Reserved
+      break;
+  }
+  for (;;) {}
+//return 0U;
+}

ComputeGraph/tests/RTE/CMSIS/RTX_Config.h

@@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.5.2
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+ 
+#ifdef   _RTE_
+#include "RTE_Components.h"
+#ifdef    RTE_RTX_CONFIG_H
+#include  RTE_RTX_CONFIG_H
+#endif
+#endif
+ 
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+ 
+// <h>System Configuration
+// =======================
+ 
+//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+//   <i> Defines the combined global dynamic memory size.
+//   <i> Default: 32768
+#ifndef OS_DYNAMIC_MEM_SIZE
+#define OS_DYNAMIC_MEM_SIZE         32768
+#endif
+ 
+//   <o>Kernel Tick Frequency [Hz] <1-1000000>
+//   <i> Defines base time unit for delays and timeouts.
+//   <i> Default: 1000 (1ms tick)
+#ifndef OS_TICK_FREQ
+#define OS_TICK_FREQ                1000
+#endif
+ 
+//   <e>Round-Robin Thread switching
+//   <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN_ENABLE
+#define OS_ROBIN_ENABLE             1
+#endif
+ 
+//     <o>Round-Robin Timeout <1-1000>
+//     <i> Defines how many ticks a thread will execute before a thread switch.
+//     <i> Default: 5
+#ifndef OS_ROBIN_TIMEOUT
+#define OS_ROBIN_TIMEOUT            5
+#endif
+ 
+//   </e>
+ 
+//   <o>ISR FIFO Queue
+//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
+//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
+//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
+//   <i> RTOS Functions called from ISR store requests to this buffer.
+//   <i> Default: 16 entries
+#ifndef OS_ISR_FIFO_QUEUE
+#define OS_ISR_FIFO_QUEUE           16
+#endif
+ 
+//   <q>Object Memory usage counters
+//   <i> Enables object memory usage counters (requires RTX source variant).
+#ifndef OS_OBJ_MEM_USAGE
+#define OS_OBJ_MEM_USAGE            0
+#endif
+ 
+// </h>
+ 
+// <h>Thread Configuration
+// =======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_THREAD_OBJ_MEM
+#define OS_THREAD_OBJ_MEM           0
+#endif
+ 
+//     <o>Number of user Threads <1-1000>
+//     <i> Defines maximum number of user threads that can be active at the same time.
+//     <i> Applies to user threads with system provided memory for control blocks.
+#ifndef OS_THREAD_NUM
+#define OS_THREAD_NUM               1
+#endif
+ 
+//     <o>Number of user Threads with default Stack size <0-1000>
+//     <i> Defines maximum number of user threads with default stack size.
+//     <i> Applies to user threads with zero stack size specified.
+#ifndef OS_THREAD_DEF_STACK_NUM
+#define OS_THREAD_DEF_STACK_NUM     0
+#endif
+ 
+//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+//     <i> Defines the combined stack size for user threads with user-provided stack size.
+//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
+//     <i> Default: 0
+#ifndef OS_THREAD_USER_STACK_SIZE
+#define OS_THREAD_USER_STACK_SIZE   0
+#endif
+ 
+//   </e>
+ 
+//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
+//   <i> Defines stack size for threads with zero stack size specified.
+//   <i> Default: 3072
+#ifndef OS_STACK_SIZE
+#define OS_STACK_SIZE               3072
+#endif
+ 
+//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+//   <i> Defines stack size for Idle thread.
+//   <i> Default: 512
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE   512
+#endif
+ 
+//   <o>Idle Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_IDLE_THREAD_TZ_MOD_ID
+#define OS_IDLE_THREAD_TZ_MOD_ID    0
+#endif
+ 
+//   <q>Stack overrun checking
+//   <i> Enables stack overrun check at thread switch (requires RTX source variant).
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STACK_CHECK
+#define OS_STACK_CHECK              0
+#endif
+ 
+//   <q>Stack usage watermark
+//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.
+//   <i> Enabling this option increases significantly the execution time of thread creation.
+#ifndef OS_STACK_WATERMARK
+#define OS_STACK_WATERMARK          0
+#endif
+ 
+//   <o>Processor mode for Thread execution
+//     <0=> Unprivileged mode
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#ifndef OS_PRIVILEGE_MODE
+#define OS_PRIVILEGE_MODE           1
+#endif
+ 
+// </h>
+ 
+// <h>Timer Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_TIMER_OBJ_MEM
+#define OS_TIMER_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Timer objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_TIMER_NUM
+#define OS_TIMER_NUM                1
+#endif
+ 
+//   </e>
+ 
+//   <o>Timer Thread Priority
+//      <8=> Low
+//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
+//     <40=> High
+//     <48=> Realtime
+//   <i> Defines priority for timer thread
+//   <i> Default: High
+#ifndef OS_TIMER_THREAD_PRIO
+#define OS_TIMER_THREAD_PRIO        40
+#endif
+ 
+//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+//   <i> Defines stack size for Timer thread.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 512
+#ifndef OS_TIMER_THREAD_STACK_SIZE
+#define OS_TIMER_THREAD_STACK_SIZE  512
+#endif
+ 
+//   <o>Timer Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_TIMER_THREAD_TZ_MOD_ID
+#define OS_TIMER_THREAD_TZ_MOD_ID   0
+#endif
+ 
+//   <o>Timer Callback Queue entries <0-256>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 4
+#ifndef OS_TIMER_CB_QUEUE
+#define OS_TIMER_CB_QUEUE           4
+#endif
+ 
+// </h>
+ 
+// <h>Event Flags Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_EVFLAGS_OBJ_MEM
+#define OS_EVFLAGS_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Event Flags objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_EVFLAGS_NUM
+#define OS_EVFLAGS_NUM              1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Mutex Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MUTEX_OBJ_MEM
+#define OS_MUTEX_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Mutex objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MUTEX_NUM
+#define OS_MUTEX_NUM                1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Semaphore Configuration
+// ==========================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_SEMAPHORE_OBJ_MEM
+#define OS_SEMAPHORE_OBJ_MEM        0
+#endif
+ 
+//     <o>Number of Semaphore objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_SEMAPHORE_NUM
+#define OS_SEMAPHORE_NUM            1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Memory Pool Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MEMPOOL_OBJ_MEM
+#define OS_MEMPOOL_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Memory Pool objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MEMPOOL_NUM
+#define OS_MEMPOOL_NUM              1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MEMPOOL_DATA_SIZE
+#define OS_MEMPOOL_DATA_SIZE        0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Message Queue Configuration
+// ==============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MSGQUEUE_OBJ_MEM
+#define OS_MSGQUEUE_OBJ_MEM         0
+#endif
+ 
+//     <o>Number of Message Queue objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MSGQUEUE_NUM
+#define OS_MSGQUEUE_NUM             1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MSGQUEUE_DATA_SIZE
+#define OS_MSGQUEUE_DATA_SIZE       0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Event Recorder Configuration
+// ===============================
+ 
+//   <e>Global Initialization
+//   <i> Initialize Event Recorder during 'osKernelInitialize'.
+#ifndef OS_EVR_INIT
+#define OS_EVR_INIT                 1
+#endif
+ 
+//     <q>Start recording
+//     <i> Start event recording after initialization.
+#ifndef OS_EVR_START
+#define OS_EVR_START                1
+#endif
+ 
+//     <h>Global Event Filter Setup
+//     <i> Initial recording level applied to all components.
+//       <o.0>Error events
+//       <o.1>API function call events
+//       <o.2>Operation events
+//       <o.3>Detailed operation events
+//     </h>
+#ifndef OS_EVR_LEVEL
+#define OS_EVR_LEVEL                0x00U
+#endif
+ 
+//     <h>RTOS Event Filter Setup
+//     <i> Recording levels for RTX components.
+//     <i> Only applicable if events for the respective component are generated.
+ 
+//       <e.7>Memory Management
+//       <i> Recording level for Memory Management events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MEMORY_LEVEL
+#define OS_EVR_MEMORY_LEVEL         0x81U
+#endif
+ 
+//       <e.7>Kernel
+//       <i> Recording level for Kernel events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_KERNEL_LEVEL
+#define OS_EVR_KERNEL_LEVEL         0x81U
+#endif
+ 
+//       <e.7>Thread
+//       <i> Recording level for Thread events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_THREAD_LEVEL
+#define OS_EVR_THREAD_LEVEL         0x85U
+#endif
+ 
+//       <e.7>Generic Wait
+//       <i> Recording level for Generic Wait events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_WAIT_LEVEL
+#define OS_EVR_WAIT_LEVEL           0x81U
+#endif
+ 
+//       <e.7>Thread Flags
+//       <i> Recording level for Thread Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_THFLAGS_LEVEL
+#define OS_EVR_THFLAGS_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Event Flags
+//       <i> Recording level for Event Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_EVFLAGS_LEVEL
+#define OS_EVR_EVFLAGS_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Timer
+//       <i> Recording level for Timer events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_TIMER_LEVEL
+#define OS_EVR_TIMER_LEVEL          0x81U
+#endif
+ 
+//       <e.7>Mutex
+//       <i> Recording level for Mutex events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MUTEX_LEVEL
+#define OS_EVR_MUTEX_LEVEL          0x81U
+#endif
+ 
+//       <e.7>Semaphore
+//       <i> Recording level for Semaphore events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_SEMAPHORE_LEVEL
+#define OS_EVR_SEMAPHORE_LEVEL      0x81U
+#endif
+ 
+//       <e.7>Memory Pool
+//       <i> Recording level for Memory Pool events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MEMPOOL_LEVEL
+#define OS_EVR_MEMPOOL_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Message Queue
+//       <i> Recording level for Message Queue events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MSGQUEUE_LEVEL
+#define OS_EVR_MSGQUEUE_LEVEL       0x81U
+#endif
+ 
+//     </h>
+ 
+//   </e>
+ 
+//   <h>RTOS Event Generation
+//   <i> Enables event generation for RTX components (requires RTX source variant).
+ 
+//     <q>Memory Management
+//     <i> Enables Memory Management event generation.
+#ifndef OS_EVR_MEMORY
+#define OS_EVR_MEMORY               1
+#endif
+ 
+//     <q>Kernel
+//     <i> Enables Kernel event generation.
+#ifndef OS_EVR_KERNEL
+#define OS_EVR_KERNEL               1
+#endif
+ 
+//     <q>Thread
+//     <i> Enables Thread event generation.
+#ifndef OS_EVR_THREAD
+#define OS_EVR_THREAD               1
+#endif
+ 
+//     <q>Generic Wait
+//     <i> Enables Generic Wait event generation.
+#ifndef OS_EVR_WAIT
+#define OS_EVR_WAIT                 1
+#endif
+ 
+//     <q>Thread Flags
+//     <i> Enables Thread Flags event generation.
+#ifndef OS_EVR_THFLAGS
+#define OS_EVR_THFLAGS              1
+#endif
+ 
+//     <q>Event Flags
+//     <i> Enables Event Flags event generation.
+#ifndef OS_EVR_EVFLAGS
+#define OS_EVR_EVFLAGS              1
+#endif
+ 
+//     <q>Timer
+//     <i> Enables Timer event generation.
+#ifndef OS_EVR_TIMER
+#define OS_EVR_TIMER                1
+#endif
+ 
+//     <q>Mutex
+//     <i> Enables Mutex event generation.
+#ifndef OS_EVR_MUTEX
+#define OS_EVR_MUTEX                1
+#endif
+ 
+//     <q>Semaphore
+//     <i> Enables Semaphore event generation.
+#ifndef OS_EVR_SEMAPHORE
+#define OS_EVR_SEMAPHORE            1
+#endif
+ 
+//     <q>Memory Pool
+//     <i> Enables Memory Pool event generation.
+#ifndef OS_EVR_MEMPOOL
+#define OS_EVR_MEMPOOL              1
+#endif
+ 
+//     <q>Message Queue
+//     <i> Enables Message Queue event generation.
+#ifndef OS_EVR_MSGQUEUE
+#define OS_EVR_MSGQUEUE             1
+#endif
+ 
+//   </h>
+ 
+// </h>
+ 
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#ifndef OS_THREAD_LIBSPACE_NUM
+#define OS_THREAD_LIBSPACE_NUM      4
+#endif
+#else
+#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
+#endif
+ 
+//------------- <<< end of configuration section >>> ---------------------------
+ 
+#endif  // RTX_CONFIG_H_

ComputeGraph/tests/RTE/CMSIS/RTX_Config.h.base@5.5.2

@@ -0,0 +1,580 @@
+/*
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.5.2
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+ 
+#ifdef   _RTE_
+#include "RTE_Components.h"
+#ifdef    RTE_RTX_CONFIG_H
+#include  RTE_RTX_CONFIG_H
+#endif
+#endif
+ 
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+ 
+// <h>System Configuration
+// =======================
+ 
+//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+//   <i> Defines the combined global dynamic memory size.
+//   <i> Default: 32768
+#ifndef OS_DYNAMIC_MEM_SIZE
+#define OS_DYNAMIC_MEM_SIZE         32768
+#endif
+ 
+//   <o>Kernel Tick Frequency [Hz] <1-1000000>
+//   <i> Defines base time unit for delays and timeouts.
+//   <i> Default: 1000 (1ms tick)
+#ifndef OS_TICK_FREQ
+#define OS_TICK_FREQ                1000
+#endif
+ 
+//   <e>Round-Robin Thread switching
+//   <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN_ENABLE
+#define OS_ROBIN_ENABLE             1
+#endif
+ 
+//     <o>Round-Robin Timeout <1-1000>
+//     <i> Defines how many ticks a thread will execute before a thread switch.
+//     <i> Default: 5
+#ifndef OS_ROBIN_TIMEOUT
+#define OS_ROBIN_TIMEOUT            5
+#endif
+ 
+//   </e>
+ 
+//   <o>ISR FIFO Queue
+//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
+//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
+//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
+//   <i> RTOS Functions called from ISR store requests to this buffer.
+//   <i> Default: 16 entries
+#ifndef OS_ISR_FIFO_QUEUE
+#define OS_ISR_FIFO_QUEUE           16
+#endif
+ 
+//   <q>Object Memory usage counters
+//   <i> Enables object memory usage counters (requires RTX source variant).
+#ifndef OS_OBJ_MEM_USAGE
+#define OS_OBJ_MEM_USAGE            0
+#endif
+ 
+// </h>
+ 
+// <h>Thread Configuration
+// =======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_THREAD_OBJ_MEM
+#define OS_THREAD_OBJ_MEM           0
+#endif
+ 
+//     <o>Number of user Threads <1-1000>
+//     <i> Defines maximum number of user threads that can be active at the same time.
+//     <i> Applies to user threads with system provided memory for control blocks.
+#ifndef OS_THREAD_NUM
+#define OS_THREAD_NUM               1
+#endif
+ 
+//     <o>Number of user Threads with default Stack size <0-1000>
+//     <i> Defines maximum number of user threads with default stack size.
+//     <i> Applies to user threads with zero stack size specified.
+#ifndef OS_THREAD_DEF_STACK_NUM
+#define OS_THREAD_DEF_STACK_NUM     0
+#endif
+ 
+//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+//     <i> Defines the combined stack size for user threads with user-provided stack size.
+//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.
+//     <i> Default: 0
+#ifndef OS_THREAD_USER_STACK_SIZE
+#define OS_THREAD_USER_STACK_SIZE   0
+#endif
+ 
+//   </e>
+ 
+//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
+//   <i> Defines stack size for threads with zero stack size specified.
+//   <i> Default: 3072
+#ifndef OS_STACK_SIZE
+#define OS_STACK_SIZE               3072
+#endif
+ 
+//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+//   <i> Defines stack size for Idle thread.
+//   <i> Default: 512
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE   512
+#endif
+ 
+//   <o>Idle Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_IDLE_THREAD_TZ_MOD_ID
+#define OS_IDLE_THREAD_TZ_MOD_ID    0
+#endif
+ 
+//   <q>Stack overrun checking
+//   <i> Enables stack overrun check at thread switch (requires RTX source variant).
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STACK_CHECK
+#define OS_STACK_CHECK              0
+#endif
+ 
+//   <q>Stack usage watermark
+//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.
+//   <i> Enabling this option increases significantly the execution time of thread creation.
+#ifndef OS_STACK_WATERMARK
+#define OS_STACK_WATERMARK          0
+#endif
+ 
+//   <o>Processor mode for Thread execution
+//     <0=> Unprivileged mode
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#ifndef OS_PRIVILEGE_MODE
+#define OS_PRIVILEGE_MODE           1
+#endif
+ 
+// </h>
+ 
+// <h>Timer Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_TIMER_OBJ_MEM
+#define OS_TIMER_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Timer objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_TIMER_NUM
+#define OS_TIMER_NUM                1
+#endif
+ 
+//   </e>
+ 
+//   <o>Timer Thread Priority
+//      <8=> Low
+//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
+//     <40=> High
+//     <48=> Realtime
+//   <i> Defines priority for timer thread
+//   <i> Default: High
+#ifndef OS_TIMER_THREAD_PRIO
+#define OS_TIMER_THREAD_PRIO        40
+#endif
+ 
+//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+//   <i> Defines stack size for Timer thread.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 512
+#ifndef OS_TIMER_THREAD_STACK_SIZE
+#define OS_TIMER_THREAD_STACK_SIZE  512
+#endif
+ 
+//   <o>Timer Thread TrustZone Module Identifier
+//   <i> Defines TrustZone Thread Context Management Identifier.
+//   <i> Applies only to cores with TrustZone technology.
+//   <i> Default: 0 (not used)
+#ifndef OS_TIMER_THREAD_TZ_MOD_ID
+#define OS_TIMER_THREAD_TZ_MOD_ID   0
+#endif
+ 
+//   <o>Timer Callback Queue entries <0-256>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 4
+#ifndef OS_TIMER_CB_QUEUE
+#define OS_TIMER_CB_QUEUE           4
+#endif
+ 
+// </h>
+ 
+// <h>Event Flags Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_EVFLAGS_OBJ_MEM
+#define OS_EVFLAGS_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Event Flags objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_EVFLAGS_NUM
+#define OS_EVFLAGS_NUM              1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Mutex Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MUTEX_OBJ_MEM
+#define OS_MUTEX_OBJ_MEM            0
+#endif
+ 
+//     <o>Number of Mutex objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MUTEX_NUM
+#define OS_MUTEX_NUM                1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Semaphore Configuration
+// ==========================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_SEMAPHORE_OBJ_MEM
+#define OS_SEMAPHORE_OBJ_MEM        0
+#endif
+ 
+//     <o>Number of Semaphore objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_SEMAPHORE_NUM
+#define OS_SEMAPHORE_NUM            1
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Memory Pool Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MEMPOOL_OBJ_MEM
+#define OS_MEMPOOL_OBJ_MEM          0
+#endif
+ 
+//     <o>Number of Memory Pool objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MEMPOOL_NUM
+#define OS_MEMPOOL_NUM              1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MEMPOOL_DATA_SIZE
+#define OS_MEMPOOL_DATA_SIZE        0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Message Queue Configuration
+// ==============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#ifndef OS_MSGQUEUE_OBJ_MEM
+#define OS_MSGQUEUE_OBJ_MEM         0
+#endif
+ 
+//     <o>Number of Message Queue objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MSGQUEUE_NUM
+#define OS_MSGQUEUE_NUM             1
+#endif
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#ifndef OS_MSGQUEUE_DATA_SIZE
+#define OS_MSGQUEUE_DATA_SIZE       0
+#endif
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Event Recorder Configuration
+// ===============================
+ 
+//   <e>Global Initialization
+//   <i> Initialize Event Recorder during 'osKernelInitialize'.
+#ifndef OS_EVR_INIT
+#define OS_EVR_INIT                 0
+#endif
+ 
+//     <q>Start recording
+//     <i> Start event recording after initialization.
+#ifndef OS_EVR_START
+#define OS_EVR_START                1
+#endif
+ 
+//     <h>Global Event Filter Setup
+//     <i> Initial recording level applied to all components.
+//       <o.0>Error events
+//       <o.1>API function call events
+//       <o.2>Operation events
+//       <o.3>Detailed operation events
+//     </h>
+#ifndef OS_EVR_LEVEL
+#define OS_EVR_LEVEL                0x00U
+#endif
+ 
+//     <h>RTOS Event Filter Setup
+//     <i> Recording levels for RTX components.
+//     <i> Only applicable if events for the respective component are generated.
+ 
+//       <e.7>Memory Management
+//       <i> Recording level for Memory Management events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MEMORY_LEVEL
+#define OS_EVR_MEMORY_LEVEL         0x81U
+#endif
+ 
+//       <e.7>Kernel
+//       <i> Recording level for Kernel events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_KERNEL_LEVEL
+#define OS_EVR_KERNEL_LEVEL         0x81U
+#endif
+ 
+//       <e.7>Thread
+//       <i> Recording level for Thread events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_THREAD_LEVEL
+#define OS_EVR_THREAD_LEVEL         0x85U
+#endif
+ 
+//       <e.7>Generic Wait
+//       <i> Recording level for Generic Wait events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_WAIT_LEVEL
+#define OS_EVR_WAIT_LEVEL           0x81U
+#endif
+ 
+//       <e.7>Thread Flags
+//       <i> Recording level for Thread Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_THFLAGS_LEVEL
+#define OS_EVR_THFLAGS_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Event Flags
+//       <i> Recording level for Event Flags events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_EVFLAGS_LEVEL
+#define OS_EVR_EVFLAGS_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Timer
+//       <i> Recording level for Timer events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_TIMER_LEVEL
+#define OS_EVR_TIMER_LEVEL          0x81U
+#endif
+ 
+//       <e.7>Mutex
+//       <i> Recording level for Mutex events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MUTEX_LEVEL
+#define OS_EVR_MUTEX_LEVEL          0x81U
+#endif
+ 
+//       <e.7>Semaphore
+//       <i> Recording level for Semaphore events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_SEMAPHORE_LEVEL
+#define OS_EVR_SEMAPHORE_LEVEL      0x81U
+#endif
+ 
+//       <e.7>Memory Pool
+//       <i> Recording level for Memory Pool events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MEMPOOL_LEVEL
+#define OS_EVR_MEMPOOL_LEVEL        0x81U
+#endif
+ 
+//       <e.7>Message Queue
+//       <i> Recording level for Message Queue events.
+//         <o.0>Error events
+//         <o.1>API function call events
+//         <o.2>Operation events
+//         <o.3>Detailed operation events
+//       </e>
+#ifndef OS_EVR_MSGQUEUE_LEVEL
+#define OS_EVR_MSGQUEUE_LEVEL       0x81U
+#endif
+ 
+//     </h>
+ 
+//   </e>
+ 
+//   <h>RTOS Event Generation
+//   <i> Enables event generation for RTX components (requires RTX source variant).
+ 
+//     <q>Memory Management
+//     <i> Enables Memory Management event generation.
+#ifndef OS_EVR_MEMORY
+#define OS_EVR_MEMORY               1
+#endif
+ 
+//     <q>Kernel
+//     <i> Enables Kernel event generation.
+#ifndef OS_EVR_KERNEL
+#define OS_EVR_KERNEL               1
+#endif
+ 
+//     <q>Thread
+//     <i> Enables Thread event generation.
+#ifndef OS_EVR_THREAD
+#define OS_EVR_THREAD               1
+#endif
+ 
+//     <q>Generic Wait
+//     <i> Enables Generic Wait event generation.
+#ifndef OS_EVR_WAIT
+#define OS_EVR_WAIT                 1
+#endif
+ 
+//     <q>Thread Flags
+//     <i> Enables Thread Flags event generation.
+#ifndef OS_EVR_THFLAGS
+#define OS_EVR_THFLAGS              1
+#endif
+ 
+//     <q>Event Flags
+//     <i> Enables Event Flags event generation.
+#ifndef OS_EVR_EVFLAGS
+#define OS_EVR_EVFLAGS              1
+#endif
+ 
+//     <q>Timer
+//     <i> Enables Timer event generation.
+#ifndef OS_EVR_TIMER
+#define OS_EVR_TIMER                1
+#endif
+ 
+//     <q>Mutex
+//     <i> Enables Mutex event generation.
+#ifndef OS_EVR_MUTEX
+#define OS_EVR_MUTEX                1
+#endif
+ 
+//     <q>Semaphore
+//     <i> Enables Semaphore event generation.
+#ifndef OS_EVR_SEMAPHORE
+#define OS_EVR_SEMAPHORE            1
+#endif
+ 
+//     <q>Memory Pool
+//     <i> Enables Memory Pool event generation.
+#ifndef OS_EVR_MEMPOOL
+#define OS_EVR_MEMPOOL              1
+#endif
+ 
+//     <q>Message Queue
+//     <i> Enables Message Queue event generation.
+#ifndef OS_EVR_MSGQUEUE
+#define OS_EVR_MSGQUEUE             1
+#endif
+ 
+//   </h>
+ 
+// </h>
+ 
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#ifndef OS_THREAD_LIBSPACE_NUM
+#define OS_THREAD_LIBSPACE_NUM      4
+#endif
+#else
+#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
+#endif
+ 
+//------------- <<< end of configuration section >>> ---------------------------
+ 
+#endif  // RTX_CONFIG_H_

ComputeGraph/tests/RTE/Compiler/EventRecorderConf.h

@@ -0,0 +1,34 @@
+/*------------------------------------------------------------------------------
+ * MDK - Component ::Event Recorder
+ * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    EventRecorderConf.h
+ * Purpose: Event Recorder Configuration
+ * Rev.:    V1.1.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Event Recorder
+
+//   <o>Number of Records
+//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
+//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
+//     <65536=>65536
+//   <i>Configures size of Event Record Buffer (each record is 16 bytes)
+//   <i>Must be 2^n (min=8, max=65536)
+#define EVENT_RECORD_COUNT      64U
+
+//   <o>Time Stamp Source
+//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer
+//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
+//   <i>Selects source for 32-bit time stamp
+#define EVENT_TIMESTAMP_SOURCE  0
+
+//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
+//   <i>Defines initial time stamp clock frequency (0 when not used)
+#define EVENT_TIMESTAMP_FREQ    50000000U
+
+// </h>
+
+//------------- <<< end of configuration section >>> ---------------------------

ComputeGraph/tests/RTE/Compiler/EventRecorderConf.h.base@1.1.0

@@ -0,0 +1,34 @@
+/*------------------------------------------------------------------------------
+ * MDK - Component ::Event Recorder
+ * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    EventRecorderConf.h
+ * Purpose: Event Recorder Configuration
+ * Rev.:    V1.1.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>Event Recorder
+
+//   <o>Number of Records
+//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
+//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
+//     <65536=>65536
+//   <i>Configures size of Event Record Buffer (each record is 16 bytes)
+//   <i>Must be 2^n (min=8, max=65536)
+#define EVENT_RECORD_COUNT      64U
+
+//   <o>Time Stamp Source
+//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer
+//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
+//   <i>Selects source for 32-bit time stamp
+#define EVENT_TIMESTAMP_SOURCE  0
+
+//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
+//   <i>Defines initial time stamp clock frequency (0 when not used)
+#define EVENT_TIMESTAMP_FREQ    0U
+
+// </h>
+
+//------------- <<< end of configuration section >>> ---------------------------

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/RTE_Device.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define   RTE_USART0                     1
+
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define   RTE_USART1                     1
+
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define   RTE_ISRAM0_MPC                 1
+
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
+#define   RTE_ISRAM1_MPC                 1
+
+// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
+// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
+#define   RTE_SRAM_MPC                   1
+
+// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
+#define   RTE_QSPI_MPC                   1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN_EXP0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN_EXP1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP2             1
+
+// <q> Flash device emulated by SRAM [Driver_Flash0]
+// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
+#define   RTE_FLASH0                     1
+
+// <q> I2C SBCon [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define   RTE_I2C0                    1
+
+#endif  /* __RTE_DEVICE_H */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/RTE_Device.h.base@1.1.0

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define   RTE_USART0                     1
+
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define   RTE_USART1                     1
+
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define   RTE_ISRAM0_MPC                 1
+
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
+#define   RTE_ISRAM1_MPC                 1
+
+// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
+// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
+#define   RTE_SRAM_MPC                   1
+
+// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
+#define   RTE_QSPI_MPC                   1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN_EXP0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_MAIN_EXP1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP0             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP1             1
+
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
+#define   RTE_PPC_SSE300_PERIPH_EXP2             1
+
+// <q> Flash device emulated by SRAM [Driver_Flash0]
+// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
+#define   RTE_FLASH0                     1
+
+// <q> I2C SBCon [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define   RTE_I2C0                    1
+
+#endif  /* __RTE_DEVICE_H */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_DRIVER_CONFIG_H__
+#define __CMSIS_DRIVER_CONFIG_H__
+
+#include "system_SSE300MPS3.h"
+#include "device_cfg.h"
+#include "device_definition.h"
+#include "platform_base_address.h"
+
+#endif  /* __CMSIS_DRIVER_CONFIG_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_DRIVER_CONFIG_H__
+#define __CMSIS_DRIVER_CONFIG_H__
+
+#include "system_SSE300MPS3.h"
+#include "device_cfg.h"
+#include "device_definition.h"
+#include "platform_base_address.h"
+
+#endif  /* __CMSIS_DRIVER_CONFIG_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/device_cfg.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DEVICE_CFG_H__
+#define __DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief Configuration file native driver re-targeting
+ *
+ * \details This file can be used to add native driver specific macro
+ *          definitions to select which peripherals are available in the build.
+ *
+ * This is a default device configuration file with all peripherals enabled.
+ */
+
+/* Secure only peripheral configuration */
+
+/* ARM MPS3 IO SCC */
+#define MPS3_IO_S
+#define MPS3_IO_DEV                 MPS3_IO_DEV_S
+
+/* I2C_SBCon */
+#define I2C0_SBCON_S
+#define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
+
+/* I2S */
+#define MPS3_I2S_S
+#define MPS3_I2S_DEV                MPS3_I2S_DEV_S
+
+/* ARM UART Controller PL011 */
+#define UART0_CMSDK_S
+#define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
+#define UART1_CMSDK_S
+#define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
+
+#define DEFAULT_UART_BAUDRATE    115200U
+
+/* To be used as CODE and DATA sram */
+#define MPC_ISRAM0_S
+#define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
+
+#define MPC_ISRAM1_S
+#define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
+
+#define MPC_SRAM_S
+#define MPC_SRAM_DEV                MPC_SRAM_DEV_S
+
+#define MPC_QSPI_S
+#define MPC_QSPI_DEV                MPC_QSPI_DEV_S
+
+/** System Counter Armv8-M */
+#define SYSCOUNTER_CNTRL_ARMV8_M_S
+#define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
+
+#define SYSCOUNTER_READ_ARMV8_M_S
+#define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
+/**
+ * Arbitrary scaling values for test purposes
+ */
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
+
+/* System timer */
+#define SYSTIMER0_ARMV8_M_S
+#define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
+#define SYSTIMER1_ARMV8_M_S
+#define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
+#define SYSTIMER2_ARMV8_M_S
+#define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
+#define SYSTIMER3_ARMV8_M_S
+#define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
+
+#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+
+/* CMSDK GPIO driver structures */
+#define GPIO0_CMSDK_S
+#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
+#define GPIO1_CMSDK_S
+#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
+#define GPIO2_CMSDK_S
+#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
+#define GPIO3_CMSDK_S
+#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
+
+/* System Watchdogs */
+#define SYSWDOG_ARMV8_M_S
+#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
+
+/* ARM MPC SIE 300 driver structures */
+#define MPC_VM0_S
+#define MPC_VM0_DEV MPC_VM0_DEV_S
+#define MPC_VM1_S
+#define MPC_VM1_DEV MPC_VM1_DEV_S
+#define MPC_SSRAM2_S
+#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
+#define MPC_SSRAM3_S
+#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
+
+/* ARM PPC driver structures */
+#define PPC_SSE300_MAIN0_S
+#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
+#define PPC_SSE300_MAIN_EXP0_S
+#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
+#define PPC_SSE300_MAIN_EXP1_S
+#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
+#define PPC_SSE300_MAIN_EXP2_S
+#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
+#define PPC_SSE300_MAIN_EXP3_S
+#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
+#define PPC_SSE300_PERIPH0_S
+#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
+#define PPC_SSE300_PERIPH1_S
+#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
+#define PPC_SSE300_PERIPH_EXP0_S
+#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
+#define PPC_SSE300_PERIPH_EXP1_S
+#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
+#define PPC_SSE300_PERIPH_EXP2_S
+#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
+#define PPC_SSE300_PERIPH_EXP3_S
+#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
+
+/* ARM SPI PL022 */
+/* Invalid device stubs are not defined */
+#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
+#define SPI1_PL022_S
+#define SPI1_PL022_DEV SPI1_PL022_DEV_S
+
+
+#endif  /* __DEVICE_CFG_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.3

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DEVICE_CFG_H__
+#define __DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief Configuration file native driver re-targeting
+ *
+ * \details This file can be used to add native driver specific macro
+ *          definitions to select which peripherals are available in the build.
+ *
+ * This is a default device configuration file with all peripherals enabled.
+ */
+
+/* Secure only peripheral configuration */
+
+/* ARM MPS3 IO SCC */
+#define MPS3_IO_S
+#define MPS3_IO_DEV                 MPS3_IO_DEV_S
+
+/* I2C_SBCon */
+#define I2C0_SBCON_S
+#define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
+
+/* I2S */
+#define MPS3_I2S_S
+#define MPS3_I2S_DEV                MPS3_I2S_DEV_S
+
+/* ARM UART Controller PL011 */
+#define UART0_CMSDK_S
+#define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
+#define UART1_CMSDK_S
+#define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
+
+#define DEFAULT_UART_BAUDRATE    115200U
+
+/* To be used as CODE and DATA sram */
+#define MPC_ISRAM0_S
+#define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
+
+#define MPC_ISRAM1_S
+#define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
+
+#define MPC_SRAM_S
+#define MPC_SRAM_DEV                MPC_SRAM_DEV_S
+
+#define MPC_QSPI_S
+#define MPC_QSPI_DEV                MPC_QSPI_DEV_S
+
+/** System Counter Armv8-M */
+#define SYSCOUNTER_CNTRL_ARMV8_M_S
+#define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
+
+#define SYSCOUNTER_READ_ARMV8_M_S
+#define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
+/**
+ * Arbitrary scaling values for test purposes
+ */
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
+#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
+
+/* System timer */
+#define SYSTIMER0_ARMV8_M_S
+#define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
+#define SYSTIMER1_ARMV8_M_S
+#define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
+#define SYSTIMER2_ARMV8_M_S
+#define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
+#define SYSTIMER3_ARMV8_M_S
+#define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
+
+#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
+
+/* CMSDK GPIO driver structures */
+#define GPIO0_CMSDK_S
+#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
+#define GPIO1_CMSDK_S
+#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
+#define GPIO2_CMSDK_S
+#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
+#define GPIO3_CMSDK_S
+#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
+
+/* System Watchdogs */
+#define SYSWDOG_ARMV8_M_S
+#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
+
+/* ARM MPC SIE 300 driver structures */
+#define MPC_VM0_S
+#define MPC_VM0_DEV MPC_VM0_DEV_S
+#define MPC_VM1_S
+#define MPC_VM1_DEV MPC_VM1_DEV_S
+#define MPC_SSRAM2_S
+#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
+#define MPC_SSRAM3_S
+#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
+
+/* ARM PPC driver structures */
+#define PPC_SSE300_MAIN0_S
+#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
+#define PPC_SSE300_MAIN_EXP0_S
+#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
+#define PPC_SSE300_MAIN_EXP1_S
+#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
+#define PPC_SSE300_MAIN_EXP2_S
+#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
+#define PPC_SSE300_MAIN_EXP3_S
+#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
+#define PPC_SSE300_PERIPH0_S
+#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
+#define PPC_SSE300_PERIPH1_S
+#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
+#define PPC_SSE300_PERIPH_EXP0_S
+#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
+#define PPC_SSE300_PERIPH_EXP1_S
+#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
+#define PPC_SSE300_PERIPH_EXP2_S
+#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
+#define PPC_SSE300_PERIPH_EXP3_S
+#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
+
+/* ARM SPI PL022 */
+/* Invalid device stubs are not defined */
+#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
+#define SPI1_PL022_S
+#define SPI1_PL022_DEV SPI1_PL022_DEV_S
+
+
+#endif  /* __DEVICE_CFG_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct

@@ -0,0 +1,78 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
+
+;/*
+; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; */
+
+#include "region_defs.h"
+
+LR_CODE S_CODE_START {
+    ER_CODE S_CODE_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+    }
+
+    /*
+     * Place the CMSE Veneers (containing the SG instruction) after the code, in
+     * a separate 32 bytes aligned region so that the SAU can programmed to just
+     * set this region as Non-Secure Callable. The maximum size of this
+     * executable region makes it only used the space left over by the ER_CODE
+     * region so that you can rely on code+veneer size combined will not exceed
+     * the S_CODE_SIZE value. We also substract from the available space the
+     * area used to align this section on 32 bytes boundary (for SAU conf).
+     */
+    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
+        *(Veneer$$CMSE)
+    }
+    /*
+     * This dummy region ensures that the next one will be aligned on a 32 bytes
+     * boundary, so that the following region will not be mistakenly configured
+     * as Non-Secure Callable by the SAU.
+     */
+    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    CODE_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
+
+    ER_DATA S_DATA_START {
+        .ANY (+ZI +RW)
+    }
+
+    #if HEAP_SIZE > 0
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
+    }
+    #endif
+
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    SRAM_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0

@@ -0,0 +1,78 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
+
+;/*
+; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; */
+
+#include "region_defs.h"
+
+LR_CODE S_CODE_START {
+    ER_CODE S_CODE_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+    }
+
+    /*
+     * Place the CMSE Veneers (containing the SG instruction) after the code, in
+     * a separate 32 bytes aligned region so that the SAU can programmed to just
+     * set this region as Non-Secure Callable. The maximum size of this
+     * executable region makes it only used the space left over by the ER_CODE
+     * region so that you can rely on code+veneer size combined will not exceed
+     * the S_CODE_SIZE value. We also substract from the available space the
+     * area used to align this section on 32 bytes boundary (for SAU conf).
+     */
+    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
+        *(Veneer$$CMSE)
+    }
+    /*
+     * This dummy region ensures that the next one will be aligned on a 32 bytes
+     * boundary, so that the following region will not be mistakenly configured
+     * as Non-Secure Callable by the SAU.
+     */
+    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    CODE_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)
+
+    ER_DATA S_DATA_START {
+        .ANY (+ZI +RW)
+    }
+
+    #if HEAP_SIZE > 0
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
+    }
+    #endif
+
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
+    }
+
+    /* This empty, zero long execution region is here to mark the limit address
+     * of the last execution region that is allocated in SRAM.
+     */
+    SRAM_WATERMARK +0 EMPTY 0x0 {
+    }
+    /* Make sure that the sections allocated in the SRAM does not exceed the
+     * size of the SRAM available.
+     */
+    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/platform_base_address.h

@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2019-2021 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_base_address.h
+ * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
+ *        Ethos-U55 platform.
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H__
+#define __PLATFORM_BASE_ADDRESS_H__
+
+/* ======= Defines peripherals memory map addresses ======= */
+/* Non-secure memory map addresses */
+#define ITCM_BASE_NS                     0x00000000 /* Instruction TCM Non-Secure base address */
+#define SRAM_BASE_NS                     0x01000000 /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS                    0x20000000 /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS                    0x20020000 /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS                    0x20040000 /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS                    0x20060000 /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS                   0x21000000 /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS                   0x21100000 /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS                0x28000000 /* QSPI SRAM Non-Secure base address */
+/* Non-Secure Subsystem peripheral region */
+#define CPU0_PWRCTRL_BASE_NS             0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
+#define CPU0_IDENTITY_BASE_NS            0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
+#define SSE300_NSACFG_BASE_NS            0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
+/* Non-Secure MSTEXPPILL Peripheral region */
+#define GPIO0_CMSDK_BASE_NS              0x41100000 /* GPIO 0 Non-Secure base address */
+#define GPIO1_CMSDK_BASE_NS              0x41101000 /* GPIO 1 Non-Secure base address */
+#define GPIO2_CMSDK_BASE_NS              0x41102000 /* GPIO 2 Non-Secure base address */
+#define GPIO3_CMSDK_BASE_NS              0x41103000 /* GPIO 3 Non-Secure base address */
+#define FMC_CMSDK_GPIO_0_BASE_NS         0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
+#define FMC_CMSDK_GPIO_1_BASE_NS         0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
+#define FMC_CMSDK_GPIO_2_BASE_NS         0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
+#define FMC_CMSDK_GPIO_3_BASE_NS         0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
+#define EXTERNAL_MANAGER_0_BASE_NS       0x41200000 /* External manager 0 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_1_BASE_NS       0x41201000 /* External manager 1 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_2_BASE_NS       0x41202000 /* External manager 2 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_3_BASE_NS       0x41203000 /* External manager 3 (Unused) Non-Secure base address */
+#define ETHERNET_BASE_NS                 0x41400000 /* Ethernet Non-Secure base address */
+#define USB_BASE_NS                      0x41500000 /* USB Non-Secure base address */
+#define USER_APB0_BASE_NS                0x41700000 /* User APB 0 Non-Secure base address */
+#define USER_APB1_BASE_NS                0x41701000 /* User APB 1 Non-Secure base address */
+#define USER_APB2_BASE_NS                0x41702000 /* User APB 2 Non-Secure base address */
+#define USER_APB3_BASE_NS                0x41703000 /* User APB 3 Non-Secure base address */
+#define QSPI_CONFIG_BASE_NS              0x41800000 /* QSPI Config Non-Secure base address */
+#define QSPI_WRITE_BASE_NS               0x41801000 /* QSPI Write Non-Secure base address */
+/* Non-Secure Subsystem peripheral region */
+#define SYSTIMER0_ARMV8_M_BASE_NS        0x48000000 /* System Timer 0 Non-Secure base address */
+#define SYSTIMER1_ARMV8_M_BASE_NS        0x48001000 /* System Timer 1 Non-Secure base address */
+#define SYSTIMER2_ARMV8_M_BASE_NS        0x48002000 /* System Timer 2 Non-Secure base address */
+#define SYSTIMER3_ARMV8_M_BASE_NS        0x48003000 /* System Timer 3 Non-Secure base address */
+#define SSE300_SYSINFO_BASE_NS           0x48020000 /* SSE-300 System info Block Non-Secure base address */
+#define SLOWCLK_TIMER_CMSDK_BASE_NS      0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
+#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS    0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
+#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS  0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
+#define SYSCNTR_READ_BASE_NS             0x48101000 /* System Counter Read Secure base address */
+/* Non-Secure MSTEXPPIHL Peripheral region */
+#define ETHOS_U55_APB_BASE_NS            0x48102000 /* Ethos-U55 APB Non-Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_NS     0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_NS     0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
+#define FPGA_SBCon_I2C_TOUCH_BASE_NS     0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
+#define FPGA_SBCon_I2C_AUDIO_BASE_NS     0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
+#define FPGA_SPI_ADC_BASE_NS             0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
+#define FPGA_SPI_SHIELD0_BASE_NS         0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
+#define FPGA_SPI_SHIELD1_BASE_NS         0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
+#define SBCon_I2C_SHIELD0_BASE_NS        0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
+#define SBCon_I2C_SHIELD1_BASE_NS        0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
+#define USER_APB_BASE_NS                 0x49207000 /* USER APB Non-Secure base address */
+#define FPGA_DDR4_EEPROM_BASE_NS         0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
+#define FMC_USER_APB0                    0x4920C000 /* FMC User APB0 */
+#define FMC_USER_APB1                    0x4920D000 /* FMC User APB1 */
+#define FMC_USER_APB2                    0x4920E000 /* FMC User APB2 */
+#define FMC_USER_APB3                    0x4920F000 /* FMC User APB3 */
+#define FPGA_SCC_BASE_NS                 0x49300000 /* FPGA - SCC registers Non-Secure base address */
+#define FPGA_I2S_BASE_NS                 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
+#define FPGA_IO_BASE_NS                  0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
+#define UART0_BASE_NS                    0x49303000 /* UART 0 Non-Secure base address */
+#define UART1_BASE_NS                    0x49304000 /* UART 1 Non-Secure base address */
+#define UART2_BASE_NS                    0x49305000 /* UART 2 Non-Secure base address */
+#define UART3_BASE_NS                    0x49306000 /* UART 3 Non-Secure base address */
+#define UART4_BASE_NS                    0x49307000 /* UART 4 Non-Secure base address */
+#define UART5_BASE_NS                    0x49308000 /* UART 5 Non-Secure base address */
+#define CLCD_Config_Reg_BASE_NS          0x4930A000 /* CLCD Config Reg Non-Secure base address */
+#define RTC_BASE_NS                      0x4930B000 /* RTC Non-Secure base address */
+#define DDR4_BLK0_BASE_NS                0x60000000 /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS                0x80000000 /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK4_BASE_NS                0xA0000000 /* DDR4 block 4 Non-Secure base address */
+#define DDR4_BLK6_BASE_NS                0xC0000000 /* DDR4 block 6 Non-Secure base address */
+
+/* Secure memory map addresses */
+#define ITCM_BASE_S                      0x10000000 /* Instruction TCM Secure base address */
+#define SRAM_BASE_S                      0x11000000 /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S                     0x30000000 /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S                     0x30020000 /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S                     0x30040000 /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S                     0x30060000 /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S                    0x31000000 /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S                    0x31100000 /* Internal SRAM Area Secure base address */
+#define QSPI_SRAM_BASE_S                 0x38000000 /* QSPI SRAM Secure base address */
+/* Secure Subsystem peripheral region */
+#define CPU0_SECCTRL_BASE_S              0x50011000 /* CPU 0 Local Security Control Block Secure base address */
+#define CPU0_PWRCTRL_BASE_S              0x50012000 /* CPU 0 Power Control Block Secure base address */
+#define CPU0_IDENTITY_BASE_S             0x5001F000 /* CPU 0 Identity Block Secure base address */
+#define SSE300_SACFG_BASE_S              0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
+#define MPC_ISRAM0_BASE_S                0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
+#define MPC_ISRAM1_BASE_S                0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
+/* Secure MSTEXPPILL Peripheral region */
+#define GPIO0_CMSDK_BASE_S               0x51100000 /* GPIO 0 Secure base address */
+#define GPIO1_CMSDK_BASE_S               0x51101000 /* GPIO 1 Secure base address */
+#define GPIO2_CMSDK_BASE_S               0x51102000 /* GPIO 2 Secure base address */
+#define GPIO3_CMSDK_BASE_S               0x51103000 /* GPIO 3 Secure base address */
+#define FMC_CMSDK_GPIO_0_BASE_S          0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
+#define FMC_CMSDK_GPIO_1_BASE_S          0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
+#define FMC_CMSDK_GPIO_2_BASE_S          0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
+#define FMC_CMSDK_GPIO_3_BASE_S          0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
+#define EXTERNAL_MANAGER0_BASE_S         0x51200000 /* External Manager 0 (Unused) Secure base address */
+#define EXTERNAL_MANAGER1_BASE_S         0x51201000 /* External Manager 1 (Unused) Secure base address */
+#define EXTERNAL_MANAGER2_BASE_S         0x51202000 /* External Manager 2 (Unused) Secure base address */
+#define EXTERNAL_MANAGER3_BASE_S         0x51203000 /* External Manager 3 (Unused) Secure base address */
+#define ETHERNET_BASE_S                  0x51400000 /* Ethernet Secure base address */
+#define USB_BASE_S                       0x51500000 /* USB Secure base address */
+#define USER_APB0_BASE_S                 0x51700000 /* User APB 0 Secure base address */
+#define USER_APB1_BASE_S                 0x51701000 /* User APB 1 Secure base address */
+#define USER_APB2_BASE_S                 0x51702000 /* User APB 2 Secure base address */
+#define USER_APB3_BASE_S                 0x51703000 /* User APB 3 Secure base address */
+#define QSPI_CONFIG_BASE_S               0x51800000 /* QSPI Config Secure base address */
+#define QSPI_WRITE_BASE_S                0x51801000 /* QSPI Write Secure base address */
+#define MPC_SRAM_BASE_S                  0x57000000 /* SRAM Memory Protection Controller Secure base address */
+#define MPC_QSPI_BASE_S                  0x57001000 /* QSPI Memory Protection Controller Secure base address */
+#define MPC_DDR4_BASE_S                  0x57002000 /* DDR4 Memory Protection Controller Secure base address */
+/* Secure Subsystem peripheral region */
+#define SYSTIMER0_ARMV8_M_BASE_S         0x58000000 /* System Timer 0 Secure base address */
+#define SYSTIMER1_ARMV8_M_BASE_S         0x58001000 /* System Timer 1 Secure base address */
+#define SYSTIMER2_ARMV8_M_BASE_S         0x58002000 /* System Timer 0 Secure base address */
+#define SYSTIMER3_ARMV8_M_BASE_S         0x58003000 /* System Timer 1 Secure base address */
+#define SSE300_SYSINFO_BASE_S            0x58020000 /* SSE-300 System info Block Secure base address */
+#define SSE300_SYSCTRL_BASE_S            0x58021000 /* SSE-300 System control Block Secure base address */
+#define SSE300_SYSPPU_BASE_S             0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
+#define SSE300_CPU0PPU_BASE_S            0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
+#define SSE300_MGMTPPU_BASE_S            0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
+#define SSE300_DBGPPU_BASE_S             0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
+#define SLOWCLK_WDOG_CMSDK_BASE_S        0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
+#define SLOWCLK_TIMER_CMSDK_BASE_S       0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
+#define SYSWDOG_ARMV8_M_CNTRL_BASE_S     0x58040000 /* Secure Watchdog Timer control frame Secure base address */
+#define SYSWDOG_ARMV8_M_REFRESH_BASE_S   0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
+#define SYSCNTR_CNTRL_BASE_S             0x58100000 /* System Counter Control Secure base address */
+#define SYSCNTR_READ_BASE_S              0x58101000 /* System Counter Read Secure base address */
+/* Secure MSTEXPPIHL Peripheral region */
+#define ETHOS_U55_APB_BASE_S             0x58102000 /* Ethos-U55 APB Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_S      0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_S      0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
+#define FPGA_SBCon_I2C_TOUCH_BASE_S      0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
+#define FPGA_SBCon_I2C_AUDIO_BASE_S      0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
+#define FPGA_SPI_ADC_BASE_S              0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
+#define FPGA_SPI_SHIELD0_BASE_S          0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
+#define FPGA_SPI_SHIELD1_BASE_S          0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
+#define SBCon_I2C_SHIELD0_BASE_S         0x59205000 /* SBCon (I2C - Shield0) Secure base address */
+#define SBCon_I2C_SHIELD1_BASE_S         0x59206000 /* SBCon (I2C – Shield1) Secure base address */
+#define USER_APB_BASE_S                  0x59207000 /* USER APB Secure base address */
+#define FPGA_DDR4_EEPROM_BASE_S          0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
+#define FMC_USER_APB_0_BASE_S            0x5920C000 /* FMC User APB0 registers Secure base address */
+#define FMC_USER_APB_1_BASE_S            0x5920D000 /* FMC User APB1 registers Secure base address */
+#define FMC_USER_APB_2_BASE_S            0x5920E000 /* FMC User APB2 registers Secure base address */
+#define FMC_USER_APB_3_BASE_S            0x5920F000 /* FMC User APB3 registers Secure base address */
+#define FPGA_SCC_BASE_S                  0x59300000 /* FPGA - SCC registers Secure base address */
+#define FPGA_I2S_BASE_S                  0x59301000 /* FPGA - I2S (Audio) Secure base address */
+#define FPGA_IO_BASE_S                   0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
+#define UART0_BASE_S                     0x59303000 /* UART 0 Secure base address */
+#define UART1_BASE_S                     0x59304000 /* UART 1 Secure base address */
+#define UART2_BASE_S                     0x59305000 /* UART 2 Secure base address */
+#define UART3_BASE_S                     0x59306000 /* UART 3 Secure base address */
+#define UART4_BASE_S                     0x59307000 /* UART 4 Secure base address */
+#define UART5_BASE_S                     0x59308000 /* UART 5 Secure base address */
+#define CLCD_Config_Reg_BASE_S           0x5930A000 /* CLCD Config Reg Secure base address */
+#define RTC_BASE_S                       0x5930B000 /* RTC Secure base address */
+#define DDR4_BLK1_BASE_S                 0x70000000 /* DDR4 block 1 Secure base address */
+#define DDR4_BLK3_BASE_S                 0x90000000 /* DDR4 block 3 Secure base address */
+#define DDR4_BLK5_BASE_S                 0xB0000000 /* DDR4 block 5 Secure base address */
+#define DDR4_BLK7_BASE_S                 0xD0000000 /* DDR4 block 7 Secure base address */
+
+/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
+#define SSE300_EWIC_BASE                 0xE0047000 /* External Wakeup Interrupt Controller
+                                                     * Access from Non-secure software is only allowed
+                                                     * if AIRCR.BFHFNMINS is set to 1 */
+
+/* Memory size definitions */
+#define ITCM_SIZE       (0x00080000) /* 512 kB */
+#define DTCM_BLK_SIZE   (0x00020000) /* 128 kB */
+#define DTCM_BLK_NUM    (0x4)        /* Number of DTCM blocks */
+#define SRAM_SIZE       (0x00100000) /* 1 MB */
+#define ISRAM0_SIZE     (0x00100000) /* 1 MB */
+#define ISRAM1_SIZE     (0x00100000) /* 1 MB */
+#define QSPI_SRAM_SIZE  (0x00800000) /* 8 MB */
+#define DDR4_BLK_SIZE   (0x10000000) /* 256 MB */
+#define DDR4_BLK_NUM    (0x8)        /* Number of DDR4 blocks */
+
+/* Defines for Driver MPC's */
+/* SRAM -- 2 MB */
+#define MPC_SRAM_RANGE_BASE_NS   (SRAM_BASE_NS)
+#define MPC_SRAM_RANGE_LIMIT_NS  (SRAM_BASE_NS + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
+#define MPC_SRAM_RANGE_BASE_S    (SRAM_BASE_S)
+#define MPC_SRAM_RANGE_LIMIT_S   (SRAM_BASE_S + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_S  (0x0)
+
+/* QSPI -- 8 MB*/
+#define MPC_QSPI_RANGE_BASE_NS   (QSPI_SRAM_BASE_NS)
+#define MPC_QSPI_RANGE_LIMIT_NS  (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
+#define MPC_QSPI_RANGE_BASE_S    (QSPI_SRAM_BASE_S)
+#define MPC_QSPI_RANGE_LIMIT_S   (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_S  (0x0)
+
+/* ISRAM0 -- 2 MB*/
+#define MPC_ISRAM0_RANGE_BASE_NS   (ISRAM0_BASE_NS)
+#define MPC_ISRAM0_RANGE_LIMIT_NS  (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
+#define MPC_ISRAM0_RANGE_BASE_S    (ISRAM0_BASE_S)
+#define MPC_ISRAM0_RANGE_LIMIT_S   (ISRAM0_BASE_S + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_S  (0x0)
+
+/* ISRAM1 -- 2 MB*/
+#define MPC_ISRAM1_RANGE_BASE_NS   (ISRAM1_BASE_NS)
+#define MPC_ISRAM1_RANGE_LIMIT_NS  (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
+#define MPC_ISRAM1_RANGE_BASE_S    (ISRAM1_BASE_S)
+#define MPC_ISRAM1_RANGE_LIMIT_S   (ISRAM1_BASE_S + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_S  (0x0)
+
+/* DDR4 -- 2GB (8 * 256 MB) */
+#define MPC_DDR4_BLK0_RANGE_BASE_NS   (DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK0_RANGE_LIMIT_NS  (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
+#define MPC_DDR4_BLK1_RANGE_BASE_S    (DDR4_BLK1_BASE_S)
+#define MPC_DDR4_BLK1_RANGE_LIMIT_S   (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK1_RANGE_OFFSET_S  (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_BASE_NS   (DDR4_BLK2_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_LIMIT_NS  (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK3_RANGE_BASE_S    (DDR4_BLK3_BASE_S)
+#define MPC_DDR4_BLK3_RANGE_LIMIT_S   (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK3_RANGE_OFFSET_S  (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_BASE_NS   (DDR4_BLK4_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_LIMIT_NS  (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK5_RANGE_BASE_S    (DDR4_BLK5_BASE_S)
+#define MPC_DDR4_BLK5_RANGE_LIMIT_S   (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK5_RANGE_OFFSET_S  (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_BASE_NS   (DDR4_BLK6_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_LIMIT_NS  (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK7_RANGE_BASE_S    (DDR4_BLK7_BASE_S)
+#define MPC_DDR4_BLK7_RANGE_LIMIT_S   (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK7_RANGE_OFFSET_S  (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
+
+#endif  /* __PLATFORM_BASE_ADDRESS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/platform_base_address.h.base@1.1.2

@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2019-2021 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_base_address.h
+ * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 +
+ *        Ethos-U55 platform.
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H__
+#define __PLATFORM_BASE_ADDRESS_H__
+
+/* ======= Defines peripherals memory map addresses ======= */
+/* Non-secure memory map addresses */
+#define ITCM_BASE_NS                     0x00000000 /* Instruction TCM Non-Secure base address */
+#define SRAM_BASE_NS                     0x01000000 /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS                    0x20000000 /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS                    0x20020000 /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS                    0x20040000 /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS                    0x20060000 /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS                   0x21000000 /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS                   0x21100000 /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS                0x28000000 /* QSPI SRAM Non-Secure base address */
+/* Non-Secure Subsystem peripheral region */
+#define CPU0_PWRCTRL_BASE_NS             0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
+#define CPU0_IDENTITY_BASE_NS            0x4001F000 /* CPU 0 Identity Block Non-Secure base address */
+#define SSE300_NSACFG_BASE_NS            0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */
+/* Non-Secure MSTEXPPILL Peripheral region */
+#define GPIO0_CMSDK_BASE_NS              0x41100000 /* GPIO 0 Non-Secure base address */
+#define GPIO1_CMSDK_BASE_NS              0x41101000 /* GPIO 1 Non-Secure base address */
+#define GPIO2_CMSDK_BASE_NS              0x41102000 /* GPIO 2 Non-Secure base address */
+#define GPIO3_CMSDK_BASE_NS              0x41103000 /* GPIO 3 Non-Secure base address */
+#define FMC_CMSDK_GPIO_0_BASE_NS         0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */
+#define FMC_CMSDK_GPIO_1_BASE_NS         0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */
+#define FMC_CMSDK_GPIO_2_BASE_NS         0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */
+#define FMC_CMSDK_GPIO_3_BASE_NS         0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */
+#define EXTERNAL_MANAGER_0_BASE_NS       0x41200000 /* External manager 0 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_1_BASE_NS       0x41201000 /* External manager 1 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_2_BASE_NS       0x41202000 /* External manager 2 (Unused) Non-Secure base address */
+#define EXTERNAL_MANAGER_3_BASE_NS       0x41203000 /* External manager 3 (Unused) Non-Secure base address */
+#define ETHERNET_BASE_NS                 0x41400000 /* Ethernet Non-Secure base address */
+#define USB_BASE_NS                      0x41500000 /* USB Non-Secure base address */
+#define USER_APB0_BASE_NS                0x41700000 /* User APB 0 Non-Secure base address */
+#define USER_APB1_BASE_NS                0x41701000 /* User APB 1 Non-Secure base address */
+#define USER_APB2_BASE_NS                0x41702000 /* User APB 2 Non-Secure base address */
+#define USER_APB3_BASE_NS                0x41703000 /* User APB 3 Non-Secure base address */
+#define QSPI_CONFIG_BASE_NS              0x41800000 /* QSPI Config Non-Secure base address */
+#define QSPI_WRITE_BASE_NS               0x41801000 /* QSPI Write Non-Secure base address */
+/* Non-Secure Subsystem peripheral region */
+#define SYSTIMER0_ARMV8_M_BASE_NS        0x48000000 /* System Timer 0 Non-Secure base address */
+#define SYSTIMER1_ARMV8_M_BASE_NS        0x48001000 /* System Timer 1 Non-Secure base address */
+#define SYSTIMER2_ARMV8_M_BASE_NS        0x48002000 /* System Timer 2 Non-Secure base address */
+#define SYSTIMER3_ARMV8_M_BASE_NS        0x48003000 /* System Timer 3 Non-Secure base address */
+#define SSE300_SYSINFO_BASE_NS           0x48020000 /* SSE-300 System info Block Non-Secure base address */
+#define SLOWCLK_TIMER_CMSDK_BASE_NS      0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */
+#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS    0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */
+#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS  0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */
+#define SYSCNTR_READ_BASE_NS             0x48101000 /* System Counter Read Secure base address */
+/* Non-Secure MSTEXPPIHL Peripheral region */
+#define ETHOS_U55_APB_BASE_NS            0x48102000 /* Ethos-U55 APB Non-Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_NS     0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_NS     0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
+#define FPGA_SBCon_I2C_TOUCH_BASE_NS     0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
+#define FPGA_SBCon_I2C_AUDIO_BASE_NS     0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
+#define FPGA_SPI_ADC_BASE_NS             0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
+#define FPGA_SPI_SHIELD0_BASE_NS         0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */
+#define FPGA_SPI_SHIELD1_BASE_NS         0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */
+#define SBCon_I2C_SHIELD0_BASE_NS        0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */
+#define SBCon_I2C_SHIELD1_BASE_NS        0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */
+#define USER_APB_BASE_NS                 0x49207000 /* USER APB Non-Secure base address */
+#define FPGA_DDR4_EEPROM_BASE_NS         0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */
+#define FMC_USER_APB0                    0x4920C000 /* FMC User APB0 */
+#define FMC_USER_APB1                    0x4920D000 /* FMC User APB1 */
+#define FMC_USER_APB2                    0x4920E000 /* FMC User APB2 */
+#define FMC_USER_APB3                    0x4920F000 /* FMC User APB3 */
+#define FPGA_SCC_BASE_NS                 0x49300000 /* FPGA - SCC registers Non-Secure base address */
+#define FPGA_I2S_BASE_NS                 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */
+#define FPGA_IO_BASE_NS                  0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */
+#define UART0_BASE_NS                    0x49303000 /* UART 0 Non-Secure base address */
+#define UART1_BASE_NS                    0x49304000 /* UART 1 Non-Secure base address */
+#define UART2_BASE_NS                    0x49305000 /* UART 2 Non-Secure base address */
+#define UART3_BASE_NS                    0x49306000 /* UART 3 Non-Secure base address */
+#define UART4_BASE_NS                    0x49307000 /* UART 4 Non-Secure base address */
+#define UART5_BASE_NS                    0x49308000 /* UART 5 Non-Secure base address */
+#define CLCD_Config_Reg_BASE_NS          0x4930A000 /* CLCD Config Reg Non-Secure base address */
+#define RTC_BASE_NS                      0x4930B000 /* RTC Non-Secure base address */
+#define DDR4_BLK0_BASE_NS                0x60000000 /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS                0x80000000 /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK4_BASE_NS                0xA0000000 /* DDR4 block 4 Non-Secure base address */
+#define DDR4_BLK6_BASE_NS                0xC0000000 /* DDR4 block 6 Non-Secure base address */
+
+/* Secure memory map addresses */
+#define ITCM_BASE_S                      0x10000000 /* Instruction TCM Secure base address */
+#define SRAM_BASE_S                      0x11000000 /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S                     0x30000000 /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S                     0x30020000 /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S                     0x30040000 /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S                     0x30060000 /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S                    0x31000000 /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S                    0x31100000 /* Internal SRAM Area Secure base address */
+#define QSPI_SRAM_BASE_S                 0x38000000 /* QSPI SRAM Secure base address */
+/* Secure Subsystem peripheral region */
+#define CPU0_SECCTRL_BASE_S              0x50011000 /* CPU 0 Local Security Control Block Secure base address */
+#define CPU0_PWRCTRL_BASE_S              0x50012000 /* CPU 0 Power Control Block Secure base address */
+#define CPU0_IDENTITY_BASE_S             0x5001F000 /* CPU 0 Identity Block Secure base address */
+#define SSE300_SACFG_BASE_S              0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */
+#define MPC_ISRAM0_BASE_S                0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */
+#define MPC_ISRAM1_BASE_S                0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */
+/* Secure MSTEXPPILL Peripheral region */
+#define GPIO0_CMSDK_BASE_S               0x51100000 /* GPIO 0 Secure base address */
+#define GPIO1_CMSDK_BASE_S               0x51101000 /* GPIO 1 Secure base address */
+#define GPIO2_CMSDK_BASE_S               0x51102000 /* GPIO 2 Secure base address */
+#define GPIO3_CMSDK_BASE_S               0x51103000 /* GPIO 3 Secure base address */
+#define FMC_CMSDK_GPIO_0_BASE_S          0x51104000 /* FMC CMSDK GPIO 0 Secure base address */
+#define FMC_CMSDK_GPIO_1_BASE_S          0x51105000 /* FMC CMSDK GPIO 1 Secure base address */
+#define FMC_CMSDK_GPIO_2_BASE_S          0x51106000 /* FMC CMSDK GPIO 2 Secure base address */
+#define FMC_CMSDK_GPIO_3_BASE_S          0x51107000 /* FMC CMSDK GPIO 3 Secure base address */
+#define EXTERNAL_MANAGER0_BASE_S         0x51200000 /* External Manager 0 (Unused) Secure base address */
+#define EXTERNAL_MANAGER1_BASE_S         0x51201000 /* External Manager 1 (Unused) Secure base address */
+#define EXTERNAL_MANAGER2_BASE_S         0x51202000 /* External Manager 2 (Unused) Secure base address */
+#define EXTERNAL_MANAGER3_BASE_S         0x51203000 /* External Manager 3 (Unused) Secure base address */
+#define ETHERNET_BASE_S                  0x51400000 /* Ethernet Secure base address */
+#define USB_BASE_S                       0x51500000 /* USB Secure base address */
+#define USER_APB0_BASE_S                 0x51700000 /* User APB 0 Secure base address */
+#define USER_APB1_BASE_S                 0x51701000 /* User APB 1 Secure base address */
+#define USER_APB2_BASE_S                 0x51702000 /* User APB 2 Secure base address */
+#define USER_APB3_BASE_S                 0x51703000 /* User APB 3 Secure base address */
+#define QSPI_CONFIG_BASE_S               0x51800000 /* QSPI Config Secure base address */
+#define QSPI_WRITE_BASE_S                0x51801000 /* QSPI Write Secure base address */
+#define MPC_SRAM_BASE_S                  0x57000000 /* SRAM Memory Protection Controller Secure base address */
+#define MPC_QSPI_BASE_S                  0x57001000 /* QSPI Memory Protection Controller Secure base address */
+#define MPC_DDR4_BASE_S                  0x57002000 /* DDR4 Memory Protection Controller Secure base address */
+/* Secure Subsystem peripheral region */
+#define SYSTIMER0_ARMV8_M_BASE_S         0x58000000 /* System Timer 0 Secure base address */
+#define SYSTIMER1_ARMV8_M_BASE_S         0x58001000 /* System Timer 1 Secure base address */
+#define SYSTIMER2_ARMV8_M_BASE_S         0x58002000 /* System Timer 0 Secure base address */
+#define SYSTIMER3_ARMV8_M_BASE_S         0x58003000 /* System Timer 1 Secure base address */
+#define SSE300_SYSINFO_BASE_S            0x58020000 /* SSE-300 System info Block Secure base address */
+#define SSE300_SYSCTRL_BASE_S            0x58021000 /* SSE-300 System control Block Secure base address */
+#define SSE300_SYSPPU_BASE_S             0x58022000 /* SSE-300 System Power Policy Unit Secure base address */
+#define SSE300_CPU0PPU_BASE_S            0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */
+#define SSE300_MGMTPPU_BASE_S            0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */
+#define SSE300_DBGPPU_BASE_S             0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */
+#define SLOWCLK_WDOG_CMSDK_BASE_S        0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */
+#define SLOWCLK_TIMER_CMSDK_BASE_S       0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
+#define SYSWDOG_ARMV8_M_CNTRL_BASE_S     0x58040000 /* Secure Watchdog Timer control frame Secure base address */
+#define SYSWDOG_ARMV8_M_REFRESH_BASE_S   0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
+#define SYSCNTR_CNTRL_BASE_S             0x58100000 /* System Counter Control Secure base address */
+#define SYSCNTR_READ_BASE_S              0x58101000 /* System Counter Read Secure base address */
+/* Secure MSTEXPPIHL Peripheral region */
+#define ETHOS_U55_APB_BASE_S             0x58102000 /* Ethos-U55 APB Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_S      0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_S      0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
+#define FPGA_SBCon_I2C_TOUCH_BASE_S      0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
+#define FPGA_SBCon_I2C_AUDIO_BASE_S      0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
+#define FPGA_SPI_ADC_BASE_S              0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
+#define FPGA_SPI_SHIELD0_BASE_S          0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */
+#define FPGA_SPI_SHIELD1_BASE_S          0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */
+#define SBCon_I2C_SHIELD0_BASE_S         0x59205000 /* SBCon (I2C - Shield0) Secure base address */
+#define SBCon_I2C_SHIELD1_BASE_S         0x59206000 /* SBCon (I2C – Shield1) Secure base address */
+#define USER_APB_BASE_S                  0x59207000 /* USER APB Secure base address */
+#define FPGA_DDR4_EEPROM_BASE_S          0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */
+#define FMC_USER_APB_0_BASE_S            0x5920C000 /* FMC User APB0 registers Secure base address */
+#define FMC_USER_APB_1_BASE_S            0x5920D000 /* FMC User APB1 registers Secure base address */
+#define FMC_USER_APB_2_BASE_S            0x5920E000 /* FMC User APB2 registers Secure base address */
+#define FMC_USER_APB_3_BASE_S            0x5920F000 /* FMC User APB3 registers Secure base address */
+#define FPGA_SCC_BASE_S                  0x59300000 /* FPGA - SCC registers Secure base address */
+#define FPGA_I2S_BASE_S                  0x59301000 /* FPGA - I2S (Audio) Secure base address */
+#define FPGA_IO_BASE_S                   0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */
+#define UART0_BASE_S                     0x59303000 /* UART 0 Secure base address */
+#define UART1_BASE_S                     0x59304000 /* UART 1 Secure base address */
+#define UART2_BASE_S                     0x59305000 /* UART 2 Secure base address */
+#define UART3_BASE_S                     0x59306000 /* UART 3 Secure base address */
+#define UART4_BASE_S                     0x59307000 /* UART 4 Secure base address */
+#define UART5_BASE_S                     0x59308000 /* UART 5 Secure base address */
+#define CLCD_Config_Reg_BASE_S           0x5930A000 /* CLCD Config Reg Secure base address */
+#define RTC_BASE_S                       0x5930B000 /* RTC Secure base address */
+#define DDR4_BLK1_BASE_S                 0x70000000 /* DDR4 block 1 Secure base address */
+#define DDR4_BLK3_BASE_S                 0x90000000 /* DDR4 block 3 Secure base address */
+#define DDR4_BLK5_BASE_S                 0xB0000000 /* DDR4 block 5 Secure base address */
+#define DDR4_BLK7_BASE_S                 0xD0000000 /* DDR4 block 7 Secure base address */
+
+/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
+#define SSE300_EWIC_BASE                 0xE0047000 /* External Wakeup Interrupt Controller
+                                                     * Access from Non-secure software is only allowed
+                                                     * if AIRCR.BFHFNMINS is set to 1 */
+
+/* Memory size definitions */
+#define ITCM_SIZE       (0x00080000) /* 512 kB */
+#define DTCM_BLK_SIZE   (0x00020000) /* 128 kB */
+#define DTCM_BLK_NUM    (0x4)        /* Number of DTCM blocks */
+#define SRAM_SIZE       (0x00100000) /* 1 MB */
+#define ISRAM0_SIZE     (0x00100000) /* 1 MB */
+#define ISRAM1_SIZE     (0x00100000) /* 1 MB */
+#define QSPI_SRAM_SIZE  (0x00800000) /* 8 MB */
+#define DDR4_BLK_SIZE   (0x10000000) /* 256 MB */
+#define DDR4_BLK_NUM    (0x8)        /* Number of DDR4 blocks */
+
+/* Defines for Driver MPC's */
+/* SRAM -- 2 MB */
+#define MPC_SRAM_RANGE_BASE_NS   (SRAM_BASE_NS)
+#define MPC_SRAM_RANGE_LIMIT_NS  (SRAM_BASE_NS + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
+#define MPC_SRAM_RANGE_BASE_S    (SRAM_BASE_S)
+#define MPC_SRAM_RANGE_LIMIT_S   (SRAM_BASE_S + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_S  (0x0)
+
+/* QSPI -- 8 MB*/
+#define MPC_QSPI_RANGE_BASE_NS   (QSPI_SRAM_BASE_NS)
+#define MPC_QSPI_RANGE_LIMIT_NS  (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
+#define MPC_QSPI_RANGE_BASE_S    (QSPI_SRAM_BASE_S)
+#define MPC_QSPI_RANGE_LIMIT_S   (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_S  (0x0)
+
+/* ISRAM0 -- 2 MB*/
+#define MPC_ISRAM0_RANGE_BASE_NS   (ISRAM0_BASE_NS)
+#define MPC_ISRAM0_RANGE_LIMIT_NS  (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
+#define MPC_ISRAM0_RANGE_BASE_S    (ISRAM0_BASE_S)
+#define MPC_ISRAM0_RANGE_LIMIT_S   (ISRAM0_BASE_S + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_S  (0x0)
+
+/* ISRAM1 -- 2 MB*/
+#define MPC_ISRAM1_RANGE_BASE_NS   (ISRAM1_BASE_NS)
+#define MPC_ISRAM1_RANGE_LIMIT_NS  (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
+#define MPC_ISRAM1_RANGE_BASE_S    (ISRAM1_BASE_S)
+#define MPC_ISRAM1_RANGE_LIMIT_S   (ISRAM1_BASE_S + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_S  (0x0)
+
+/* DDR4 -- 2GB (8 * 256 MB) */
+#define MPC_DDR4_BLK0_RANGE_BASE_NS   (DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK0_RANGE_LIMIT_NS  (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
+#define MPC_DDR4_BLK1_RANGE_BASE_S    (DDR4_BLK1_BASE_S)
+#define MPC_DDR4_BLK1_RANGE_LIMIT_S   (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK1_RANGE_OFFSET_S  (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_BASE_NS   (DDR4_BLK2_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_LIMIT_NS  (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK3_RANGE_BASE_S    (DDR4_BLK3_BASE_S)
+#define MPC_DDR4_BLK3_RANGE_LIMIT_S   (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK3_RANGE_OFFSET_S  (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_BASE_NS   (DDR4_BLK4_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_LIMIT_NS  (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK5_RANGE_BASE_S    (DDR4_BLK5_BASE_S)
+#define MPC_DDR4_BLK5_RANGE_LIMIT_S   (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK5_RANGE_OFFSET_S  (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_BASE_NS   (DDR4_BLK6_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_LIMIT_NS  (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK7_RANGE_BASE_S    (DDR4_BLK7_BASE_S)
+#define MPC_DDR4_BLK7_RANGE_LIMIT_S   (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK7_RANGE_OFFSET_S  (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
+
+#endif  /* __PLATFORM_BASE_ADDRESS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/region_defs.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "region_limits.h"
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure regions */
+#define S_CODE_START     ( S_ROM_ALIAS )
+#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
+#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
+
+#define S_DATA_START     ( S_RAM_ALIAS )
+#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
+#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
+
+#define S_DDR4_START     ( S_DDR4_ALIAS )
+#define S_DDR4_SIZE      ( TOTAL_S_DDR4_SIZE )
+#define S_DDR4_LIMIT     ( S_DDR4_START + S_DDR4_SIZE )
+
+#endif /* __REGION_DEFS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "region_limits.h"
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure regions */
+#define S_CODE_START     ( S_ROM_ALIAS )
+#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )
+#define S_CODE_LIMIT     ( S_CODE_START + S_CODE_SIZE )
+
+#define S_DATA_START     ( S_RAM_ALIAS )
+#define S_DATA_SIZE      ( TOTAL_S_RAM_SIZE )
+#define S_DATA_LIMIT     ( S_DATA_START + S_DATA_SIZE )
+
+#define S_DDR4_START     ( S_DDR4_ALIAS )
+#define S_DDR4_SIZE      ( TOTAL_S_DDR4_SIZE )
+#define S_DDR4_LIMIT     ( S_DDR4_START + S_DDR4_SIZE )
+
+#endif /* __REGION_DEFS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/region_limits.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_LIMITS_H__
+#define __REGION_LIMITS_H__
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure Code */
+#define S_ROM_ALIAS               (0x10000000) /* ITCM_BASE_S */
+#define TOTAL_S_ROM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure Data */
+#define S_RAM_ALIAS               (0x30000000) /* DTCM_BASE_S */
+#define TOTAL_S_RAM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure DDR4 */
+#define S_DDR4_ALIAS              (0x70000000) /* DDR4_BLK1_BASE_S */
+#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */
+
+/* Heap and Stack sizes for secure and nonsecure applications */
+#define HEAP_SIZE                 (0x00001000) /* 1 KiB */
+#define STACK_SIZE                (0x00000800) /* 1 KiB */
+
+#endif /* __REGION_LIMITS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018-2022 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_LIMITS_H__
+#define __REGION_LIMITS_H__
+
+/* **************************************************************
+ * WARNING: this file is parsed both by the C/C++ compiler
+ * and the linker. As a result the syntax must be valid not only
+ * for C/C++ but for the linker scripts too.
+ * Beware of the following limitations:
+ *   - LD (GCC linker) requires white space around operators.
+ *   - UL postfix for macros is not suported by the linker script
+ ****************************************************************/
+
+/* Secure Code */
+#define S_ROM_ALIAS               (0x10000000) /* ITCM_BASE_S */
+#define TOTAL_S_ROM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure Data */
+#define S_RAM_ALIAS               (0x30000000) /* DTCM_BASE_S */
+#define TOTAL_S_RAM_SIZE          (0x00080000) /* 512 kB */
+
+/* Secure DDR4 */
+#define S_DDR4_ALIAS              (0x70000000) /* DDR4_BLK1_BASE_S */
+#define TOTAL_S_DDR4_SIZE         (0x10000000) /* 256 MB */
+
+/* Heap and Stack sizes for secure and nonsecure applications */
+#define HEAP_SIZE                 (0x00000400) /* 1 KiB */
+#define STACK_SIZE                (0x00000400) /* 1 KiB */
+
+#endif /* __REGION_LIMITS_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c

@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "SSE300MPS3.h"
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler  (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name)  \
+void __WEAK __NO_RETURN handler_name(void); \
+void handler_name(void) { \
+    while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TIMER0_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_Handler)
+DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
+DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+       const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+  (pFunc)(&__INITIAL_SP),           /*      Initial Stack Pointer */
+  Reset_Handler,                    /*      Reset Handler */
+  NMI_Handler,                      /* -14: NMI Handler */
+  HardFault_Handler,                /* -13: Hard Fault Handler */
+  MemManage_Handler,                /* -12: MPU Fault Handler */
+  BusFault_Handler,                 /* -11: Bus Fault Handler */
+  UsageFault_Handler,               /* -10: Usage Fault Handler */
+  SecureFault_Handler,              /*  -9: Secure Fault Handler */
+  0,                                /*      Reserved */
+  0,                                /*      Reserved */
+  0,                                /*      Reserved */
+  SVC_Handler,                      /*  -5: SVCall Handler */
+  DebugMon_Handler,                 /*  -4: Debug Monitor Handler */
+  0,                                /*      Reserved */
+  PendSV_Handler,                   /*  -2: PendSV Handler */
+  SysTick_Handler,                  /*  -1: SysTick Handler */
+
+  NONSEC_WATCHDOG_RESET_Handler,    /*   0: Non-Secure Watchdog Reset Handler */
+  NONSEC_WATCHDOG_Handler,          /*   1: Non-Secure Watchdog Handler */
+  SLOWCLK_Timer_Handler,            /*   2: SLOWCLK Timer Handler */
+  TIMER0_Handler,                   /*   3: TIMER 0 Handler */
+  TIMER1_Handler,                   /*   4: TIMER 1 Handler */
+  TIMER2_Handler,                   /*   5: TIMER 2 Handler */
+  0,                                /*   6: Reserved */
+  0,                                /*   7: Reserved */
+  0,                                /*   8: Reserved */
+  MPC_Handler,                      /*   9: MPC Combined (Secure) Handler */
+  PPC_Handler,                      /*  10: PPC Combined (Secure) Handler */
+  MSC_Handler,                      /*  11: MSC Combined (Secure) Handler */
+  BRIDGE_ERROR_Handler,             /*  12: Bridge Error (Secure) Handler */
+  0,                                /*  13: Reserved */
+  MGMT_PPU_Handler,                 /*  14: MGMT PPU Handler */
+  SYS_PPU_Handler,                  /*  15: SYS PPU Handler */
+  CPU0_PPU_Handler,                 /*  16: CPU0 PPU Handler */
+  0,                                /*  17: Reserved */
+  0,                                /*  18: Reserved */
+  0,                                /*  19: Reserved */
+  0,                                /*  20: Reserved */
+  0,                                /*  21: Reserved */
+  0,                                /*  22: Reserved */
+  0,                                /*  23: Reserved */
+  0,                                /*  24: Reserved */
+  0,                                /*  25: Reserved */
+  DEBUG_PPU_Handler,                /*  26: DEBUG PPU Handler */
+  TIMER3_Handler,                   /*  27: TIMER 3 Handler */
+  CTI_REQ0_IRQHandler,              /*  28: CTI request 0 IRQ Handler */
+  CTI_REQ1_IRQHandler,              /*  29: CTI request 1 IRQ Handler */
+  0,                                /*  30: Reserved */
+  0,                                /*  31: Reserved */
+
+  /* External interrupts */
+  System_Timestamp_Counter_Handler, /*  32: System timestamp counter Handler */
+  UARTRX0_Handler,                  /*  33: UART 0 RX Handler */
+  UARTTX0_Handler,                  /*  34: UART 0 TX Handler */
+  UARTRX1_Handler,                  /*  35: UART 1 RX Handler */
+  UARTTX1_Handler,                  /*  36: UART 1 TX Handler */
+  UARTRX2_Handler,                  /*  37: UART 2 RX Handler */
+  UARTTX2_Handler,                  /*  38: UART 2 TX Handler */
+  UARTRX3_Handler,                  /*  39: UART 3 RX Handler */
+  UARTTX3_Handler,                  /*  40: UART 3 TX Handler */
+  UARTRX4_Handler,                  /*  41: UART 4 RX Handler */
+  UARTTX4_Handler,                  /*  42: UART 4 TX Handler */
+  UART0_Combined_Handler,           /*  43: UART 0 Combined Handler */
+  UART1_Combined_Handler,           /*  44: UART 1 Combined Handler */
+  UART2_Combined_Handler,           /*  45: UART 2 Combined Handler */
+  UART3_Combined_Handler,           /*  46: UART 3 Combined Handler */
+  UART4_Combined_Handler,           /*  47: UART 4 Combined Handler */
+  UARTOVF_Handler,                  /*  48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+  ETHERNET_Handler,                 /*  49: Ethernet Handler */
+  I2S_Handler,                      /*  50: Audio I2S Handler */
+  TOUCH_SCREEN_Handler,             /*  51: Touch Screen Handler */
+  USB_Handler,                      /*  52: USB Handler */
+  SPI_ADC_Handler,                  /*  53: SPI ADC Handler */
+  SPI_SHIELD0_Handler,              /*  54: SPI (Shield 0) Handler */
+  SPI_SHIELD1_Handler,              /*  55: SPI (Shield 0) Handler */
+  ETHOS_U55_Handler,                /*  56: Ethos-U55 Handler */
+  0,                                /*  57: Reserved */
+  0,                                /*  58: Reserved */
+  0,                                /*  59: Reserved */
+  0,                                /*  60: Reserved */
+  0,                                /*  61: Reserved */
+  0,                                /*  62: Reserved */
+  0,                                /*  63: Reserved */
+  0,                                /*  64: Reserved */
+  0,                                /*  65: Reserved */
+  0,                                /*  66: Reserved */
+  0,                                /*  67: Reserved */
+  0,                                /*  68: Reserved */
+  GPIO0_Combined_Handler,           /*  69: GPIO 0 Combined Handler */
+  GPIO1_Combined_Handler,           /*  70: GPIO 1 Combined Handler */
+  GPIO2_Combined_Handler,           /*  71: GPIO 2 Combined Handler */
+  GPIO3_Combined_Handler,           /*  72: GPIO 3 Combined Handler */
+  GPIO0_0_Handler,                  /*  73: GPIO0 Pin 0 Handler */
+  GPIO0_1_Handler,                  /*  74: GPIO0 Pin 1 Handler */
+  GPIO0_2_Handler,                  /*  75: GPIO0 Pin 2 Handler */
+  GPIO0_3_Handler,                  /*  76: GPIO0 Pin 3 Handler */
+  GPIO0_4_Handler,                  /*  77: GPIO0 Pin 4 Handler */
+  GPIO0_5_Handler,                  /*  78: GPIO0 Pin 5 Handler */
+  GPIO0_6_Handler,                  /*  79: GPIO0 Pin 6 Handler */
+  GPIO0_7_Handler,                  /*  80: GPIO0 Pin 7 Handler */
+  GPIO0_8_Handler,                  /*  81: GPIO0 Pin 8 Handler */
+  GPIO0_9_Handler,                  /*  82: GPIO0 Pin 9 Handler */
+  GPIO0_10_Handler,                 /*  83: GPIO0 Pin 10 Handler */
+  GPIO0_11_Handler,                 /*  84: GPIO0 Pin 11 Handler */
+  GPIO0_12_Handler,                 /*  85: GPIO0 Pin 12 Handler */
+  GPIO0_13_Handler,                 /*  86: GPIO0 Pin 13 Handler */
+  GPIO0_14_Handler,                 /*  87: GPIO0 Pin 14 Handler */
+  GPIO0_15_Handler,                 /*  88: GPIO0 Pin 15 Handler */
+  GPIO1_0_Handler,                  /*  89: GPIO1 Pin 0 Handler */
+  GPIO1_1_Handler,                  /*  90: GPIO1 Pin 1 Handler */
+  GPIO1_2_Handler,                  /*  91: GPIO1 Pin 2 Handler */
+  GPIO1_3_Handler,                  /*  92: GPIO1 Pin 3 Handler */
+  GPIO1_4_Handler,                  /*  93: GPIO1 Pin 4 Handler */
+  GPIO1_5_Handler,                  /*  94: GPIO1 Pin 5 Handler */
+  GPIO1_6_Handler,                  /*  95: GPIO1 Pin 6 Handler */
+  GPIO1_7_Handler,                  /*  96: GPIO1 Pin 7 Handler */
+  GPIO1_8_Handler,                  /*  97: GPIO1 Pin 8 Handler */
+  GPIO1_9_Handler,                  /*  98: GPIO1 Pin 9 Handler */
+  GPIO1_10_Handler,                 /*  99: GPIO1 Pin 10 Handler */
+  GPIO1_11_Handler,                 /*  100: GPIO1 Pin 11 Handler */
+  GPIO1_12_Handler,                 /*  101: GPIO1 Pin 12 Handler */
+  GPIO1_13_Handler,                 /*  102: GPIO1 Pin 13 Handler */
+  GPIO1_14_Handler,                 /*  103: GPIO1 Pin 14 Handler */
+  GPIO1_15_Handler,                 /*  104: GPIO1 Pin 15 Handler */
+  GPIO2_0_Handler,                  /*  105: GPIO2 Pin 0 Handler */
+  GPIO2_1_Handler,                  /*  106: GPIO2 Pin 1 Handler */
+  GPIO2_2_Handler,                  /*  107: GPIO2 Pin 2 Handler */
+  GPIO2_3_Handler,                  /*  108: GPIO2 Pin 3 Handler */
+  GPIO2_4_Handler,                  /*  109: GPIO2 Pin 4 Handler */
+  GPIO2_5_Handler,                  /*  110: GPIO2 Pin 5 Handler */
+  GPIO2_6_Handler,                  /*  111: GPIO2 Pin 6 Handler */
+  GPIO2_7_Handler,                  /*  112: GPIO2 Pin 7 Handler */
+  GPIO2_8_Handler,                  /*  113: GPIO2 Pin 8 Handler */
+  GPIO2_9_Handler,                  /*  114: GPIO2 Pin 9 Handler */
+  GPIO2_10_Handler,                 /*  115: GPIO2 Pin 10 Handler */
+  GPIO2_11_Handler,                 /*  116: GPIO2 Pin 11 Handler */
+  GPIO2_12_Handler,                 /*  117: GPIO2 Pin 12 Handler */
+  GPIO2_13_Handler,                 /*  118: GPIO2 Pin 13 Handler */
+  GPIO2_14_Handler,                 /*  119: GPIO2 Pin 14 Handler */
+  GPIO2_15_Handler,                 /*  120: GPIO2 Pin 15 Handler */
+  GPIO3_0_Handler,                  /*  121: GPIO3 Pin 0 Handler */
+  GPIO3_1_Handler,                  /*  122: GPIO3 Pin 1 Handler */
+  GPIO3_2_Handler,                  /*  123: GPIO3 Pin 2 Handler */
+  GPIO3_3_Handler,                  /*  124: GPIO3 Pin 3 Handler */
+  UARTRX5_Handler,                  /*  125: UART 5 RX Interrupt */
+  UARTTX5_Handler,                  /*  126: UART 5 TX Interrupt */
+  UART5_Handler,                    /*  127: UART 5 combined Interrupt */
+  0,                                /*  128: Reserved */
+  0,                                /*  129: Reserved */
+  0,                                /*  130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c.base@1.1.1

@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "SSE300MPS3.h"
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler  (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name)  \
+void __WEAK __NO_RETURN handler_name(void); \
+void handler_name(void) { \
+    while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TIMER0_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_Handler)
+DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
+DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+       const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+  (pFunc)(&__INITIAL_SP),           /*      Initial Stack Pointer */
+  Reset_Handler,                    /*      Reset Handler */
+  NMI_Handler,                      /* -14: NMI Handler */
+  HardFault_Handler,                /* -13: Hard Fault Handler */
+  MemManage_Handler,                /* -12: MPU Fault Handler */
+  BusFault_Handler,                 /* -11: Bus Fault Handler */
+  UsageFault_Handler,               /* -10: Usage Fault Handler */
+  SecureFault_Handler,              /*  -9: Secure Fault Handler */
+  0,                                /*      Reserved */
+  0,                                /*      Reserved */
+  0,                                /*      Reserved */
+  SVC_Handler,                      /*  -5: SVCall Handler */
+  DebugMon_Handler,                 /*  -4: Debug Monitor Handler */
+  0,                                /*      Reserved */
+  PendSV_Handler,                   /*  -2: PendSV Handler */
+  SysTick_Handler,                  /*  -1: SysTick Handler */
+
+  NONSEC_WATCHDOG_RESET_Handler,    /*   0: Non-Secure Watchdog Reset Handler */
+  NONSEC_WATCHDOG_Handler,          /*   1: Non-Secure Watchdog Handler */
+  SLOWCLK_Timer_Handler,            /*   2: SLOWCLK Timer Handler */
+  TIMER0_Handler,                   /*   3: TIMER 0 Handler */
+  TIMER1_Handler,                   /*   4: TIMER 1 Handler */
+  TIMER2_Handler,                   /*   5: TIMER 2 Handler */
+  0,                                /*   6: Reserved */
+  0,                                /*   7: Reserved */
+  0,                                /*   8: Reserved */
+  MPC_Handler,                      /*   9: MPC Combined (Secure) Handler */
+  PPC_Handler,                      /*  10: PPC Combined (Secure) Handler */
+  MSC_Handler,                      /*  11: MSC Combined (Secure) Handler */
+  BRIDGE_ERROR_Handler,             /*  12: Bridge Error (Secure) Handler */
+  0,                                /*  13: Reserved */
+  MGMT_PPU_Handler,                 /*  14: MGMT PPU Handler */
+  SYS_PPU_Handler,                  /*  15: SYS PPU Handler */
+  CPU0_PPU_Handler,                 /*  16: CPU0 PPU Handler */
+  0,                                /*  17: Reserved */
+  0,                                /*  18: Reserved */
+  0,                                /*  19: Reserved */
+  0,                                /*  20: Reserved */
+  0,                                /*  21: Reserved */
+  0,                                /*  22: Reserved */
+  0,                                /*  23: Reserved */
+  0,                                /*  24: Reserved */
+  0,                                /*  25: Reserved */
+  DEBUG_PPU_Handler,                /*  26: DEBUG PPU Handler */
+  TIMER3_Handler,                   /*  27: TIMER 3 Handler */
+  CTI_REQ0_IRQHandler,              /*  28: CTI request 0 IRQ Handler */
+  CTI_REQ1_IRQHandler,              /*  29: CTI request 1 IRQ Handler */
+  0,                                /*  30: Reserved */
+  0,                                /*  31: Reserved */
+
+  /* External interrupts */
+  System_Timestamp_Counter_Handler, /*  32: System timestamp counter Handler */
+  UARTRX0_Handler,                  /*  33: UART 0 RX Handler */
+  UARTTX0_Handler,                  /*  34: UART 0 TX Handler */
+  UARTRX1_Handler,                  /*  35: UART 1 RX Handler */
+  UARTTX1_Handler,                  /*  36: UART 1 TX Handler */
+  UARTRX2_Handler,                  /*  37: UART 2 RX Handler */
+  UARTTX2_Handler,                  /*  38: UART 2 TX Handler */
+  UARTRX3_Handler,                  /*  39: UART 3 RX Handler */
+  UARTTX3_Handler,                  /*  40: UART 3 TX Handler */
+  UARTRX4_Handler,                  /*  41: UART 4 RX Handler */
+  UARTTX4_Handler,                  /*  42: UART 4 TX Handler */
+  UART0_Combined_Handler,           /*  43: UART 0 Combined Handler */
+  UART1_Combined_Handler,           /*  44: UART 1 Combined Handler */
+  UART2_Combined_Handler,           /*  45: UART 2 Combined Handler */
+  UART3_Combined_Handler,           /*  46: UART 3 Combined Handler */
+  UART4_Combined_Handler,           /*  47: UART 4 Combined Handler */
+  UARTOVF_Handler,                  /*  48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+  ETHERNET_Handler,                 /*  49: Ethernet Handler */
+  I2S_Handler,                      /*  50: Audio I2S Handler */
+  TOUCH_SCREEN_Handler,             /*  51: Touch Screen Handler */
+  USB_Handler,                      /*  52: USB Handler */
+  SPI_ADC_Handler,                  /*  53: SPI ADC Handler */
+  SPI_SHIELD0_Handler,              /*  54: SPI (Shield 0) Handler */
+  SPI_SHIELD1_Handler,              /*  55: SPI (Shield 0) Handler */
+  ETHOS_U55_Handler,                /*  56: Ethos-U55 Handler */
+  0,                                /*  57: Reserved */
+  0,                                /*  58: Reserved */
+  0,                                /*  59: Reserved */
+  0,                                /*  60: Reserved */
+  0,                                /*  61: Reserved */
+  0,                                /*  62: Reserved */
+  0,                                /*  63: Reserved */
+  0,                                /*  64: Reserved */
+  0,                                /*  65: Reserved */
+  0,                                /*  66: Reserved */
+  0,                                /*  67: Reserved */
+  0,                                /*  68: Reserved */
+  GPIO0_Combined_Handler,           /*  69: GPIO 0 Combined Handler */
+  GPIO1_Combined_Handler,           /*  70: GPIO 1 Combined Handler */
+  GPIO2_Combined_Handler,           /*  71: GPIO 2 Combined Handler */
+  GPIO3_Combined_Handler,           /*  72: GPIO 3 Combined Handler */
+  GPIO0_0_Handler,                  /*  73: GPIO0 Pin 0 Handler */
+  GPIO0_1_Handler,                  /*  74: GPIO0 Pin 1 Handler */
+  GPIO0_2_Handler,                  /*  75: GPIO0 Pin 2 Handler */
+  GPIO0_3_Handler,                  /*  76: GPIO0 Pin 3 Handler */
+  GPIO0_4_Handler,                  /*  77: GPIO0 Pin 4 Handler */
+  GPIO0_5_Handler,                  /*  78: GPIO0 Pin 5 Handler */
+  GPIO0_6_Handler,                  /*  79: GPIO0 Pin 6 Handler */
+  GPIO0_7_Handler,                  /*  80: GPIO0 Pin 7 Handler */
+  GPIO0_8_Handler,                  /*  81: GPIO0 Pin 8 Handler */
+  GPIO0_9_Handler,                  /*  82: GPIO0 Pin 9 Handler */
+  GPIO0_10_Handler,                 /*  83: GPIO0 Pin 10 Handler */
+  GPIO0_11_Handler,                 /*  84: GPIO0 Pin 11 Handler */
+  GPIO0_12_Handler,                 /*  85: GPIO0 Pin 12 Handler */
+  GPIO0_13_Handler,                 /*  86: GPIO0 Pin 13 Handler */
+  GPIO0_14_Handler,                 /*  87: GPIO0 Pin 14 Handler */
+  GPIO0_15_Handler,                 /*  88: GPIO0 Pin 15 Handler */
+  GPIO1_0_Handler,                  /*  89: GPIO1 Pin 0 Handler */
+  GPIO1_1_Handler,                  /*  90: GPIO1 Pin 1 Handler */
+  GPIO1_2_Handler,                  /*  91: GPIO1 Pin 2 Handler */
+  GPIO1_3_Handler,                  /*  92: GPIO1 Pin 3 Handler */
+  GPIO1_4_Handler,                  /*  93: GPIO1 Pin 4 Handler */
+  GPIO1_5_Handler,                  /*  94: GPIO1 Pin 5 Handler */
+  GPIO1_6_Handler,                  /*  95: GPIO1 Pin 6 Handler */
+  GPIO1_7_Handler,                  /*  96: GPIO1 Pin 7 Handler */
+  GPIO1_8_Handler,                  /*  97: GPIO1 Pin 8 Handler */
+  GPIO1_9_Handler,                  /*  98: GPIO1 Pin 9 Handler */
+  GPIO1_10_Handler,                 /*  99: GPIO1 Pin 10 Handler */
+  GPIO1_11_Handler,                 /*  100: GPIO1 Pin 11 Handler */
+  GPIO1_12_Handler,                 /*  101: GPIO1 Pin 12 Handler */
+  GPIO1_13_Handler,                 /*  102: GPIO1 Pin 13 Handler */
+  GPIO1_14_Handler,                 /*  103: GPIO1 Pin 14 Handler */
+  GPIO1_15_Handler,                 /*  104: GPIO1 Pin 15 Handler */
+  GPIO2_0_Handler,                  /*  105: GPIO2 Pin 0 Handler */
+  GPIO2_1_Handler,                  /*  106: GPIO2 Pin 1 Handler */
+  GPIO2_2_Handler,                  /*  107: GPIO2 Pin 2 Handler */
+  GPIO2_3_Handler,                  /*  108: GPIO2 Pin 3 Handler */
+  GPIO2_4_Handler,                  /*  109: GPIO2 Pin 4 Handler */
+  GPIO2_5_Handler,                  /*  110: GPIO2 Pin 5 Handler */
+  GPIO2_6_Handler,                  /*  111: GPIO2 Pin 6 Handler */
+  GPIO2_7_Handler,                  /*  112: GPIO2 Pin 7 Handler */
+  GPIO2_8_Handler,                  /*  113: GPIO2 Pin 8 Handler */
+  GPIO2_9_Handler,                  /*  114: GPIO2 Pin 9 Handler */
+  GPIO2_10_Handler,                 /*  115: GPIO2 Pin 10 Handler */
+  GPIO2_11_Handler,                 /*  116: GPIO2 Pin 11 Handler */
+  GPIO2_12_Handler,                 /*  117: GPIO2 Pin 12 Handler */
+  GPIO2_13_Handler,                 /*  118: GPIO2 Pin 13 Handler */
+  GPIO2_14_Handler,                 /*  119: GPIO2 Pin 14 Handler */
+  GPIO2_15_Handler,                 /*  120: GPIO2 Pin 15 Handler */
+  GPIO3_0_Handler,                  /*  121: GPIO3 Pin 0 Handler */
+  GPIO3_1_Handler,                  /*  122: GPIO3 Pin 1 Handler */
+  GPIO3_2_Handler,                  /*  123: GPIO3 Pin 2 Handler */
+  GPIO3_3_Handler,                  /*  124: GPIO3 Pin 3 Handler */
+  UARTRX5_Handler,                  /*  125: UART 5 RX Interrupt */
+  UARTTX5_Handler,                  /*  126: UART 5 TX Interrupt */
+  UART5_Handler,                    /*  127: UART 5 combined Interrupt */
+  0,                                /*  128: Reserved */
+  0,                                /*  129: Reserved */
+  0,                                /*  130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+  SystemInit();                             /* CMSIS System Initialization */
+  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "SSE300MPS3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+ #define  XTAL             (32000000UL)
+ #define  SYSTEM_CLOCK     (XTAL)
+ #define  PERIPHERAL_CLOCK (25000000UL)
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    extern uint32_t __VECTOR_TABLE;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = PERIPHERAL_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+    PeripheralClock = PERIPHERAL_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U))
+    SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                   (3U << 11U*2U)  );         /* enable CP11 Full Access */
+
+    /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set
+     * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU
+     * into retention state
+     */
+    PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+    /* Enable Loop and branch info cache */
+    SCB->CCR |= SCB_CCR_LOB_Msk;
+    __DSB();
+    __ISB();
+
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "SSE300MPS3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+ #define  XTAL             (32000000UL)
+ #define  SYSTEM_CLOCK     (XTAL)
+ #define  PERIPHERAL_CLOCK (25000000UL)
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    extern uint32_t __VECTOR_TABLE;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = PERIPHERAL_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+    PeripheralClock = PERIPHERAL_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U))
+    SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                   (3U << 11U*2U)  );         /* enable CP11 Full Access */
+
+    /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set
+     * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU
+     * into retention state
+     */
+    PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+    /* Enable Loop and branch info cache */
+    SCB->CCR |= SCB_CCR_LOB_Msk;
+    __DSB();
+    __ISB();
+
+}

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#ifndef __SYSTEM_CORE_INIT_H__
+#define __SYSTEM_CORE_INIT_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;  /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t PeripheralClock;  /*!< Peripheral Clock Frequency */
+
+/**
+ * \brief  Initializes the system
+ */
+extern void SystemInit(void);
+
+/**
+ * \brief  Restores system core clock
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_CORE_INIT_H__ */

ComputeGraph/tests/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#ifndef __SYSTEM_CORE_INIT_H__
+#define __SYSTEM_CORE_INIT_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;  /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t PeripheralClock;  /*!< Peripheral Clock Frequency */
+
+/**
+ * \brief  Initializes the system
+ */
+extern void SystemInit(void);
+
+/**
+ * \brief  Restores system core clock
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_CORE_INIT_H__ */

ComputeGraph/tests/RTE/_IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'eventrecorder.IDE+VHT-Corstone-300' 
+ * Target:  'IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_asyncgraph.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'asyncgraph.CommandLine+VHT-Corstone-300' 
+ * Target:  'asyncgraph.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_asyncgraph.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'asyncgraph.IDE+VHT-Corstone-300' 
+ * Target:  'asyncgraph.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_eventrecorder.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'eventrecorder.CommandLine+VHT-Corstone-300' 
+ * Target:  'eventrecorder.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_eventrecorder.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'eventrecorder.IDE+VHT-Corstone-300' 
+ * Target:  'eventrecorder.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifo.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifo.CommandLine+VHT-Corstone-300' 
+ * Target:  'fifo.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifo.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifo.IDE+VHT-Corstone-300' 
+ * Target:  'fifo.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench.CommandLine+VHT-Corstone-300' 
+ * Target:  'fifobench.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench.IDE+VHT-Corstone-300' 
+ * Target:  'fifobench.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench_async.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench_async.CommandLine+VHT-Corstone-300' 
+ * Target:  'fifobench_async.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench_async.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench_async.IDE+VHT-Corstone-300' 
+ * Target:  'fifobench_async.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench_sync.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench_sync.CommandLine+VHT-Corstone-300' 
+ * Target:  'fifobench_sync.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_fifobench_sync.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'fifobench_sync.IDE+VHT-Corstone-300' 
+ * Target:  'fifobench_sync.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_syncgraph.CommandLine_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,29 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'syncgraph.CommandLine+VHT-Corstone-300' 
+ * Target:  'syncgraph.CommandLine+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:Semihosting:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+          #define RTE_Compiler_EventRecorder_Semihosting
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/RTE/_syncgraph.IDE_VHT-Corstone-300/RTE_Components.h

@@ -0,0 +1,31 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'syncgraph.IDE+VHT-Corstone-300' 
+ * Target:  'syncgraph.IDE+VHT-Corstone-300' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE300MPS3.h"
+
+/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
+/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */
+#define RTE_Compiler_EventRecorder
+          #define RTE_Compiler_EventRecorder_DAP
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
+
+
+#endif /* RTE_COMPONENTS_H */

ComputeGraph/tests/async/scheduler.cpp

@@ -0,0 +1,527 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+
+#include "custom.h"
+#include "GenericNodes.h"
+#include "ComplexAppNodes.h"
+#include "scheduler.h"
+
+#if !defined(CHECKERROR)
+#define CHECKERROR       if (cgStaticError < 0) \
+       {\
+         goto errorHandling;\
+       }
+
+#endif
+
+#if !defined(CG_BEFORE_ITERATION)
+#define CG_BEFORE_ITERATION
+#endif 
+
+#if !defined(CG_AFTER_ITERATION)
+#define CG_AFTER_ITERATION
+#endif 
+
+#if !defined(CG_BEFORE_SCHEDULE)
+#define CG_BEFORE_SCHEDULE
+#endif
+
+#if !defined(CG_AFTER_SCHEDULE)
+#define CG_AFTER_SCHEDULE
+#endif
+
+#if !defined(CG_BEFORE_BUFFER)
+#define CG_BEFORE_BUFFER
+#endif
+
+#if !defined(CG_BEFORE_FIFO_BUFFERS)
+#define CG_BEFORE_FIFO_BUFFERS
+#endif
+
+#if !defined(CG_BEFORE_FIFO_INIT)
+#define CG_BEFORE_FIFO_INIT
+#endif
+
+#if !defined(CG_BEFORE_NODE_INIT)
+#define CG_BEFORE_NODE_INIT
+#endif
+
+#if !defined(CG_AFTER_INCLUDES)
+#define CG_AFTER_INCLUDES
+#endif
+
+#if !defined(CG_BEFORE_SCHEDULER_FUNCTION)
+#define CG_BEFORE_SCHEDULER_FUNCTION
+#endif
+
+#if !defined(CG_BEFORE_NODE_EXECUTION)
+#define CG_BEFORE_NODE_EXECUTION
+#endif
+
+#if !defined(CG_AFTER_NODE_EXECUTION)
+#define CG_AFTER_NODE_EXECUTION
+#endif
+
+CG_AFTER_INCLUDES
+
+
+/*
+
+Description of the scheduling. 
+
+*/
+static unsigned int schedule[1864]=
+{ 
+16,6,7,8,0,2,3,12,13,5,15,3,12,13,9,1,4,14,10,11,11,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,
+4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,
+12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,
+2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,
+3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,
+12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,
+11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,
+4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,
+5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,
+5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,
+12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,
+12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,
+14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,
+14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,
+5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,
+0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,
+12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,
+5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,
+14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,
+1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,
+5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,
+14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,
+13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,
+14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,
+14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,
+15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,
+15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,
+13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,
+7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,
+3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,
+2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,
+15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,
+13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,
+13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,
+11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,
+3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,
+15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,
+15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,
+2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,
+2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,
+3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,
+16,6,7,8,0,3,12,13,2,5,15,3,12,13,9,1,10,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,
+4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,
+12,13,2,5,15,3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,
+2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,16,6,7,8,0,3,12,13,2,5,15,
+3,12,13,9,1,10,11,11,11,4,14,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,
+3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,3,12,13,2,5,15,4,14,
+};
+
+CG_BEFORE_FIFO_BUFFERS
+/***********
+
+FIFO buffers
+
+************/
+#define FIFOSIZE0 128
+#define FIFOSIZE1 128
+#define FIFOSIZE2 128
+#define FIFOSIZE3 352
+#define FIFOSIZE4 16
+#define FIFOSIZE5 16
+#define FIFOSIZE6 16
+#define FIFOSIZE7 16
+#define FIFOSIZE8 16
+#define FIFOSIZE9 16
+#define FIFOSIZE10 16
+#define FIFOSIZE11 128
+#define FIFOSIZE12 128
+#define FIFOSIZE13 128
+#define FIFOSIZE14 128
+#define FIFOSIZE15 128
+#define FIFOSIZE16 128
+#define FIFOSIZE17 128
+
+#define BUFFERSIZE1 128
+CG_BEFORE_BUFFER
+float32_t buf1[BUFFERSIZE1]={0};
+
+#define BUFFERSIZE2 128
+CG_BEFORE_BUFFER
+float32_t buf2[BUFFERSIZE2]={0};
+
+#define BUFFERSIZE3 128
+CG_BEFORE_BUFFER
+float32_t buf3[BUFFERSIZE3]={0};
+
+#define BUFFERSIZE4 352
+CG_BEFORE_BUFFER
+float32_t buf4[BUFFERSIZE4]={0};
+
+#define BUFFERSIZE5 16
+CG_BEFORE_BUFFER
+float32_t buf5[BUFFERSIZE5]={0};
+
+#define BUFFERSIZE6 16
+CG_BEFORE_BUFFER
+float32_t buf6[BUFFERSIZE6]={0};
+
+#define BUFFERSIZE7 16
+CG_BEFORE_BUFFER
+float32_t buf7[BUFFERSIZE7]={0};
+
+#define BUFFERSIZE8 16
+CG_BEFORE_BUFFER
+float32_t buf8[BUFFERSIZE8]={0};
+
+#define BUFFERSIZE9 16
+CG_BEFORE_BUFFER
+float32_t buf9[BUFFERSIZE9]={0};
+
+#define BUFFERSIZE10 16
+CG_BEFORE_BUFFER
+float32_t buf10[BUFFERSIZE10]={0};
+
+#define BUFFERSIZE11 16
+CG_BEFORE_BUFFER
+float32_t buf11[BUFFERSIZE11]={0};
+
+#define BUFFERSIZE12 128
+CG_BEFORE_BUFFER
+float32_t buf12[BUFFERSIZE12]={0};
+
+#define BUFFERSIZE13 128
+CG_BEFORE_BUFFER
+float32_t buf13[BUFFERSIZE13]={0};
+
+#define BUFFERSIZE14 128
+CG_BEFORE_BUFFER
+float32_t buf14[BUFFERSIZE14]={0};
+
+#define BUFFERSIZE15 128
+CG_BEFORE_BUFFER
+float32_t buf15[BUFFERSIZE15]={0};
+
+#define BUFFERSIZE16 128
+CG_BEFORE_BUFFER
+float32_t buf16[BUFFERSIZE16]={0};
+
+#define BUFFERSIZE17 128
+CG_BEFORE_BUFFER
+float32_t buf17[BUFFERSIZE17]={0};
+
+#define BUFFERSIZE18 128
+CG_BEFORE_BUFFER
+float32_t buf18[BUFFERSIZE18]={0};
+
+
+CG_BEFORE_SCHEDULER_FUNCTION
+uint32_t scheduler(int *error)
+{
+    int cgStaticError=0;
+    uint32_t nbSchedule=0;
+    int32_t debugCounter=1;
+
+    CG_BEFORE_FIFO_INIT;
+    /*
+    Create FIFOs objects
+    */
+    FIFO<float32_t,FIFOSIZE0,0,1> fifo0(buf1);
+    FIFO<float32_t,FIFOSIZE1,0,1> fifo1(buf2);
+    FIFO<float32_t,FIFOSIZE2,0,1> fifo2(buf3);
+    FIFO<float32_t,FIFOSIZE3,0,1> fifo3(buf4);
+    FIFO<float32_t,FIFOSIZE4,0,1> fifo4(buf5);
+    FIFO<float32_t,FIFOSIZE5,0,1> fifo5(buf6);
+    FIFO<float32_t,FIFOSIZE6,0,1> fifo6(buf7);
+    FIFO<float32_t,FIFOSIZE7,0,1> fifo7(buf8);
+    FIFO<float32_t,FIFOSIZE8,0,1> fifo8(buf9);
+    FIFO<float32_t,FIFOSIZE9,0,1> fifo9(buf10);
+    FIFO<float32_t,FIFOSIZE10,0,1> fifo10(buf11);
+    FIFO<float32_t,FIFOSIZE11,0,1> fifo11(buf12);
+    FIFO<float32_t,FIFOSIZE12,0,1> fifo12(buf13);
+    FIFO<float32_t,FIFOSIZE13,0,1> fifo13(buf14);
+    FIFO<float32_t,FIFOSIZE14,0,1> fifo14(buf15);
+    FIFO<float32_t,FIFOSIZE15,0,1> fifo15(buf16);
+    FIFO<float32_t,FIFOSIZE16,0,1> fifo16(buf17);
+    FIFO<float32_t,FIFOSIZE17,0,1> fifo17(buf18);
+
+    CG_BEFORE_NODE_INIT;
+    /* 
+    Create node objects
+    */
+    Duplicate3<float32_t,128,float32_t,128,float32_t,128,float32_t,128> dup0(fifo11,fifo12,fifo13,fifo14);
+    Duplicate2<float32_t,128,float32_t,128,float32_t,128> dup1(fifo15,fifo16,fifo17);
+    ProcessingNode12<float32_t,16,float32_t,16,float32_t,16> proc12(fifo13,fifo4,fifo5);
+    ProcessingNode13<float32_t,16,float32_t,16,float32_t,16,float32_t,16> proc13(fifo14,fifo6,fifo7,fifo8);
+    ProcessingNode21<float32_t,16,float32_t,16,float32_t,16> proc21A(fifo17,fifo4,fifo9);
+    ProcessingNode21<float32_t,16,float32_t,16,float32_t,16> proc21B(fifo5,fifo6,fifo10);
+    ProcessingNode<float32_t,128,float32_t,128> procA(fifo0,fifo1);
+    ProcessingNode<float32_t,128,float32_t,128> procB(fifo1,fifo2);
+    ProcessingNode<float32_t,128,float32_t,128> procC(fifo2,fifo11);
+    ProcessingNode<float32_t,128,float32_t,128> procD(fifo12,fifo15);
+    ProcessingNode<float32_t,128,float32_t,256> procE(fifo16,fifo3);
+    Sink<float32_t,100> sink(fifo3);
+    Sink<float32_t,16> sinkB(fifo7);
+    Sink<float32_t,16> sinkC(fifo8);
+    Sink<float32_t,16> sinkD(fifo9);
+    Sink<float32_t,16> sinkE(fifo10);
+    Source<float32_t,128> source(fifo0);
+
+    /* Run several schedule iterations */
+    CG_BEFORE_SCHEDULE;
+    while((cgStaticError==0) && (debugCounter > 0))
+    {
+        /* Run a schedule iteration */
+        CG_BEFORE_ITERATION;
+        for(unsigned long id=0 ; id < 1864; id++)
+        {
+            CG_BEFORE_NODE_EXECUTION;
+
+            cgStaticError = 0;
+            switch(schedule[id])
+            {
+                case 0:
+                {
+                    cgStaticError = dup0.prepareForRunning();
+                }
+                break;
+
+                case 1:
+                {
+                    cgStaticError = dup1.prepareForRunning();
+                }
+                break;
+
+                case 2:
+                {
+                    cgStaticError = proc12.prepareForRunning();
+                }
+                break;
+
+                case 3:
+                {
+                    cgStaticError = proc13.prepareForRunning();
+                }
+                break;
+
+                case 4:
+                {
+                    cgStaticError = proc21A.prepareForRunning();
+                }
+                break;
+
+                case 5:
+                {
+                    cgStaticError = proc21B.prepareForRunning();
+                }
+                break;
+
+                case 6:
+                {
+                    cgStaticError = procA.prepareForRunning();
+                }
+                break;
+
+                case 7:
+                {
+                    cgStaticError = procB.prepareForRunning();
+                }
+                break;
+
+                case 8:
+                {
+                    cgStaticError = procC.prepareForRunning();
+                }
+                break;
+
+                case 9:
+                {
+                    cgStaticError = procD.prepareForRunning();
+                }
+                break;
+
+                case 10:
+                {
+                    cgStaticError = procE.prepareForRunning();
+                }
+                break;
+
+                case 11:
+                {
+                    cgStaticError = sink.prepareForRunning();
+                }
+                break;
+
+                case 12:
+                {
+                    cgStaticError = sinkB.prepareForRunning();
+                }
+                break;
+
+                case 13:
+                {
+                    cgStaticError = sinkC.prepareForRunning();
+                }
+                break;
+
+                case 14:
+                {
+                    cgStaticError = sinkD.prepareForRunning();
+                }
+                break;
+
+                case 15:
+                {
+                    cgStaticError = sinkE.prepareForRunning();
+                }
+                break;
+
+                case 16:
+                {
+                    cgStaticError = source.prepareForRunning();
+                }
+                break;
+
+                default:
+                break;
+            }
+
+            if (cgStaticError == CG_SKIP_EXECUTION_ID_CODE)
+            { 
+              cgStaticError = 0;
+              continue;
+            }
+
+            CHECKERROR;
+
+            switch(schedule[id])
+            {
+                case 0:
+                {
+                   cgStaticError = dup0.run();
+                }
+                break;
+
+                case 1:
+                {
+                   cgStaticError = dup1.run();
+                }
+                break;
+
+                case 2:
+                {
+                   cgStaticError = proc12.run();
+                }
+                break;
+
+                case 3:
+                {
+                   cgStaticError = proc13.run();
+                }
+                break;
+
+                case 4:
+                {
+                   cgStaticError = proc21A.run();
+                }
+                break;
+
+                case 5:
+                {
+                   cgStaticError = proc21B.run();
+                }
+                break;
+
+                case 6:
+                {
+                   cgStaticError = procA.run();
+                }
+                break;
+
+                case 7:
+                {
+                   cgStaticError = procB.run();
+                }
+                break;
+
+                case 8:
+                {
+                   cgStaticError = procC.run();
+                }
+                break;
+
+                case 9:
+                {
+                   cgStaticError = procD.run();
+                }
+                break;
+
+                case 10:
+                {
+                   cgStaticError = procE.run();
+                }
+                break;
+
+                case 11:
+                {
+                   cgStaticError = sink.run();
+                }
+                break;
+
+                case 12:
+                {
+                   cgStaticError = sinkB.run();
+                }
+                break;
+
+                case 13:
+                {
+                   cgStaticError = sinkC.run();
+                }
+                break;
+
+                case 14:
+                {
+                   cgStaticError = sinkD.run();
+                }
+                break;
+
+                case 15:
+                {
+                   cgStaticError = sinkE.run();
+                }
+                break;
+
+                case 16:
+                {
+                   cgStaticError = source.run();
+                }
+                break;
+
+                default:
+                break;
+            }
+            CG_AFTER_NODE_EXECUTION;
+            CHECKERROR;
+        }
+       debugCounter--;
+       CG_AFTER_ITERATION;
+       nbSchedule++;
+    }
+
+errorHandling:
+    CG_AFTER_SCHEDULE;
+    *error=cgStaticError;
+    return(nbSchedule);
+}

ComputeGraph/tests/async/scheduler.h

@@ -0,0 +1,26 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+#ifndef _SCHEDULER_H_ 
+#define _SCHEDULER_H_
+
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+extern uint32_t scheduler(int *error);
+
+#ifdef   __cplusplus
+}
+#endif
+
+#endif
+

ComputeGraph/tests/asyncgraph.cproject.yml

@@ -0,0 +1,28 @@
+project:
+  groups:
+    - group: App
+      files:
+        - file: main.cpp
+        - file: async/scheduler.cpp
+
+  add-path:
+    - async
+    - .
+       
+  components:
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      for-type: 
+          - .CommandLine
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      for-type: 
+          - .IDE
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      for-type: 
+          - .IDE
+  
+  layers:
+    - layer: vht.clayer.yml 
+    - layer: cg.clayer.yml
+

ComputeGraph/tests/cg.clayer.yml

@@ -0,0 +1,7 @@
+layer:  
+  description: Compute graph headers
+
+  add-path:
+    - ../cg/src
+    - ../cg/nodes/cpp
+

ComputeGraph/tests/cprj/asyncgraph.CommandLine+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,291 @@
+build:
+  context: asyncgraph.CommandLine+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - COMMAND_LINE
+    - _RTE_
+  add-path:
+    - ../async
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_asyncgraph.CommandLine_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/asyncgraph/VHT-Corstone-300/CommandLine
+    outdir: out/asyncgraph/VHT-Corstone-300/CommandLine
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+  groups:
+    - group: App
+      files:
+        - file: ../main.cpp
+          category: sourceCpp
+        - file: ../async/scheduler.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_asyncgraph.CommandLine_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/asyncgraph.CommandLine+VHT-Corstone-300.cprj

@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/asyncgraph/VHT-Corstone-300/CommandLine" name="asyncgraph.CommandLine+VHT-Corstone-300" outdir="out/asyncgraph/VHT-Corstone-300/CommandLine" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <defines>COMMAND_LINE</defines>
+    <includes>../async;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="Semihosting" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main.cpp"/>
+      <file category="sourceCpp" name="../async/scheduler.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/asyncgraph.IDE+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,297 @@
+build:
+  context: asyncgraph.IDE+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - _RTE_
+  add-path:
+    - ../async
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_asyncgraph.IDE_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/asyncgraph/VHT-Corstone-300/IDE
+    outdir: out/asyncgraph/VHT-Corstone-300/IDE
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR@1.2.0
+      condition: ARMCC Cortex-M with EVR
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c
+          category: source
+  groups:
+    - group: App
+      files:
+        - file: ../main.cpp
+          category: sourceCpp
+        - file: ../async/scheduler.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_asyncgraph.IDE_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/asyncgraph.IDE+VHT-Corstone-300.cprj

@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/asyncgraph/VHT-Corstone-300/IDE" name="asyncgraph.IDE+VHT-Corstone-300" outdir="out/asyncgraph/VHT-Corstone-300/IDE" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <includes>../async;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0"/>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main.cpp"/>
+      <file category="sourceCpp" name="../async/scheduler.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/example.cbuild-idx.yml

@@ -0,0 +1,34 @@
+build-idx:
+  csolution: ../example.csolution_ac6.yml
+  cprojects:
+    - cproject: ../asyncgraph.cproject.yml
+      clayers:
+        - clayer: ../vht.clayer.yml
+        - clayer: ../cg.clayer.yml
+    - cproject: ../fifo.cproject.yml
+      clayers:
+        - clayer: ../vht.clayer.yml
+        - clayer: ../cg.clayer.yml
+    - cproject: ../fifobench_async.cproject.yml
+      clayers:
+        - clayer: ../vht.clayer.yml
+        - clayer: ../cg.clayer.yml
+    - cproject: ../fifobench_sync.cproject.yml
+      clayers:
+        - clayer: ../vht.clayer.yml
+        - clayer: ../cg.clayer.yml
+    - cproject: ../syncgraph.cproject.yml
+      clayers:
+        - clayer: ../vht.clayer.yml
+        - clayer: ../cg.clayer.yml
+  cbuilds:
+    - cbuild: asyncgraph.CommandLine+VHT-Corstone-300.cbuild.yml
+    - cbuild: asyncgraph.IDE+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifo.CommandLine+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifo.IDE+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifobench_async.CommandLine+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifobench_async.IDE+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifobench_sync.CommandLine+VHT-Corstone-300.cbuild.yml
+    - cbuild: fifobench_sync.IDE+VHT-Corstone-300.cbuild.yml
+    - cbuild: syncgraph.CommandLine+VHT-Corstone-300.cbuild.yml
+    - cbuild: syncgraph.IDE+VHT-Corstone-300.cbuild.yml

ComputeGraph/tests/cprj/fifo.CommandLine+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,288 @@
+build:
+  context: fifo.CommandLine+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - COMMAND_LINE
+    - _RTE_
+  add-path:
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifo.CommandLine_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifo/VHT-Corstone-300/CommandLine
+    outdir: out/fifo/VHT-Corstone-300/CommandLine
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifo.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_fifo.CommandLine_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifo.CommandLine+VHT-Corstone-300.cprj

@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifo/VHT-Corstone-300/CommandLine" name="fifo.CommandLine+VHT-Corstone-300" outdir="out/fifo/VHT-Corstone-300/CommandLine" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <defines>COMMAND_LINE</defines>
+    <includes>..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="Semihosting" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifo.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/fifo.IDE+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,294 @@
+build:
+  context: fifo.IDE+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - _RTE_
+  add-path:
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifo.IDE_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifo/VHT-Corstone-300/IDE
+    outdir: out/fifo/VHT-Corstone-300/IDE
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR@1.2.0
+      condition: ARMCC Cortex-M with EVR
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c
+          category: source
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifo.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_fifo.IDE_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifo.IDE+VHT-Corstone-300.cprj

@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifo/VHT-Corstone-300/IDE" name="fifo.IDE+VHT-Corstone-300" outdir="out/fifo/VHT-Corstone-300/IDE" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <includes>..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0"/>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifo.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/fifobench_async.CommandLine+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,295 @@
+build:
+  context: fifobench_async.CommandLine+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - COMMAND_LINE
+    - _RTE_
+  add-path:
+    - ../fifobench_async
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifobench_async.CommandLine_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifobench_async/VHT-Corstone-300/CommandLine
+    outdir: out/fifobench_async/VHT-Corstone-300/CommandLine
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifobench.cpp
+          category: sourceCpp
+        - file: ../fifobench_async/scheduler.cpp
+          category: sourceCpp
+        - file: ../custom_bench.cpp
+          category: sourceCpp
+        - file: ../timing.c
+          category: sourceC
+  constructed-files:
+    - file: ../RTE/_fifobench_async.CommandLine_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifobench_async.CommandLine+VHT-Corstone-300.cprj

@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifobench_async/VHT-Corstone-300/CommandLine" name="fifobench_async.CommandLine+VHT-Corstone-300" outdir="out/fifobench_async/VHT-Corstone-300/CommandLine" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <defines>COMMAND_LINE</defines>
+    <includes>../fifobench_async;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="Semihosting" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifobench.cpp"/>
+      <file category="sourceCpp" name="../fifobench_async/scheduler.cpp"/>
+      <file category="sourceCpp" name="../custom_bench.cpp"/>
+      <file category="sourceC" name="../timing.c"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/fifobench_async.IDE+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,301 @@
+build:
+  context: fifobench_async.IDE+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - _RTE_
+  add-path:
+    - ../fifobench_async
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifobench_async.IDE_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifobench_async/VHT-Corstone-300/IDE
+    outdir: out/fifobench_async/VHT-Corstone-300/IDE
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR@1.2.0
+      condition: ARMCC Cortex-M with EVR
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c
+          category: source
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifobench.cpp
+          category: sourceCpp
+        - file: ../fifobench_async/scheduler.cpp
+          category: sourceCpp
+        - file: ../custom_bench.cpp
+          category: sourceCpp
+        - file: ../timing.c
+          category: sourceC
+  constructed-files:
+    - file: ../RTE/_fifobench_async.IDE_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifobench_async.IDE+VHT-Corstone-300.cprj

@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifobench_async/VHT-Corstone-300/IDE" name="fifobench_async.IDE+VHT-Corstone-300" outdir="out/fifobench_async/VHT-Corstone-300/IDE" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <includes>../fifobench_async;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0"/>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifobench.cpp"/>
+      <file category="sourceCpp" name="../fifobench_async/scheduler.cpp"/>
+      <file category="sourceCpp" name="../custom_bench.cpp"/>
+      <file category="sourceC" name="../timing.c"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/fifobench_sync.CommandLine+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,295 @@
+build:
+  context: fifobench_sync.CommandLine+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - COMMAND_LINE
+    - _RTE_
+  add-path:
+    - ../fifobench_sync
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifobench_sync.CommandLine_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifobench_sync/VHT-Corstone-300/CommandLine
+    outdir: out/fifobench_sync/VHT-Corstone-300/CommandLine
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifobench.cpp
+          category: sourceCpp
+        - file: ../fifobench_sync/scheduler.cpp
+          category: sourceCpp
+        - file: ../custom_bench.cpp
+          category: sourceCpp
+        - file: ../timing.c
+          category: sourceC
+  constructed-files:
+    - file: ../RTE/_fifobench_sync.CommandLine_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifobench_sync.CommandLine+VHT-Corstone-300.cprj

@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifobench_sync/VHT-Corstone-300/CommandLine" name="fifobench_sync.CommandLine+VHT-Corstone-300" outdir="out/fifobench_sync/VHT-Corstone-300/CommandLine" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <defines>COMMAND_LINE</defines>
+    <includes>../fifobench_sync;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="Semihosting" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifobench.cpp"/>
+      <file category="sourceCpp" name="../fifobench_sync/scheduler.cpp"/>
+      <file category="sourceCpp" name="../custom_bench.cpp"/>
+      <file category="sourceC" name="../timing.c"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/fifobench_sync.IDE+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,301 @@
+build:
+  context: fifobench_sync.IDE+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - _RTE_
+  add-path:
+    - ../fifobench_sync
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_fifobench_sync.IDE_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/fifobench_sync/VHT-Corstone-300/IDE
+    outdir: out/fifobench_sync/VHT-Corstone-300/IDE
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR@1.2.0
+      condition: ARMCC Cortex-M with EVR
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c
+          category: source
+  groups:
+    - group: App
+      files:
+        - file: ../main_fifobench.cpp
+          category: sourceCpp
+        - file: ../fifobench_sync/scheduler.cpp
+          category: sourceCpp
+        - file: ../custom_bench.cpp
+          category: sourceCpp
+        - file: ../timing.c
+          category: sourceC
+  constructed-files:
+    - file: ../RTE/_fifobench_sync.IDE_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/fifobench_sync.IDE+VHT-Corstone-300.cprj

@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/fifobench_sync/VHT-Corstone-300/IDE" name="fifobench_sync.IDE+VHT-Corstone-300" outdir="out/fifobench_sync/VHT-Corstone-300/IDE" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <includes>../fifobench_sync;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0"/>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main_fifobench.cpp"/>
+      <file category="sourceCpp" name="../fifobench_sync/scheduler.cpp"/>
+      <file category="sourceCpp" name="../custom_bench.cpp"/>
+      <file category="sourceC" name="../timing.c"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/syncgraph.CommandLine+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,291 @@
+build:
+  context: syncgraph.CommandLine+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - COMMAND_LINE
+    - _RTE_
+  add-path:
+    - ../sync
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_syncgraph.CommandLine_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/syncgraph/VHT-Corstone-300/CommandLine
+    outdir: out/syncgraph/VHT-Corstone-300/CommandLine
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+  groups:
+    - group: App
+      files:
+        - file: ../main.cpp
+          category: sourceCpp
+        - file: ../sync/scheduler.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_syncgraph.CommandLine_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/syncgraph.CommandLine+VHT-Corstone-300.cprj

@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/syncgraph/VHT-Corstone-300/CommandLine" name="syncgraph.CommandLine+VHT-Corstone-300" outdir="out/syncgraph/VHT-Corstone-300/CommandLine" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <defines>COMMAND_LINE</defines>
+    <includes>../sync;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="Semihosting" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main.cpp"/>
+      <file category="sourceCpp" name="../sync/scheduler.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/cprj/syncgraph.IDE+VHT-Corstone-300.cbuild.yml

@@ -0,0 +1,297 @@
+build:
+  context: syncgraph.IDE+VHT-Corstone-300
+  compiler: AC6
+  device: ARM::SSE-300-MPS3
+  processor:
+    fpu: on
+    trustzone: non-secure
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3
+    - pack: ARM::CMSIS@5.9.0
+      path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      path: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+      path: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2
+  debug: off
+  misc:
+    ASM:
+      - -masm=auto
+    C:
+      - -Wsign-compare
+      - -Wdouble-promotion
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -Werror
+      - -std=c11
+      - -Ofast
+      - -ffast-math
+      - -Wno-packed
+      - -Wno-missing-variable-declarations
+      - -Wno-missing-prototypes
+      - -Wno-missing-noreturn
+      - -Wno-sign-conversion
+      - -Wno-nonportable-include-path
+      - -Wno-reserved-id-macro
+      - -Wno-unused-macros
+      - -Wno-documentation-unknown-command
+      - -Wno-documentation
+      - -Wno-license-management
+      - -Wno-parentheses-equality
+      - -Wno-reserved-identifier
+    CPP:
+      - -fno-rtti
+      - -DNDEBUG
+      - -Wall
+      - -Wextra
+      - -std=c++11
+      - -Ofast
+      - -ffast-math
+    Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+  define:
+    - _RTE_
+  add-path:
+    - ../sync
+    - ..
+    - ../../cg/src
+    - ../../cg/nodes/cpp
+    - ../RTE/Device/SSE-300-MPS3
+    - ../RTE/CMSIS
+    - ../RTE/Compiler
+    - ../RTE/_syncgraph.IDE_VHT-Corstone-300
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/PrivateInclude
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/Core/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Include
+    - ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Platform
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Device/Include
+    - ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver
+    - ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Include
+  output-type: exe
+  output-dirs:
+    gendir: ../generated
+    intdir: tmp/syncgraph/VHT-Corstone-300/IDE
+    outdir: out/syncgraph/VHT-Corstone-300/IDE
+    rtedir: ../RTE
+  components:
+    - component: ARM::CMSIS:CORE@5.6.0
+      condition: ARMv6_7_8-M Device
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:CORE
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+      condition: CMSISCORE
+      from-pack: ARM::CMSIS-DSP@1.14.3
+      selected-by: ARM::CMSIS:DSP&Source@1.14.3
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BasicMathFunctions/BasicMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/BayesFunctions/BayesFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTables.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/CommonTables/CommonTablesF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/ControllerFunctions/ControllerFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/DistanceFunctions/DistanceFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FastMathFunctions/FastMathFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/FilteringFunctions/FilteringFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/InterpolationFunctions/InterpolationFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/MatrixFunctions/MatrixFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/QuaternionMathFunctions/QuaternionMathFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SVMFunctions/SVMFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/StatisticsFunctions/StatisticsFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/SupportFunctions/SupportFunctionsF16.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctions.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.14.3/Source/TransformFunctions/TransformFunctionsF16.c
+          category: source
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      condition: RTOS2 RTX5
+      from-pack: ARM::CMSIS@5.9.0
+      selected-by: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_delay.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evflags.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_evr.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_kernel.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_lib.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_memory.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mempool.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_mutex.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_system.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_thread.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/RTX/Source/rtx_timer.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS/5.9.0/CMSIS/RTOS2/Source/os_systick.c
+          category: source
+        - file: ../RTE/CMSIS/RTX_Config.c
+          category: source
+          attr: config
+          version: 5.1.1
+        - file: ../RTE/CMSIS/RTX_Config.h
+          category: header
+          attr: config
+          version: 5.5.2
+    - component: ARM::Device:Definition@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Definition
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Board/Device_Definition/device_definition.c
+          category: source
+        - file: ../RTE/Device/SSE-300-MPS3/platform_base_address.h
+          category: header
+          attr: config
+          version: 1.1.2
+    - component: ARM::Device:Startup&Baremetal@1.2.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Device:Startup&Baremetal
+      files:
+        - file: ../RTE/Device/SSE-300-MPS3/cmsis_driver_config.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/RTE_Device.h
+          category: header
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/device_cfg.h
+          category: header
+          attr: config
+          version: 1.1.3
+        - file: ../RTE/Device/SSE-300-MPS3/region_defs.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/region_limits.h
+          category: header
+          attr: config
+          version: 1.0.0
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h
+          category: header
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct
+          category: linkerScript
+          attr: config
+          version: 1.1.0
+        - file: ../RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c
+          category: source
+          attr: config
+          version: 1.1.1
+        - file: ../RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c
+          category: source
+          attr: config
+          version: 1.1.1
+    - component: ARM::Native Driver:SysCounter@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysCounter
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_cntrl_drv.c
+          category: source
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/syscounter_armv8-m_read_drv.c
+          category: source
+    - component: ARM::Native Driver:SysTimer@1.1.0
+      condition: SSE-300-MPS3 Device
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:SysTimer
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_drv.c
+          category: source
+    - component: ARM::Native Driver:Timeout@1.0.0
+      condition: SSE-300-MPS3 Systimer Syscounter
+      from-pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+      selected-by: ARM::Native Driver:Timeout
+      files:
+        - file: ${CMSIS_PACK_ROOT}/ARM/V2M_MPS3_SSE_300_BSP/1.3.0/Native_Driver/systimer_armv8-m_timeout.c
+          category: source
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      condition: Cortex-M Device
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/EventRecorder.c
+          category: source
+        - file: ../RTE/Compiler/EventRecorderConf.h
+          category: header
+          attr: config
+          version: 1.1.0
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR@1.2.0
+      condition: ARMCC Cortex-M with EVR
+      from-pack: Keil::ARM_Compiler@1.7.2
+      selected-by: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      files:
+        - file: ${CMSIS_PACK_ROOT}/Keil/ARM_Compiler/1.7.2/Source/retarget_io.c
+          category: source
+  groups:
+    - group: App
+      files:
+        - file: ../main.cpp
+          category: sourceCpp
+        - file: ../sync/scheduler.cpp
+          category: sourceCpp
+  constructed-files:
+    - file: ../RTE/_syncgraph.IDE_VHT-Corstone-300/RTE_Components.h
+      category: header

ComputeGraph/tests/cprj/syncgraph.IDE+VHT-Corstone-300.cprj

@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<cprj schemaVersion="1.0.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="CPRJ.xsd">
+  <created timestamp="2023-03-10T08:19:46" tool="csolution 1.4.0"/>
+
+  <info isLayer="false">
+    <description>Automatically generated project</description>
+  </info>
+
+  <packages>
+    <package name="CMSIS-DSP" vendor="ARM" version="1.14.3:1.14.3"/>
+    <package name="CMSIS" vendor="ARM" version="5.9.0:5.9.0"/>
+    <package name="V2M_MPS3_SSE_300_BSP" vendor="ARM" version="1.3.0:1.3.0"/>
+    <package name="ARM_Compiler" vendor="Keil" version="1.7.2:1.7.2"/>
+  </packages>
+
+  <compilers>
+    <compiler name="AC6" version="6.19.0"/>
+  </compilers>
+
+  <target Ddsp="DSP" Dfpu="DP_FPU" Dmve="FP_MVE" Dname="SSE-300-MPS3" Dsecure="Non-secure" Dtz="TZ" Dvendor="ARM:82">
+    <output intdir="tmp/syncgraph/VHT-Corstone-300/IDE" name="syncgraph.IDE+VHT-Corstone-300" outdir="out/syncgraph/VHT-Corstone-300/IDE" rtedir="../RTE" type="exe"/>
+    <options debug="off"/>
+    <asflags add="-masm=auto" compiler="AC6"/>
+    <cflags add="-Wsign-compare -Wdouble-promotion -DNDEBUG -Wall -Wextra -Werror -std=c11 -Ofast -ffast-math -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier" compiler="AC6"/>
+    <cxxflags add="-fno-rtti -DNDEBUG -Wall -Wextra -std=c++11 -Ofast -ffast-math" compiler="AC6"/>
+    <ldflags add="--entry=Reset_Handler --info=summarysizes --info=sizes --info=totals --info=unused --info=veneers" compiler="AC6" file="../RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct"/>
+    <includes>../sync;..;../../cg/src;../../cg/nodes/cpp</includes>
+  </target>
+
+  <components>
+    <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0"/>
+    <component Cclass="CMSIS" Cgroup="DSP" Cvariant="Source" Cvendor="ARM" Cversion="1.14.3"/>
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.4">
+      <file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.1"/>
+      <file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Definition" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="Board/Platform/platform_base_address.h" version="1.1.2"/>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="Baremetal" Cvendor="ARM" Cversion="1.2.0" rtedir="../RTE">
+      <file attr="config" category="header" name="CMSIS_Driver/Config/Baremetal/cmsis_driver_config.h" version="1.1.1"/>
+      <file attr="config" category="header" name="CMSIS_Driver/Config/RTE_Device.h" version="1.1.0"/>
+      <file attr="config" category="header" name="Device/Config/Baremetal/device_cfg.h" version="1.1.3"/>
+      <file attr="config" category="header" name="Device/Include/region_defs.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/region_limits.h" version="1.0.0"/>
+      <file attr="config" category="header" name="Device/Include/system_SSE300MPS3.h" version="1.1.1"/>
+      <file attr="config" category="linkerScript" name="Device/Source/armclang/fvp_sse300_mps3_s.sct" version="1.1.0"/>
+      <file attr="config" category="source" name="Device/Source/startup_fvp_sse300_mps3.c" version="1.1.1"/>
+      <file attr="config" category="source" name="Device/Source/system_SSE300MPS3.c" version="1.1.1"/>
+    </component>
+    <component Cclass="Native Driver" Cgroup="SysCounter" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="SysTimer" Cvendor="ARM" Cversion="1.1.0"/>
+    <component Cclass="Native Driver" Cgroup="Timeout" Cvendor="ARM" Cversion="1.0.0"/>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.5.1">
+      <file attr="config" category="header" name="Config/EventRecorderConf.h" version="1.1.0"/>
+    </component>
+    <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="EVR" Cvendor="Keil" Cversion="1.2.0"/>
+  </components>
+
+  <files>
+    <group name="App">
+      <file category="sourceCpp" name="../main.cpp"/>
+      <file category="sourceCpp" name="../sync/scheduler.cpp"/>
+    </group>
+  </files>
+</cprj>
+

ComputeGraph/tests/create_async.py

@@ -0,0 +1,35 @@
+# Include definition of the nodes
+from nodes import * 
+# Include definition of the graph
+from graph_complex import * 
+
+# Create a configuration object
+conf=Configuration()
+# The number of schedule iteration is limited to 1
+# to prevent the scheduling from running forever
+# (which should be the case for a stream computation)
+conf.debugLimit=1
+# Disable inclusion of CMSIS-DSP headers so that we don't have
+# to recompile CMSIS-DSP for such a simple example
+conf.CMSISDSP = False
+
+conf.appNodesCName = "ComplexAppNodes.h"
+
+conf.asynchronous = True 
+
+# Compute a static scheduling of the graph 
+# The size of FIFO is also computed
+scheduling = the_graph.computeSchedule(config=conf)
+
+# Print some statistics about the compute schedule
+# and the memory usage
+print("Schedule length = %d" % scheduling.scheduleLength)
+print("Memory usage %d bytes" % scheduling.memory)
+
+# Generate the C++ code for the static scheduler
+scheduling.ccode("async",conf)
+
+# Generate a graphviz representation of the graph
+with open("dot/async.dot","w") as f:
+    scheduling.graphviz(f)
+

ComputeGraph/tests/create_fifobench_async.py

@@ -0,0 +1,35 @@
+# Include definition of the nodes
+from nodes import * 
+# Include definition of the graph
+from graph_bench_async import * 
+
+# Create a configuration object
+conf=Configuration()
+# The number of schedule iteration is limited to 1
+# to prevent the scheduling from running forever
+# (which should be the case for a stream computation)
+conf.debugLimit=10
+
+conf.asynchronous = True 
+conf.customCName = "custom_bench.h"
+conf.appNodesCName = "BenchAppNodes.h"
+conf.cOptionalArgs=["float32_t* inputArray",
+                    "float32_t* outputArray"
+                   ]
+
+# Compute a static scheduling of the graph 
+# The size of FIFO is also computed
+scheduling = the_graph.computeSchedule(config=conf)
+
+# Print some statistics about the compute schedule
+# and the memory usage
+print("Schedule length = %d" % scheduling.scheduleLength)
+print("Memory usage %d bytes" % scheduling.memory)
+
+# Generate the C++ code for the static scheduler
+scheduling.ccode("fifobench_async",conf)
+
+# Generate a graphviz representation of the graph
+with open("dot/fifobench_async.dot","w") as f:
+    scheduling.graphviz(f)
+

ComputeGraph/tests/create_fifobench_sync.py

@@ -0,0 +1,33 @@
+# Include definition of the nodes
+from nodes import * 
+# Include definition of the graph
+from graph_bench_sync import * 
+
+# Create a configuration object
+conf=Configuration()
+# The number of schedule iteration is limited to 1
+# to prevent the scheduling from running forever
+# (which should be the case for a stream computation)
+conf.debugLimit=10
+conf.customCName = "custom_bench.h"
+conf.appNodesCName = "BenchAppNodes.h"
+conf.cOptionalArgs=["float32_t* inputArray",
+                    "float32_t* outputArray"
+                   ]
+
+# Compute a static scheduling of the graph 
+# The size of FIFO is also computed
+scheduling = the_graph.computeSchedule(config=conf)
+
+# Print some statistics about the compute schedule
+# and the memory usage
+print("Schedule length = %d" % scheduling.scheduleLength)
+print("Memory usage %d bytes" % scheduling.memory)
+
+# Generate the C++ code for the static scheduler
+scheduling.ccode("fifobench_sync",conf)
+
+# Generate a graphviz representation of the graph
+with open("dot/fifobench_sync.dot","w") as f:
+    scheduling.graphviz(f)
+

ComputeGraph/tests/create_sync.py

@@ -0,0 +1,33 @@
+# Include definition of the nodes
+from nodes import * 
+# Include definition of the graph
+from graph_complex import * 
+
+# Create a configuration object
+conf=Configuration()
+# The number of schedule iteration is limited to 1
+# to prevent the scheduling from running forever
+# (which should be the case for a stream computation)
+conf.debugLimit=1
+# Disable inclusion of CMSIS-DSP headers so that we don't have
+# to recompile CMSIS-DSP for such a simple example
+conf.CMSISDSP = False
+
+conf.appNodesCName = "ComplexAppNodes.h"
+
+# Compute a static scheduling of the graph 
+# The size of FIFO is also computed
+scheduling = the_graph.computeSchedule(config=conf)
+
+# Print some statistics about the compute schedule
+# and the memory usage
+print("Schedule length = %d" % scheduling.scheduleLength)
+print("Memory usage %d bytes" % scheduling.memory)
+
+# Generate the C++ code for the static scheduler
+scheduling.ccode("sync",conf)
+
+# Generate a graphviz representation of the graph
+with open("dot/sync.dot","w") as f:
+    scheduling.graphviz(f)
+

ComputeGraph/tests/custom.h

@@ -0,0 +1,5 @@
+#ifndef _CUSTOM_H_
+
+typedef float float32_t;
+
+#endif 

ComputeGraph/tests/custom_bench.h

@@ -0,0 +1,7 @@
+#ifndef _CUSTOM_H_
+
+#define HALF 0.5
+extern const float32_t HANN[256];
+
+
+#endif 

ComputeGraph/tests/dot/fifobench_async.dot

@@ -0,0 +1,143 @@
+
+
+
+
+digraph structs {
+    node [shape=plaintext]
+    rankdir=LR
+    edge [arrowsize=0.5]
+    fontname="times"
+
+
+
+arm_mult_f321 [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD PORT="ia"><FONT POINT-SIZE="9.0">ia</FONT></TD>
+    <TD ALIGN="CENTER" ROWSPAN="2">arm_mult_f32<BR/>(CMSIS-DSP)</TD>
+    <TD PORT="o"><FONT POINT-SIZE="9.0">o</FONT></TD>
+  </TR>
+<TR>
+<TD PORT="ib"><FONT POINT-SIZE="9.0">ib</FONT></TD>
+
+ 
+<TD></TD></TR>
+
+</TABLE>>];
+
+audioOverlap [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">audioOverlap<BR/>(OverlapAdd)</TD>
+  </TR>
+</TABLE>>];
+
+audioWin [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">audioWin<BR/>(SlidingBuffer)</TD>
+  </TR>
+</TABLE>>];
+
+cfft [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">cfft<BR/>(CFFT)</TD>
+  </TR>
+</TABLE>>];
+
+icfft [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">icfft<BR/>(ICFFT)</TD>
+  </TR>
+</TABLE>>];
+
+sink [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">sink<BR/>(ArraySink)</TD>
+  </TR>
+</TABLE>>];
+
+src [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">src<BR/>(ArraySource)</TD>
+  </TR>
+</TABLE>>];
+
+toCmplx [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">toCmplx<BR/>(ToComplex)</TD>
+  </TR>
+</TABLE>>];
+
+toReal [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">toReal<BR/>(ToReal)</TD>
+  </TR>
+</TABLE>>];
+
+
+
+src:i -> audioWin:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >128</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >192</FONT>
+</TD></TR></TABLE>>]
+
+audioWin:i -> arm_mult_f321:ia [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+arm_mult_f321:o -> toCmplx:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+toCmplx:i -> cfft:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+cfft:i -> icfft:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+icfft:i -> toReal:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+toReal:i -> audioOverlap:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+audioOverlap:i -> sink:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >192</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >128</FONT>
+</TD></TR></TABLE>>]
+
+HANN [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">HANN</TD>
+  </TR>
+</TABLE>>];
+
+HANN:i -> arm_mult_f321:ib
+
+}

ComputeGraph/tests/dot/fifobench_sync.dot

@@ -0,0 +1,143 @@
+
+
+
+
+digraph structs {
+    node [shape=plaintext]
+    rankdir=LR
+    edge [arrowsize=0.5]
+    fontname="times"
+
+
+
+arm_mult_f321 [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD PORT="ia"><FONT POINT-SIZE="9.0">ia</FONT></TD>
+    <TD ALIGN="CENTER" ROWSPAN="2">arm_mult_f32<BR/>(CMSIS-DSP)</TD>
+    <TD PORT="o"><FONT POINT-SIZE="9.0">o</FONT></TD>
+  </TR>
+<TR>
+<TD PORT="ib"><FONT POINT-SIZE="9.0">ib</FONT></TD>
+
+ 
+<TD></TD></TR>
+
+</TABLE>>];
+
+audioOverlap [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">audioOverlap<BR/>(OverlapAdd)</TD>
+  </TR>
+</TABLE>>];
+
+audioWin [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">audioWin<BR/>(SlidingBuffer)</TD>
+  </TR>
+</TABLE>>];
+
+cfft [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">cfft<BR/>(CFFT)</TD>
+  </TR>
+</TABLE>>];
+
+icfft [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">icfft<BR/>(ICFFT)</TD>
+  </TR>
+</TABLE>>];
+
+sink [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">sink<BR/>(ArraySink)</TD>
+  </TR>
+</TABLE>>];
+
+src [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">src<BR/>(ArraySource)</TD>
+  </TR>
+</TABLE>>];
+
+toCmplx [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">toCmplx<BR/>(ToComplex)</TD>
+  </TR>
+</TABLE>>];
+
+toReal [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">toReal<BR/>(ToReal)</TD>
+  </TR>
+</TABLE>>];
+
+
+
+src:i -> audioWin:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >128</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >192</FONT>
+</TD></TR></TABLE>>]
+
+audioWin:i -> arm_mult_f321:ia [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+arm_mult_f321:o -> toCmplx:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+toCmplx:i -> cfft:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+cfft:i -> icfft:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+icfft:i -> toReal:i [label="f32(512)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >512</FONT>
+</TD></TR></TABLE>>]
+
+toReal:i -> audioOverlap:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >256</FONT>
+</TD></TR></TABLE>>]
+
+audioOverlap:i -> sink:i [label="f32(256)"
+,headlabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >192</FONT>
+</TD></TR></TABLE>>
+,taillabel=<<TABLE BORDER="0" CELLPADDING="2"><TR><TD><FONT COLOR="blue" POINT-SIZE="12.0" >128</FONT>
+</TD></TR></TABLE>>]
+
+HANN [label=<
+<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">
+  <TR>
+    <TD ALIGN="CENTER" PORT="i">HANN</TD>
+  </TR>
+</TABLE>>];
+
+HANN:i -> arm_mult_f321:ib
+
+}

ComputeGraph/tests/example.csolution_ac6.yml

@@ -0,0 +1,72 @@
+solution:
+  compiler: AC6
+  misc:
+    - C:
+      - -Wsign-compare 
+      - -Wdouble-promotion 
+      - -DNDEBUG 
+      - -Wall 
+      - -Wextra  
+      - -Werror
+      - -std=c11 
+      - -Ofast 
+      - -ffast-math
+      - -Wno-packed 
+      - -Wno-missing-variable-declarations 
+      - -Wno-missing-prototypes 
+      - -Wno-missing-noreturn 
+      - -Wno-sign-conversion 
+      - -Wno-nonportable-include-path 
+      - -Wno-reserved-id-macro 
+      - -Wno-unused-macros 
+      - -Wno-documentation-unknown-command 
+      - -Wno-documentation 
+      - -Wno-license-management 
+      - -Wno-parentheses-equality 
+      - -Wno-reserved-identifier
+    - CPP:
+      - -fno-rtti 
+      - -DNDEBUG 
+      - -Wall 
+      - -Wextra  
+      - -std=c++11 
+      - -Ofast 
+      - -ffast-math
+    - ASM:
+      - -masm=auto
+    - Link:
+      - --entry=Reset_Handler
+      - --info=summarysizes
+      - --info=sizes
+      - --info=totals
+      - --info=unused
+      - --info=veneers
+
+  packs:
+    - pack: ARM::CMSIS-DSP@1.14.3
+    - pack: ARM::CMSIS@5.9.0
+    - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0
+    - pack: Keil::ARM_Compiler@1.7.2
+
+
+  target-types:
+    - type: VHT-Corstone-300
+      device: ARM::SSE-300-MPS3
+
+
+  build-types:
+    - type: CommandLine
+      debug: off
+      define:
+        - COMMAND_LINE
+
+    - type: IDE
+      debug: off
+
+
+  projects:
+    - project: ./syncgraph.cproject.yml    
+    - project: ./asyncgraph.cproject.yml
+    - project: ./fifobench_sync.cproject.yml
+    - project: ./fifobench_async.cproject.yml
+    - project: ./fifo.cproject.yml

ComputeGraph/tests/fifo.cproject.yml

@@ -0,0 +1,26 @@
+project:
+  groups:
+    - group: App
+      files:
+        - file: main_fifo.cpp
+
+  add-path:
+    - .
+       
+  components:
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      for-type: 
+          - .CommandLine
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      for-type: 
+          - .IDE
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      for-type: 
+          - .IDE
+  
+  layers:
+    - layer: vht.clayer.yml 
+    - layer: cg.clayer.yml
+

ComputeGraph/tests/fifobench_async.cproject.yml

@@ -0,0 +1,30 @@
+project:
+  groups:
+    - group: App
+      files:
+        - file: main_fifobench.cpp
+        - file: fifobench_async/scheduler.cpp
+        - file: custom_bench.cpp
+        - file: timing.c
+
+  add-path:
+    - fifobench_async
+    - .
+       
+  components:
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      for-type: 
+          - .CommandLine
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      for-type: 
+          - .IDE
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      for-type: 
+          - .IDE
+  
+  layers:
+    - layer: vht.clayer.yml 
+    - layer: cg.clayer.yml
+

ComputeGraph/tests/fifobench_async/scheduler.cpp

@@ -0,0 +1,339 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+
+#include "arm_math.h"
+#include "custom_bench.h"
+#include "GenericNodes.h"
+#include "BenchAppNodes.h"
+#include "scheduler.h"
+
+#if !defined(CHECKERROR)
+#define CHECKERROR       if (cgStaticError < 0) \
+       {\
+         goto errorHandling;\
+       }
+
+#endif
+
+#if !defined(CG_BEFORE_ITERATION)
+#define CG_BEFORE_ITERATION
+#endif 
+
+#if !defined(CG_AFTER_ITERATION)
+#define CG_AFTER_ITERATION
+#endif 
+
+#if !defined(CG_BEFORE_SCHEDULE)
+#define CG_BEFORE_SCHEDULE
+#endif
+
+#if !defined(CG_AFTER_SCHEDULE)
+#define CG_AFTER_SCHEDULE
+#endif
+
+#if !defined(CG_BEFORE_BUFFER)
+#define CG_BEFORE_BUFFER
+#endif
+
+#if !defined(CG_BEFORE_FIFO_BUFFERS)
+#define CG_BEFORE_FIFO_BUFFERS
+#endif
+
+#if !defined(CG_BEFORE_FIFO_INIT)
+#define CG_BEFORE_FIFO_INIT
+#endif
+
+#if !defined(CG_BEFORE_NODE_INIT)
+#define CG_BEFORE_NODE_INIT
+#endif
+
+#if !defined(CG_AFTER_INCLUDES)
+#define CG_AFTER_INCLUDES
+#endif
+
+#if !defined(CG_BEFORE_SCHEDULER_FUNCTION)
+#define CG_BEFORE_SCHEDULER_FUNCTION
+#endif
+
+#if !defined(CG_BEFORE_NODE_EXECUTION)
+#define CG_BEFORE_NODE_EXECUTION
+#endif
+
+#if !defined(CG_AFTER_NODE_EXECUTION)
+#define CG_AFTER_NODE_EXECUTION
+#endif
+
+CG_AFTER_INCLUDES
+
+
+/*
+
+Description of the scheduling. 
+
+*/
+static unsigned int schedule[25]=
+{ 
+6,2,0,7,3,4,8,1,6,2,0,7,3,4,8,1,5,2,0,7,3,4,8,1,5,
+};
+
+CG_BEFORE_FIFO_BUFFERS
+/***********
+
+FIFO buffers
+
+************/
+#define FIFOSIZE0 256
+#define FIFOSIZE1 256
+#define FIFOSIZE2 256
+#define FIFOSIZE3 512
+#define FIFOSIZE4 512
+#define FIFOSIZE5 512
+#define FIFOSIZE6 256
+#define FIFOSIZE7 256
+
+#define BUFFERSIZE1 256
+CG_BEFORE_BUFFER
+float32_t buf1[BUFFERSIZE1]={0};
+
+#define BUFFERSIZE2 256
+CG_BEFORE_BUFFER
+float32_t buf2[BUFFERSIZE2]={0};
+
+#define BUFFERSIZE3 256
+CG_BEFORE_BUFFER
+float32_t buf3[BUFFERSIZE3]={0};
+
+#define BUFFERSIZE4 512
+CG_BEFORE_BUFFER
+float32_t buf4[BUFFERSIZE4]={0};
+
+#define BUFFERSIZE5 512
+CG_BEFORE_BUFFER
+float32_t buf5[BUFFERSIZE5]={0};
+
+#define BUFFERSIZE6 512
+CG_BEFORE_BUFFER
+float32_t buf6[BUFFERSIZE6]={0};
+
+#define BUFFERSIZE7 256
+CG_BEFORE_BUFFER
+float32_t buf7[BUFFERSIZE7]={0};
+
+#define BUFFERSIZE8 256
+CG_BEFORE_BUFFER
+float32_t buf8[BUFFERSIZE8]={0};
+
+
+CG_BEFORE_SCHEDULER_FUNCTION
+uint32_t scheduler(int *error,float32_t* inputArray,
+                              float32_t* outputArray)
+{
+    int cgStaticError=0;
+    uint32_t nbSchedule=0;
+    int32_t debugCounter=10;
+
+    CG_BEFORE_FIFO_INIT;
+    /*
+    Create FIFOs objects
+    */
+    FIFO<float32_t,FIFOSIZE0,0,1> fifo0(buf1);
+    FIFO<float32_t,FIFOSIZE1,0,1> fifo1(buf2);
+    FIFO<float32_t,FIFOSIZE2,0,1> fifo2(buf3);
+    FIFO<float32_t,FIFOSIZE3,0,1> fifo3(buf4);
+    FIFO<float32_t,FIFOSIZE4,0,1> fifo4(buf5);
+    FIFO<float32_t,FIFOSIZE5,0,1> fifo5(buf6);
+    FIFO<float32_t,FIFOSIZE6,0,1> fifo6(buf7);
+    FIFO<float32_t,FIFOSIZE7,0,1> fifo7(buf8);
+
+    CG_BEFORE_NODE_INIT;
+    /* 
+    Create node objects
+    */
+    OverlapAdd<float32_t,256,128> audioOverlap(fifo6,fifo7);
+    SlidingBuffer<float32_t,256,128> audioWin(fifo0,fifo1);
+    CFFT<float32_t,512,float32_t,512> cfft(fifo3,fifo4);
+    ICFFT<float32_t,512,float32_t,512> icfft(fifo4,fifo5);
+    ArraySink<float32_t,192> sink(fifo7,outputArray);
+    ArraySource<float32_t,192> src(fifo0,inputArray);
+    ToComplex<float32_t,256,float32_t,512> toCmplx(fifo2,fifo3);
+    ToReal<float32_t,512,float32_t,256> toReal(fifo5,fifo6);
+
+    /* Run several schedule iterations */
+    CG_BEFORE_SCHEDULE;
+    while((cgStaticError==0) && (debugCounter > 0))
+    {
+        /* Run a schedule iteration */
+        CG_BEFORE_ITERATION;
+        for(unsigned long id=0 ; id < 25; id++)
+        {
+            CG_BEFORE_NODE_EXECUTION;
+
+            cgStaticError = 0;
+            switch(schedule[id])
+            {
+                case 0:
+                {
+                                        
+                    bool canRun=true;
+                    canRun &= !fifo1.willUnderflowWith(256);
+                    canRun &= !fifo2.willOverflowWith(256);
+
+                    if (!canRun)
+                    {
+                      cgStaticError = CG_SKIP_EXECUTION_ID_CODE;
+                    }
+                    else
+                    {
+                        cgStaticError = 0;
+                    }
+                }
+                break;
+
+                case 1:
+                {
+                    cgStaticError = audioOverlap.prepareForRunning();
+                }
+                break;
+
+                case 2:
+                {
+                    cgStaticError = audioWin.prepareForRunning();
+                }
+                break;
+
+                case 3:
+                {
+                    cgStaticError = cfft.prepareForRunning();
+                }
+                break;
+
+                case 4:
+                {
+                    cgStaticError = icfft.prepareForRunning();
+                }
+                break;
+
+                case 5:
+                {
+                    cgStaticError = sink.prepareForRunning();
+                }
+                break;
+
+                case 6:
+                {
+                    cgStaticError = src.prepareForRunning();
+                }
+                break;
+
+                case 7:
+                {
+                    cgStaticError = toCmplx.prepareForRunning();
+                }
+                break;
+
+                case 8:
+                {
+                    cgStaticError = toReal.prepareForRunning();
+                }
+                break;
+
+                default:
+                break;
+            }
+
+            if (cgStaticError == CG_SKIP_EXECUTION_ID_CODE)
+            { 
+              cgStaticError = 0;
+              continue;
+            }
+
+            CHECKERROR;
+
+            switch(schedule[id])
+            {
+                case 0:
+                {
+                   
+                  {
+
+                   float32_t* i0;
+                   float32_t* o2;
+                   i0=fifo1.getReadBuffer(256);
+                   o2=fifo2.getWriteBuffer(256);
+                   arm_mult_f32(i0,HANN,o2,256);
+                   cgStaticError = 0;
+                  }
+                }
+                break;
+
+                case 1:
+                {
+                   cgStaticError = audioOverlap.run();
+                }
+                break;
+
+                case 2:
+                {
+                   cgStaticError = audioWin.run();
+                }
+                break;
+
+                case 3:
+                {
+                   cgStaticError = cfft.run();
+                }
+                break;
+
+                case 4:
+                {
+                   cgStaticError = icfft.run();
+                }
+                break;
+
+                case 5:
+                {
+                   cgStaticError = sink.run();
+                }
+                break;
+
+                case 6:
+                {
+                   cgStaticError = src.run();
+                }
+                break;
+
+                case 7:
+                {
+                   cgStaticError = toCmplx.run();
+                }
+                break;
+
+                case 8:
+                {
+                   cgStaticError = toReal.run();
+                }
+                break;
+
+                default:
+                break;
+            }
+            CG_AFTER_NODE_EXECUTION;
+            CHECKERROR;
+        }
+       debugCounter--;
+       CG_AFTER_ITERATION;
+       nbSchedule++;
+    }
+
+errorHandling:
+    CG_AFTER_SCHEDULE;
+    *error=cgStaticError;
+    return(nbSchedule);
+}

ComputeGraph/tests/fifobench_async/scheduler.h

@@ -0,0 +1,27 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+#ifndef _SCHEDULER_H_ 
+#define _SCHEDULER_H_
+
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+extern uint32_t scheduler(int *error,float32_t* inputArray,
+                              float32_t* outputArray);
+
+#ifdef   __cplusplus
+}
+#endif
+
+#endif
+

ComputeGraph/tests/fifobench_sync.cproject.yml

@@ -0,0 +1,30 @@
+project:
+  groups:
+    - group: App
+      files:
+        - file: main_fifobench.cpp
+        - file: fifobench_sync/scheduler.cpp
+        - file: custom_bench.cpp
+        - file: timing.c
+
+  add-path:
+    - fifobench_sync
+    - .
+       
+  components:
+    - component: ARM::CMSIS:DSP&Source@1.14.3
+    - component: ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&Semihosting@1.5.1
+      for-type: 
+          - .CommandLine
+    - component: Keil::Compiler&ARM Compiler:Event Recorder&DAP@1.5.1
+      for-type: 
+          - .IDE
+    - component: Keil::Compiler&ARM Compiler:I/O:STDOUT&EVR
+      for-type: 
+          - .IDE
+  
+  layers:
+    - layer: vht.clayer.yml 
+    - layer: cg.clayer.yml
+

ComputeGraph/tests/fifobench_sync/scheduler.cpp

@@ -0,0 +1,258 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+
+#include "arm_math.h"
+#include "custom_bench.h"
+#include "GenericNodes.h"
+#include "BenchAppNodes.h"
+#include "scheduler.h"
+
+#if !defined(CHECKERROR)
+#define CHECKERROR       if (cgStaticError < 0) \
+       {\
+         goto errorHandling;\
+       }
+
+#endif
+
+#if !defined(CG_BEFORE_ITERATION)
+#define CG_BEFORE_ITERATION
+#endif 
+
+#if !defined(CG_AFTER_ITERATION)
+#define CG_AFTER_ITERATION
+#endif 
+
+#if !defined(CG_BEFORE_SCHEDULE)
+#define CG_BEFORE_SCHEDULE
+#endif
+
+#if !defined(CG_AFTER_SCHEDULE)
+#define CG_AFTER_SCHEDULE
+#endif
+
+#if !defined(CG_BEFORE_BUFFER)
+#define CG_BEFORE_BUFFER
+#endif
+
+#if !defined(CG_BEFORE_FIFO_BUFFERS)
+#define CG_BEFORE_FIFO_BUFFERS
+#endif
+
+#if !defined(CG_BEFORE_FIFO_INIT)
+#define CG_BEFORE_FIFO_INIT
+#endif
+
+#if !defined(CG_BEFORE_NODE_INIT)
+#define CG_BEFORE_NODE_INIT
+#endif
+
+#if !defined(CG_AFTER_INCLUDES)
+#define CG_AFTER_INCLUDES
+#endif
+
+#if !defined(CG_BEFORE_SCHEDULER_FUNCTION)
+#define CG_BEFORE_SCHEDULER_FUNCTION
+#endif
+
+#if !defined(CG_BEFORE_NODE_EXECUTION)
+#define CG_BEFORE_NODE_EXECUTION
+#endif
+
+#if !defined(CG_AFTER_NODE_EXECUTION)
+#define CG_AFTER_NODE_EXECUTION
+#endif
+
+CG_AFTER_INCLUDES
+
+
+/*
+
+Description of the scheduling. 
+
+*/
+static unsigned int schedule[25]=
+{ 
+6,2,0,7,3,4,8,1,6,2,0,7,3,4,8,1,5,2,0,7,3,4,8,1,5,
+};
+
+CG_BEFORE_FIFO_BUFFERS
+/***********
+
+FIFO buffers
+
+************/
+#define FIFOSIZE0 256
+#define FIFOSIZE1 256
+#define FIFOSIZE2 256
+#define FIFOSIZE3 512
+#define FIFOSIZE4 512
+#define FIFOSIZE5 512
+#define FIFOSIZE6 256
+#define FIFOSIZE7 256
+
+#define BUFFERSIZE1 256
+CG_BEFORE_BUFFER
+float32_t buf1[BUFFERSIZE1]={0};
+
+#define BUFFERSIZE2 256
+CG_BEFORE_BUFFER
+float32_t buf2[BUFFERSIZE2]={0};
+
+#define BUFFERSIZE3 256
+CG_BEFORE_BUFFER
+float32_t buf3[BUFFERSIZE3]={0};
+
+#define BUFFERSIZE4 512
+CG_BEFORE_BUFFER
+float32_t buf4[BUFFERSIZE4]={0};
+
+#define BUFFERSIZE5 512
+CG_BEFORE_BUFFER
+float32_t buf5[BUFFERSIZE5]={0};
+
+#define BUFFERSIZE6 512
+CG_BEFORE_BUFFER
+float32_t buf6[BUFFERSIZE6]={0};
+
+#define BUFFERSIZE7 256
+CG_BEFORE_BUFFER
+float32_t buf7[BUFFERSIZE7]={0};
+
+#define BUFFERSIZE8 256
+CG_BEFORE_BUFFER
+float32_t buf8[BUFFERSIZE8]={0};
+
+
+CG_BEFORE_SCHEDULER_FUNCTION
+uint32_t scheduler(int *error,float32_t* inputArray,
+                              float32_t* outputArray)
+{
+    int cgStaticError=0;
+    uint32_t nbSchedule=0;
+    int32_t debugCounter=10;
+
+    CG_BEFORE_FIFO_INIT;
+    /*
+    Create FIFOs objects
+    */
+    FIFO<float32_t,FIFOSIZE0,0,0> fifo0(buf1);
+    FIFO<float32_t,FIFOSIZE1,1,0> fifo1(buf2);
+    FIFO<float32_t,FIFOSIZE2,1,0> fifo2(buf3);
+    FIFO<float32_t,FIFOSIZE3,1,0> fifo3(buf4);
+    FIFO<float32_t,FIFOSIZE4,1,0> fifo4(buf5);
+    FIFO<float32_t,FIFOSIZE5,1,0> fifo5(buf6);
+    FIFO<float32_t,FIFOSIZE6,1,0> fifo6(buf7);
+    FIFO<float32_t,FIFOSIZE7,0,0> fifo7(buf8);
+
+    CG_BEFORE_NODE_INIT;
+    /* 
+    Create node objects
+    */
+    OverlapAdd<float32_t,256,128> audioOverlap(fifo6,fifo7);
+    SlidingBuffer<float32_t,256,128> audioWin(fifo0,fifo1);
+    CFFT<float32_t,512,float32_t,512> cfft(fifo3,fifo4);
+    ICFFT<float32_t,512,float32_t,512> icfft(fifo4,fifo5);
+    ArraySink<float32_t,192> sink(fifo7,outputArray);
+    ArraySource<float32_t,192> src(fifo0,inputArray);
+    ToComplex<float32_t,256,float32_t,512> toCmplx(fifo2,fifo3);
+    ToReal<float32_t,512,float32_t,256> toReal(fifo5,fifo6);
+
+    /* Run several schedule iterations */
+    CG_BEFORE_SCHEDULE;
+    while((cgStaticError==0) && (debugCounter > 0))
+    {
+        /* Run a schedule iteration */
+        CG_BEFORE_ITERATION;
+        for(unsigned long id=0 ; id < 25; id++)
+        {
+            CG_BEFORE_NODE_EXECUTION;
+
+            switch(schedule[id])
+            {
+                case 0:
+                {
+                   
+                  {
+
+                   float32_t* i0;
+                   float32_t* o2;
+                   i0=fifo1.getReadBuffer(256);
+                   o2=fifo2.getWriteBuffer(256);
+                   arm_mult_f32(i0,HANN,o2,256);
+                   cgStaticError = 0;
+                  }
+                }
+                break;
+
+                case 1:
+                {
+                   cgStaticError = audioOverlap.run();
+                }
+                break;
+
+                case 2:
+                {
+                   cgStaticError = audioWin.run();
+                }
+                break;
+
+                case 3:
+                {
+                   cgStaticError = cfft.run();
+                }
+                break;
+
+                case 4:
+                {
+                   cgStaticError = icfft.run();
+                }
+                break;
+
+                case 5:
+                {
+                   cgStaticError = sink.run();
+                }
+                break;
+
+                case 6:
+                {
+                   cgStaticError = src.run();
+                }
+                break;
+
+                case 7:
+                {
+                   cgStaticError = toCmplx.run();
+                }
+                break;
+
+                case 8:
+                {
+                   cgStaticError = toReal.run();
+                }
+                break;
+
+                default:
+                break;
+            }
+            CG_AFTER_NODE_EXECUTION;
+            CHECKERROR;
+        }
+       debugCounter--;
+       CG_AFTER_ITERATION;
+       nbSchedule++;
+    }
+
+errorHandling:
+    CG_AFTER_SCHEDULE;
+    *error=cgStaticError;
+    return(nbSchedule);
+}

ComputeGraph/tests/fifobench_sync/scheduler.h

@@ -0,0 +1,27 @@
+/*
+
+Generated with CMSIS-DSP Compute Graph Scripts.
+The generated code is not covered by CMSIS-DSP license.
+
+The support classes and code is covered by CMSIS-DSP license.
+
+*/
+
+#ifndef _SCHEDULER_H_ 
+#define _SCHEDULER_H_
+
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+extern uint32_t scheduler(int *error,float32_t* inputArray,
+                              float32_t* outputArray);
+
+#ifdef   __cplusplus
+}
+#endif
+
+#endif
+

ComputeGraph/tests/graph_bench_async.py

@@ -0,0 +1,49 @@
+# Include definitions from the Python package to
+# define datatype for the IOs and to have access to the
+# Graph class
+from cmsisdsp.cg.scheduler import *
+from nodes_bench import * 
+
+FS=16000
+# You can try with 120
+AUDIO_INTERRUPT_LENGTH = 192
+WINSIZE=256
+OVERLAP=128
+floatType=CType(F32)
+
+
+### Define nodes
+src=ArraySource("src",floatType,AUDIO_INTERRUPT_LENGTH)
+src.addVariableArg("inputArray")
+
+sliding=SlidingBuffer("audioWin",floatType,WINSIZE,OVERLAP)
+overlap=OverlapAdd("audioOverlap",floatType,WINSIZE,OVERLAP)
+window=Dsp("mult",floatType,WINSIZE)
+
+toCmplx=ToComplex("toCmplx",floatType,WINSIZE)
+toReal=ToReal("toReal",floatType,WINSIZE)
+fft=CFFT("cfft",floatType,WINSIZE)
+ifft=ICFFT("icfft",floatType,WINSIZE)
+
+hann=Constant("HANN")
+sink=ArraySink("sink",floatType,AUDIO_INTERRUPT_LENGTH)
+sink.addVariableArg("outputArray")
+
+the_graph = Graph()
+
+the_graph.connect(src.o, sliding.i)
+
+# Windowinthe_graph
+the_graph.connect(sliding.o, window.ia)
+the_graph.connect(hann,window.ib)
+
+# FFT
+the_graph.connect(window.o,toCmplx.i)
+the_graph.connect(toCmplx.o,fft.i)
+the_graph.connect(fft.o,ifft.i)
+the_graph.connect(ifft.o,toReal.i)
+
+
+# Overlap add
+the_graph.connect(toReal.o,overlap.i)
+the_graph.connect(overlap.o,sink.i)

ComputeGraph/tests/graph_bench_sync.py

@@ -0,0 +1,49 @@
+# Include definitions from the Python package to
+# define datatype for the IOs and to have access to the
+# Graph class
+from cmsisdsp.cg.scheduler import *
+from nodes_bench import * 
+
+FS=16000
+# You can try with 120
+AUDIO_INTERRUPT_LENGTH = 192
+WINSIZE=256
+OVERLAP=128
+floatType=CType(F32)
+
+
+### Define nodes
+src=ArraySource("src",floatType,AUDIO_INTERRUPT_LENGTH)
+src.addVariableArg("inputArray")
+
+sliding=SlidingBuffer("audioWin",floatType,WINSIZE,OVERLAP)
+overlap=OverlapAdd("audioOverlap",floatType,WINSIZE,OVERLAP)
+window=Dsp("mult",floatType,WINSIZE)
+
+toCmplx=ToComplex("toCmplx",floatType,WINSIZE)
+toReal=ToReal("toReal",floatType,WINSIZE)
+fft=CFFT("cfft",floatType,WINSIZE)
+ifft=ICFFT("icfft",floatType,WINSIZE)
+
+hann=Constant("HANN")
+sink=ArraySink("sink",floatType,AUDIO_INTERRUPT_LENGTH)
+sink.addVariableArg("outputArray")
+
+the_graph = Graph()
+
+the_graph.connect(src.o, sliding.i)
+
+# Windowinthe_graph
+the_graph.connect(sliding.o, window.ia)
+the_graph.connect(hann,window.ib)
+
+# FFT
+the_graph.connect(window.o,toCmplx.i)
+the_graph.connect(toCmplx.o,fft.i)
+the_graph.connect(fft.o,ifft.i)
+the_graph.connect(ifft.o,toReal.i)
+
+
+# Overlap add
+the_graph.connect(toReal.o,overlap.i)
+the_graph.connect(overlap.o,sink.i)

ComputeGraph/tests/graph_complex.py

@@ -0,0 +1,120 @@
+# Include definitions from the Python package to
+# define datatype for the IOs and to have access to the
+# Graph class
+from cmsisdsp.cg.scheduler import *
+# Include definition of the nodes
+from nodes import * 
+
+class ProcessingNode12(GenericNode):
+    def __init__(self,name,theType,inLength,outLength):
+        GenericNode.__init__(self,name)
+        self.addInput("i",theType,inLength)
+        self.addOutput("oa",theType,outLength)
+        self.addOutput("ob",theType,outLength)
+
+    @property
+    def typeName(self):
+        return "ProcessingNode12"
+
+class ProcessingNode13(GenericNode):
+    def __init__(self,name,theType,inLength,outLength):
+        GenericNode.__init__(self,name)
+        self.addInput("i",theType,inLength)
+        self.addOutput("oa",theType,outLength)
+        self.addOutput("ob",theType,outLength)
+        self.addOutput("oc",theType,outLength)
+
+    @property
+    def typeName(self):
+        return "ProcessingNode13"
+
+class ProcessingNode21(GenericNode):
+    def __init__(self,name,theType,inLength,outLength):
+        GenericNode.__init__(self,name)
+        self.addInput("ia",theType,inLength)
+        self.addInput("ib",theType,inLength)
+        self.addOutput("o",theType,outLength)
+
+    @property
+    def typeName(self):
+        return "ProcessingNode21"
+
+
+class Sink(GenericSink):
+    def __init__(self,name,theType,inLength):
+        GenericSink.__init__(self,name)
+        self.addInput("i",theType,inLength)
+
+    @property
+    def typeName(self):
+        return "Sink"
+
+class Source(GenericSource):
+    def __init__(self,name,theType,inLength):
+        GenericSource.__init__(self,name)
+        self.addOutput("o",theType,inLength)
+
+    @property
+    def typeName(self):
+        return "Source"
+
+class ProcessingNode(GenericNode):
+    def __init__(self,name,theType,inLength,outLength):
+        GenericNode.__init__(self,name)
+        self.addInput("i",theType,inLength)
+        self.addOutput("o",theType,outLength)
+
+    @property
+    def typeName(self):
+        return "ProcessingNode"
+
+
+
+### Define nodes
+floatType=CType(F32)
+src=Source("source",floatType,128)
+srcb=Source("sourceb",floatType,16)
+srcc=Source("sourcec",floatType,16)
+
+pa=ProcessingNode("procA",floatType,128,128)
+pb=ProcessingNode("procB",floatType,128,128)
+pc=ProcessingNode("procC",floatType,128,128)
+pd=ProcessingNode("procD",floatType,128,128)
+pe=ProcessingNode("procE",floatType,128,256)
+
+p12=ProcessingNode12("proc12",floatType,16,16)
+p13=ProcessingNode13("proc13",floatType,16,16)
+p21A=ProcessingNode21("proc21A",floatType,16,16)
+p21B=ProcessingNode21("proc21B",floatType,16,16)
+
+#dsp=Dsp("add",floatType,NB)
+sink=Sink("sink",floatType,100)
+sinkb=Sink("sinkB",floatType,16)
+sinkc=Sink("sinkC",floatType,16)
+sinkd=Sink("sinkD",floatType,16)
+sinke=Sink("sinkE",floatType,16)
+
+the_graph = Graph()
+
+the_graph.connect(src.o,pa.i)
+the_graph.connect(pa.o,pb.i)
+the_graph.connect(pb.o,pc.i)
+the_graph.connect(pc.o,pd.i)
+the_graph.connect(pd.o,pe.i)
+the_graph.connect(pe.o,sink.i)
+
+the_graph.connect(pc.o,p12.i)
+the_graph.connect(pc.o,p13.i)
+
+the_graph.connect(pd.o,p21A.ia)
+the_graph.connect(p12.oa,p21A.ib)
+the_graph.connect(p12.ob,p21B.ia)
+
+the_graph.connect(p13.oa,p21B.ib)
+the_graph.connect(p13.ob,sinkb.i)
+the_graph.connect(p13.oc,sinkc.i)
+
+the_graph.connect(p21A.o,sinkd.i)
+the_graph.connect(p21B.o,sinke.i)
+
+

ComputeGraph/tests/main.cpp

@@ -0,0 +1,44 @@
+#include <cstdio>
+#include <cstdint>
+#if defined(COMMAND_LINE)
+#include <cstdlib>
+#endif
+#include "scheduler.h"
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+#include "cmsis_os2.h"
+
+
+void app_main (void *argument)
+{
+    int error;
+    uint32_t nbSched = 0;
+    (void)argument;
+
+    printf("Start\n\r");
+
+
+    nbSched=scheduler(&error);
+    printf("Number of schedule iterations = %d\n\r",nbSched);
+    printf("Error code = %d\n\r",error);
+
+
+#if defined(COMMAND_LINE)
+    exit(0);
+#else
+    osThreadExit();
+#endif
+}
+
+int main(void)
+{
+  // System Initialization
+  SystemCoreClockUpdate();
+
+
+  osKernelInitialize();                 // Initialize CMSIS-RTOS
+  osThreadNew(app_main, NULL, NULL);    // Create application main thread
+  osKernelStart();                      // Start thread execution
+  for (;;) {}
+}

ComputeGraph/tests/main_fifo.cpp

@@ -0,0 +1,103 @@
+#include <cstdio>
+#include <cstdint>
+#if defined(COMMAND_LINE)
+#include <cstdlib>
+#endif
+
+#include <cassert>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+
+#include "arm_math_types.h"
+#include "GenericNodes.h"
+
+#define BUFSIZE 100
+#define FIFOSIZE0 100
+
+float32_t buf1[BUFSIZE]={0};
+
+template<typename T, int length>
+class FIFOPublicSync : public FIFO<T,length,0,0>
+{
+public:
+    FIFOPublicSync(T *buffer,int delay=0):FIFO<T,length,0,0>(buffer,delay){};
+
+    int getReadPos() const{return(this->readPos);};
+    int getWritePos() const{return(this->writePos);};
+};
+
+template<typename T, int length>
+class FIFOPublicAsync : public FIFO<T,length,0,1>
+{
+public:
+    FIFOPublicAsync(T *buffer,int delay=0):FIFO<T,length,0,1>(buffer,delay){};
+
+    int getReadPos() const{return(this->readPos);};
+    int getWritePos() const{return(this->writePos);};
+};
+
+int main(void)
+{
+  float32_t *in,*out;
+  // System Initialization
+  SystemCoreClockUpdate();
+
+  (void)in;
+  (void)out;
+
+  FIFOPublicSync<float32_t,FIFOSIZE0> fifo_sync(buf1);
+
+  printf("SYNC\r\n");
+  memset(buf1,0,sizeof(float32_t)*BUFSIZE);
+
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+  assert(fifo_sync.getWritePos() + 50 <= FIFOSIZE0);
+  out = fifo_sync.getWriteBuffer(50);
+  
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+  assert(fifo_sync.getWritePos() + 50 <= FIFOSIZE0);
+  out = fifo_sync.getWriteBuffer(30);
+  
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+  in = fifo_sync.getReadBuffer(20);
+  
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+  in = fifo_sync.getReadBuffer(20);
+  
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+  assert(fifo_sync.getWritePos() + 50 > FIFOSIZE0);
+  out = fifo_sync.getWriteBuffer(30);
+  assert(fifo_sync.getWritePos() <= FIFOSIZE0);
+
+  printf("r=%d, w=%d\n\r",fifo_sync.getReadPos(),fifo_sync.getWritePos());
+
+  FIFOPublicAsync<float32_t,FIFOSIZE0> fifo_async(buf1);
+
+  printf("\r\nASYNC\r\n");
+  memset(buf1,0,sizeof(float32_t)*BUFSIZE);
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+  assert(fifo_async.getWritePos() + 50 <= FIFOSIZE0);
+  out = fifo_async.getWriteBuffer(50);
+  
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+  assert(fifo_async.getWritePos() + 50 <= FIFOSIZE0);
+  out = fifo_async.getWriteBuffer(30);
+  
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+  in = fifo_async.getReadBuffer(20);
+  
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+  in = fifo_async.getReadBuffer(20);
+  
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+  assert(fifo_async.getWritePos() + 50 > FIFOSIZE0);
+  out = fifo_async.getWriteBuffer(30);
+  assert(fifo_async.getWritePos() <= FIFOSIZE0);
+
+  printf("r=%d, w=%d\n\r",fifo_async.getReadPos(),fifo_async.getWritePos());
+
+
+  
+  
+}

ComputeGraph/tests/main_fifobench.cpp

@@ -0,0 +1,128 @@
+#include <cstdio>
+#include <cstdint>
+#if defined(COMMAND_LINE)
+#include <cstdlib>
+#endif
+
+#include "arm_math.h"
+#include "scheduler.h"
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+#include "cmsis_os2.h"
+
+float32_t input_buffer[192]={0};
+float32_t output_buffer[192]={0};
+
+extern "C" {
+extern void initCycleMeasurement();
+extern void cycleMeasurementStart();
+extern void cycleMeasurementStop();
+extern int32_t getCycles();
+}
+
+#define OVERHEADLOOP 100
+
+uint32_t memtest[50]={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,
+29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49};
+
+void mem(const uint32_t * ptr)
+{
+__asm volatile ("LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+                "LDR R0,[%[src],#4]\n"
+               :[src] "+r" (ptr)
+               :
+               :"memory","r0"
+               );
+}
+
+int main(void)
+{
+  // System Initialization
+  SystemCoreClockUpdate();
+
+
+  int error;
+  uint32_t nbSched = 0;
+  int32_t overhead = 0;
+
+
+  printf("Start\n\r");
+
+  initCycleMeasurement();
+
+  for(int i=0;i<OVERHEADLOOP;i++)
+   {
+      cycleMeasurementStart();
+      mem(memtest);
+      cycleMeasurementStop();
+      overhead += getCycles() - 50;
+   }
+
+  overhead = overhead / OVERHEADLOOP;
+  printf("Measurement overhead %d\r\n",overhead);
+
+  cycleMeasurementStart();
+  nbSched=scheduler(&error,input_buffer,output_buffer);
+  cycleMeasurementStop();
+  int32_t cycles = getCycles() - overhead;
+
+  printf("Number of schedule iterations = %d\n\r",nbSched);
+  printf("Error code = %d\n\r",error);
+  printf("Cycles = %d\n\r",cycles);
+
+
+#if defined(COMMAND_LINE)
+    exit(0);
+#else
+    osThreadExit();
+#endif
+}