| 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586 |
- /******************************************************************************
- * @file arm_vec_filtering.h
- * @brief Private header file for CMSIS DSP Library
- * @version V1.7.0
- * @date 30. October 2019
- ******************************************************************************/
- /*
- * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- #ifndef _ARM_VEC_FILTERING_H_
- #define _ARM_VEC_FILTERING_H_
- #include "arm_math.h"
- #include "arm_helium_utils.h"
- #ifdef __cplusplus
- extern "C"
- {
- #endif
- #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
- #define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, count)\
- { \
- float32_t const *pSrcX, *pSrcY; \
- f32x4_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- acc2Vec = vdupq_n_f32(0.0f); \
- acc3Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- pSrcY = (float32_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- xVec = vldrwq_f32(&pSrcX[2]); \
- acc2Vec = vfmaq_f32(acc2Vec, xVec, yVec); \
- xVec = vldrwq_f32(&pSrcX[3]); \
- acc3Vec = vfmaq_f32(acc3Vec, xVec, yVec); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- xVec = vldrwq_f32(&pSrcX[2]); \
- acc2Vec = vfmaq_m_f32(acc2Vec, xVec, yVec, p0); \
- xVec = vldrwq_f32(&pSrcX[3]); \
- acc3Vec = vfmaq_m_f32(acc3Vec, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- } \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- acc2 = vecAddAcrossF32Mve(acc2Vec); \
- acc3 = vecAddAcrossF32Mve(acc3Vec); \
- }
- #define MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count) \
- { \
- float32_t const *pSrcX, *pSrcY; \
- f32x4_t accVec, xVec, yVec; \
- uint32_t k; \
- \
- accVec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- pSrcY = (float32_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- accVec = vfmaq_f32(accVec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- accVec = vfmaq_m_f32(accVec, xVec, yVec, p0);\
- } \
- acc = vecAddAcrossF32Mve(accVec); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count)\
- { \
- float32_t const *pSrcX, *pSrcY; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- pSrcY = (float32_t const *) pY; \
- k = (count-1) >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- k = (count-1) % 0x4U; \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp32q(k+1); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count)\
- { \
- float32_t const *pSrcX, *pSrcY; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- pSrcY = (float32_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- } \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\
- { \
- float32_t const *pSrcX, *pSrcY; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- pSrcY = (float32_t const *) pY; \
- k = count >> 2; \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- yVec = vldrwq_f32(&pSrcY[-1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x4U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- mve_pred16_t p0 = vctp32q(k+1); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- yVec = vldrwq_f32(&pSrcY[-1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec,p0); \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); \
- pSrcY += 4; \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec,p0); \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count) \
- { \
- float32_t const *pSrcX; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- k = (count - 1) >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = (count - 1) % 0x4U; \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- p0 = vctp32q(k+1); \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count) \
- { \
- float32_t const *pSrcX; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- xVec = vldrwq_f32(&pSrcX[1]); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- } \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\
- { \
- float32_t const *pSrcX; \
- const float32_t *pY1 = pY + 1; \
- f32x4_t acc0Vec, acc1Vec, xVec, yVec; \
- uint32_t k; \
- \
- acc0Vec = vdupq_n_f32(0.0f); \
- acc1Vec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- pY-=4; \
- acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \
- yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \
- pY1-=4; \
- acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x4U; \
- /* use predication to finalize MAC sum */ \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp32q(k); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \
- yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp32q(k+1); \
- acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \
- \
- acc0 = vecAddAcrossF32Mve(acc0Vec); \
- acc1 = vecAddAcrossF32Mve(acc1Vec); \
- }
- #define MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count) \
- { \
- float32_t const *pSrcX; \
- f32x4_t accVec, xVec, yVec; \
- uint32_t k; \
- \
- accVec = vdupq_n_f32(0.0f); \
- pSrcX = (float32_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- accVec = vfmaq_f32(accVec, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \
- accVec = vfmaq_m_f32(accVec, xVec, yVec, p0); \
- } \
- acc = vecAddAcrossF32Mve(accVec); \
- }
- #endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
- #if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
- #define MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count) \
- { \
- q31_t const *pSrcX; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc = vmlaldavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- acc = vmlaldavaq_p(acc, xVec, yVec, p0); \
- } \
- acc = asrl(acc, 31); \
- }
- #define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\
- { \
- q31_t const *pSrcX; \
- const q31_t *pY1 = pY + 1; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- pY-=4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \
- pY1-=4; \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x4U; \
- /* use predication to finalize MAC sum */ \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp32q(k); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp32q(k+1); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count) \
- { \
- q31_t const *pSrcX; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- k = (count-1) >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = (count - 1) % 0x4U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp32q(k+1); \
- xVec = vld1q(pSrcX); \
- pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count) \
- { \
- q31_t const *pSrcX; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count) \
- { \
- q31_t const *pSrcX; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- pY-=4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vldrwq_s32(&pSrcX[2]); \
- acc2 = vmlaldavaq(acc2, xVec, yVec); \
- xVec = vldrwq_s32(&pSrcX[3]); \
- acc3 = vmlaldavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrwq_s32(&pSrcX[2]); \
- acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrwq_s32(&pSrcX[3]); \
- acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- acc2 = asrl(acc2, 31); \
- acc3 = asrl(acc3, 31); \
- }
- #define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\
- { \
- q31_t const *pSrcX, *pSrcY; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- pSrcY = (q31_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_s32(&pSrcY[-1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x4U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- mve_pred16_t p0 = vctp32q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vldrwq_s32(&pSrcY[-1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count)\
- { \
- q31_t const *pSrcX, *pSrcY; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- pSrcY = (q31_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- acc = vmlaldavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- acc = vmlaldavaq_p(acc, xVec, yVec, p0); \
- } \
- acc = asrl(acc, 31); \
- }
- #define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count)\
- { \
- q31_t const *pSrcX, *pSrcY; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- pSrcY = (q31_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vldrwq_s32(&pSrcX[2]); \
- acc2 = vmlaldavaq(acc2, xVec, yVec); \
- xVec = vldrwq_s32(&pSrcX[3]); \
- acc3 = vmlaldavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrwq_s32(&pSrcX[2]); \
- acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrwq_s32(&pSrcX[3]); \
- acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- acc2 = asrl(acc2, 31); \
- acc3 = asrl(acc3, 31); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count)\
- { \
- q31_t const *pSrcX, *pSrcY; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- pSrcY = (q31_t const *) pY; \
- k = count >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x4U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count)\
- { \
- q31_t const *pSrcX, *pSrcY; \
- q31x4_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q31_t const *) pX; \
- pSrcY = (q31_t const *) pY; \
- k = (count-1) >> 2; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- k = (count-1) % 0x4U; \
- mve_pred16_t p0 = vctp32q(k); \
- yVec = vld1q(pSrcY); pSrcY += 4; \
- xVec = vldrwq_s32(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp32q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 4; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 31); \
- acc1 = asrl(acc1, 31); \
- }
- #define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\
- { \
- q15_t const *pSrcX, *pSrcY; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- pSrcY = (q15_t const *) pY; \
- k = count >> 3; \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vldrhq_s16(&pSrcY[-1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x8U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- mve_pred16_t p0 = vctp16q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vldrhq_s16(&pSrcY[-1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- p0 = vctp16q(k); \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count)\
- { \
- q15_t const *pSrcX, *pSrcY; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- pSrcY = (q15_t const *) pY; \
- k = count >> 3; \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- acc = vmlaldavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- acc = vmlaldavaq_p(acc, xVec, yVec, p0); \
- } \
- acc = asrl(acc, 15); \
- acc = __SSAT(acc, 16); \
- }
- #define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count)\
- { \
- q15_t const *pSrcX, *pSrcY; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- pSrcY = (q15_t const *) pY; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vldrhq_s16(&pSrcX[2]); \
- acc2 = vmlaldavaq(acc2, xVec, yVec); \
- xVec = vldrhq_s16(&pSrcX[3]); \
- acc3 = vmlaldavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrhq_s16(&pSrcX[2]); \
- acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrhq_s16(&pSrcX[3]); \
- acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc2 = asrl(acc2, 15); \
- acc3 = asrl(acc3, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- acc2 = __SSAT(acc2, 16); \
- acc3 = __SSAT(acc3, 16); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count)\
- { \
- q15_t const *pSrcX, *pSrcY; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- pSrcY = (q15_t const *) pY; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count)\
- { \
- q15_t const *pSrcX, *pSrcY; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- pSrcY = (q15_t const *) pY; \
- k = (count-1) >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- k = (count-1) % 0x8U; \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vld1q(pSrcY); pSrcY += 8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp16q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\
- { \
- q15_t const *pSrcX; \
- const q15_t *pY1 = pY + 1; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- pY-=8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \
- pY1-=8; \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x8U; \
- /* use predication to finalize MAC sum */ \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp16q(k); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp16q(k+1); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count) \
- { \
- q15_t const *pSrcX; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- pY-=8; \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc = vmlaldavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- acc = vmlaldavaq_p(acc, xVec, yVec, p0); \
- } \
- acc = asrl(acc, 15); \
- acc = __SSAT(acc, 16); \
- }
- #define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count) \
- { \
- q15_t const *pSrcX; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- pY-=8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vldrhq_s16(&pSrcX[2]); \
- acc2 = vmlaldavaq(acc2, xVec, yVec); \
- xVec = vldrhq_s16(&pSrcX[3]); \
- acc3 = vmlaldavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrhq_s16(&pSrcX[2]); \
- acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrhq_s16(&pSrcX[3]); \
- acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc2 = asrl(acc2, 15); \
- acc3 = asrl(acc3, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- acc2 = __SSAT(acc2, 16); \
- acc3 = __SSAT(acc3, 16); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count) \
- { \
- q15_t const *pSrcX; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- k = count >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- pY-=8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x8U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count) \
- { \
- q15_t const *pSrcX; \
- q15x8_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q15_t const *) pX; \
- k = (count-1) >> 3; \
- \
- while (k > 0U) \
- { \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- pY-=8; \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = (count - 1) % 0x8U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp16q(k); \
- yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \
- xVec = vldrhq_s16(&pSrcX[1]); \
- acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp16q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 8; \
- acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = asrl(acc0, 15); \
- acc1 = asrl(acc1, 15); \
- acc0 = __SSAT(acc0, 16); \
- acc1 = __SSAT(acc1, 16); \
- }
- #define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\
- { \
- q7_t const *pSrcX, *pSrcY; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- pSrcY = (q7_t const *) pY; \
- k = count >> 4; \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vldrbq_s8(&pSrcY[-1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x10U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- mve_pred16_t p0 = vctp8q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vldrbq_s8(&pSrcY[-1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec,p0); \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- p0 = vctp8q(k); \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec,p0); \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- }
- #define MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count)\
- { \
- q7_t const *pSrcX, *pSrcY; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- pSrcY = (q7_t const *) pY; \
- k = count >> 4; \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- acc = vmladavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- acc = vmladavaq_p(acc, xVec, yVec, p0); \
- } \
- acc =(acc >> 7); \
- acc = __SSAT(acc, 8); \
- }
- #define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count)\
- { \
- q7_t const *pSrcX, *pSrcY; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- pSrcY = (q7_t const *) pY; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vldrbq_s8(&pSrcX[2]); \
- acc2 = vmladavaq(acc2, xVec, yVec); \
- xVec = vldrbq_s8(&pSrcX[3]); \
- acc3 = vmladavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrbq_s8(&pSrcX[2]); \
- acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrbq_s8(&pSrcX[3]); \
- acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc2 = (acc2 >> 7); \
- acc3 = (acc3 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- acc2 = __SSAT(acc2, 8); \
- acc3 = __SSAT(acc3, 8); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count)\
- { \
- q7_t const *pSrcX, *pSrcY; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- pSrcY = (q7_t const *) pY; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* loop + tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- } \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- }
- #define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count)\
- { \
- q7_t const *pSrcX, *pSrcY; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- pSrcY = (q7_t const *) pY; \
- k = (count-1) >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- k = (count-1) % 0x10U; \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vld1q(pSrcY); pSrcY += 16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp8q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- }
- #define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\
- { \
- q7_t const *pSrcX; \
- const q7_t *pY1 = pY + 1; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- pY-=16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \
- pY1-=16; \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = count % 0x10U; \
- /* use predication to finalize MAC sum */ \
- /* acc0 requires exact number of sample */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp8q(k); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \
- /* acc1 requires 1 additional sample */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp8q(k+1); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- }
- #define MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count) \
- { \
- q7_t const *pSrcX; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- pY-=16; \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc = vmladavaq(acc, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- acc = vmladavaq_p(acc, xVec, yVec, p0); \
- } \
- acc = __SSAT(acc >> 7, 8); \
- }
- #define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count) \
- { \
- q7_t const *pSrcX; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- pY-=16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vldrbq_s8(&pSrcX[2]); \
- acc2 = vmladavaq(acc2, xVec, yVec); \
- xVec = vldrbq_s8(&pSrcX[3]); \
- acc3 = vmladavaq(acc3, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- xVec = vldrbq_s8(&pSrcX[2]); \
- acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \
- xVec = vldrbq_s8(&pSrcX[3]); \
- acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = __SSAT(acc0 >> 7, 8); \
- acc1 = __SSAT(acc1 >> 7, 8); \
- acc2 = __SSAT(acc2 >> 7, 8); \
- acc3 = __SSAT(acc3 >> 7, 8); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count) \
- { \
- q7_t const *pSrcX; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- k = count >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- pY-=16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- /* Loop with tail predication expected here */ \
- k = count % 0x10U; \
- if (k > 0U) \
- { \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- } \
- acc0 = __SSAT(acc0 >> 7, 8); \
- acc1 = __SSAT(acc1 >> 7, 8); \
- }
- #define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count) \
- { \
- q7_t const *pSrcX; \
- q7x16_t xVec, yVec; \
- uint32_t k; \
- \
- pSrcX = (q7_t const *) pX; \
- k = (count-1) >> 4; \
- \
- while (k > 0U) \
- { \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- pY-=16; \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq(acc1, xVec, yVec); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq(acc0, xVec, yVec); \
- /* Decrement the loop counter */ \
- k--; \
- } \
- k = (count - 1) % 0x10U; \
- /* use predication to finalize MAC sum */ \
- /* acc1 requires exact number of sample (count-1) */ \
- /* disable extra lanes in final MAC computation */ \
- mve_pred16_t p0 = vctp8q(k); \
- yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \
- xVec = vldrbq_s8(&pSrcX[1]); \
- acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \
- /* acc0 requires 1 additional sample (count) */ \
- /* so add 1 to unmask an extra lane in final MAC computation */ \
- p0 = vctp8q(k+1); \
- xVec = vld1q(pSrcX); pSrcX += 16; \
- acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \
- \
- acc0 = (acc0 >> 7); \
- acc1 = (acc1 >> 7); \
- acc0 = __SSAT(acc0, 8); \
- acc1 = __SSAT(acc1, 8); \
- }
- #endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
- #ifdef __cplusplus
- }
- #endif
- #endif /* _ARM_VEC_FILTERING_H_ */
|