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@@ -155,15 +155,28 @@ extern unsigned int SystemCoreClock;
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-/*********************************************************************
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-*
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-* Defines, fixed
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-*
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-**********************************************************************
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-*/
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-#define DWT_CTRL (*(volatile rt_uint32_t*) (0xE0001000uL)) // DWT Control Register
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-#define NOCYCCNT_BIT (1uL << 25) // Cycle counter support bit
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-#define CYCCNTENA_BIT (1uL << 0) // Cycle counter enable bit
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+//==================== DWT & CoreDebug 地址定义 ====================//
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+
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+#define DWT_CTRL (*(volatile unsigned int *)0xE0001000u) // DWT Control Register
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+#define DWT_CYCCNT (*(volatile unsigned int *)0xE0001004u) // DWT Cycle Counter Register
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+#define DEMCR (*(volatile unsigned int *)0xE000EDFCu) // Debug Exception and Monitor Control Register
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+
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+//==================== 位定义 ====================//
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+
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+#define TRCENA_BIT (1u << 24) // DEMCR[24] = TRCENA: Trace enable
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+#define CYCCNTENA_BIT (1u << 0) // DWT_CTRL[0] = CYCCNTENA: Cycle Counter Enable
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+#define NOCYCCNT_BIT (1u << 25) // DWT_CTRL[25] = NOCYCCNT: Cycle Counter not present
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+
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+//==================== 启用 DWT Cycle Counter 的宏 ====================//
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+
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+#define ENABLE_DWT_CYCLE_COUNTER() \
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+ do { \
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+ DEMCR |= TRCENA_BIT; /* Enable trace */ \
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+ if ((DWT_CTRL & NOCYCCNT_BIT) == 0) { /* If CYCCNT is supported */ \
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+ DWT_CYCCNT = 0; /* Clear counter */ \
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+ DWT_CTRL |= CYCCNTENA_BIT; /* Enable counter */ \
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+ } \
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+ } while (0)
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/*********************************************************************
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*
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@@ -198,11 +211,7 @@ void SEGGER_SYSVIEW_Conf(void) {
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// The cycle counter must be activated in order
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// to use time related functions.
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//
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- if ((DWT_CTRL & NOCYCCNT_BIT) == 0) { // Cycle counter supported?
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- if ((DWT_CTRL & CYCCNTENA_BIT) == 0) { // Cycle counter not enabled?
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- DWT_CTRL |= CYCCNTENA_BIT; // Enable Cycle counter
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- }
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- }
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+ ENABLE_DWT_CYCLE_COUNTER();
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#endif
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SEGGER_SYSVIEW_Init(SYSVIEW_TIMESTAMP_FREQ, SYSVIEW_CPU_FREQ,
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&SYSVIEW_X_OS_TraceAPI, _cbSendSystemDesc);
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