Release v1.1.0

Include/stm32h503xx.h

@@ -1356,6 +1356,7 @@ typedef struct
   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
 } NSSLIB_pFunc_TypeDef;
 
+
 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
 
 
@@ -10575,11 +10576,12 @@ typedef struct
 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk              (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
 #define TAMP_ATCR1_ATPER_Pos                (24U)
 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk

Include/stm32h562xx.h

@@ -2111,6 +2111,7 @@ typedef struct
   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
 } NSSLIB_pFunc_TypeDef;
 
+
 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
 
 
@@ -15786,11 +15787,12 @@ typedef struct
 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk              (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
 #define TAMP_ATCR1_ATPER_Pos                (24U)
 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
@@ -21125,8 +21127,6 @@ typedef struct
                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
                                                         ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
-                                                        ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
-                                                        ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -21254,15 +21254,9 @@ typedef struct
                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
-                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) || \
-                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) || \
-                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S) || \
-                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S) || \
                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
-                                         ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
-                                         ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

Include/stm32h563xx.h

@@ -2299,6 +2299,7 @@ typedef struct
   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
 } NSSLIB_pFunc_TypeDef;
 
+
 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
 
 
@@ -17882,11 +17883,12 @@ typedef struct
 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk              (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
 #define TAMP_ATCR1_ATPER_Pos                (24U)
 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
@@ -23261,8 +23263,6 @@ typedef struct
                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
                                                         ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
-                                                        ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
-                                                        ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -23390,15 +23390,9 @@ typedef struct
                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
-                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) || \
-                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) || \
-                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S) || \
-                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S) || \
                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
-                                         ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
-                                         ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

Include/stm32h573xx.h

@@ -2394,6 +2394,31 @@ typedef struct
   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
 } NSSLIB_pFunc_TypeDef;
 
+/*
+ * Certificate address description
+ */
+#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U)
+#define CERT_CHIP_PACK1_SIZE (0x200U)
+#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U)
+#define CERT_CHIP_PACK2_SIZE (0x200U)
+
+#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR)
+#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE)
+
+#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET  (152U)
+#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR  (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET)
+#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET   (216U)
+#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR     (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET)
+#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET   (484U)
+#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR   (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET)
+
+#define CERT_ST_DUA_USER_PUB_KEY_OFFSET     (12U)
+#define CERT_ST_DUA_USER_PUB_KEY_ADDR       (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET)
+#define CERT_ST_DUA_USER_SIGN_OFFSET      (76U)
+#define CERT_ST_DUA_USER_SIGN_ADDR        (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET)
+#define CERT_ST_DUA_USER_SERIAL_OFFSET      (140U)
+#define CERT_ST_DUA_USER_SERIAL_ADDR      (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET)
+
 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
 
 
@@ -18439,11 +18464,12 @@ typedef struct
 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
-#define TAMP_ATCR1_ATCKSEL_Msk              (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
 #define TAMP_ATCR1_ATPER_Pos                (24U)
 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
@@ -24186,8 +24212,6 @@ typedef struct
                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
                                                         ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
-                                                        ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
-                                                        ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -24315,15 +24339,9 @@ typedef struct
                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
 
 /******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
-                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) || \
                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) || \
-                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) || \
-                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S) || \
-                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S) || \
                                          ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
-                                         ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
-                                         ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

Include/stm32h5xx.h

@@ -78,10 +78,10 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number 1.0.0
+  * @brief CMSIS Device version number 1.1.0
   */
 #define __STM32H5_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32H5_CMSIS_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32H5_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
 #define __STM32H5_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32H5_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32H5_CMSIS_VERSION        ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\

Release_Notes.html

@@ -30,10 +30,21 @@
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history"><strong>Update History</strong></h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section1" Checked aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
+<input type="checkbox" id="collapse-section2" Checked aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
+<li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
+<li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
+<li>Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
 <li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
 </ul>
 </div>

Source/Templates/arm/startup_stm32h503xx.s

@@ -89,8 +89,8 @@ __Vectors       DCD     __initial_sp                     ; Top of Stack
                 DCD     EXTI1_IRQHandler                 ; EXTI Line1 interrupt
                 DCD     EXTI2_IRQHandler                 ; EXTI Line2 interrupt
                 DCD     EXTI3_IRQHandler                 ; EXTI Line3 interrupt
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
+                DCD     EXTI4_IRQHandler                 ; EXTI Line4 interrupt
+                DCD     EXTI5_IRQHandler                 ; EXTI Line5 interrupt
                 DCD     EXTI6_IRQHandler                 ; EXTI Line6 interrupt
                 DCD     EXTI7_IRQHandler                 ; EXTI Line7 interrupt
                 DCD     EXTI8_IRQHandler                 ; EXTI Line8 interrupt